CMOS-MEMS three-dimensional integration technology
By using dry etching technology with the wafer's own metal layer as a mask in CMOS-MEMS devices, the problem of poor compatibility between MEMS and CMOS processes is solved, enabling high-precision, low-cost fabrication of three-dimensional integrated devices and improving device sensitivity and signal transmission efficiency.
CN122126795APending Publication Date: 2026-06-02BEIJING INST OF TECH
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF TECH
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-02
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Figure CN122126795A_ABST
Abstract
This invention provides a CMOS-MEMS three-dimensional integrated device and its fabrication method, belonging to the field of semiconductor device technology. This invention exposes a first metal layer by etching the top silicon dioxide layer. Using the first metal layer as a mask, a pre-defined mechanical structure within the wafer is released, avoiding the use of an external mask and overcoming the limitations imposed by the processing precision of external masks on MEMS. Through the design of the etching path, the pre-defined mechanical structure can be obtained while meeting processing precision requirements, ensuring the sensitivity and signal transmission efficiency of the MEMS. This invention uses only dry etching, eliminating the need for developing solutions and avoiding exposure processes, thus improving processing efficiency.
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