Deposition masks, methods for manufacturing them, and electronic devices made using them.

Abstract

The present disclosure relates to a deposition mask, a method of manufacturing a deposition mask, and an electronic device manufactured using the deposition mask. The deposition mask includes a mask frame having a cell opening, a film on the mask frame and having a plurality of pixel openings communicating with the cell opening, and a mask alignment key on the mask frame and having a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0176197, filed on December 2, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to deposition masks, methods of manufacturing deposition masks, and electronic devices manufactured using deposition masks. Background Technology

[0004] Wearable devices have been developed in the form of glasses and / or helmets, in which the focal point is formed at a distance close to the user's eyes (e.g., in front of the user's eyes). For example, the wearable device may be a head-mounted display (HMD) device or augmented reality (hereinafter referred to as "AR") glasses. Such wearable devices can provide the user with AR images or virtual reality (hereinafter referred to as "VR") images.

[0005] In the case of wearable devices such as HMD devices or AR glasses, a display resolution of approximately 3000 PPI (pixels per inch) or higher is desired or required to allow users to use them for extended periods without experiencing dizziness. For this purpose, organic light-emitting diode on silicon (OLEDoS) technology has emerged for high-resolution, small-scale organic light-emitting display devices. OLEDoS is a technology that arranges organic light-emitting diodes (OLEDs) on a semiconductor substrate on which complementary metal-oxide-semiconductor (CMOS) elements are arranged.

[0006] To manufacture display panels with a high resolution of approximately 3000 PPI or higher, a high-resolution deposition mask is required or necessary. For example, a deposition mask can be manufactured by forming a film with multiple pixel openings on a mask substrate such as a silicon wafer and partially removing the mask substrate to form cell openings that expose the pixel openings.

[0007] In the deposition process for forming the light-emitting material layer of a display panel, a backplane substrate can be disposed on a deposition mask, and vapor-deposited material provided from the deposition source can be deposited on the backplane substrate through pixel openings in the deposition mask. Substrate alignment bonds can be disposed on the backplane substrate, and mask alignment bonds can be disposed on the deposition mask. The positional information of the substrate alignment bonds and mask alignment bonds can be acquired by a camera, and based on the positional information, the backplane substrate can be aligned above the deposition mask. Summary of the Invention

[0008] The aspects and features of embodiments of this disclosure refer to a deposition mask with a mask alignment key having improved recognition rate, a method for manufacturing a deposition mask, and an electronic device manufactured using the deposition mask.

[0009] However, the embodiments of this disclosure are not limited to those described herein. The above and additional aspects and features of the embodiments of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains, by referring to the detailed description of this disclosure provided herein or by practicing the embodiments presented herein.

[0010] According to one or more embodiments of the present disclosure, a deposition mask may include: a mask frame having cell openings; a membrane on the mask frame (e.g., disposed on the mask frame) and having a plurality of pixel openings communicating with the cell openings; and a mask alignment key on the mask frame (e.g., disposed on the mask frame) and having a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

[0011] According to one or more embodiments of this disclosure, the mask alignment key may be in the membrane (e.g., arranged in the membrane), and the mask frame may have key openings that expose the mask alignment key and the membrane around (e.g., surrounding) a portion of the mask alignment key.

[0012] According to one or more embodiments of this disclosure, the deposition mask may also include a plurality of dummy keys on a mask frame (e.g., arranged on a mask frame), and each of the dummy keys may have the same thickness as the mask alignment key.

[0013] According to one or more embodiments of this disclosure, the membrane may be disposed on the mask alignment key, dummy key, and mask frame (e.g., arranged on the mask alignment key, dummy key, and mask frame).

[0014] According to one or more embodiments of this disclosure, the mask alignment key may have the same thickness as the film.

[0015] According to one or more embodiments of the present disclosure, the mask frame may have key openings that expose portions of the membrane, and mask alignment keys may be located on portions of the membrane exposed by the key openings (e.g., arranged on portions of the membrane exposed by the key openings).

[0016] According to one or more embodiments of this disclosure, the deposition mask may also include a plurality of dummy keys on the film (e.g., arranged on the film), and each of the dummy keys may have the same thickness as the mask alignment key.

[0017] According to one or more embodiments of the present disclosure, each of the first inorganic film patterns may be a silicon oxide film pattern having a thickness of about 90 nanometers (nm) to about 110 nm, each of the second inorganic film patterns may be a silicon nitride film pattern having a thickness of about 40 nm to about 60 nm, and the mask alignment key may include three to eleven or four to twelve first inorganic film patterns and three to eleven second inorganic film patterns.

[0018] According to one or more embodiments of the present disclosure, each of the first inorganic film patterns may be a silicon oxide film pattern having a thickness of about 40 nm to about 60 nm, each of the second inorganic film patterns may be a silicon nitride film pattern having a thickness of about 90 nm to about 110 nm, and the mask alignment bond may include five to thirteen or six to fourteen first inorganic film patterns and five to thirteen second inorganic film patterns.

[0019] According to one or more embodiments of this disclosure, the mask alignment key may have a light reflectivity of about 0.5 or greater for light having a wavelength of about 390 nm to about 440 nm or a wavelength of about 500 nm to about 560 nm.

[0020] According to one or more embodiments of the present disclosure, a method of manufacturing a deposition mask may include: forming mask alignment bonds on a mask substrate; forming a film having a plurality of pixel openings exposing the mask substrate on the mask substrate; and patterning the mask substrate to form cell openings communicating with the pixel openings. The mask alignment bonds may be formed as having a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

[0021] According to one or more embodiments of this disclosure, forming a mask alignment bond may include: forming a multilayer inorganic film on a mask substrate in which a first inorganic film and a second inorganic film are alternately stacked; and patterning the multilayer inorganic film to form a mask alignment bond on the mask substrate. The film may be formed on the mask alignment bond and the mask substrate.

[0022] According to one or more embodiments of this disclosure, the method may further include patterning a mask substrate to form key openings that expose the mask alignment bonds and the film around (e.g., around) portions of the mask alignment bonds.

[0023] According to one or more embodiments of this disclosure, the method may further include patterning a multilayer inorganic film to form a plurality of dummy bonds on a mask substrate. The dummy bonds may be formed synchronously (e.g., simultaneously) with mask alignment bonds, and the film may be formed on the mask alignment bonds, the dummy bonds, and the mask substrate.

[0024] According to one or more embodiments of this disclosure, forming a film may include forming a front inorganic film on a mask substrate and patterning the front inorganic film to form a pixel aperture. Forming a mask alignment bond may include forming a multilayer inorganic film on the front inorganic film in which a first inorganic film and a second inorganic film are alternately stacked, and patterning the multilayer inorganic film to form a mask alignment bond on the front inorganic film. In this case, the pixel aperture may be formed after the mask alignment bond is formed.

[0025] According to one or more embodiments of the present disclosure, the method may further include patterning a mask substrate to form bond openings in portions of the exposed film, and mask alignment bonds may be formed on portions of the film exposed by the bond openings.

[0026] According to one or more embodiments of this disclosure, the method may further include patterning a multilayer inorganic film to form a plurality of dummy bonds on the preceding inorganic film, and the dummy bonds may be formed synchronously (e.g., simultaneously) with mask alignment bonds.

[0027] According to one or more embodiments of the present disclosure, each of the first inorganic film patterns may be a silicon oxide film pattern having a thickness of about 90 nm to about 110 nm, each of the second inorganic film patterns may be a silicon nitride film pattern having a thickness of about 40 nm to about 60 nm, and the mask alignment bond may include three to eleven or four to twelve first inorganic film patterns and three to eleven second inorganic film patterns.

[0028] According to one or more embodiments of the present disclosure, each of the first inorganic film patterns may be a silicon oxide film pattern having a thickness of about 40 nm to about 60 nm, each of the second inorganic film patterns may be a silicon nitride film pattern having a thickness of about 90 nm to about 110 nm, and the mask alignment bond may include five to thirteen or six to fourteen first inorganic film patterns and five to thirteen second inorganic film patterns.

[0029] According to one or more embodiments of this disclosure, the mask alignment key may have a light reflectivity of about 0.5 or greater for light having a wavelength of about 390 nm to about 440 nm or a wavelength of about 500 nm to about 560 nm.

[0030] According to one or more embodiments of this disclosure, an electronic device may include a display panel. The display panel may include a substrate and a plurality of light-emitting layers formed on the substrate using a deposition mask. The deposition mask may include: a mask frame having cell openings; a film on the mask frame (e.g., disposed on the mask frame) and having a plurality of pixel openings communicating with the cell openings; and a mask alignment key on the mask frame (e.g., disposed on the mask frame) and having a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

[0031] According to one or more embodiments of the present disclosure as described above, the mask alignment key may have a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked. The mask alignment key may have a light reflectance of about 0.5 or greater for light with wavelengths of about 390 nm to about 440 nm or about 500 nm to about 560 nm, thereby significantly improving the recognition rate of the mask alignment key. This improved recognition rate is used for precise alignment during the deposition process, ensuring that the vapor-deposited material is accurately deposited onto the backplane substrate through the pixel openings. The enhanced visibility of the mask alignment key allows for better positional information obtained via a camera, facilitating more accurate alignment of the backplane substrate over the deposition mask. Therefore, this results in higher quality and resolution of the final display panels, making them suitable for advanced applications requiring high resolution and minimal user discomfort, such as AR and VR devices.

[0032] Other features and embodiments of this disclosure will be apparent to those skilled in the art from the following detailed description and accompanying drawings. Attached Figure Description

[0033] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. The above and other aspects and features of this disclosure will become more apparent and understood from the following description of exemplary embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure; Figure 2 This is a schematic diagram illustrating an electronic device according to one or more embodiments of the present disclosure; Figure 3 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure; Figure 4 This illustrates one or more embodiments according to this disclosure. Figure 3 Block diagram of the display device shown; Figure 5 This illustrates one or more embodiments according to this disclosure. Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown; Figure 6 This illustrates one or more embodiments according to this disclosure. Figure 3 A schematic floor plan of an example of a display panel shown; Figure 7 This illustrates one or more embodiments according to this disclosure. Figure 6A schematic enlarged plan view of an example of the display area shown; Figure 8 This illustrates one or more embodiments according to this disclosure. Figure 6 A schematic enlarged plan view of another example of the display area shown; Figure 9 This illustrates one or more embodiments of the present disclosure along... Figure 7 A schematic cross-sectional view of an example display panel, shown by line I1-I1'. Figure 10 This illustrates one or more embodiments of the present disclosure along... Figure 7 A schematic cross-sectional view of another example of a display panel, shown by line I1-I1'. Figure 11 This is a schematic perspective view illustrating an example of a head-mounted display according to one or more embodiments of the present disclosure; Figure 12 This illustrates one or more embodiments according to this disclosure. Figure 11 A schematic exploded perspective view of the head-mounted display shown; Figure 13 This is a schematic perspective view illustrating another example of a head-mounted display according to one or more embodiments of the present disclosure; Figure 14 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including a deposition mask according to one or more embodiments of the present disclosure; Figure 15 This illustrates one or more embodiments according to this disclosure. Figure 14 A schematic bottom view of the backplate substrate shown; Figure 16 This illustrates one or more embodiments according to this disclosure. Figure 14 A schematic plan view of the deposition mask shown; Figure 17 This illustrates one or more embodiments according to this disclosure. Figure 16 A schematic plan view of the mask cell area shown; Figure 18 It is along one or more embodiments of this disclosure. Figure 17 A schematic cross-sectional view taken by line I2-I2' shown; Figure 19 This illustrates one or more embodiments according to this disclosure. Figure 16 A schematic cross-sectional view of the mask alignment key shown; Figure 20 This illustrates one or more embodiments according to this disclosure. Figure 14A schematic cross-sectional view of the camera shown; Figure 21 This illustrates the use according to one or more embodiments of the present disclosure. Figure 20 A schematic cross-sectional view of the method for detecting substrate alignment keys and mask alignment keys using a camera, as shown in the diagram; Figure 22 This is a cross-sectional view showing a deposition mask according to one or more embodiments of the present disclosure; Figure 23 This is a schematic plan view showing a deposition mask according to one or more embodiments of the present disclosure; Figure 24 This illustrates one or more embodiments according to this disclosure. Figure 23 A schematic cross-sectional view of the mask alignment key and spacer shown; Figure 25 This is a schematic cross-sectional view showing a deposition mask according to one or more embodiments of the present disclosure; Figures 26 to 32 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to one or more embodiments of the present disclosure; and Figures 33 to 36 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to one or more embodiments of the present disclosure. Detailed Implementation

[0034] This disclosure will now be described more fully below with reference to the accompanying drawings, in which one or more embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as being limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0035] It will also be understood that if an element or layer is referred to as being “on” another element or layer (e.g., when an element or layer is referred to as being “on” another element or layer), it can be directly on the other element or layer, or there may be one or more intervening layers in between. Conversely, “directly on” can mean that there is no additional intervening element or layer between the element or layer and the other element or layer. Throughout the disclosure, the same or similar reference numerals denote the same or similar components.

[0036] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed herein may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural (e.g., simultaneously) unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” can mean “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, if used in this disclosure (e.g., when used in this disclosure), the terms “comprise(s)” and / or “include(s)” and / or “has(have)” specify the presence of the stated features, areas, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, numbers, steps, operations, elements, components, and / or groups thereof. Additionally, the terms "comprise(s)", "include(s)", "has(have)", or other similar terms include or support the terms "consisting of" and "substantially consisting of", indicating the presence of the stated features, numbers, steps, operations, elements, and / or components, while other features, numbers, steps, operations, elements, components, and / or groups thereof are absent or substantially absent. Furthermore, when describing embodiments of this disclosure, the word "may" means "one or more embodiments of this disclosure".

[0038] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations described in the drawings, the relative terms are intended to encompass different orientations of the device. For example, if a device in one of the drawings is flipped (e.g., inverted), an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the drawing, the term “down” may (e.g., simultaneously) encompass both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped (e.g., inverted), an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the term “below” or “under” may (e.g., simultaneously) encompass both “up” and “down” orientations.

[0039] Features of each of the various embodiments of this disclosure may be combined with each other in part or in whole, and may be technically different from each other in their cooperation. Furthermore, the various embodiments may be implemented independently of each other or may be implemented together in relation to each other.

[0040] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated value and may refer to an acceptable deviation from the stated value as determined by one of ordinary skill in the art. For example, "about" may refer to one or more standard deviations, or to ±30%, ±20%, ±10%, or ±5% of the stated value.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in general dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0042] This document describes embodiments with reference to cross-sectional views that serve as schematic diagrams of one or more embodiments of this disclosure. Variations in the illustrated shapes should be anticipated, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but should include, for example, deviations in shape due to manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, in one or more embodiments, the acute angles shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0043] In the following description, one or more embodiments will be described in more detail with reference to the accompanying drawings.

[0044] The display device according to one or more embodiments of the present disclosure can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments of the present disclosure includes the display device described herein, and may also include modules or devices with additional functions in addition to the display device.

[0045] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0046] refer to Figure 1An electronic device 10 according to one or more embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0047] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0048] The memory 13 can store the data information required for the operation of the processor 12 and / or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0049] The power module 14 may include a power supply module (such as, for example, a power adapter or a battery) and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0050] At least one of the components of the electronic device 10 according to one or more embodiments of the present disclosure may include the display device 20 according to one or more embodiments of the present disclosure, which will be described later (see [link to relevant documentation]). Figure 3 Furthermore, some modules that are functionally included in a module may be included in the display device 20, while other modules may be provided separately from the display device 20. For example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided within the electronic device 10 in the form of other devices besides the display device 20.

[0051] Figure 2 This is a schematic diagram illustrating an electronic device according to one or more embodiments of the present disclosure.

[0052] refer to Figure 2 The display device 20 according to one or more embodiments of the present disclosure may include not only image display electronic devices such as smartphones 10_1a, tablet PCs (personal computers) 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and vehicle electronic devices 10_3 (such as CID (central information display) and interior mirror displays, central instrument panels, and dashboards arranged on the dashboard of a car) that include display modules.

[0053] Figure 3 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure. Figure 4 This illustrates one or more embodiments. Figure 3 Block diagram of the display device shown.

[0054] refer to Figure 3 and Figure 4 The display device 20 according to one or more embodiments can be a device for displaying moving or still images. The display device 20 according to one or more embodiments can be used as an electronic device 10 or a display module 11 of an electronic device 10. For example, the display device 20 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. The display device 20 according to one or more embodiments can be applied as a display module 11 of an electronic device 10 such as a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. The display device 20 according to one or more embodiments can be applied to an electronic device 10 such as a smartwatch, a smartwatch phone, or a head-mounted display (HMD) for realizing virtual and augmented reality.

[0055] The display device 20 according to one or more embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0056] In one or more embodiments, the display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded with a set or predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 20 may conform to the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0057] Display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, scan driver 610, emission driver 620, and data driver 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0058] Multiple pixels PX can be arranged in the display area DAA. In one or more embodiments, the multiple pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2. Multiple scan lines SL and multiple emission control lines EL can extend along the first direction DR1 and be arranged along the second direction DR2. Multiple data lines DL can extend along the second direction DR2 and be arranged relative to each other along the first direction DR1.

[0059] Multiple scan lines SL may include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple transmit control lines EL include multiple first transmit control lines ECL1 and multiple second transmit control lines ECL2.

[0060] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. For example... Figure 5 As shown, the multiple sub-pixels SP1, SP2, and SP3 can each include multiple pixel transistors, and these pixel transistors can be formed and arranged on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 9 For example, in one or more embodiments, the plurality of pixel transistors of the data driver 700 may be formed of complementary metal-oxide-semiconductor (CMOS), but embodiments of the present disclosure are not limited thereto.

[0061] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to (e.g., one) a write scan line GWL, (e.g., one) a control scan line GCL, (e.g., one) a bias scan line GBL, (e.g., one) a first emission control line ECL1, (e.g., one) a second emission control line ECL2, and (e.g., one) a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage from the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0062] In one or more embodiments, the scan driver 610, the transmit driver 620, and the data driver 700 may each be arranged in the non-display area NDA.

[0063] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor model]). Figure 9 For example, in one or more embodiments, the plurality of scanning transistors and the plurality of light-emitting transistors may be formed by CMOS, but the embodiments of this disclosure are not limited thereto.

[0064] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from a timing control circuit (e.g., a timing controller) 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0065] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and outputs them sequentially to a first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and outputs them sequentially to a second transmit control line ECL2.

[0066] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 9 For example, in one or more embodiments, multiple data transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto.

[0067] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. At this point, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and data voltage (e.g., analog data voltage) can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0068] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one (e.g.) surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer and / or a graphite layer having high thermal conductivity, such as silver (Ag), copper (Cu), and / or aluminum (Al).

[0069] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [link to PDA1]) using conductive adhesive components such as anisotropic conductive film. Figure 6 Multiple first pads PD1 (see) Figure 6 In one or more embodiments, the circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Although in Figure 3 The circuit board 300 is shown folded, but it can be bent. In this respect, one end of the circuit board 300 can be positioned on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the first pad portion of the display panel 100, PDA1, using conductive adhesive members (see [link to PDA1]). Figure 6 Multiple first pads PD1 (see) Figure 6 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0070] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0071] The power supply circuit (e.g., power supply unit) 500 can generate multiple panel driving voltages based on an external power supply voltage. For example, in one or more embodiments, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later in conjunction with... Figure 5 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0072] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this regard, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0073] In one or more embodiments, each of the timing control circuit 400 and the power supply circuit 500 may be arranged in the non-display area NDA of the display panel 100, similar to the scan driver 610, transmit driver 620, and data driver 700. In these embodiments, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor panel]). Figure 9 On. For example, in one or more embodiments, the plurality of timing transistors and the plurality of power transistors may be formed by CMOS, but embodiments of the present disclosure are not limited thereto. In one or more embodiments, each of the timing control circuit 400 and the power supply circuit 500 may be arranged on the data driver 700 and the first pad portion of PDA1 (see Figure 6 )between.

[0074] Figure 5 This illustrates one or more embodiments according to this disclosure. Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown.

[0075] refer to Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, the second drive voltage line VDL, and the third drive voltage line VIL. A first drive voltage VSS, corresponding to a low potential voltage, is applied to the first drive voltage line VSL; a second drive voltage VDD, corresponding to a high potential voltage, is applied to the second drive voltage line VDL; and a third drive voltage VINT, corresponding to the initialization voltage, is applied to the third drive voltage line VIL.

[0076] In one or more embodiments, the first sub-pixel SP1 may include a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0077] The light-emitting element LE emits light in response to a drive current flowing through the channel region of the first transistor T1. The emission amount (e.g., emission intensity) of the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. In one or more embodiments, the light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in these embodiments, the light-emitting element LE can be a miniature light-emitting diode.

[0078] The first transistor T1 may be a driving transistor that controls the source-drain current (hereinafter referred to as "driving current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode.

[0079] The second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0080] The third transistor T3 can be arranged between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this purpose, if the gate electrode and drain electrode of the first transistor T1 are connected (e.g., when the gate electrode and drain electrode of the first transistor T1 are connected), the first transistor T1 can operate like a diode.

[0081] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0082] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0083] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0084] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, in one or more embodiments, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments of this disclosure are not limited thereto. In one or more embodiments, each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. In one or more embodiments, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0085] Despite Figure 5 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 5 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 5 Those shown in the image.

[0086] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can each be essentially combined with each other. Figure 5 The equivalent circuit diagram of the first sub-pixel SP1 is the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0087] Figure 6 This illustrates one or more embodiments according to this disclosure. Figure 3 A schematic floor plan of an example of a display panel shown.

[0088] refer to Figure 6The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0089] The scan driver 610 may be arranged on a first side of the display area DAA, and the transmit driver 620 may be arranged on a second side of the display area DAA (opposite to the first side). For example, in one or more embodiments, the scan driver 610 may be arranged on one side of the display area DAA in a first direction DR1, and the transmit driver 620 may be arranged on the other side of the display area DAA in the first direction DR1. However, embodiments of this disclosure are not limited thereto; for example, in one or more embodiments, the scan driver 610 and the transmit driver 620 may be arranged (e.g., simultaneously) on both the first and second sides of the display area DAA.

[0090] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, in one or more embodiments, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700. This means that the first pad portion PDA1 is positioned further toward the edge of the display panel 100 than the data driver 700, ensuring that it is outside the area occupied by the data driver 700 in the second direction DR2. This positioning facilitates the connection of the first pads PD1 to the circuit board 300 via conductive adhesive members, thereby facilitating the overall assembly and function of the display panel 100.

[0091] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is functioning correctly. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0092] The second pad portion PDA2 can be disposed on the fourth side of the display area DAA. For example, in one or more embodiments, the second pad portion PDA2 can be disposed on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be disposed outside the second distribution circuit 720 in the second direction DR2. For example, the second pad portion PDA2 can be disposed closer to the edge of the display panel 100 than the second distribution circuit 720.

[0093] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to a plurality of data lines DL. For example, in one or more embodiments, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P data lines DL (P is a positive integer of 2 or greater), and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2.

[0094] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the opposite side of the display area DAA in a second direction DR2. In the context of this disclosure and unless otherwise defined, "one side of the display area DAA in a second direction DR2" refers to a specific side of the display area DAA along the direction marked DR2. For example, if DR2 represents a vertical direction, this could indicate the bottom side of the display area DAA. Conversely, "the opposite side of the display area DAA in a second direction DR2" refers to the opposite side of the display area DAA along the same direction DR2, continuing the previous example, which could indicate the top side of the display area DAA. These phrases are used to describe the positioning of components such as distribution circuits on the opposite side of the display area DAA along a specified direction DR2.

[0095] The cathode connection portion CCA can be the display element layer EML within the non-display area NDA (see [link]). Figure 9 The second electrode CAT (see) Figure 9The region connected to the first drive voltage line VSL. In one or more embodiments, the cathode connection portion CCA may be disposed outside at least one side of the display area DAA. For example, the cathode connection portion CCA may be disposed outside at least one side of the display area DAA selected from the left, right, top, and bottom sides. In one or more embodiments, the cathode connection portion CCA may be arranged as follows: Figure 6 The diagram shows a method for minimizing or reducing deviations in the first drive voltage VSS caused by voltage drops (IR drops) or voltage rises (IR rises) of the second electrode CAT in the display area DAA.

[0096] Figure 7 This illustrates one or more embodiments according to this disclosure. Figure 6 A schematic enlarged plan view of an example of the display area shown. Figure 8 This illustrates one or more embodiments. Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0097] refer to Figure 7 and Figure 8 Each of pixel PX includes a first emission region EA1, a second emission region EA2, and a third emission region EA3. The first emission region EA1 is the emission region of the first sub-pixel SP1, the second emission region EA2 is the emission region of the second sub-pixel SP2, and the third emission region EA3 is the emission region of the third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a via VA9. For example, a via VA9 is a feature included in each of the sub-pixels. (See later...) Figure 9 A more detailed description of the through-hole VA9.

[0098] In the plan view, the first launch area EA1, the second launch area EA2, and the third launch area EA3 can each have the following characteristics: Figure 7 and Figure 8 The quadrilateral or hexagonal shapes shown are not limited to the embodiments disclosed herein. In one or more embodiments, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may each independently have polygonal shapes, circular shapes, elliptical shapes, or atypical shapes other than quadrilateral and hexagonal shapes in a plan view.

[0099] like Figure 7As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0100] In one or more embodiments, such as Figure 8 As shown, the emission regions EA1, EA2, EA3, and EA4 can each have a hexagonal shape in the plan view. In this respect, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent in the second direction DR2. Furthermore, the first emission region EA1 and the second emission region EA2 can be adjacent in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second diagonal direction DD2. Additionally, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction positive (e.g., perpendicular) to the first diagonal direction DD1.

[0101] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. In one or more embodiments, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band. For example, the blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 370 nm to 460 nm, the green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 480 nm to 560 nm, and the red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 600 nm to 750 nm.

[0102] Each of the multiple pixels in PX can be like Figure 7 The diagram shows three launch zones: EA1, EA2, and EA3, or it can be as follows: Figure 8The diagram shows four emission regions: EA1, EA2, EA3, and EA4. In this respect, the fourth emission region EA4 can emit the same second beam as the second emission region EA2, but the embodiments disclosed herein are not limited thereto.

[0103] In one or more embodiments, the emission regions of a plurality of pixels PX can be arranged in a strip structure in which the emission regions are arranged in a first direction DR1, such as... Figure 8 The emission areas EA1, EA2, EA3, and EA4 shown are arranged in a diamond-shaped PenTile. ® The structure, or the hexagonal structure in which the emission area is arranged, is a hexagonal structure. (PenTile) ® It is an officially registered trademark of Samsung Display Co., Ltd.

[0104] Figure 9 It is shown along according to one or more embodiments. Figure 7 The schematic cross-sectional view of an example display panel shown is taken by line I1-I1'.

[0105] refer to Figure 9 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizer (POL).

[0106] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may include (e.g., a reference) Figure 5 The first transistor T1 to the sixth transistor T6 are described.

[0107] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type (type) impurity. Multiple well regions WA can be arranged on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type (type) impurity. The second type (type) impurity can be different from the first type (type) impurity. For example, in one or more embodiments, if the first type (type) impurity is a P-type impurity (e.g., when the first type (type) impurity is a P-type impurity), then the second type (type) impurity can be an N-type impurity. In one or more embodiments, if the first type (type) impurity is an N-type impurity (e.g., when the first type (type) impurity is an N-type impurity), then the second type (type) impurity can be a P-type impurity.

[0108] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0109] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0110] Each of the source region SA and drain region DA can be a region doped with a first type (species) impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on the third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0111] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. Due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased, thereby increasing the length of the channel region CH in each of the pixel transistors PTR.

[0112] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0113] Multiple contact terminals (CTEs) can be arranged on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can each be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them.

[0114] The third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed without being covered by the third semiconductor insulating film (SINS3).

[0115] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be independently made of silicon carbonitride (SiCN) or based on silicon oxide (SiO2). x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0116] In one or more embodiments, the semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In these embodiments, the thin-film transistors can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0117] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8, multiple through holes VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8 and VA9, and multiple interlayer insulating films INS1, INS2, INS3, INS4, INS5, INS6, INS7, INS8 and INS9.

[0118] Interlayer insulating films INS1 to INS9 are used to insulate first conductive layers ML1 to eighth conductive layers ML8. First conductive layers ML1 to eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 5 The circuit of the first sub-pixel SP1 shown.

[0119] For example, in one or more embodiments, the first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection between the first transistor T1 to the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region DA corresponding to the drain electrode of the fourth transistor T4, the source region SA corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0120] The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The first through-holes VA1 to VA8 can be made of substantially the same material. In one or more embodiments, the first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments of this disclosure are not limited thereto.

[0121] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. In one or more embodiments, the ninth interlayer insulating film INS9 can be made of silicon oxide (SiO2) based material. x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0122] Each of the ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or including any of them.

[0123] The display element layer (EML) can be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0124] The reflective electrode RL can be disposed on the ninth interlayer insulating film INS9. Each of the reflective electrodes RL may include at least one selected from reflective electrodes RL1, RL2, RL3, and RL4. For example, in one or more embodiments, such as Figure 9 As shown, each of the reflective electrodes RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0125] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth through-hole VA9. Each of the second reflective electrodes RL2 can be disposed on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be disposed on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be disposed on its corresponding third reflective electrode RL3.

[0126] Because the second reflective electrode RL2 is the electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0127] The first reflective electrode RL1 may be formed of an alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, in one or more embodiments, the first reflective electrode RL1 may comprise titanium nitride (TiN), the second reflective electrode RL2 may comprise aluminum (Al), the third reflective electrode RL3 may comprise titanium nitride (TiN), and the fourth reflective electrode RL4 may comprise titanium (Ti).

[0128] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to planarize the stepped portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0129] In one or more embodiments, the tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 may each be based on silicon oxide (SiO2). x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0130] The eleventh interlayer insulating film INS11 can be an optical auxiliary layer used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0131] For example, in one or more implementations, such as Figure 9 As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In this respect, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0132] Each of the tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and connect to the corresponding exposed fourth reflective electrode RL4. The tenth vias VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0133] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth via VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them. For example, in one or more embodiments, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0134] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a region of the light-emitting element (LE) comprising the first electrode AND, the light-emitting stack IL, and the second electrode CAT.

[0135] The first emitting region EA1 can be defined as the region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in a first sub-pixel SP1 to emit light. The second emitting region EA2 can be defined as the region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in a second sub-pixel SP2 to emit light. The third emitting region EA3 can be defined as the region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in a third sub-pixel SP3 to emit light.

[0136] A pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). In one or more embodiments, the first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). xIn one or more embodiments, the first pixel defining film PDL1 and the third pixel defining film PDL3 may be formed from an inorganic film based on silicon nitride (SiN). x The inorganic film is formed from silicon oxide (SiO2), while the second pixel defining film PDL2 can be formed from silicon oxide (SiO2). x The inorganic film is formed. In one or more embodiments, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of about 500 Å.

[0137] To reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the greater the possibility of the film being cut on the inclined portion.

[0138] Each of the plurality of trench TRCs may extend through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In one or more embodiments, the eleventh interlayer insulating film INS11 may be partially recessed at each of the plurality of trench TRCs.

[0139] At least one trench TRC can be arranged between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 Two trench TRCs are shown arranged between adjacent sub-pixels SP1, SP2 and SP3, but the embodiments of this disclosure are not limited thereto.

[0140] The light-emitting stacked ILs can include multiple stacked IL1, IL2 and IL3. Figure 9 The illustration shows a three-level cascaded structure of a light-emitting stack IL comprising a first stack IL1, a second stack IL2, and a third stack IL3; however, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, such as Figure 10 As shown, the light-emitting stack IL can have a secondary cascaded structure comprising two stacked layers.

[0141] In a three-stage cascaded structure, in one or more embodiments, the light-emitting stack IL may have a cascaded structure comprising multiple intermediate layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first stack IL1 configured to emit a first light, a second stack IL2 configured to emit a second light, and a third stack IL3 configured to emit a third light. The first stack IL1, the second stack IL2, and the third stack IL3 may be stacked sequentially (e.g., in the order stated).

[0142] The first stack IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer (e.g., in the stated order) are sequentially stacked. The second stack IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer (e.g., in the stated order) are sequentially stacked. The third stack IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer (e.g., in the stated order) are sequentially stacked.

[0143] In one or more embodiments, a first charge-generating layer for providing charge (e.g., holes) to the second stack IL2 and electrons to the first stack IL1 may be disposed between the first stack IL1 and the second stack IL2. The first charge-generating layer may include an N-type charge-generating layer that provides electrons to the first stack IL1 and a P-type charge-generating layer that provides holes to the second stack IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0144] A second charge-generating layer for providing charge (e.g., holes) to the third stack IL3 and electrons to the second stack IL2 may be disposed between the second stack IL2 and the third stack IL3. The second charge-generating layer may include an N-type charge-generating layer that provides electrons to the second stack IL2 and a P-type charge-generating layer that provides holes to the third stack IL3.

[0145] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and the residual film RIL disposed on the bottom surface of each trench TRC can include the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be disposed in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be arranged to cover the second stacked layer IL2 in each of the trench TRCs.

[0146] In a three-level cascaded structure, each of the multiple trench TRCs can be a structure for cutting off the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the display element layers EML between adjacent sub-pixels SP1, SP2, and SP3. Furthermore, in a two-level cascaded structure, each of the multiple trench TRCs can be a structure for cutting off the lower stack and the charge generation layer disposed between the lower and upper stacks.

[0147] To stably cut off the first stack IL1 and the second stack IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs on the third-direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL on the third-direction DR3. Different structures can exist to replace the trench TRCs in order to cut off the charge generation layer and hole transport layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. For example, in one or more embodiments, inverted conical partition walls can be arranged on the pixel defining film PDL instead of trench TRCs.

[0148] also, Figure 9 The illustration shows a light-emitting stack IL arranged in each of the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, instead of the light-emitting stack IL, the first light-emitting layer may be arranged in the first emission region EA1, and may not be arranged in the second emission regions EA2 and the third emission region EA3. Furthermore, the second light-emitting layer may be arranged in the second emission region EA2, and may not be arranged in the first emission region EA1 and the third emission region EA3. Additionally, the third light-emitting layer may be arranged in the third emission region EA3, and may not be arranged in the first emission region EA1 and the second emission region EA2. In these embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may not be provided.

[0149] The second electrode CAT can be disposed on the light-emitting stack IL. For example, the second electrode CAT can be disposed on the third stack IL3. In one or more embodiments, the second electrode CAT can be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity effect.

[0150] An encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film selected from TFE1 and TFE3 to prevent or reduce the permeation of oxygen and / or moisture into the display element layer EML. For example, the encapsulation layer TFE includes at least one inorganic film (such as TFE1 or TFE3) to prevent or reduce the permeation of oxygen and / or moisture into the display element layer EML. For example, in one or more embodiments, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE3. The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 may be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may each be independently formed from multiple layers, in which silicon nitride (SiN) materials are alternately stacked. x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium oxide (TiO) x ) layer and aluminum oxide (AlO) x One or more inorganic membranes within a layer.

[0151] Furthermore, the encapsulation layer TFE may include at least one encapsulation organic film TFE2 to protect the display element layer EML from impurities such as dust. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. In one or more embodiments, the encapsulation organic film TFE2 may be a monomer. In one or more embodiments, the encapsulation organic film TFE2 may be an organic film such as that formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0152] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Furthermore, the adhesive layer ADL can be a transparent adhesive component, such as a transparent adhesive or a transparent adhesive resin.

[0153] The optical layer (OPL) includes multiple color filters CF1, CF2, and CF3, multiple lenses (LNS), and a filler layer (FIL). The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may each be arranged on the adhesive layer (ADL).

[0154] The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, namely light in the blue wavelength band. The blue wavelength band can be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0155] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, namely light in the green wavelength band. The green wavelength band can be from approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0156] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color, namely light in the red wavelength band. The red wavelength band can be from approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0157] Multiple lenses LNS can be arranged on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed in front of the display device 20. In one or more embodiments, each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0158] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a set or predetermined refractive index, such that light travels in the third-direction DR3 at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can also be a planarization layer. The filler layer FIL can be an organic film, such as one formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0159] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. In one or more embodiments, when the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In these embodiments, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. In one or more embodiments, when the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0160] A polarizer (POL) can be disposed on (e.g., one) surface of a CVL (CVL) cover layer. The polarizer POL can be a structure used to reduce or prevent visibility reduction caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, in one or more embodiments, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. However, if the visibility reduction caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3 (e.g., when the visibility reduction caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3), a polarizer POL may not be provided.

[0161] Figure 10 This illustrates one or more embodiments of the present disclosure along... Figure 7 The schematic cross-sectional view of another example of a display panel, shown by line I1-I1'.

[0162] Figure 10 Implementation methods and Figure 9 The difference in the implementation is that the first electrode AND of each of the light-emitting elements LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation methods and Figure 9 The implementation differs further in that, instead of providing a trench TRC, it provides a third pixel defining film PDL3 and a fourth pixel defining film PDL4 with an eaves-shaped or mushroom-shaped cross-sectional structure. In the description... Figure 10 When implementing one or more of the embodiments, the existing ones will not be provided. Figure 9 Redundant descriptions of components described in one or more embodiments.

[0163] refer to Figure 10In one or more embodiments, a plurality of connection electrodes ANC may be disposed on a first portion AA1 of the ninth interlayer insulating film INS9. Each of the plurality of connection electrodes ANC may be disposed on a corresponding first portion AA1 of the ninth interlayer insulating film INS9. The plurality of connection electrodes ANC may be formed of an alloy or compound selected from any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or formed of a transparent conductive oxide. For example, in one or more embodiments, the plurality of connection electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto.

[0164] Multiple reflective electrodes RL can be arranged on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be arranged on its corresponding connecting electrode ANC. The multiple reflective electrodes RL can be formed of any one or an alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, in one or more embodiments, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity.

[0165] Multiple optical auxiliary films (OALs) can be disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on its corresponding reflective electrode (RL). In one or more embodiments, the multiple optical auxiliary films (OALs) can be made of silicon oxide (SiO2)-based materials. x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0166] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be disposed on the reflective electrode RL, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. The thickness of the optical auxiliary film OAL can be substantially the same in the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0167] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in each of the first emission region EA1 and the third emission region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be set taking into account the wavelength and resonant distance of the light emitted from the first stack IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stack IL2 of the light-emitting stack IL.

[0168] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0169] The first electrode AND of each of the light-emitting elements LE can be disposed on its corresponding optical auxiliary film OAL. Because the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each of the light-emitting elements LE can be disposed on the top and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Therefore, the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Thus, compared to when the first electrode AND of each of the light-emitting elements LE is connected to the reflective electrode RL exposed through a through-hole in the optical auxiliary film OAL, the number of masking processes can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0170] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connection electrode ANC, the first through hole VA1 to the ninth through hole VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0171] The ninth interlayer insulating film INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3 and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. In one or more embodiments, the thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same.

[0172] In one or more embodiments, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 may be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this respect, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 may be exposed, and the first electrode AND of each of the light-emitting elements LE may be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0173] The first electrode AND of each of the light-emitting elements LE can be formed of an alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or formed of a transparent conductive oxide. For example, in one or more embodiments, the first electrode AND of each of the light-emitting elements LE may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiments disclosed herein are not limited thereto.

[0174] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0175] The pixel-limiting film (PDL) may include a first pixel-limiting film (PDL1), a second pixel-limiting film (PDL2), a third pixel-limiting film (PDL3), and a fourth pixel-limiting film (PDL4).

[0176] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the light-emitting elements LE. For example, the first pixel defining film PDL1 can cover a portion of the top surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0177] The planarization film PNS is a film used to planarize the stepped portions caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0178] The planarization film PNS can be disposed on the first pixel defining film PDL1, which covers the side surface of the first electrode AND, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can also be disposed on the first pixel defining film PDL1, which is disposed on the second part AA2 of the ninth interlayer insulating film INS9.

[0179] The planarization film PNS can be disposed between adjacent connecting electrodes ANC on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL on the first direction DR1 or the second direction DR2.

[0180] The step layer STPL is not present in the second emission region EA2, but it is present in each of the first emission region EA1 and the third emission region EA3. Therefore, the heights of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emission region EA2 can be smaller than the heights of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the second emission region EA2.

[0181] Conversely, the top surface of the planarization film PNS can be flatly connected to the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the first emission region EA1 and the third emission region EA3. For example, the planarization film PNS may not cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in each of the first emission region EA1 and the third emission region EA3.

[0182] The second pixel defining film PDL2 can be disposed on the first pixel defining film PDL1 and the planarization film PNS, the third pixel defining film PDL3 can be disposed on the second pixel defining film PDL2, and the fourth pixel defining film PDL4 can be disposed on the third pixel defining film PDL3. In one or more embodiments, the first pixel defining film PDL1 and the third pixel defining film PDL3 can each be based on silicon nitride (SiN). x The inorganic film is formed, while the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS can each be based on silicon oxide (SiO2). xThe inorganic film is formed. The first pixel defining film PDL1 is formed of a material different from that of the planarization film PNS, and can therefore be used as a stop in the chemical mechanical polishing process for the planarization film PNS.

[0183] When both the planarization film PNS and the second pixel defining film PDL2 are formed (e.g., simultaneously) based on silicon oxide (SiO2) x When the inorganic film is formed, the planarization film PNS and the second pixel-defining film PDL2 can be formed as a single film.

[0184] Because the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, the bottom surface of the fourth pixel defining film PDL4 can be exposed and not covered by the third pixel defining film PDL3. For example, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have an eaves-shaped or mushroom-shaped cross-sectional structure.

[0185] The light-emitting stack IL can be disposed on the first electrode AND and the pixel defining film PDL. The light-emitting stack IL can include a first stack IL1 and a second stack IL2 that emit different lights. When the light-emitting stack IL has a two-level cascaded structure, one of the first stack IL1 and the second stack IL2 can emit light including a wavelength range selected from any one of a first light, a second light, and a third light, and the other can emit light including a wavelength range of the other two lights. For example, in one or more embodiments, the first stack IL1 can emit light including a wavelength range of the first light and a wavelength range of the third light, and the second stack IL2 can emit light including a wavelength range of the second light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band.

[0186] A charge-generating layer for providing charge (e.g., holes) to the second stack IL2 and electrons to the first stack IL1 may be disposed between the first stack IL1 and the second stack IL2. The charge-generating layer may include an N-type charge-generating layer that provides electrons to the first stack IL1 and a P-type charge-generating layer that provides holes to the second stack IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0187] The first stack IL1 is not formed on the exposed bottom surface of the fourth pixel defining film PDL4 that is not covered by the third pixel defining film PDL3, and therefore can be cut off by the eaves-shaped or mushroom-shaped cross-sectional structure of the third pixel defining film PDL3 and the fourth pixel defining film PDL4. At this point, the first hole transport layer of the first stack IL1 and the charge generation layer disposed between the first stack IL1 and the second stack IL2 can also be cut off. Furthermore, although... Figure 10 The second stack IL2 is shown to be connected without being disconnected. However, the second hole transport layer of the second stack IL2 can also be disconnected, and the second electron transport layer of the second stack IL2 can be connected without being disconnected. Therefore, leakage current can be prevented or reduced from flowing through the first hole transport layer of the first stack IL1, the second hole transport layer of the second stack IL2, and the charge generation layer between adjacent emitting regions EA1, EA2, and EA3. Therefore, the emission of light different from the initially expected light by the light-emitting stack IL in adjacent emitting regions EA1, EA2, and EA3 due to the influence of the above current can be prevented or reduced.

[0188] although Figure 10 The illustration shows a secondary cascaded structure in which the light-emitting stack IL comprises two stacked layers IL1 and IL2, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting stack IL may have, for example, a secondary cascaded structure in which the light-emitting stack IL comprises two stacked layers IL1 and IL2. Figure 9 The diagram shows a three-stage cascaded structure comprising three stacked layers. In these embodiments, it can be designed to cut off the charge-generating layers between the first stack IL1 and the second stack IL2, as well as between the second stack IL2 and the third stack IL3, by adjusting the height of the third pixel defining film PDL3. In one or more embodiments, as... Figure 9 As shown, a trench TRC can be added that penetrates the first pixel defining film PDL1, the planarization film PNS, the second pixel defining film PDL2, and the third pixel defining film PDL3. In these embodiments, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but the embodiments of this disclosure are not limited thereto.

[0189] Figure 11 This is a schematic perspective view illustrating an example of a head-mounted display according to one or more embodiments of the present disclosure. Figure 12 This illustrates one or more embodiments. Figure 11 The diagram shows a schematic exploded perspective view of the head-mounted display.

[0190] refer to Figure 11 and Figure 12 A head-mounted display 1000 according to one or more embodiments includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0191] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. This is because each of the first display device 20_1 and the second display device 20_2 is substantially combined with... Figures 3 to 10 Since the display devices 20 described are the same, no description of the first display device 20_1 and the second display device 20_2 will be provided.

[0192] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0193] The intermediate frame 1400 can be arranged between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0194] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert an externally input image source into digital video data DATA, and send the digital video data DATA to the first display device 20_1 and the second display device 20_2 via connectors.

[0195] In one or more embodiments, the control circuit board 1600 can send digital video data DATA corresponding to a left-eye image that is improved or optimized for the user's left eye to a first display device 20_1, and can send digital video data DATA corresponding to a right-eye image that is improved or optimized for the user's right eye to a second display device 20_2. In one or more embodiments, the control circuit board 1600 can send the same digital video data DATA to the first display device 20_1 and the second display device 20_2.

[0196] The display device housing 1100 is used to house a first display device 20_1, a second display device 20_2, an intermediate frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 11 and Figure 12The first eyepiece 1210 and the second eyepiece 1220 are shown arranged separately, but embodiments of this disclosure are not limited thereto. In one or more embodiments, the first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0197] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0198] A headband 1300 is used to secure the display device housing 1100 to a user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. In one or more embodiments, when the display device housing 1100 is implemented to be lightweight and compact, such as Figure 13 As shown, the head-mounted display 1000 may have an eyeglass frame instead of a headband 1300.

[0199] Figure 13 This is a schematic perspective view illustrating another example of a head-mounted display according to one or more embodiments of the present disclosure.

[0200] refer to Figure 13 The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path changing component 1070, and a display device housing 1200_1.

[0201] The display device housing 1200_1 may include a display device 20_3, an optical component 1060, and a light path changing component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image, a combination of a virtual image displayed on the display device 20_3 and a real image seen through the right eye lens 1020, through their right eye.

[0202] Figure 13The illustration shows the display device housing 1200_1 positioned at the right end of the support frame 1030, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in these embodiments, the image displayed on the display device 20_3 may be provided to the user's left eye. In one or more embodiments, the display device housing 1200_1 may be positioned (e.g., simultaneously) at both the left and right ends of the support frame 1030, and in these embodiments, the user may (e.g., simultaneously) view the image displayed on the display device 20_3 through both the left and right eyes.

[0203] Figure 14 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including the deposition mask according to one or more embodiments of the present disclosure.

[0204] refer to Figure 14 On display panel 100 (see Figure 6 In the manufacturing process of [the material], a light-emitting material layer can be formed on a backplane substrate 3000 using a deposition apparatus 2000. For example, multiple light-emitting layers can be formed on the substrate using a deposition mask 4000. For example, such as... Figure 9 As shown, a semiconductor backplane SBP and a light-emitting element backplane EBP can be disposed on a backplane substrate 3000, and a reflective electrode layer RL (i.e., reflective electrode RL) and insulating films INS10 and INS11 can be disposed on the light-emitting element backplane EBP. An electrode pattern (e.g., a first electrode AND serving as an anode electrode) and a pixel-defining film PDL exposing the first electrode AND can be disposed on an eleventh interlayer insulating film INS11, and the first electrode AND can be electrically connected to the reflective electrode layer RL through a via VA10. In one or more embodiments, the deposition apparatus 2000 can form a first light-emitting layer on the first electrode AND in a first emission region EA1. The deposition apparatus 2000 can form a second light-emitting layer on the first electrode AND in a second emission region EA2. Additionally, the deposition apparatus 2000 can form a third light-emitting layer on the first electrode AND in a third emission region EA3.

[0205] The deposition apparatus 2000 may include a deposition source 2200 for providing vapor deposition material onto a backplane substrate 3000, a substrate chuck 2300 supporting the backplane substrate 3000 facing the deposition source 2200, and a mask chuck 2400 disposed between the deposition source 2200 and the substrate chuck 2300 to support a deposition mask 4000 facing the backplane substrate 3000. The deposition source 2200, substrate chuck 2300, and mask chuck 2400 may be arranged in a processing chamber (or evaporation chamber) 2100.

[0206] Processing chamber 2100 may have an internal space, and the deposition process for forming a deposition material layer on backplane substrate 3000 can be performed within the internal space of processing chamber 2100. Processing chamber 2100 may be connected to a vacuum pump, and a vacuum atmosphere can be generated within the internal space of processing chamber 2100 by the vacuum pump. Openings for loading / unloading backplane substrate 3000 and deposition mask 4000 may be provided on one of the walls of processing chamber 2100, and the openings may be opened and closed by gate valves.

[0207] Deposition source 2200 can be arranged in processing chamber 2100, and deposition material can be stored in deposition source 2200. Deposition source 2200 can evaporate deposition material such as organic material, inorganic material, conductive material, etc., toward backplane substrate 3000, and the evaporated deposition material can be deposited on backplane substrate 3000 through deposition mask 4000. For example, deposition source 2200 can evaporate organic material for forming a light-emitting material layer on backplane substrate 3000, and a heater for evaporating organic material can be provided. The evaporated organic material can be deposited on electrode patterns on backplane substrate 3000 through (e.g., via) deposition mask 4000. Figure 14 As shown, in one or more embodiments, the deposition source 2200 may be arranged on the central portion of the bottom surface of the processing chamber 2100; however, in one or more embodiments, the deposition source 2200 may be configured to move horizontally by a separate actuator.

[0208] The substrate chuck 2300 may be disposed above the deposition source 2200 and may support the backplane substrate 3000 such that the backplane substrate 3000 faces the deposition source 2200. For example, in one or more embodiments, the substrate chuck 2300 may be an electrostatic chuck that uses electrostatic force to hold the rear surface of the backplane substrate 3000. For example, an electrode pattern (i.e., a first electrode AND) may be disposed on the front surface of the backplane substrate 3000, and the substrate chuck 2300 may hold the rear surface of the backplane substrate 3000 such that the front surface of the backplane substrate 3000 faces downward, i.e., towards the deposition source 2200.

[0209] Multiple lifting fingers 2350 for loading the backplane substrate 3000 onto the substrate chuck 2300 can be arranged in the processing chamber 2100. The lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved vertically by finger actuators 2360 respectively. For example, three or four lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400.

[0210] The backplane substrate 3000 can be loaded into the processing chamber 2100 by a transfer robot and transferred from the transfer robot to the lifting finger 2350 below the substrate chuck 2300. At this point, the rear surface of the backplane substrate 3000 can face the bottom surface of the substrate chuck 2300, and the lifting finger 2350 can support the leading edge portion of the backplane substrate 3000. The finger actuator 2360 can raise the lifting finger 2350, bringing the backplane substrate 3000 close to the bottom surface of the substrate chuck 2300, and the rear surface of the backplane substrate 3000 can be held on the bottom surface of the substrate chuck 2300 by electrostatic force.

[0211] Finger actuators 2360 can be disposed on the top cover of the processing chamber 2100 and can be connected to lifting fingers 2350 respectively via drive shafts 2362 extending vertically through the top cover of the processing chamber 2100. Finger actuators 2360 can vertically move lifting fingers 2350 to load or unload the backplane substrate 3000. Furthermore, finger actuators 2360 can rotate lifting fingers 2350 relative to their respective drive shafts 2362. For example, finger actuators 2360 can rotate lifting fingers 2350 such that the ends of lifting fingers 2350 do not overlap with the substrate chuck 2300 and the mask chuck 2400, thereby enabling vertical movement of lifting fingers 2350. Additionally, finger actuators 2360 can rotate lifting fingers 2350 such that the ends of lifting fingers 2350 overlap with the edge portion of the backplane substrate 3000 to support the edge portion of the backplane substrate 3000.

[0212] The deposition mask 4000 can be loaded into the processing chamber 2100 by a transfer robot and transferred to a lifting finger 2350 above the mask chuck 2400. An edge portion of the deposition mask 4000 can be positioned on the end of the lifting finger 2350, and a finger actuator 2360 can lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. At this point, a recess can be provided at the edge portion of the top surface of the mask chuck 2400 for inserting the end of the lifting finger 2350, and the finger actuator 2360 can rotate the lifting finger 2350 such that the lifting finger 2350 does not overlap with the mask chuck 2400 after the deposition mask 4000 has been loaded onto it.

[0213] The mask chuck 2400 can support the edge portion of the deposition mask 4000. For example, in one or more embodiments, the mask chuck 2400 can be an electrostatic chuck configured to use electrostatic forces to hold the edge portion of the deposition mask 4000. In one or more embodiments, the mask chuck 2400 can have a circular opening to expose the deposition mask 4000 toward the deposition source 2200. For example, the mask chuck 2400 can have a disk shape or a quadrilateral plate shape with a circular opening.

[0214] The deposition apparatus 2000 may include a substrate chuck driver 2500 for moving a substrate chuck 2300 and a mask chuck driver 2600 for moving a mask chuck 2400. For example, the substrate chuck driver 2500 may move the substrate chuck 2300 in a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplane substrate 3000. In this respect, the first direction DR1 may be a first horizontal direction, the second direction DR2 may be a second horizontal direction positive (e.g., perpendicular) to the first direction DR1, and the third direction DR3 may be a vertical direction. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0215] The substrate chuck driver 2500 can rotate the substrate chuck 2300 about the Z-axis to adjust the azimuth angle of the backplane substrate 3000. Furthermore, the substrate chuck driver 2500 can rotate the substrate chuck 2300 about the X-axis and about the Y-axis to adjust the tilt of the backplane substrate 3000. For example, the substrate chuck driver 2500 may include a hexapod actuator 2510 that provides motion in six degrees of freedom (X, Y, Z, θx, θy, and θz).

[0216] The substrate chuck driver 2500 may include a substrate stage 2520 on which a hexapod actuator 2510 is mounted, and a second actuator 2530 connected to the substrate stage 2520. The substrate stage 2520 may be arranged horizontally in the processing chamber 2100, and the second actuator 2530 may be arranged above the processing chamber 2100. The second actuator 2530 may be connected to the substrate stage 2520 via a plurality of drive shafts 2532 extending through the top cover of the processing chamber 2100 in a third direction DR3 (i.e., the vertical direction (Z-axis direction)), and may move the substrate stage 2520 in the direction of the central axis of the hexapod actuator 2510 (i.e., the vertical direction). For example, the second actuator 2530 may be configured to use a brushless DC motor, a linear motor, a direct drive (DD) motor, etc., and may adjust the height of the substrate chuck 2300 for loading or unloading the backplane substrate 3000.

[0217] The hexa-legged actuator 2510 may include a first platform connected to the substrate chuck 2300, a second platform mounted to the substrate stage 2520, and six sub-actuators arranged between the first and second platforms. For example, the six sub-actuators may each be configured to use a brushless DC motor, a voice coil linear motor, a stepper motor, a direct drive (DD) motor, a servo motor, etc., and may move and rotate the first platform to adjust the horizontal position, vertical position, azimuth angle, and tilt of the backplane substrate 3000.

[0218] The mask chuck driver 2600 can move and rotate the mask chuck 2400 to adjust the horizontal position and azimuth angle of the deposition mask 4000. The mask chuck driver 2600 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and rotate the mask chuck 2400 relative to its central axis. For example, the mask chuck driver 2600 can move the mask chuck 2400 in a first direction DR1 (X-axis) and a second direction DR2 (Y-axis), and can rotate the mask chuck 2400 relative to a third direction DR3 (Z-axis).

[0219] The mask chuck driver 2600 may include, for example, a piezoelectric actuator 2610 that provides motion in three degrees of freedom (X, Y, and θz). The piezoelectric actuator 2610 may have an opening communicating with a circular opening of the mask chuck 2400. The mask chuck 2400 may be arranged upwardly spaced from the piezoelectric actuator 2610 by a predetermined or set distance. For example, a plurality of support members 2612 may be arranged on the piezoelectric actuator 2610, and the mask chuck 2400 may be arranged on the plurality of support members 2612.

[0220] The mask chuck driver 2600 may include a mask stage 2620 horizontally arranged in the processing chamber 2100 and supporting the piezoelectric actuator 2610. For example, the mask stage 2620 may have an opening communicating with the opening of the piezoelectric actuator 2610 and may be supported by a plurality of pillars 2622 connected to the top cover of the processing chamber 2100.

[0221] After the backplane substrate 3000 and the deposition mask 4000 are mounted onto the substrate chuck 2300 and mask chuck 2400, respectively, the second actuator 2530 can lower the substrate chuck 2300 so that the backplane substrate 3000 is adjacent to the deposition mask 4000. The hexapod actuator 2510 can adjust the gap between the backplane substrate 3000 and the deposition mask 4000, and can adjust the tilt of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400. For example, in one or more embodiments, multiple gap sensors for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 can be mounted at the substrate chuck 2300, and the hexapod actuator 2510 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the measurements from the gap sensors.

[0222] Figure 15 This illustrates one or more embodiments according to this disclosure. Figure 14 A schematic bottom view of the backplate substrate shown.

[0223] refer to Figure 15The backplane substrate 3000 may include a plurality of display cell areas 3010 and a scribing area 3020 disposed between the display cell areas 3010. In one or more embodiments, such as Figure 15 As shown, the display cell area 3010 can be arranged in a matrix along the first direction DR1 and the second direction DR2, and can be individualized into the display panel 100 by a cutting process after the display manufacturing process is completed (see [reference]). Figure 3 For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction that is positive (e.g., perpendicular) to the first direction DR1. In one or more embodiments, each of the display cell areas 3010 can, for example, have a quadrilateral shape as shown in the figure.

[0224] For example, each of the display cell areas 3010 may include a semiconductor backplane SBP, a light-emitting element backplane EBP disposed on the semiconductor backplane SBP, a reflective electrode layer RL (i.e., reflective electrode RL) disposed on the light-emitting element backplane EBP, and a tenth interlayer insulating film INS10 disposed between adjacent reflective electrode layers RL and an eleventh interlayer insulating film INS11 disposed on the reflective electrode layer RL, such as Figure 9 As shown in the diagram. Furthermore, each of the display cell areas 3010 may include multiple electrode patterns (e.g., multiple first electrodes AND arranged on the eleventh interlayer insulating film INS11), and the first electrodes AND can be connected to the reflective electrode layer RL through multiple through-holes VA10, as shown in the diagram. Figure 9 As shown in the diagram. In this respect, the electrode pattern of the display cell area 3010 can be arranged on the front surface of the back substrate 3000, and the substrate chuck 2300 can hold the rear surface of the back substrate 3000 such that the electrode pattern of the display cell area 3010 faces downward, i.e., facing the deposition source 2200.

[0225] Figure 16 This illustrates one or more embodiments according to this disclosure. Figure 14 A schematic plan view of the deposition mask shown. Figure 17 This illustrates one or more embodiments. Figure 16 A schematic plan view of the mask cell area shown. Figure 18 It is along one or more embodiments Figure 17 The schematic cross-sectional view shown is taken by line I2-I2'.

[0226] refer to Figures 16 to 18The deposition mask 4000 may include mask cell regions 4210 corresponding to display cell regions 3010 of the backplane substrate 3000. Each of the mask cell regions 4210 may have a plurality of pixel openings 4212 that expose the first electrode AND in the deposition process. For example, the deposition mask 4000 may include a mask frame 4100 and a film 4200 disposed on the mask frame 4100. In this respect, the film 4200 may include a plurality of mask cell regions 4210, and each of the mask cell regions 4210 may have a plurality of pixel openings 4212.

[0227] For example, mask frame 4100 may have cell openings 4110 and include rib regions 4120 defining the cell openings 4110. Membrane 4200 may include mask cell regions 4210 respectively disposed on the cell openings 4110 and grid regions 4220 surrounding (e.g., around) the mask cell regions 4210. For example, the grid regions 4220 of membrane 4200 may be disposed on the rib regions 4120 of mask frame 4100.

[0228] Mask cell region 4210 can be exposed toward deposition source 2200 through cell opening 4110, and pixel opening 4212 can be formed to penetrate through mask cell region 4210. For example, pixel opening 4212 can communicate with cell opening 4110. In this respect, while performing the deposition process, vapor-deposited material provided from deposition source 2200 can be deposited on the first electrode AND of backplane substrate 3000 through cell opening 4110 and pixel opening 4212.

[0229] like Figure 16 As shown, in one or more embodiments, the mask cell region 4210 may be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the first direction DR1 may be a first horizontal direction, and the second direction DR2 may be a second horizontal direction that is positive (e.g., perpendicular) to the first direction DR1. In one or more embodiments, the mask cell region 4210 may, for example, have a quadrilateral shape as shown, and the pixel opening 4212 may be arranged to correspond to the first electrode AND of any one of the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0230] The mask frame 4100 can be made of single-crystal silicon. For example, in one or more embodiments, a single-crystal silicon substrate having a thickness in the range of about 700 micrometers (μm) to about 800 μm (e.g., about 775 μm) can be used as the mask frame 4100. The film 4200 can be made of silicon nitride (SiN). xIt is made of chemical vapor deposition (CVD) and can be formed to have a thickness of about 0.3 μm to about 3 μm (e.g., about 1 μm) by chemical vapor deposition (CVD) process.

[0231] Film 4200 can be disposed on the front surface of mask frame 4100, and rear inorganic film 4300 can be disposed on the rear surface of mask frame 4100. Rear inorganic film 4300 can be made of silicon nitride (SiN). x It can be made and formed by a CVD process. For example, membrane 4200 and post-inorganic membrane 4300 can be formed simultaneously (e.g., at the same time) by a CVD process. For example, the front inorganic membrane and post-inorganic membrane 4300 can be formed simultaneously (e.g., at the same time) on the front and rear surfaces of the mask frame 4100 by a CVD process, respectively, and the front inorganic membrane can be used as membrane 4200.

[0232] The pixel opening 4212 of the film 4200 can be formed by an anisotropic etching process. For example, after forming the exposed portion of the photoresist pattern in which the pixel opening 4212 is to be formed on the film 4200, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., reactive ion etching (RIE) process) to form the pixel opening 4212 through the film 4200.

[0233] The post-inorganic film 4300 may have a first post-opening 4310 corresponding to the cell opening 4110 of the mask frame 4100, and may be used as an etching mask in an etching process for forming the cell opening 4110 of the mask frame 4100. For example, after forming an exposed portion of a photoresist pattern on the post-inorganic film 4300 in which the first post-opening 4310 is to be formed, the photoresist pattern may be used as an etching mask to perform an anisotropic etching process (e.g., a RIE process) to form the first post-opening 4310 through the post-inorganic film 4300.

[0234] Cell openings 4110 of the mask frame 4100 can be formed by an anisotropic etching process using the inorganic film 4300 as an etching mask. For example, cell openings 4110 of the mask frame 4100 can be formed by performing a wet etching process using an etchant including tetramethylammonium hydroxide (TMAH; (CH3)4NOH) or potassium hydroxide (KOH). The wet etching process is performed until the film 4200 is exposed, such that pixel openings 4212 of the film 4200 can communicate with cell openings 4110 of the mask frame 4100.

[0235] According to one or more embodiments of this disclosure, the deposition mask 4000 may include mask alignment keys 4400 for alignment with the backplane substrate 3000 during the deposition process. For example, as Figure 16As shown, a plurality of mask alignment keys 4400 can be arranged on the edge portions of the deposition mask 4000, and as... Figure 15 As shown, the substrate alignment key 3030 corresponding to the mask alignment key 4400 can be arranged on the edge portion of the backplane substrate 3000. Figure 16 As shown, in one or more embodiments, the deposition mask 4000 may include four mask alignment keys 4400, but the number of mask alignment keys 4400 may vary, and therefore the scope of this disclosure is not limited by the number of mask alignment keys 4400.

[0236] Figure 19 This illustrates one or more embodiments according to this disclosure. Figure 16 A schematic cross-sectional view of the mask alignment key shown.

[0237] refer to Figure 16 and Figure 19 The membrane 4200 may include a mask region 4202 comprising a mask cell region 4210 and a grid region 4220, and an annular edge region 4204 surrounding (e.g., around) the mask region 4202. A mask alignment key 4400 may be disposed on a mask frame 4100. For example, in one or more embodiments, the mask alignment key 4400 may be disposed in the edge region 4204 of the membrane 4200, and the mask frame 4100 may have a key opening 4130 exposing the mask alignment key 4400 and portions of the membrane 4200 surrounding (e.g., around) the mask alignment key 4400. In this respect, the portion of the membrane 4200 exposed through the key opening 4130 may serve as a key region 4230.

[0238] For example, in one or more embodiments, the edge region 4204 of the film 4200 may include a plurality of bond regions 4230, and a plurality of mask alignment bonds 4400 may be respectively arranged in the bond regions 4230. Furthermore, the mask frame 4100 may have a plurality of bond openings 4130 respectively exposing the bond regions 4230, and the post-inorganic film 4300 may have a second post opening 4320 corresponding to the bond openings 4130 of the mask frame 4100. In this respect, the second post opening 4320 may be formed simultaneously (e.g., concurrently) with the first post opening 4310. For example, after forming the exposed portion of the photoresist pattern on the post-inorganic film 4300 in which the first post opening 4310 and the second post opening 4320 are to be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., RIE process) to form the first post opening 4310 and the second post opening 4320 through the post-inorganic film 4300.

[0239] The bond openings 4130 of the mask frame 4100 can be formed simultaneously (e.g., concurrently) with the cell openings 4110. For example, the cell openings 4110 and bond openings 4130 of the mask frame 4100 can be formed simultaneously (e.g., concurrently) by an anisotropic etching process using the inorganic film 4300 as an etching mask. For example, the cell openings 4110 and bond openings 4130 of the mask frame 4100 can be formed simultaneously (e.g., concurrently) by a wet etching process using an etchant containing TMAH ((CH3)4NOH) or potassium hydroxide (KOH). The wet etching process can be performed until the film 4200 is exposed, and therefore, the pixel openings 4212 of the film 4200 can communicate with the cell openings 4110 of the mask frame 4100, and the mask alignment bonds 4400 and bond regions 4230 of the film 4200 can be exposed through the bond openings 4130 of the mask frame 4100.

[0240] Return to reference Figure 14 The deposition apparatus 2000 may include a substrate alignment bond 3030 for detecting (see Figure 15 ) and mask alignment key 4400 (see Figure 16 The deposition apparatus 2000 may include four cameras 2700 for detecting substrate alignment bonds 3030 and mask alignment bonds 4400, for example, in one or more embodiments. In one or more embodiments, the backplane substrate 3000 and the deposition mask 4000 may each include two substrate alignment bonds 3030 and two mask alignment bonds 4400, and in these embodiments, the deposition apparatus 2000 may include two cameras 2700 for detecting the two substrate alignment bonds 3030 and the two mask alignment bonds 4400.

[0241] As described above, after adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 using the substrate chuck driver 2500, positional alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. Positional alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed based on the positional information of the substrate alignment key 3030 and the mask alignment key 4400 detected by the camera 2700.

[0242] Figure 20 This illustrates one or more embodiments according to this disclosure. Figure 14 A schematic cross-sectional view of the camera shown. Figure 21 This illustrates the use according to one or more embodiments. Figure 20 A schematic cross-sectional view of the method for detecting substrate alignment keys and mask alignment keys using a camera, as shown.

[0243] refer to Figure 20 and Figure 21A camera 2700 for detecting substrate alignment keys 3030 and mask alignment keys 4400 can be arranged on one side of the mask chuck 2400. Furthermore, an illumination unit 2720 for providing illumination light to the deposition mask 4000 and the backing substrate 3000 can be arranged on one side of the mask chuck 2400. The illumination light provided from the illumination unit 2720 can pass through the key regions 4230 of the deposition mask 4000 and illuminate the backing substrate 3000. For example, in one or more embodiments, the mask chuck 2400 can be provided with a through-hole 2410 for allowing illumination light to pass through it, and the deposition mask 4000 can be arranged on the mask chuck 2400 such that the key opening 4130 of the mask frame 4100 communicates with the through-hole 2410 of the mask chuck 2400.

[0244] Illumination light can be projected onto the bonding region 4230 of the film 4200 through the through-hole 2410 of the mask chuck 2400 and the bond opening 4130 of the mask frame 4100, and can pass through the bond region 4230 to illuminate the backplane substrate 3000. An optical unit 2710 for guiding the illumination light can be disposed below the mask chuck 2400. The optical unit 2710 can connect the illumination unit 2720 to the through-hole 2410 of the mask chuck 2400. For example, the illumination unit 2720 may include an illumination lamp, such as a halogen lamp or an LED lamp, for providing illumination light, and the optical unit 2710 may include a beam splitter 2712 and a reflector 2714 to guide the illumination light.

[0245] Beam splitter 2712 can transmit a portion of the illumination light provided from illumination unit 2720, and the illumination light passing through beam splitter 2712 can be reflected by reflector 2714 toward bond region 4230 of membrane 4200. For example... Figure 21 As shown, a portion of the illumination light reflected by reflector 2714 can illuminate the mask alignment key 4400, and another portion of the illumination light reflected by reflector 2714 can pass through the bonding region 4230 of the film 4200 and illuminate the back substrate 3000. At this point, the substrate alignment key 3030 on the back substrate 3000 can be arranged above the bonding region 4230 of the film 4200, and the camera 2700 can be connected to the optical unit 2710. The light reflected by the mask alignment key 4400 can be guided to the camera 2700 by reflector 2714 and beam splitter 2712, and the light reflected by the back substrate 3000 and substrate alignment key 3030 can pass through the bonding region 4230 of the film 4200 and then be guided to the camera 2700 by reflector 2714 and beam splitter 2712.

[0246] Camera 2700 can acquire image information, including position information of mask alignment key 4400 and substrate alignment key 3030, from light guided by reflector 2714 and beam splitter 2712. Substrate chuck driver 2500 or mask chuck driver 2600 can perform alignment between backplane substrate 3000 and deposition mask 4000 based on the image information acquired by camera 2700. For example, in one or more embodiments, hexapod actuator 2510 can adjust the position of substrate chuck 2300 based on the image information acquired by camera 2700, such that the electrode pattern on backplane substrate 300 is positioned above pixel opening 4212 of deposition mask 400. In one or more embodiments, piezoelectric actuator 2610 can adjust the position of mask chuck 2400 based on the image information acquired by camera 2700, such that the electrode pattern on backplane substrate 3000 is positioned above pixel opening 4212 of deposition mask 4000.

[0247] Return to reference Figure 19 In order to obtain more accurate positional information of the mask alignment key 4400, it is desirable and preferred that the mask alignment key 4400 has a relatively high light reflectivity. For example, in order to sufficiently increase the contrast between the image of the mask alignment key 4400 and the background image in the image information acquired by the camera 2700, it is desirable and preferred that the mask alignment key 4400 has a light reflectivity of about 0.5 or greater, which can significantly improve the recognition rate of the mask alignment key 4400.

[0248] According to one or more embodiments of this disclosure, the mask alignment key 4400 may have a structure in which a first inorganic film pattern 4412 and a second inorganic film pattern 4414 are alternately stacked. For example, the mask alignment key 4400 may include stacked bond pattern pairs 4410, and each of the bond pattern pairs 4410 may include stacked first inorganic film pattern 4412 and second inorganic film pattern 4414. The first inorganic film pattern 4412 may be made of silicon oxide (SiO2) having a refractive index of about 1.4. x The second inorganic film pattern 4414 can be made of silicon nitride (SiN) having a refractive index of about 1.9. xThe mask alignment bond 4400 is fabricated as follows: For example, each of the bond pattern pairs 4410 may include a first inorganic film pattern 4412 and a second inorganic film pattern 4414 disposed on the first inorganic film pattern 4412. For example, each of the bond pattern pairs 4410 may include a silicon oxide film pattern and a silicon nitride film pattern disposed on the silicon oxide film pattern. For example, in such an arrangement, the mask alignment bond 4400 is composed of alternating layers of silicon oxide film and silicon nitride film, thereby generating a multilayer structure. Each bond pattern pair 4410 consists of a layer of silicon oxide film (first inorganic film pattern 4412) followed by a layer of silicon nitride film (second inorganic film pattern 4414), and this sequence is repeated multiple times. This alternating stacking enhances the optical properties of the mask alignment bond 4400, such as its light reflectivity, which is crucial for improving recognition rate during the alignment process.

[0249] The light reflectivity of the mask alignment bond 4400 can be calculated using Snell's law and Fresnel's equation. For example, the light reflectivity of the mask alignment bond 4400 can vary depending on the thickness of the first inorganic film pattern 4412, the thickness of the second inorganic film pattern 4414, the number of bond pattern pairs 4410, and the wavelength of the illuminating light.

[0250] In one or more embodiments, the mask alignment key 4400 may include three to eleven or four to twelve first inorganic film patterns 4412 and three to eleven second inorganic film patterns 4414. According to one or more embodiments of this disclosure, if the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes three to six bond pattern pairs 4410 (e.g., when the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes three to six bond pattern pairs 4410), then the mask alignment key 4400 may have a light reflectance of about 0.5 or greater for illumination light having a wavelength of about 390 nm to about 440 nm. For example, in one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 413 nm is used (e.g., when the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 413 nm is used), then the mask alignment key 4400 comprising three to six bond pattern pairs 4410 may have a light reflectance of about 0.5 or greater. For example, the mask alignment key 4400 comprising four bond pattern pairs 4410 may have a light reflectance of about 0.61, and the mask alignment key 4400 comprising five bond pattern pairs 4410 may have a light reflectance of about 0.62.

[0251] In one or more embodiments, the number of first inorganic film patterns 4412 may be one more than the number of second inorganic film patterns 4414. For example, in one or more embodiments, the uppermost pattern of the mask alignment key 4400 may be the first inorganic film pattern 4412, and in these embodiments, the uppermost first inorganic film pattern 4412 may be used as a protective film pattern for the mask alignment key 4400. For example, the mask alignment key 4400 may include four to seven first inorganic film patterns 4412 and three to six second inorganic film patterns 4414.

[0252] According to one or more embodiments of this disclosure, if the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes four to eleven bond pattern pairs 4410 (e.g., when the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes four to eleven bond pattern pairs 4410), then the mask alignment key 4400 may have a light reflectance of about 0.5 or greater for illumination light having a wavelength of about 500 nm to about 560 nm. For example, in one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 530 nm is used (e.g., when the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 530 nm is used), then the mask alignment key 4400 comprising four to eleven bond pattern pairs 4410 may have a light reflectance of about 0.5 or greater. For example, the mask alignment key 4400 comprising six bond pattern pairs 4410 may have a light reflectance of about 0.65, and the mask alignment key 4400 comprising seven bond pattern pairs 4410 may have a light reflectance of about 0.68.

[0253] In one or more embodiments, the number of first inorganic film patterns 4412 may be one more than the number of second inorganic film patterns 4414. For example, the uppermost pattern of the mask alignment key 4400 may be the first inorganic film pattern 4412, and in these embodiments, the uppermost first inorganic film pattern 4412 may be used as a protective film pattern for the mask alignment key 4400. For example, the mask alignment key 4400 may include five to twelve first inorganic film patterns 4412 and four to eleven second inorganic film patterns 4414.

[0254] In one or more embodiments, the mask alignment key 4400 may include five to thirteen or six to fourteen first inorganic film patterns 4412 and five to thirteen second inorganic film patterns 4414. According to yet another embodiment of this disclosure, if the first inorganic film pattern 4412 has a thickness of about 40 nm to about 60 nm, the second inorganic film pattern 4414 has a thickness of about 90 nm to about 110 nm, and the mask alignment key 4400 includes five to thirteen bond pattern pairs 4410 (e.g., when the first inorganic film pattern 4412 has a thickness of about 40 nm to about 60 nm, the second inorganic film pattern 4414 has a thickness of about 90 nm to about 110 nm, and the mask alignment key 4400 includes five to thirteen bond pattern pairs 4410), then the mask alignment key 4400 may have a light reflectance of about 0.5 or greater for illumination light having a wavelength of about 500 nm to about 560 nm. For example, in one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 50 nm, the second inorganic film pattern 4414 has a thickness of about 100 nm, and illumination light with a wavelength of about 530 nm is used (e.g., when the first inorganic film pattern 4412 has a thickness of about 50 nm, the second inorganic film pattern 4414 has a thickness of about 100 nm, and illumination light with a wavelength of about 530 nm is used), then the mask alignment key 4400 comprising five to thirteen bond pattern pairs 4410 may have a light reflectance of about 0.5 or greater. For example, the mask alignment key 4400 comprising eleven bond pattern pairs 4410 may have a light reflectance of about 0.98.

[0255] In one or more embodiments, the number of first inorganic film patterns 4412 may be one more than the number of second inorganic film patterns 4414. For example, the uppermost pattern of the mask alignment key 4400 may be the first inorganic film pattern 4412, and in these embodiments, the uppermost first inorganic film pattern 4412 may be used as a protective film pattern for the mask alignment key 4400. For example, the mask alignment key 4400 may include six to fourteen first inorganic film patterns 4412 and five to thirteen second inorganic film patterns 4414.

[0256] Return to reference Figure 14After aligning the backplane substrate 3000 and the deposition mask 4000 as described above, the hexapod actuator 2510 can position the backplane substrate 3000 onto the deposition mask 4000. For example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 so that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes a preset gap, such as a gap of several μm. In another example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 so that the backplane substrate 3000 is in close contact with the deposition mask 4000. Subsequently, the deposition source 2200 can provide vapor-phase deposition material (e.g., vapor-phase organic material) toward the deposition mask 4000, and the vapor-phase deposition material can be deposited on the backplane substrate 3000 through the pixel openings 4212 of the deposition mask 4000.

[0257] According to one or more embodiments of this disclosure, the mask alignment key 4400 may have the same thickness as the film 4200, and therefore, the deposition mask 4000 may have a flat top surface. As a result, if the backplane substrate 3000 is positioned above the deposition mask 4000 (e.g., when the backplane substrate 3000 is positioned above the deposition mask 4000), the gap between the backplane substrate 3000 and the deposition mask 4000 can become substantially uniform. Therefore, the pixel positioning accuracy (PPA) of the organic light-emitting layer formed on the backplane substrate 3000 can be improved, and the size and thickness of the organic light-emitting layer can become substantially uniform.

[0258] Figure 22 This is a cross-sectional view showing a deposition mask according to one or more embodiments of the present disclosure.

[0259] refer to Figure 22 A deposition mask 4000 according to one or more embodiments of the present disclosure may include a mask frame 4100, a film 4200, a post-inorganic film 4300, and a mask alignment key 4400. The mask frame 4100 may have a plurality of cell openings 4110 and may include rib regions 4120 defining the cell openings 4110 (see [link to documentation]). Figure 18 The membrane 4200 may include mask cell regions 4210 respectively arranged on cell openings 4110 and grid regions 4220 defining mask cell regions 4210 (see [link to relevant documentation]). Figure 18 The grid area 4220 of the membrane 4200 can be arranged on the rib area 4120 of the mask frame 4100, and each of the mask cell area 4210 of the membrane 4200 can have multiple pixel openings 4212.

[0260] Membrane 4200 may include a mask region 4202 comprising a mask cell region 4210 and a grid region 4220 (see [link to mask region]). Figure 16) and the annular edge region 4204 surrounding (e.g., around) the mask region 4202 (see Figure 16 The mask frame 4100 may have key openings 4130 that expose portions of the edge regions 4204 of the membrane 4200. In this respect, the edge portions of the membrane 4200 exposed through the key openings 4130 may serve as key regions 4230, and mask alignment keys 4400 may be arranged on the key regions 4230 of the membrane 4200, respectively. For example, each exposed portion of the membrane 4200 through the key openings 4130 may serve as a key region 4230, and mask alignment keys 4400 may be arranged on the key regions 4230.

[0261] Mask alignment key 4400 may include stacked key pattern pairs 4410 (see...) Figure 19 Furthermore, each of the bond pattern pairs 4410 may include a stacked first inorganic film pattern 4412 and a second inorganic film pattern 4414. Except that the mask alignment bonds 4400 are arranged on the bond regions 4230 of the film 4200, the deposition mask 4000 according to this embodiment is consistent with the above-referenced... Figures 16 to 19 The descriptions are essentially the same, and therefore their additional detailed descriptions will not be repeated.

[0262] Figure 23 This is a schematic plan view showing a deposition mask according to one or more embodiments of the present disclosure. Figure 24 This illustrates one or more embodiments. Figure 23 A schematic cross-sectional view of the mask alignment key and spacer shown.

[0263] refer to Figure 23 and Figure 24 A deposition mask 4000 according to one or more embodiments of the present disclosure may include a mask frame 4100, a film 4200, a post-inorganic film 4300, a mask alignment key 4400, and a dummy key 4450. The mask frame 4100 may have a plurality of cell openings 4110 (see [link to documentation]). Figure 18 ), and may include a rib region 4120 that defines the cell opening 4110 (see Figure 18 The membrane 4200 may include mask cell regions 4210 respectively arranged on cell openings 4110 and grid regions 4220 defining the mask cell regions 4210. The grid regions 4220 of the membrane 4200 may be arranged on the rib regions 4120 of the mask frame 4100, and each of the mask cell regions 4210 of the membrane 4200 may have multiple pixel openings 4212 (see...). Figure 18 ).

[0264] The membrane 4200 may include a mask region 4202 comprising a mask cell region 4210 and a grid region 4220, and an annular edge region 4204 surrounding (e.g., around) the mask region 4202. The mask frame 4100 may have a plurality of key openings 4130, and portions of the membrane 4200 exposed through the key openings 4130 may be used as key regions 4230. Furthermore, mask alignment keys 4400 may be arranged on the key regions 4230. In this embodiment, except for the dummy key 4450, the remaining elements are the same as those referenced above. Figure 22 The descriptions are essentially the same, and therefore will not be repeated or additional descriptions will be provided.

[0265] According to one or more embodiments, the deposition mask 4000 may include a plurality of dummy bonds 4450. If the backplane substrate 3000 is positioned above the deposition mask 4000 (e.g., when the backplane substrate 3000 is positioned above the deposition mask 4000), the dummy bonds 4450 may be used to maintain a substantially uniform gap between the backplane substrate 3000 and the deposition mask 4000. For example, the dummy bonds 4450 may serve as spacers for maintaining a substantially uniform gap between the backplane substrate 3000 and the deposition mask 4000. For example, a plurality of dummy bonds 4450 may be arranged on the grid region 4220 of the film 4200, and each of the dummy bonds 4450 may have the same thickness as the mask alignment bond 4400. Furthermore, the dummy bonds 4450 may be formed synchronously (e.g., simultaneously) with the mask alignment bond 4400, and therefore may have the same stacking structure as the mask alignment bond 4400. For example, each of the dummy keys 4450 may include multiple key pattern pairs, and each key pattern pair may include a first inorganic film pattern and a second inorganic film pattern disposed on the first inorganic film pattern.

[0266] Figure 25 This is a schematic cross-sectional view showing a deposition mask according to one or more embodiments of the present disclosure.

[0267] refer to Figure 25 A deposition mask 4000 according to one or more embodiments of the present disclosure may include a mask frame 4100, a film 4200, a post-inorganic film 4300, a mask alignment key 4400, and a dummy key 4450. The mask frame 4100 may have a plurality of cell openings 4110 (see [link to documentation]). Figure 18 ), and may include a rib region 4120 that defines the cell opening 4110 (see Figure 18 The membrane 4200 may include mask cell regions 4210 respectively arranged on cell openings 4110 (see...). Figure 18 ) and the grid area 4220 that defines the mask cell area 4210 (see Figure 18The grid area 4220 of the membrane 4200 can be arranged on the rib area 4120 of the mask frame 4100, and each of the mask cell areas 4210 of the membrane 4200 can have multiple pixel openings 4212 (see...). Figure 18 ).

[0268] Membrane 4200 may include a mask region 4202 comprising a mask cell region 4210 and a grid region 4220 (see [link to mask region]). Figure 16 ) and the annular edge region 4204 surrounding (e.g., around) the mask region 4202 (see Figure 16 The mask frame 4100 may have multiple key openings 4130, and the portions of the membrane 4200 exposed through the key openings 4130 may be used as key regions 4230 respectively. Furthermore, mask alignment keys 4400 may be arranged in the key regions 4230 and exposed through the key openings 4130 of the mask frame 4100. In this embodiment, except for the dummy key 4450, the remaining elements are the same as those referenced above. Figures 16 to 19 The descriptions are essentially the same, and therefore will not be repeated or additional descriptions will be provided.

[0269] According to one or more embodiments, the deposition mask 4000 may include a mask alignment key 4400 and a plurality of dummy keys 4450. The mask alignment key 4400 and dummy keys 4450 may be disposed on a mask frame 4100, and a film 4200 may be disposed on the mask alignment key 4400, the dummy keys 4450, and the mask frame 4100. For example, in one or more embodiments, the dummy key 4450 may be disposed on a rib region 4120 of the mask frame 4100. For example, the film 4200 may include a first protrusion 4240 disposed on the mask alignment key 4400 and a second protrusion 4242 disposed on the dummy keys 4450. In this respect, if the backplane substrate 3000 is positioned above the deposition mask 4000 (e.g., when the backplane substrate 3000 is positioned above the deposition mask 4000), the first protrusion 4240 and the second protrusion 4242 of the film 4200 can be used as spacers to maintain a substantially uniform gap between the backplane substrate 3000 and the deposition mask 4000.

[0270] For example, multiple dummy bonds 4450 can be arranged on the rib region 4120 of the mask frame 4100, and each of the dummy bonds 4450 can have the same thickness as the mask alignment bond 4400. Therefore, the first protrusion 4240 formed on the mask alignment bond 4400 and the second protrusion 4242 formed on the dummy bond 4450 can have the same height, thereby ensuring that the gap between the backplane substrate 3000 and the deposition mask 4000 remains uniform (e.g., substantially uniform). Furthermore, the dummy bonds 4450 can be formed synchronously (e.g., simultaneously) with the mask alignment bond 4400, and therefore can have the same stacking structure as the mask alignment bond 4400. For example, each of the dummy bonds 4450 can include multiple bond pattern pairs, and each of the bond pattern pairs can include a first inorganic film pattern and a second inorganic film pattern disposed on the first inorganic film pattern.

[0271] Figures 26 to 32 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to one or more embodiments of the present disclosure.

[0272] refer to Figure 26 A multilayer inorganic film 4010 can be formed on the mask substrate 4002. The mask substrate 4002 can be made of single-crystal silicon. For example, in one or more embodiments, a single-crystal silicon substrate having a thickness of about 700 μm to about 800 μm (e.g., about 775 μm) can be used as the mask substrate 4002 and can be used as the mask frame 4100 for depositing the mask 4000 (see [link]). Figure 18 ).

[0273] The multilayer inorganic film 4010 may have a structure in which a first inorganic film 4022 and a second inorganic film 4024 are alternately stacked. For example, the multilayer inorganic film 4010 may include stacked inorganic film pairs 4020, and each of the inorganic film pairs 4020 may include a first inorganic film 4022 and a second inorganic film 4024. For example, the multilayer inorganic film 4010 may include a plurality of first inorganic films 4022 and a plurality of second inorganic films 4024, and the first inorganic films 4022 and the second inorganic films 4024 may be alternately stacked on a mask substrate 4002. In one or more embodiments, the first inorganic film 4022 may be made of silicon oxide (SiO2). x The second inorganic film 4024 can be made of silicon nitride (SiN). xThe inorganic film 4010 is fabricated using alternating layers of silicon oxide and silicon nitride films. For example, in this arrangement, the multilayer inorganic film 4010 is composed of alternating layers of silicon oxide and silicon nitride films, thus creating a multilayer structure. Each inorganic film pair 4020 consists of a silicon oxide film (first inorganic film 4022) followed by a silicon nitride film (second inorganic film 4024), and this sequence is repeated multiple times. This alternating stacking enhances the optical properties of the multilayer inorganic film 4010, such as its light reflectivity and durability, which is crucial for improving the performance and reliability of the mask substrate 4002.

[0274] For example, in one or more embodiments, a multilayer inorganic film 4010 can be formed on the front surface of a mask substrate 4002 using a CVD process. For instance, a first source gas containing silicon, such as monosilane (SiH4), disilane (Si2H6), or dichlorosilane (DCS) (SiH2Cl2), and a second source gas containing oxygen, such as O2, CO2, NO, or N2O, can be supplied to the mask substrate 4002, and a silicon oxide film serving as a first inorganic film 4022 can be formed through a reaction between the first and second source gases. Subsequently, the first source gas and a third source gas containing nitrogen, such as N2 or NH3, can be supplied to the first inorganic film 4022, and a silicon nitride film serving as a second inorganic film 4024 can be formed through a reaction between the first and third source gases.

[0275] For example, in one or more embodiments, the first inorganic film 4022 may be formed having a thickness of about 90 nm to about 110 nm, the second inorganic film 4024 may be formed having a thickness of about 40 nm to about 60 nm, and the multilayer inorganic film 4010 may be formed comprising three to eleven pairs of inorganic film 4020. In this respect, a multilayer inorganic film 4010 comprising three to six pairs of inorganic film 4020 may have a light reflectance of about 0.5 or greater for light with wavelengths of about 390 nm to about 440 nm, and a multilayer inorganic film 4010 comprising four to eleven pairs of inorganic film 4020 may have a light reflectance of about 0.5 or greater for light with wavelengths of about 500 nm to about 560 nm.

[0276] In one or more embodiments, the uppermost inorganic film of the multilayer inorganic film 4010 may be a first inorganic film 4022. For example, the number of first inorganic films 4022 may be one more than the number of second inorganic films 4024. In one or more embodiments, if the first inorganic film 4022 has a thickness of about 90 nm to about 110 nm and the second inorganic film 4024 has a thickness of about 40 nm to about 60 nm (e.g., when the first inorganic film 4022 has a thickness of about 90 nm to about 110 nm and the second inorganic film 4024 has a thickness of about 40 nm to about 60 nm), then the multilayer inorganic film 4010 may include four to twelve first inorganic films 4022 and three to eleven second inorganic films 4024.

[0277] In one or more embodiments, the first inorganic film 4022 may be formed having a thickness of about 40 nm to about 60 nm, the second inorganic film 4024 may be formed having a thickness of about 90 nm to about 110 nm, and the multilayer inorganic film 4010 may be formed comprising five to thirteen pairs of inorganic films 4020. In these embodiments, the multilayer inorganic film 4010 may have a light reflectance of about 0.5 or greater for light with a wavelength of about 500 nm to about 560 nm.

[0278] In one or more embodiments, the uppermost inorganic film of the multilayer inorganic film 4010 may be a first inorganic film 4022. For example, the number of first inorganic films 4022 may be one more than the number of second inorganic films 4024. In one or more embodiments, if the first inorganic film 4022 has a thickness of about 40 nm to about 60 nm and the second inorganic film 4024 has a thickness of about 90 nm to about 110 nm (e.g., when the first inorganic film 4022 has a thickness of about 40 nm to about 60 nm and the second inorganic film 4024 has a thickness of about 90 nm to about 110 nm), then the multilayer inorganic film 4010 may include six to fourteen first inorganic films 4022 and five to thirteen second inorganic films 4024.

[0279] refer to Figure 27 A multilayer inorganic film 4010 can be patterned to form mask alignment bonds 4400 on a mask substrate 4002. The mask alignment bonds 4400 can be formed on edge portions of the mask substrate 4002. For example, two or four mask alignment bonds 4400 can be formed on edge portions of the mask substrate 4002. However, because the number of mask alignment bonds 4400 can vary, the scope of this disclosure is not limited thereto.

[0280] For example, after forming a photoresist pattern on the multilayer inorganic film 4010 to expose areas other than the portion where the mask alignment bonds 4400 are to be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., RIE process) to form the mask alignment bonds 4400 on the mask substrate 4002. The RIE process can be performed using a first reactant gas containing fluorine such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc., a second reactant gas containing oxygen such as O2, NO, NO2, etc., and sputtering gases such as He, Ne, Ar, Xe, etc., until the front surface of the mask substrate 4002 is exposed.

[0281] The mask alignment bond 4400 may have a structure in which a first inorganic film pattern 4412 and a second inorganic film pattern 4414 are alternately stacked. For example, each of the mask alignment bonds 4400 may include stacked bond pattern pairs 4410, and each of the bond pattern pairs 4410 may include stacked first inorganic film pattern 4412 and second inorganic film pattern 4414. The first inorganic film pattern 4412 may be a silicon oxide film pattern formed from a first inorganic film 4022, and the second inorganic film pattern 4414 may be a silicon nitride film pattern formed from a second inorganic film 4024. For example, the mask alignment bond 4400 may be formed to have a light reflectance of about 0.5 or greater. For example, in such an arrangement, the mask alignment bond 4400 is composed of alternating layers of silicon oxide film and silicon nitride film, thereby generating a multilayer structure. Each pair of alignment keys 4410 consists of a silicon oxide film (first inorganic film pattern 4412) followed by a silicon nitride film (second inorganic film pattern 4414), and this sequence is repeated multiple times. This alternating stacking enhances the optical properties of the mask alignment keys 4400, such as their light reflectivity, which is crucial for improving recognition rates during the alignment process. Specifically, the mask alignment keys 4400 are designed to have a light reflectivity of approximately 0.5 or greater, ensuring that they are easily detected by the alignment system, thereby facilitating precise positioning and improving the overall performance of the electronic device.

[0282] According to one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes three to six bond pattern pairs 4410 (e.g., when the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes three to six bond pattern pairs 4410), then the mask alignment key 4400 may have a light reflectance of about 0.5 or greater for illumination light having a wavelength of about 390 nm to about 440 nm. For example, if the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 413 nm is used (e.g., when the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 413 nm is used), then the mask alignment bond 4400 comprising three to six bond pattern pairs 4410 may have a light reflectance of about 0.5 or greater.

[0283] In one or more embodiments, the number of first inorganic film patterns 4412 may be one more than the number of second inorganic film patterns 4414. For example, the uppermost pattern of the mask alignment key 4400 may be the first inorganic film pattern 4412, and in this respect, the uppermost first inorganic film pattern 4412 may serve as a protective film pattern for the mask alignment key 4400. For example, in one or more embodiments, the mask alignment key 4400 may include four to seven first inorganic film patterns 4412 and three to six second inorganic film patterns 4414.

[0284] According to one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes four to eleven bond pattern pairs 4410 (for example, when the first inorganic film pattern 4412 has a thickness of about 90 nm to about 110 nm, the second inorganic film pattern 4414 has a thickness of about 40 nm to about 60 nm, and the mask alignment key 4400 includes four to eleven bond pattern pairs 4410), then the mask alignment key 4400 may have a light reflectance of about 0.5 or greater for illumination light having a wavelength of about 500 nm to about 560 nm. For example, in one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 530 nm is used (e.g., when the first inorganic film pattern 4412 has a thickness of about 100 nm, the second inorganic film pattern 4414 has a thickness of about 50 nm, and illumination light with a wavelength of about 530 nm is used), then the mask alignment key 4400 comprising four to eleven bond pattern pairs 4410 may have a light reflectivity of about 0.5 or greater.

[0285] In one or more embodiments, the number of first inorganic film patterns 4412 may be one more than the number of second inorganic film patterns 4414. For example, the uppermost pattern of the mask alignment key 4400 may be the first inorganic film pattern 4412, and in this respect, the uppermost first inorganic film pattern 4412 may serve as a protective film pattern for the mask alignment key 4400. For example, in one or more embodiments, the mask alignment key 4400 may include five to twelve first inorganic film patterns 4412 and four to eleven second inorganic film patterns 4414.

[0286] According to one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 40 nm to about 60 nm, the second inorganic film pattern 4414 has a thickness of about 90 nm to about 110 nm, and the mask alignment key 4400 includes five to thirteen bond pattern pairs 4410 (for example, when the first inorganic film pattern 4412 has a thickness of about 40 nm to about 60 nm, the second inorganic film pattern 4414 has a thickness of about 90 nm to about 110 nm, and the mask alignment key 4400 includes five to thirteen bond pattern pairs 4410), then the mask alignment key 4400 may have a light reflectance of about 0.5 or greater for illumination light having a wavelength of about 500 nm to about 560 nm. For example, in one or more embodiments, if the first inorganic film pattern 4412 has a thickness of about 50 nm, the second inorganic film pattern 4414 has a thickness of about 100 nm, and illumination light with a wavelength of about 530 nm is used (e.g., when the first inorganic film pattern 4412 has a thickness of about 50 nm, the second inorganic film pattern 4414 has a thickness of about 100 nm, and illumination light with a wavelength of about 530 nm is used), then the mask alignment key 4400 comprising five to thirteen bond pattern pairs 4410 may have a light reflectance of about 0.5 or greater.

[0287] In one or more embodiments, the number of first inorganic film patterns 4412 may be one more than the number of second inorganic film patterns 4414. For example, the uppermost pattern of the mask alignment key 4400 may be the first inorganic film pattern 4412, and in this respect, the uppermost first inorganic film pattern 4412 may serve as a protective film pattern for the mask alignment key 4400. For example, in one or more embodiments, the mask alignment key 4400 may include six to fourteen first inorganic film patterns 4412 and five to thirteen second inorganic film patterns 4414.

[0288] refer to Figure 28 A film 4200 can be formed on the mask substrate 4002 and the mask alignment bond 4400. For example, in one or more embodiments, the film 4200 may comprise silicon nitride (SiN). x And it can be formed by CVD process. For example, a silicon source gas such as monosilane (SiH4), disilane (Si2H6) or dichlorosilane (DCS) (SiH2Cl2) and a nitrogen source gas such as N2 or NH3 can be supplied to the mask substrate 4002, and a film 4200 with a thickness of about 0.3 μm to about 3 μm can be formed by the reaction between the silicon source gas and the nitrogen source gas.

[0289] According to this embodiment, the membrane 4200 may be made of silicon-rich silicon nitride to reduce residual stress. For example, in one or more embodiments, the membrane 4200 may be formed to have a residual stress of about 500 MPa or less, and the ratio of silicon content (e.g., amount) to nitrogen content (e.g., amount) in the membrane 4200 may be about 0.8 to about 1.2.

[0290] A film 4200 can be formed on the front surface of the mask substrate 4002, and a rear inorganic film 4300 can be formed on the rear surface of the mask substrate 4002. The rear inorganic film 4300 can be made of silicon nitride (SiN). x It can be made and formed by a CVD process. For example, the front inorganic film 4200 and the back inorganic film 4300 can be formed simultaneously (e.g., concurrently) by a CVD process. For example, by a CVD process, the front inorganic film and the back inorganic film 4300 can be formed simultaneously (e.g., concurrently) on the front and back surfaces of the mask substrate 4002, respectively, and the front inorganic film can be used as film 4200.

[0291] refer to Figure 29 In one or more embodiments, a portion of the pre-inorganic film formed on the mask alignment key 4400, namely the first protrusion 4240 of the film 4200 (see...) can be removed. Figure 28 For example, the first protrusion 4240 of the film 4200 formed on the mask alignment key 4400 can be removed by a chemical mechanical polishing (CMP) process. In these embodiments, the film 4200 can be formed to have the same thickness as or greater than the mask alignment key 4400, and the CMP process can be performed until the mask alignment key 4400 is exposed. As a result, the thickness of the film 4200 can be made equal to the thickness of the mask alignment key 4400 by the CMP process.

[0292] refer to Figure 30 The film 4200 can be patterned to form a plurality of pixel openings 4212 exposing the front portion of the mask substrate 4002. For example, after forming a photoresist pattern on the film 4200 to expose the portion where the pixel openings 4212 are to be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., RIE process) to form the pixel openings 4212 exposing the front portion of the mask substrate 4002. The RIE process can be performed using a first reactant gas containing fluorine such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc., a second reactant gas containing oxygen such as O2, NO, NO2, etc., and sputtering gases such as He, Ne, Ar, Xe, etc., until the front surface of the mask substrate 4002 is exposed.

[0293] According to one or more embodiments of this disclosure, a structure such as... can be formed on the mask substrate 4002. Figure 25 The diagram shows multiple dummy bonds 4450. For example, the dummy bonds 4450 can be formed from a multilayer inorganic film 4010. For example, by patterning the multilayer inorganic film 4010, the dummy bonds 4450 can be formed simultaneously (e.g., concurrently) with the mask alignment bonds 4400. For example, after forming a photoresist pattern on the multilayer inorganic film 4010 that exposes areas other than the portions where the mask alignment bonds 4400 and dummy bonds 4450 are to be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., a RIE process) to form the mask alignment bonds 4400 and dummy bonds 4450 on the mask substrate 4002. In these embodiments, the film 4200 can be formed on the front surface of the mask substrate 4002, the mask alignment bonds 4400, and the dummy bonds 4450, and a CMP process for removing the first protrusion 4240 of the film 4200 may not be provided. Furthermore, the portion of the pre-inorganic film formed on the mask alignment bond 4400 and the portion of the pre-inorganic film formed on the dummy bond 4450 (i.e., as...) Figure 25 The first protrusion 4240 and the second protrusion 4242 of the film 4200 shown can be retained instead of being removed and can be used as spacers to maintain a substantially uniform gap between the backing substrate 3000 and the deposition mask 4000.

[0294] refer to Figure 31 and Figure 32 A mask frame 4100 can be formed from a mask substrate 4002 by patterning the mask substrate 4002. For example, the mask substrate 4002 can be patterned to form a mask frame 4100 having a cell opening 4110 communicating with a pixel opening 4212 and a bond opening 4130 exposing a mask alignment bond 4400. For example, after forming a photoresist pattern on the back inorganic film 4300 to expose the portions to which the first back opening 4310 and the second back opening 4320 will be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., RIE process) to form the first back opening 4310 and the second back opening 4320 exposing the back portions of the mask substrate 4002, as shown. Figure 31 As shown, a RIE process for forming the first back opening 4310 and the second back opening 4320 can be performed using a first reactant gas containing fluorine, such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc., a second reactant gas containing oxygen, such as O2, NO, NO2, etc., and sputtering gases such as He, Ne, Ar, Xe, etc., until the back surface of the mask substrate 4002 is exposed.

[0295] After the first rear opening 4310 and the second rear opening 4320 are formed, as Figure 32 As shown, cell openings 4110 communicating with pixel openings 4212 and bond openings 4130 exposing mask alignment bonds 4400 can be formed. For example, cell openings 4110 and bond openings 4130 can be formed using a wet etching process using an etchant containing TMAH ((CH3)4NOH) or potassium hydroxide (KOH). The wet etching process can be performed until the film 4200 is exposed, thereby allowing the pixel openings 4212 of the film 4200 to communicate with the cell openings 4110 of the mask frame 4100. Furthermore, bond openings 4130 can be formed to expose the mask alignment bonds 4400 and portions of the film 4200 surrounding (e.g., around) the mask alignment bonds 4400 (i.e., bond regions 4230 (see [reference]). Figure 19 In this respect, the post-inorganic film 4300 can be used as an etching mask in wet etching processes.

[0296] Figures 33 to 36 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to one or more embodiments of the present disclosure.

[0297] refer to Figure 33 In one or more embodiments, a film 4200 may be formed on a mask substrate 4002. For example, a monocrystalline silicon substrate may be used as the mask substrate 4002. The film 4200 may contain silicon nitride and may be formed by a CVD process. For example, a silicon source gas such as monosilane (SiH4), disilane (Si2H6), or dichlorosilane (DCS) (SiH2Cl2) and a nitrogen source gas such as N2 or NH3 may be supplied to the mask substrate 4002, and the film 4200 may be formed to a thickness of about 0.3 μm to about 3 μm by a reaction between the silicon source gas and the nitrogen source gas.

[0298] A film 4200 can be formed on the front surface of the mask substrate 4002, and a post-inorganic film 4300 can be formed on the rear surface of the mask substrate 4002. The post-inorganic film 4300 can be made of silicon nitride and can be formed by a CVD process. For example, film 4200 and post-inorganic film 4300 can be formed simultaneously (e.g., concurrently) by a CVD process. For example, by a CVD process, the front inorganic film and the post-inorganic film 4300 can be formed simultaneously (e.g., concurrently) on the front and rear surfaces of the mask substrate 4002, respectively, and the front inorganic film can be used as film 4200.

[0299] refer to Figure 34A multilayer inorganic film 4010 can be formed on film 4200. The multilayer inorganic film 4010 can have a structure in which a first inorganic film and a second inorganic film are alternately stacked. For example, the multilayer inorganic film 4010 can include stacked pairs of inorganic films, and each of the inorganic film pairs can include a first inorganic film and a second inorganic film. For example, the first inorganic film can be a silicon oxide film, and the second inorganic film can be a silicon nitride film. In this embodiment, besides the multilayer inorganic film 4010 being formed on film 4200, the multilayer inorganic film 4010 is similar to the above-referenced... Figure 26 The descriptions are essentially the same and will therefore not be repeated or further descriptions provided. For example, in this arrangement, the multilayer inorganic film 4010 consists of alternating layers of silicon oxide and silicon nitride films, thus creating a multilayer structure. Each inorganic film pair consists of a silicon oxide film (first inorganic film) followed by a silicon nitride film (second inorganic film), and this sequence is repeated multiple times. This alternating stacking enhances the optical properties and durability of the multilayer inorganic film, which is crucial for improving the performance and reliability of film 4200.

[0300] refer to Figure 35 Multilayer inorganic films 4010 can be patterned to be applied to the edge region 4204 of film 4200 (see [reference]). Figure 16 Mask alignment bonds 4400 are formed on the film 4200. For example, after forming a photoresist pattern on the multilayer inorganic film 4010 that exposes areas other than the portion where the mask alignment bonds 4400 are to be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., RIE process) to form mask alignment bonds 4400 on the film 4200. In this embodiment, except that the mask alignment bonds 4400 are formed on the edge region 4204 of the film 4200, the mask alignment bonds 4400 are formed on the edge region 4204 of the film 4200. Figure 27 The descriptions are essentially the same, and therefore will not be repeated or additional descriptions will be provided.

[0301] According to this embodiment, the preceding inorganic film used as film 4200 can be made of silicon-rich silicon nitride (silicon-rich SiN). For example, the ratio of silicon content (e.g., amount) to nitrogen content (e.g., amount) in the preceding inorganic film used as film 4200 can be from about 0.8 to about 1.2. In this respect, the ratio of silicon content (e.g., amount) to nitrogen content (e.g., amount) in the second inorganic film of the multilayer inorganic film 4010 can be less than the ratio of silicon content (e.g., amount) to nitrogen content (e.g., amount) in film 4200. For example, in one or more embodiments, the second inorganic film of the multilayer inorganic film 4010 can be made of stoichiometric silicon nitride (Si3N4). Therefore, the etching rate of film 4200 can be relatively slow compared to the etching rate of the second inorganic film of multilayer inorganic film 4010, and the preceding inorganic film used as film 4200 in the RIE process for forming mask alignment bonds 4400 can be used as an etching stop film.

[0302] refer to Figure 36 The front inorganic film used as the film 4200 can be patterned to form pixel openings 4212 that expose the front portion of the mask substrate 4002. Subsequently, the rear inorganic film 4300 can be patterned to form a first rear opening 4310 and a second rear opening 4320, and cell openings 4110 and bond openings 4130 can be formed by using an anisotropic etching process with the rear inorganic film 4300 as an etching mask. For example, a mask frame 4100 with cell openings 4110 and bond openings 4130 can be formed from the mask substrate 4002 by patterning the mask substrate 4002. At this point, mask alignment bonds 4400 can be arranged in the bond region 4230 of the film 4200 exposed through the bond openings 4130 (see...). Figure 22 In this embodiment, the method for forming pixel opening 4212, the method for forming the first rear opening 4310 and the second rear opening 4320, and the method for forming cell opening 4110 and key opening 4130 are the same as those described above. Figures 30 to 32 The descriptions are essentially the same, and therefore will not be repeated or additional descriptions will be provided.

[0303] According to one or more embodiments of this disclosure, dummy bonds 4450 may be formed on membrane 4200, such as Figure 23 and Figure 24As shown in the diagram. For example, dummy bonds 4450 can be formed from a multilayer inorganic film 4010. For example, by patterning the multilayer inorganic film 4010, dummy bonds 4450 can be formed synchronously (e.g., simultaneously) with mask alignment bonds 4400. For example, after forming a photoresist pattern on the multilayer inorganic film 4010 that exposes areas other than the portions where mask alignment bonds 4400 and dummy bonds 4450 are to be formed, the photoresist pattern can be used as an etch mask to perform an anisotropic etching process (e.g., RIE process) to form mask alignment bonds 4400 and dummy bonds 4450 on film 4200. At this point, the RIE process can be performed until the preceding inorganic film used as film 4200 is exposed, and the preceding inorganic film can be used as an etch stop film. According to this embodiment, dummy bonds 4450 can be used as spacers for maintaining a substantially uniform gap between the backplane substrate 3000 and the deposition mask 4000.

[0304] In this disclosure, when placed after / before an element in a list, expressions such as "at least one of," "one of," and "selected from" modify the elements of the entire list rather than individual elements in the list. For example, "at least one of a, b, and c," "selected from at least one of a, b, and c," "selected from at least one of a to c," etc., can mean only a, only b, only c, both a and b (including both a and b), both a and c (including both a and c), both b and c (including both b and c), all of a, b, and c, or variations thereof.

[0305] In the context of this application and unless otherwise specified, the terms “use,” “using,” and “used” may be understood as synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0306] Any numerical range described herein is intended to include all subranges containing the same numerical precision within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and inclusive of) the described minimum value of 1.0 and the described maximum value of 10.0, i.e., such as 2.4 to 7.6, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this disclosure is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this disclosure, including the claims, to clearly describe any subranges contained within the range expressly described herein.

[0307] Display modules, display devices, electronic devices / equipment, deposition mask manufacturing equipment, vacuum deposition equipment (such as thermal deposition equipment, electron beam evaporators, chemical vapor deposition equipment, etc.), device manufacturing equipment, or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on a single integrated circuit (IC) chip or on separate IC chips. Additionally, various components of these devices can be implemented on flexible printed circuit films, tape-on-a-package (TCP), printed circuit boards (PCBs), or formed on a substrate. Furthermore, various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components for performing the various functions described herein. The computer program instructions are stored in memory implemented in the computing device, such as random access memory (RAM), which can be used, for example, standard storage devices. The computer program instructions can also be stored, for example, on other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed to one or more other computing devices.

[0308] In light of the entire contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of one another or in combination with one another in any suitable way, unless otherwise stated or implied.

[0309] This disclosure should not be construed as being limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art.

[0310] While this disclosure has been specifically shown and described with reference to one or more embodiments thereof, those skilled in the art will understand that one or more suitable changes in form and detail may be made in this disclosure without departing from the spirit or scope of this disclosure as defined by the appended claims and their equivalents.

Claims

1. Deposition mask, including: Mask frame with cell openings; A membrane, on the mask frame, having a plurality of pixel openings communicating with the cell openings; as well as A mask alignment key is provided on the mask frame and has a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

2. The deposition mask according to claim 1, wherein, The mask alignment key is in the membrane, and The mask frame has a key opening that exposes the mask alignment key and the portion of the membrane surrounding the mask alignment key.

3. The deposition mask according to claim 2, further comprising a plurality of dummy keys on the mask frame, in, Each of the dummy keys has the same thickness as the mask alignment key.

4. The deposition mask according to claim 3, wherein, The membrane is on the mask alignment key, the dummy key, and the mask frame.

5. The deposition mask according to claim 1, wherein, The mask frame has key openings that expose portions of the membrane, and The mask alignment key is on the portion of the membrane exposed by the key opening.

6. The deposition mask according to claim 5, further comprising a plurality of dummy bonds on the film, in, Each of the dummy keys has the same thickness as the mask alignment key.

7. The deposition mask according to claim 1, wherein, Each of the first inorganic film patterns is a silicon oxide film pattern with a thickness of 90 nm to 110 nm. Each of the second inorganic film patterns is a silicon nitride film pattern with a thickness of 40 nm to 60 nm, and The mask alignment key comprises three to eleven or four to twelve first inorganic film patterns and three to eleven second inorganic film patterns.

8. The deposition mask according to claim 1, wherein, Each of the first inorganic film patterns is a silicon oxide film pattern with a thickness of 40 nm to 60 nm. Each of the second inorganic film patterns is a silicon nitride film pattern with a thickness of 90 nm to 110 nm, and The mask alignment key comprises five to thirteen or six to fourteen first inorganic film patterns and five to thirteen second inorganic film patterns.

9. The deposition mask according to claim 1, wherein, The mask alignment key has a light reflectivity of 0.5 or greater for light with wavelengths of 390 nm to 440 nm or 500 nm to 560 nm.

10. A method for manufacturing a deposition mask, comprising: Form mask alignment bonds on the mask substrate; A film having a plurality of pixel openings exposing the mask substrate is formed on the mask substrate; as well as The mask substrate is patterned to form cell openings that communicate with the pixel openings. The mask alignment key is formed as a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

11. The method according to claim 10, wherein, Forming the mask alignment key includes: A multilayer inorganic film is formed on the mask substrate in which a first inorganic film and a second inorganic film are alternately stacked; and The multilayer inorganic film is patterned to form the mask alignment bonds on the mask substrate. The film is formed on the mask alignment key and the mask substrate.

12. The method of claim 11, further comprising patterning the mask substrate to form key openings that expose the mask alignment key and a portion of the film surrounding the mask alignment key.

13. The method of claim 11, further comprising patterning the multilayer inorganic film to form a plurality of dummy bonds on the mask substrate, in, The dummy key is formed synchronously with the mask alignment key, and The film is formed on the mask alignment bond, the dummy bond, and the mask substrate.

14. The method of claim 10, wherein, Forming the membrane includes: An inorganic film is formed on the mask substrate; and Patterning the front inorganic film to form the pixel opening, and Forming the mask alignment key includes: A multilayer inorganic membrane is formed on the prior inorganic membrane, wherein a first inorganic membrane and a second inorganic membrane are alternately stacked; and Patterning the multilayer inorganic film to form the mask alignment bond on the front inorganic film, and The pixel opening is formed after the mask alignment key is formed.

15. The method of claim 14, further comprising patterning the mask substrate to form bond openings in portions exposing the film. in, The mask alignment key is formed on the portion of the membrane exposed by the key opening.

16. The method of claim 14, further comprising patterning the multilayer inorganic film to form a plurality of dummy bonds on the preceding inorganic film, in, The dummy key is formed synchronously with the mask alignment key.

17. The method according to claim 10, wherein, Each of the first inorganic film patterns is a silicon oxide film pattern with a thickness of 90 nm to 110 nm. Each of the second inorganic film patterns is a silicon nitride film pattern with a thickness of 40 nm to 60 nm, and The mask alignment key comprises three to eleven or four to twelve first inorganic film patterns and three to eleven second inorganic film patterns.

18. The method according to claim 10, wherein, Each of the first inorganic film patterns is a silicon oxide film pattern with a thickness of 40 nm to 60 nm. Each of the second inorganic film patterns is a silicon nitride film pattern with a thickness of 90 nm to 110 nm, and The mask alignment key comprises five to thirteen or six to fourteen first inorganic film patterns and five to thirteen second inorganic film patterns.

19. The method according to claim 10, wherein, The mask alignment key has a light reflectivity of 0.5 or greater for light with wavelengths of 390 nm to 440 nm or 500 nm to 560 nm.

20. Electronic devices, including display panels, in, The display panel includes a substrate and multiple light-emitting layers formed on the substrate using a deposition mask, and The deposition mask includes: Mask frame with cell openings; A membrane, on the mask frame and having a plurality of pixel openings communicating with the cell openings; and A mask alignment key is provided on the mask frame and has a structure in which a first inorganic film pattern and a second inorganic film pattern are alternately stacked.

Images