Deposition method, deposition apparatus, and electronic device

Abstract

A deposition method, deposition apparatus, and electronic device are disclosed. The deposition method includes: forming a capacitor between a substrate and a deposition mask; measuring the capacitance of the capacitor; aligning the substrate and the deposition mask with each other based on the measured capacitance; and providing deposition material onto the substrate through the deposition mask to form a deposition material layer on the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0176104, filed on December 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to deposition methods, deposition equipment, and electronic devices manufactured from deposition equipment. Background Technology

[0004] Wearable devices have been developed in the form of glasses or helmets, in which a focal point is formed at a distance close to the user's eyes. For example, the wearable device may be a head-mounted display (“HMD”) or augmented reality (“AR”) glasses. The wearable device may provide the user with AR or virtual reality (“VR”) visuals.

[0005] In the case of wearable devices such as HMDs or AR glasses, a display specification of approximately 3000 pixels per inch (PPI) or higher is desired to allow users to use them for extended periods without experiencing dizziness. For this purpose, organic light-emitting diodes on silicon (“OLEDoS”) technology is emerging for high-resolution, relatively small organic light-emitting display devices. OLEDoS technology is the technique of forming organic light-emitting diodes (“OLEDs”) on a semiconductor substrate on which complementary metal-oxide-semiconductor (“CMOS”) elements are disposed.

[0006] To manufacture display panels with a high resolution of approximately 3000 PPI or higher, high-resolution deposition masks are desired. For example, a deposition mask can be manufactured by forming a film (or diaphragm) defining multiple pixel openings on a substrate such as a silicon wafer, and partially removing the substrate to define unit openings that expose the pixel openings.

[0007] In the deposition process for forming the light-emitting layer of a display panel, a backplane substrate can be positioned on a deposition mask, and vapor-deposited material provided from a deposition source can be deposited on the backplane substrate through pixel openings in the deposition mask. Substrate alignment keys can be set on the backplane substrate, and mask alignment keys can be set on the deposition mask. Position information of the substrate alignment keys and mask alignment keys can be obtained using a high-resolution camera and illumination device, and the backplane substrate can be aligned on the deposition mask based on this position information. Summary of the Invention

[0008] Embodiments of this disclosure provide a deposition method and deposition apparatus that enable the alignment of a substrate and a deposition mask with each other without the use of a camera and lighting device, as well as electronic devices manufactured by the deposition apparatus.

[0009] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of this disclosure.

[0010] In embodiments of this disclosure, the deposition method may include: forming a capacitor between a substrate and a deposition mask; measuring the capacitance of the capacitor; aligning the substrate and the deposition mask with each other based on the measured capacitance of the capacitor; and providing deposition material onto the substrate through the deposition mask to form a deposition material layer on the substrate.

[0011] In one embodiment, measuring capacitance may include at least one of a moving substrate and a deposition mask, and measuring the change in capacitance while moving the substrate and the deposition mask simultaneously.

[0012] In an embodiment, at least one of the moving substrate and the deposition mask may include either the rotating substrate and the deposition mask, or either the moving substrate and the deposition mask.

[0013] In one embodiment, the gap between the substrate and the deposition mask can remain constant while at least one of the substrate and the deposition mask is moved.

[0014] In one embodiment, aligning the substrate and the deposition mask with each other may include moving at least one of the substrate and the deposition mask such that the capacitance is maximized.

[0015] In an embodiment, the deposition method may include: preparing a substrate including at least one first measuring electrode; preparing a deposition mask including at least one second measuring electrode; placing the substrate on the deposition mask such that at least one first measuring electrode and at least one second measuring electrode face each other; measuring the capacitance between at least one first measuring electrode and at least one second measuring electrode; aligning the substrate and the deposition mask with each other based on the measured capacitance; and providing deposition material onto the substrate through the deposition mask to form a deposition material layer on the substrate.

[0016] In an embodiment, measuring capacitance may include: rotating a substrate or a deposition mask; measuring a first capacitance value between at least one first measuring electrode and at least one second measuring electrode while rotating the substrate or deposition mask; moving the substrate or deposition mask while maintaining a constant gap between the substrate and the deposition mask; and measuring a second capacitance value between at least one first measuring electrode and at least one second measuring electrode while moving the substrate or deposition mask.

[0017] In one embodiment, aligning the substrate and the deposition mask with each other may include adjusting the position and angle of the substrate or the deposition mask such that the capacitance between at least one first measuring electrode and at least one second measuring electrode is maximized.

[0018] In an embodiment, the substrate may include a plurality of first measurement electrodes, and the deposition mask may include a plurality of second measurement electrodes. The substrate may be placed on the deposition mask such that the plurality of first measurement electrodes face the plurality of second measurement electrodes respectively, and the plurality of first measurement electrodes and the plurality of second measurement electrodes may have the same shape.

[0019] In an embodiment, measuring capacitance may include: rotating a substrate or deposition mask; and simultaneously measuring a plurality of first capacitance values ​​between a plurality of first measuring electrodes and a plurality of second measuring electrodes. Aligning the substrate and deposition mask with each other may include: detecting the azimuth angle of the substrate or deposition mask; and adjusting the azimuth angle of the substrate or deposition mask such that the plurality of first capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes become all equal.

[0020] In an embodiment, measuring capacitance may further include: moving the substrate or deposition mask while maintaining a constant gap between the substrate and the deposition mask; and measuring a plurality of second capacitance values ​​between a plurality of first measuring electrodes and a plurality of second measuring electrodes while moving the substrate or deposition mask. Aligning the substrate and the deposition mask with each other may further include: detecting the position of the substrate or deposition mask; and moving the substrate or deposition mask such that all of the plurality of second capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes become maximum.

[0021] In an embodiment, measuring capacitance may include: moving the substrate or deposition mask while maintaining a constant gap between the substrate and the deposition mask; and measuring a plurality of first capacitance values ​​between a plurality of first measurement electrodes and a plurality of second measurement electrodes while moving the substrate or deposition mask. Aligning the substrate and the deposition mask with each other may include: detecting the position of the substrate or deposition mask; and moving the substrate or deposition mask such that the plurality of first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes become all equal.

[0022] In an embodiment, measuring capacitance may further include: rotating the substrate or deposition mask; and simultaneously measuring a plurality of second capacitance values ​​between a plurality of first measuring electrodes and a plurality of second measuring electrodes. Aligning the substrate and deposition mask with each other may further include: detecting the azimuth angle of the substrate or deposition mask; and adjusting the azimuth angle of the substrate or deposition mask such that all of the plurality of second capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes become maximum.

[0023] In an embodiment, the substrate may include a plurality of first measurement electrodes and a plurality of third measurement electrodes, and the deposition mask may include a plurality of second measurement electrodes and a plurality of fourth measurement electrodes. The substrate may be placed on the deposition mask such that the plurality of first measurement electrodes face the plurality of second measurement electrodes respectively, and the third measurement electrodes face the fourth measurement electrodes respectively. The plurality of first measurement electrodes and the plurality of second measurement electrodes may extend in a first direction, and the third measurement electrodes and the fourth measurement electrodes may extend in a second direction perpendicular to the first direction.

[0024] In an embodiment, measuring capacitance may include: rotating a substrate or a deposition mask; and simultaneously rotating the substrate or deposition mask while measuring a plurality of first capacitance values ​​between a plurality of first measurement electrodes and a plurality of second measurement electrodes, and a plurality of second capacitance values ​​between a plurality of third measurement electrodes and a plurality of fourth measurement electrodes. Aligning the substrate and the deposition mask with each other may include: detecting the azimuth angle of the substrate or deposition mask; and adjusting the azimuth angle of the substrate or deposition mask such that the plurality of first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes become equal to each other, and the plurality of second capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes become equal to each other.

[0025] In an embodiment, measuring capacitance may further include: moving the substrate or deposition mask while maintaining a constant gap between the substrate and the deposition mask; and measuring a plurality of third capacitance values ​​between a plurality of first measuring electrodes and a plurality of second measuring electrodes, and a plurality of fourth capacitance values ​​between a plurality of third measuring electrodes and a plurality of fourth measuring electrodes, while moving the substrate or deposition mask. Aligning the substrate and the deposition mask with each other may further include: detecting the position of the substrate or deposition mask; and moving the substrate or deposition mask such that the plurality of third capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes, and the plurality of fourth capacitance values ​​between the plurality of third measuring electrodes and the plurality of fourth measuring electrodes, all become maximum and all become equal.

[0026] In an embodiment, measuring capacitance may include: moving the substrate or deposition mask while maintaining a constant gap between the substrate and the deposition mask; and measuring a plurality of first capacitance values ​​between a plurality of first measurement electrodes and a plurality of second measurement electrodes, and a plurality of second capacitance values ​​between a plurality of third measurement electrodes and a plurality of fourth measurement electrodes, while moving the substrate or deposition mask. Aligning the substrate and the deposition mask with each other may include: detecting the position of the substrate or deposition mask; and moving the substrate or deposition mask such that the plurality of first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes become equal to each other and the plurality of second capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes become equal to each other.

[0027] In an embodiment, measuring capacitance may further include: rotating the substrate or deposition mask; and simultaneously measuring a plurality of third capacitance values ​​between a plurality of first measuring electrodes and a plurality of second measuring electrodes, and a plurality of fourth capacitance values ​​between a plurality of third measuring electrodes and a plurality of fourth measuring electrodes. Aligning the substrate and the deposition mask with each other may further include: detecting the azimuth angle of the substrate or deposition mask; and adjusting the azimuth angle of the substrate or deposition mask such that the plurality of third capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes, and the plurality of fourth capacitance values ​​between the plurality of third measuring electrodes and the plurality of fourth measuring electrodes, all become maximum and all become equal.

[0028] In an embodiment, the substrate may include a first measuring electrode and at least one third measuring electrode, and the deposition mask may include a second measuring electrode and at least one fourth measuring electrode. The substrate may be placed on the deposition mask such that a first measuring electrode faces a second measuring electrode, and at least one third measuring electrode faces at least one fourth measuring electrode. A first measuring electrode and a second measuring electrode may have the same annular shape, and at least one third measuring electrode and at least one fourth measuring electrode may have the same shape.

[0029] In an embodiment, the deposition method may further include adjusting the parallelism between the substrate and the deposition mask.

[0030] In embodiments of this disclosure, the deposition apparatus may include: a deposition source for providing deposition material; a substrate chuck disposed above the deposition source and supporting a substrate including at least one first measuring electrode; a mask chuck disposed between the deposition source and the substrate chuck and supporting a deposition mask including at least one second measuring electrode; a sensor for measuring the capacitance between at least one first measuring electrode and at least one second measuring electrode; and a chuck driver for aligning the substrate and the deposition mask with each other based on the capacitance measured by the sensor.

[0031] In an embodiment, the substrate may further include at least one first contact pad and at least one first connection line connecting at least one first measurement electrode to at least one first contact pad. The deposition mask may further include at least one second contact pad and at least one second connection line connecting at least one second measurement electrode to at least one second contact pad. The sensor may include at least one first probe pin connected to at least one first contact pad and at least one second probe pin connected to at least one second contact pad.

[0032] In one embodiment, the sensor may be disposed in a mask chuck, and the deposition mask may define a through opening (or through-hole) through which at least one first probe pin passes.

[0033] In an embodiment, the deposition mask may include a mask substrate, and at least one second measurement electrode, at least one second contact pad, and at least one second interconnect may be disposed on the mask substrate. The mask substrate may define a contact opening that exposes at least one second contact pad, and at least one second probe pin may contact at least one second contact pad through the contact opening.

[0034] In an embodiment, the chuck driver can move the substrate chuck or the mask chuck such that the capacitance between at least one first measurement electrode and at least one second measurement electrode is maximized to align the substrate and the deposition mask with each other.

[0035] In an embodiment, the substrate may include a plurality of first measurement electrodes, the deposition mask may include a plurality of second measurement electrodes, and the first and second measurement electrodes may have the same shape.

[0036] In an embodiment, the chuck driver can rotate or move the base chuck or mask chuck horizontally so that the capacitance values ​​between the first measuring electrode and the second measuring electrode become equal.

[0037] In an embodiment, the chuck driver can move the base chuck or mask chuck horizontally or rotate it so that the capacitance between the first measuring electrode and the second measuring electrode becomes maximized.

[0038] In an embodiment, the substrate may include a plurality of first measurement electrodes and a plurality of third measurement electrodes, and the deposition mask may include a plurality of second measurement electrodes and a plurality of fourth measurement electrodes. The first and second measurement electrodes may extend in a first direction, and the third and fourth measurement electrodes may extend in a second direction perpendicular to the first direction.

[0039] In an embodiment, the chuck driver can rotate or move the base chuck or mask chuck horizontally such that the capacitance values ​​between the first and second measuring electrodes become equal, and the capacitance values ​​between the third and fourth measuring electrodes become equal.

[0040] In an embodiment, the chuck driver can move horizontally or rotate the base chuck or mask chuck such that the capacitance values ​​between the first and second measuring electrodes, as well as between the third and fourth measuring electrodes, become all maximum and all equal.

[0041] In an embodiment, the substrate may include a first measuring electrode and at least one third measuring electrode, and the deposition mask may include a second measuring electrode and at least one fourth measuring electrode. The first and second measuring electrodes may have the same annular shape, and the at least one third measuring electrode and the at least one fourth measuring electrode may have the same shape.

[0042] In one embodiment, the chuck driver can horizontally move the base chuck or mask chuck to maximize the capacitance between the first and second measuring electrodes.

[0043] In an embodiment, the chuck driver can rotate the base chuck or mask chuck such that the capacitance between at least one third measuring electrode and at least one fourth measuring electrode becomes maximum.

[0044] In an embodiment, the deposition apparatus may further include a gap sensor for measuring the gap between the substrate chuck and the mask chuck, and the chuck driver may adjust the tilt of the substrate chuck based on the measurement value of the gap sensor.

[0045] In embodiments of this disclosure, the electronic device may include a display panel. The display panel may include a substrate and a light-emitting layer formed on the substrate by a deposition apparatus, and the substrate may include at least one first measurement electrode. The deposition apparatus may include: a deposition source for providing deposition material; a substrate chuck disposed above the deposition source and supporting the substrate; a mask chuck disposed between the deposition source and the substrate chuck and supporting a deposition mask including at least one second measurement electrode; a sensor for measuring the capacitance between at least one first measurement electrode and at least one second measurement electrode; and a chuck driver for aligning the substrate and the deposition mask with each other based on the capacitance measured by the sensor.

[0046] In embodiments of this disclosure, the electronic device may further include at least one of a processor, a memory, and a power module.

[0047] Through this embodiment, alignment between the substrate and the deposition mask can be performed based on the capacitance between them. As a result, high-resolution cameras and illumination devices used for detecting general alignment keys can be eliminated, thereby significantly reducing the manufacturing cost of display panels, display devices, or electronic devices, etc.

[0048] Other features and embodiments may be apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0049] The above and other advantages and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0050] Figure 1 This is a block diagram of an embodiment of an electronic device according to the present disclosure;

[0051] Figure 2 This is a schematic diagram of an embodiment of an electronic device according to the present disclosure;

[0052] Figure 3This is an exploded perspective view illustrating an embodiment of a display device according to the present disclosure;

[0053] Figure 4 It is shown Figure 3 Block diagram of the display device shown;

[0054] Figure 5 It is shown Figure 4 The equivalent circuit diagram of the embodiment of the first sub-pixel shown;

[0055] Figure 6 It is shown Figure 3 A schematic plan view of an embodiment of the display panel shown;

[0056] Figure 7 It is shown Figure 6 A schematic enlarged plan view of an embodiment of the display area shown;

[0057] Figure 8 It is shown Figure 6 A schematic enlarged plan view of another embodiment of the display area shown;

[0058] Figure 9 It shows along Figure 7 A schematic cross-sectional view of an embodiment of the display panel, taken by line I1-I1' shown;

[0059] Figure 10 It shows along Figure 7 A schematic cross-sectional view of another embodiment of the display panel, shown by line I1-I1';

[0060] Figure 11 This is a schematic perspective view illustrating an embodiment of a head-mounted display;

[0061] Figure 12 It is shown Figure 11 A schematic exploded perspective view of the head-mounted display shown;

[0062] Figure 13 This is a schematic perspective view illustrating another embodiment of a head-mounted display;

[0063] Figure 14 This is a schematic diagram illustrating an embodiment of a deposition apparatus according to the present disclosure;

[0064] Figure 15 It is shown Figure 14 A schematic bottom view of the backplate base shown;

[0065] Figure 16 It is shown Figure 14 A schematic plan view of the deposition mask shown;

[0066] Figure 17 It is shown Figure 16 A schematic enlarged plan view of the mask unit area shown;

[0067] Figure 18 It is along Figure 17 The schematic cross-sectional view taken by line I2-I2' shown in the figure;

[0068] Figure 19 It is shown Figure 14 A schematic cross-sectional view of the base chuck and mask chuck shown;

[0069] Figure 20 It is shown Figure 19 A schematic plan view of the mask chuck shown;

[0070] Figure 21 It is shown Figure 19 and Figure 20 A schematic enlarged cross-sectional view of the sensor shown;

[0071] Figure 22 It is shown Figure 21 A schematic enlarged cross-sectional view of the through opening shown;

[0072] Figure 23 It is shown Figure 21 A schematic enlarged cross-sectional view of the contact opening shown;

[0073] Figure 24 and Figure 25 It is shown Figure 15 and Figure 16 A schematic diagram showing the first and second measuring electrodes facing each other;

[0074] Figures 26 to 29 It shows the use Figure 15 and Figure 16 A schematic plan view of the method by which the first and second measuring electrodes align the backplane substrate and the deposition mask with each other;

[0075] Figure 30 It is shown Figure 15 A schematic bottom view of another embodiment of the backplate substrate shown;

[0076] Figure 31 It is shown Figure 16 A schematic plan view of another embodiment of the deposition mask shown;

[0077] Figure 32 It is shown Figure 20 A schematic plan view of another embodiment of the sensor shown;

[0078] Figures 33 to 36 It shows the use Figure 30 and Figure 31 A schematic plan view of the method by which the first, second, third, and fourth measuring electrodes align the backplane substrate and the deposition mask with each other;

[0079] Figure 37 It is shown Figure 15 A schematic bottom view of another embodiment of the backplate substrate shown;

[0080] Figure 38 It is shown Figure 16 A schematic plan view of another embodiment of the deposition mask shown; and

[0081] Figure 39 This is a flowchart illustrating an embodiment of the deposition method according to the present disclosure. Detailed Implementation

[0082] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0083] It will also be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or an intervening element or layer may be present. Throughout the specification, the same reference numerals indicate the same components.

[0084] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0086] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device is flipped in a drawing, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in a drawing, an element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0087] Features of each of the various embodiments of this disclosure may be combined in part or in whole with each other and may be technically different from each other, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0088] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0089] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and shall not be interpreted in an idealized or overly formalized sense.

[0090] Embodiments are described herein with reference to cross-sectional views of schematic diagrams as idealized examples. Thus, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but should include deviations in shape due to, for example, manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0091] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0092] The display device in the embodiments of this disclosure can be applied to various electronic devices. Electronic devices according to embodiments of this disclosure include the aforementioned display device, and may also include modules or devices with additional functions besides the display device.

[0093] Figure 1 This is a block diagram of an embodiment of an electronic device according to the present disclosure.

[0094] Reference Figure 1 The electronic device 10 in the embodiments of this disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0095] The processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0096] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0097] The power module 14 may include a power module, such as a power adapter or battery, and a power conversion module, which converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0098] At least one of the components of the electronic device 10 according to embodiments of the present disclosure may be included in the display device 20 in embodiments of the present disclosure (see reference). Figure 3 Furthermore, some modules that are functionally included in a single module may be included in the display device 20, while other modules may be provided separately from the display device 20. In an embodiment, for example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 instead of the display device 20.

[0099] Figure 2 This is a schematic diagram of an embodiment of an electronic device according to the present disclosure.

[0100] Reference Figure 2 The various electronic devices used in the display device 20 in the embodiments of this disclosure may include not only image display electronic devices such as smartphones 10_1a, tablet personal computers (“PC”) 10_1b, laptop computers 10_1c, televisions (“TV”) 10_1d and desktop monitors 10_1e, but also wearable electronic devices such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c that include display modules, and vehicle electronic devices 10_3 such as central information displays (“CID”) arranged on the dashboard, central instrument panel and dashboard of a car, and rearview mirror displays.

[0101] Figure 3 This is an exploded perspective view showing a display device according to the present disclosure. Figure 4 It is shown Figure 3 Block diagram of the display device shown.

[0102] Reference Figure 3 and Figure 4 The display device 20 in the embodiments can be a device for displaying moving or still images. The display device 20 in the embodiments can be used as electronic device 10 (see reference 10). Figure 1 ) or the display module 11 of the electronic device 10 (see reference) Figure 1In embodiments, for example, the display device 20 can be applied to portable electronic devices 10, such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation systems, or ultra-mobile PCs (“UMPCs”). The display device 20 can also be applied as a display module 11 of electronic devices 10, such as televisions, laptops, monitors, billboards, or Internet of Things (“IoT”) terminals. Furthermore, the display device 20 can be applied to electronic devices 10, such as smartwatches, smartwatch phones, or head-mounted displays (“HMDs”) for implementing virtual and augmented reality.

[0103] The display device 20 in the embodiment may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (timing controller) 400, and a power supply circuit (power supply unit) 500.

[0104] The display panel 100 may have a planar shape similar to a quadrilateral. In an embodiment, for example, the display panel 100 may have a planar shape similar to a quadrilateral, having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 20 may conform to the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0105] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0106] Multiple pixels (PX) can be set in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix along the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and be arranged along the first direction (DR1).

[0107] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0108] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 5 The multiple pixel transistors shown can be formed by semiconductor processes and disposed on a semiconductor substrate SSUB (see reference). Figure 9 In embodiments, for example, the plurality of pixel transistors may include or be composed of complementary metal-oxide-semiconductor (“CMOS”), but this disclosure is not limited thereto.

[0109] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0110] The scan driver 610, transmit driver 620, and data driver 700 can be located in the non-display area NDA.

[0111] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB (see reference SSUB) using semiconductor processes. Figure 9 In this embodiment, for example, the plurality of scanning transistors and the plurality of light-emitting transistors may include or be composed of CMOS, but this disclosure is not limited thereto.

[0112] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line GBL.

[0113] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and sequentially output the first transmit control signal to the first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and sequentially output the second transmit control signal to the second transmit control line ECL2.

[0114] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see reference) using semiconductor processes. Figure 9 In this embodiment, for example, the plurality of data transistors may include or be composed of CMOS, but this disclosure is not limited thereto.

[0115] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the analog data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0116] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal (such as silver (Ag), copper (Cu), or aluminum (Al)) or graphite having relatively high thermal conductivity.

[0117] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see reference) via conductive adhesive components such as anisotropic conductive film. Figure 6 Multiple first pads PD1 (refer to) Figure 6 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 3 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the first pad portion PDA1 of the display panel 100 (see reference 100) via a conductive adhesive component. Figure 6 Multiple first pads PD1 (refer to) Figure 6 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0118] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0119] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. In an embodiment, for example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply these voltages to the display panel 100. This will be discussed later in conjunction with... Figure 5 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0120] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (“IC”) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0121] In an alternative embodiment, similar to scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors may be formed on a semiconductor substrate SSUB (see reference SSUB) using semiconductor processes. Figure 9 In an embodiment, for example, the multiple timing transistors and multiple power transistors may include or be composed of CMOS, but this disclosure is not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 may be disposed in the data driver 700 and the first pad portion PDA1 (see reference). Figure 6 )between.

[0122] Figure 5 It is shown Figure 4 The equivalent circuit diagram of the embodiment of the first sub-pixel shown.

[0123] Reference Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first drive voltage VSS corresponding to a relatively low potential voltage (see reference). Figure 4 The first driving voltage line VSL applied, and the second driving voltage VDD corresponding to the relatively high potential voltage (refer to) Figure 4 The second driving voltage line VDL and the third driving voltage VINT corresponding to the initialization voltage (refer to) are applied. Figure 4 The third driving voltage line VIL applied.

[0124] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0125] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. In embodiments, for example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0126] The first transistor T1 may be a driving transistor that controls the source-drain current (referred to herein as the “drive current”) flowing between its source and drain electrodes according to the voltage applied to its gate electrode.

[0127] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0128] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this purpose, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode.

[0129] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0130] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal on the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0131] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0132] Each of the first transistors T1 through T6 may be a metal-oxide-semiconductor field-effect transistor (“MOSFET”). In an embodiment, for example, each of the first transistors T1 through T6 may be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 through T6 may be an N-type MOSFET. In an alternative embodiment, some of the first transistors T1 through T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0133] Despite Figure 5 The diagram shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 5 The equivalent circuit diagram is shown. In embodiments, for example, the number of transistors and capacitors of the first sub-pixel SP1 is not limited to... Figure 5 The number of transistors and capacitors shown.

[0134] In addition, the second sub-pixel SP2 (refer to) Figure 4 The equivalent circuit diagram of the third sub-pixel SP3 (refer to) Figure 4 The equivalent circuit diagram of ) can be combined with Figure 5 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0135] Figure 6 It is shown Figure 3 A schematic plan view of an embodiment of the display panel shown.

[0136] Reference Figure 6In this embodiment, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0137] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. In an embodiment, for example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the opposite side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and both the scan driver 610 and the transmit driver 620 can be disposed on either the first or second side of the display area DAA.

[0138] The first pad portion of PDA1 may include a connection to circuit board 300 (see reference) via a conductive adhesive component. Figure 3 Multiple first pads PD1 of pads or bumps. The first pad portion PDA1 can be disposed on the third side of the display area DAA. In an embodiment, for example, the first pad portion PDA1 can be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 can be disposed outside the data driver 700 on the second direction DR2.

[0139] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board comprising or composed of rigid materials, or a flexible printed circuit board comprising or composed of flexible materials.

[0140] The second pad portion PDA2 can be disposed on the fourth side of the display area DAA. In an embodiment, for example, the second pad portion PDA2 can be disposed on the opposite side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be disposed outside the second distribution circuit 720 in the second direction DR2.

[0141] The first distribution circuit 710 distributes the data voltage applied through the first pad portion of PDA1 to multiple data lines DL (see reference). Figure 5In an embodiment, for example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. In an embodiment, for example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2.

[0142] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. In an embodiment, for example, the second distribution circuit 720 can be disposed on the opposite side of the display area DAA in the second direction DR2.

[0143] The cathode connection (CCA) can be the display element layer (EML) within it (see reference). Figure 9 The second electrode CAT (refer to) Figure 9 The first drive voltage line VSL connected to the non-display area NDA (refer to) Figure 5 The cathode connection portion (CCA) can be disposed outside at least one side of the display area (DAA). In an embodiment, for example, the cathode connection portion (CCA) can be disposed outside at least one of the left, right, upper, and lower sides of the display area (DAA). In an alternative embodiment, for example, as... Figure 6 As shown, the cathode connection CCA can be configured to surround the display area DAA in order to minimize the first drive voltage VSS (refer to) caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA. Figure 4 The deviation in ).

[0144] Figure 7 It is shown Figure 6 A schematic enlarged plan view of an embodiment of the display area shown. Figure 8 It is shown Figure 6 A schematic enlarged plan view of another embodiment of the display area shown.

[0145] Reference Figure 7 and Figure 8 Multiple pixel PX (refer to) Figure 6Each of the sub-pixels includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0146] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can be arranged as follows in the plan view: Figure 7 and Figure 8 The quadrilateral or hexagonal shape shown is not the only one described herein. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than quadrilaterals or hexagons in the plan view.

[0147] like Figure 7 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0148] In alternative embodiments, such as Figure 8 As shown, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. In this case, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent to each other in the second direction DR2. Furthermore, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the second diagonal direction DD2. Additionally, the first emission region EA1 and the fourth emission region EA4 can be adjacent to each other in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent to each other in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0149] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, the third sub-pixel SP3 can emit a third light, and the fourth sub-pixel SP4 can emit a second light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band. In an embodiment, for example, the blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 370 nanometers (nm) to 460 nm, the green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 480 nm to 560 nm, and the red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 600 nm to 750 nm.

[0150] like Figure 7 As shown, each of the multiple pixels PX may include three emission regions EA1, EA2, and EA3, or as... Figure 8 Each of the plurality of pixels PX shown may include four emission regions EA1, EA2, EA3, and EA4. In this case, the fourth emission region EA4 may emit the same second light as the second emission region EA2, but this disclosure is not limited thereto.

[0151] The emission regions of multiple pixels PX can be arranged in a strip structure along the first direction DR1, wherein the emission regions EA1, EA2, EA3, and EA4 are as follows: Figure 8 The arrangement shown is in a diamond shape. The structure or the hexagonal structure in which the emission area is arranged is a hexagonal structure.

[0152] Figure 9 It shows along Figure 7 The schematic cross-sectional view of an embodiment of the display panel shown is taken by line I1-I1'.

[0153] Reference Figure 9 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0154] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1 to SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be referenced... Figure 5 The first transistor T1 to the sixth transistor T6 are described.

[0155] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. In an embodiment, for example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. In an alternative embodiment, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0156] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0157] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can be disposed on the lower insulating film (BINS).

[0158] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on the third direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the opposite side of the gate electrode GE.

[0159] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 can have a lower impurity concentration than the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 can have a lower impurity concentration than the drain region DA. Due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased, thereby increasing the length of the channel region CH of each of the multiple pixel transistors PTR.

[0160] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0161] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each of the multiple pixel transistors (PTRs) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can include any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or be composed of any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0162] The third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3).

[0163] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 may include silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic films based on silicon carbonitride (SiCN) or silicon oxide (SiO2) x The inorganic membrane composition is based on ) but this disclosure is not limited thereto.

[0164] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate comprising a polymer such as polyimide. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0165] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple interlayer insulating films INS1 to INS9.

[0166] Interlayer insulating films INS1 to INS9 are used to insulate first conductive layers ML1 to eighth conductive layers ML8. First conductive layers ML1 to eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 5 The circuit of the first sub-pixel SP1 shown.

[0167] In an embodiment, for example, combined with Figure 5The first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection between the first transistor T1 to the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0168] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise or be composed of substantially the same material as each other. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these materials, or an alloy comprising any one of these materials. The first interlayer insulating films INS1 to INS8 may comprise or be composed of substantially the same material as each other. The first interlayer insulating films INS1 to INS8 may comprise silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The inorganic membrane composition is based on ) but this disclosure is not limited thereto.

[0169] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The inorganic membrane composition is based on ) but this disclosure is not limited thereto.

[0170] Each of the plurality of ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 may comprise any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or be composed of any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0171] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0172] The reflective electrode RL can be disposed on the ninth interlayer insulating film INS9. Each of the plurality of reflective electrodes RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. In an embodiment, for example, as shown... Figure 9 As shown, each of the plurality of reflective electrodes RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0173] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth via VA9. Each of the plurality of second reflective electrodes RL2 can be disposed on its corresponding first reflective electrode RL1. Each of the plurality of third reflective electrodes RL3 can be disposed on its corresponding second reflective electrode RL2. Each of the plurality of fourth reflective electrodes RL4 can be disposed on its corresponding third reflective electrode RL3.

[0174] Since the second reflective electrode RL2 is the electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0175] The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 may comprise any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride thereof, or be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In embodiments, for example, the first reflective electrode RL1 may comprise titanium nitride (TiN) or be composed of titanium nitride (TiN), the second reflective electrode RL2 may comprise aluminum (Al) or be composed of aluminum (Al), the third reflective electrode RL3 may comprise titanium nitride (TiN) or be composed of titanium nitride (TiN), and the fourth reflective electrode RL4 may comprise titanium (Ti).

[0176] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to flatten the step portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0177] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The inorganic membrane composition is based on ) but this disclosure is not limited thereto.

[0178] The eleventh interlayer insulating film INS11 can be an optical auxiliary layer for adjusting the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0179] In an embodiment, for example, such as Figure 9 As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0180] Each of the plurality of tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and connect to the exposed fourth reflective electrode RL4. The tenth via VA10 can comprise any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination thereof, or is composed of any one or an alloy containing any of these. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0181] The first electrode AND of each of the plurality of light-emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE can include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy or nitride containing any one of them, or is composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy or nitride containing any one of them. In an embodiment, for example, the first electrode AND of each of the plurality of light-emitting elements LE can be titanium nitride (TiN).

[0182] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of a plurality of light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL can separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a region in which a light-emitting element LE comprising the first electrode AND, a light-emitting stack IL, and a second electrode CAT is disposed.

[0183] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0184] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The composition is an inorganic film based on silicon nitride (SiN). In an alternative embodiment, the first pixel defining film PDL1 and the third pixel defining film PDL3 may comprise silicon nitride (SiN). x Inorganic films based on silicon nitride (SiN) or made of silicon nitride (SiN) x The second pixel defining film PDL2 may include silicon oxide (SiO2) and an inorganic film composition based on silicon oxide. x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The film is composed of inorganic films based on a matrix. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have approximately 500 angstroms. The thickness.

[0185] To reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage (step coverage ratio), the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage ratio refers to the ratio of the thickness of the film coated on the inclined portion to the thickness of the film coated on the flat portion. The lower the step coverage ratio, the more likely the film will be cut at the inclined portion.

[0186] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. The eleventh interlayer insulating film INS11 can be partially recessed at each of the multiple trench TRCs.

[0187] At least one trench TRC can be set between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 Two trench TRCs are shown positioned between adjacent sub-pixels SP1, SP2, and SP3, but this disclosure is not limited thereto.

[0188] The light-emitting stack IL can include multiple stacked layers IL1, IL2 and IL3. Figure 9 The illustration shows a light-emitting stack IL having a triple-tandem structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. In embodiments, for example, such as... Figure 10 As shown, the light-emitting stack IL can have a dual-tandem structure including two stacked layers IL1 and IL2.

[0189] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different lights. In an embodiment, for example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a second light, and a third stacked layer IL3 that emits a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially.

[0190] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are stacked sequentially. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are stacked sequentially. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer are stacked sequentially.

[0191] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0192] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0193] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and the residual film RIL disposed on the bottom surface of each trench TRC can be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be defined in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be configured to cover the second stacked layer IL2 in each of the plurality of trench TRCs.

[0194] In a three-series structure, each of the multiple trench TRCs can be a structure for cutting off the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the display element layers EML between adjacent sub-pixels SP1, SP2, and SP3. Furthermore, in a two-series structure, each of the multiple trench TRCs can be a structure for cutting off the charge generation layer and the lower stacked layer disposed between the lower stacked layer and the upper stacked layer.

[0195] To stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. Different structures can replace the trench TRCs to cut off the charge generation layer and hole transport layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In an embodiment, for example, instead of trench TRCs, a reverse tapered separator wall can be provided on the pixel defining film PDL.

[0196] also, Figure 9The light-emitting stack IL is shown to be disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but this disclosure is not limited thereto. In embodiments, instead of the light-emitting stack IL, the first light-emitting layer may be disposed in the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, the second light-emitting layer may be disposed in the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Furthermore, the third light-emitting layer may be disposed in the third emission region EA3 and may be omitted from the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0197] The second electrode CAT can be disposed on the light-emitting stack IL. That is, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can include a transparent conductive material (“TCO”) such as indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) that can transmit light, or a semi-transparent conductive material such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag, or is composed of a transparent conductive material (“TCO”) such as indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) that can transmit light, or a semi-transparent conductive material such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag. When the second electrode CAT includes or is composed of a semi-transparent conductive material, the light emission efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity effect.

[0198] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 may be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may contain silicon nitride (SiN). x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium oxide (TiO) x ) layer and aluminum oxide (AlO) x A multilayer consisting of one or more inorganic layers stacked alternately, or consisting of silicon nitride (SiN) layers. x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium oxide (TiO) x ) layer and aluminum oxide (AlO)x A multilayer composition consisting of one or more inorganic layers stacked alternately.

[0199] Furthermore, the encapsulation layer TFE may include at least one encapsulation organic film TFE2 to protect the display element layer EML from foreign matter such as dust. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. In an alternative embodiment, the encapsulation organic film TFE2 may be an organic film comprising polymers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0200] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Furthermore, the adhesive layer ADL can be a transparent adhesive component comprising, for example, a transparent adhesive or a transparent adhesive resin.

[0201] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0202] The first color filter CF1 may overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 may transmit light of a first color, namely, light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit light of the first color emitted from the first emission region EA1.

[0203] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, namely, light in the green wavelength band. The green wavelength band can be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0204] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color, that is, light in the red wavelength band. The red wavelength band can be approximately 600nm to approximately 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0205] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be a structure for increasing the proportion of light traveling to the front of the display device 10. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0206] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a predetermined refractive index such that light propagates in the third-direction DR3 at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film comprising polymers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0207] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin substrate. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin substrate, it can be directly applied to the filler layer FIL.

[0208] A polarizing plate (POL) can be disposed on one surface of the CVL (container layer). The polarizing plate (POL) can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. In embodiments, for example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizing plate (POL) can be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0209] Figure 10 It shows along Figure 7 The schematic cross-sectional view of another embodiment of the display panel shown is taken by line I1-I1'.

[0210] Figure 10 Implementation examples and Figure 9 The difference in the embodiment is that the first electrode AND of each of the plurality of light-emitting elements LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation examples and Figure 9 The embodiment differs further in that the trench TRC is omitted, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have an eaves-shaped or mushroom-shaped cross-sectional structure. Figure 10 In the embodiments, the parts already included will be omitted. Figure 9 The redundant description of the components described in the embodiments.

[0211] Reference Figure 10 Multiple connecting electrodes ANC can be respectively disposed on the first portion AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be disposed on the first portion AA1 of the ninth interlayer insulating film INS9 corresponding to it. The multiple connecting electrodes ANC may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), alloys or nitrides or transparent conductive oxides containing any one of them, or be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), alloys or nitrides or transparent conductive oxides containing any one of them. In embodiments, for example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (“ITO”), or indium zinc oxide (“IZO”), but this disclosure is not limited thereto.

[0212] Multiple reflective electrodes RL can be disposed on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be disposed on its corresponding connecting electrode ANC. The multiple reflective electrodes RL can include any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or composed of any one or an alloy containing any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In an embodiment, for example, each of the multiple reflective electrodes RL can include aluminum (Al) having a relatively high reflectivity.

[0213] Multiple optical auxiliary films (OALs) can be separately disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on its corresponding reflective electrode (RL). The multiple optical auxiliary films (OALs) may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The inorganic membrane composition is based on ) but this disclosure is not limited thereto.

[0214] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be disposed on the reflective electrode RL, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. The thickness of the optical auxiliary film OAL can be substantially the same in the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0215] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first emission region EA1 and the third emission region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be determined by considering the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0216] Each of the multiple light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0217] The first electrode AND of each of the plurality of light-emitting elements LE can be disposed on its corresponding optical auxiliary film OAL. Since the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each of the plurality of light-emitting elements LE can be disposed on the top and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Therefore, the first electrode AND of each of the plurality of light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to when the first electrode AND of each of the plurality of light-emitting elements LE is connected to the reflective electrode RL exposed through a through-hole penetrating the optical auxiliary film OAL, the number of masking processes can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0218] The first electrode AND of each of the multiple light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the connecting electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE.

[0219] The ninth interlayer insulating film INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3 and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same.

[0220] In an alternative embodiment, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 may be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this case, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 may be exposed, and the first electrode AND of each of the plurality of light-emitting elements LE may be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0221] The first electrode AND of each of the plurality of light-emitting elements LE may comprise any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy or nitride thereof, or a transparent conductive oxide thereof, or may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy or nitride thereof, or a transparent conductive oxide thereof. In embodiments, for example, the first electrode AND of each of the plurality of light-emitting elements LE may comprise titanium (Ti), titanium nitride (TiN), indium tin oxide (“ITO”), or indium zinc oxide (“IZO”), but this disclosure is not limited thereto.

[0222] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0223] The pixel-limited film (PDL) may include a first pixel-limited film (PDL1), a second pixel-limited film (PDL2), a third pixel-limited film (PDL3), and a fourth pixel-limited film (PDL4).

[0224] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the plurality of light-emitting elements LE. Specifically, the first pixel defining film PDL1 can cover a portion of the top surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0225] The planarization film PNS is a film used to planarize the stepped portions caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0226] The planarization film PNS can be disposed on the first pixel defining film PDL1, which covers the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can also be disposed on the first pixel defining film PDL1, which is disposed on the second portion AA2 of the ninth interlayer insulating film INS9.

[0227] The planarization film PNS can be disposed between adjacent connecting electrodes ANC on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL on the first direction DR1 or the second direction DR2.

[0228] The step layer STPL is not in the second emission region EA2, but is present in each of the first emission region EA1 and the third emission region EA3. Therefore, the heights of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emission region EA2 can be smaller than the heights of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the second emission region EA2.

[0229] Conversely, the top surface of the planarization film PNS can be flatly connected to the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the first emission region EA1 and the third emission region EA3. That is, the planarization film PNS may not cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in each of the first emission region EA1 and the third emission region EA3.

[0230] The second pixel limiting film PDL2 can be disposed on the first pixel limiting film PDL1 and the planarization film PNS, the third pixel limiting film PDL3 can be disposed on the second pixel limiting film PDL2, and the fourth pixel limiting film PDL4 can be disposed on the third pixel limiting film PDL3. The first pixel limiting film PDL1 and the third pixel limiting film PDL3 may include silicon nitride (SiN). x Inorganic films based on silicon nitride (SiN) or made of silicon nitride (SiN) xThe film is composed of inorganic films based on silicon dioxide (SiO2), while the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS may include silicon dioxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x The first pixel defining film PDL1 is composed of an inorganic film based on a material different from or composed of a material different from the material of the planarization film PNS, and therefore, the first pixel defining film PDL1 can be used as a stop in the chemical mechanical polishing process used for the planarization film PNS.

[0231] When the planarization film PNS and the second pixel defining film PDL2 are both formed as silicon oxide (SiO) x When using an inorganic film based on a substrate, the planarization film PNS and the second pixel-defining film PDL2 can be formed as a single film.

[0232] Because the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, the bottom surface of the fourth pixel defining film PDL4 can be exposed without being covered by the third pixel defining film PDL3. In other words, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have an eaves-shaped or mushroom-shaped cross-sectional structure.

[0233] A light-emitting stack IL can be disposed on a first electrode AND and a pixel-defining film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different types of light. When the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light within a wavelength range including any one of a first light, a second light, and a third light, and the other (additionally) of the first stacked layer IL1 and the second stacked layer IL2 can emit light within a wavelength range including the remaining (additionally) two types of light. In an embodiment, for example, the first stacked layer IL1 can emit light including the wavelength range of the first light and the wavelength range of the third light, and the second stacked layer IL2 can emit light including the wavelength range of the second light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band.

[0234] A charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0235] The first stacked layer IL1 is not formed on the exposed bottom surface of the fourth pixel-defining film PDL4, which is not covered by the third pixel-defining film PDL3, and therefore can be cut off by the eaves-shaped or mushroom-shaped cross-sectional structure of the third pixel-defining film PDL3 and the fourth pixel-defining film PDL4. In this case, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be cut off. Furthermore, although Figure 10 The diagram shows that the second stacked layer IL2 is connected without being disconnected, but the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, leakage current can be prevented from flowing between the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer between adjacent (adjacent) emission regions EA1, EA2, and EA3. Therefore, it is possible to prevent the light-emitting stacks IL in adjacent (adjacent) emission regions EA1, EA2, and EA3 from emitting light other than the initially intended light due to the aforementioned current.

[0236] although Figure 10 The illustration shows a dual-tandem structure in which the light-emitting stack IL comprises two stacked layers IL1 and IL2, but this disclosure is not limited thereto. In embodiments, for example, the light-emitting stack IL may have a structure including, for example, Figure 9 The diagram shows a triple-tandem structure of three stacked layers IL1, IL2, and IL3. In this case, it can be designed such that the charge-generating layer between the first stacked layer IL1 and the second stacked layer IL2, as well as the charge-generating layer between the second stacked layer IL2 and the third stacked layer IL3, can be cut off by adjusting the height of the third pixel-defining film PDL3. In an alternative embodiment, as... Figure 9 As shown, a trench TRC that penetrates the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can be attached. In this case, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but this disclosure is not limited thereto.

[0237] Figure 11 This is a schematic perspective view illustrating one embodiment of a head-mounted display. Figure 12 It is shown Figure 11 The schematic exploded perspective view of the head-mounted display shown.

[0238] Reference Figure 11 and Figure 12The head-mounted display 1000 in the embodiment includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0239] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. Because each of the first display device 20_1 and the second display device 20_2 is combined... Figures 3 to 10 The display devices 20 described are substantially the same, therefore the description of the first display device 20_1 and the second display device 20_2 will be omitted.

[0240] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0241] The intermediate frame 1400 can be disposed between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0242] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data and transmit the digital video data to the first display device 20_1 and the second display device 20_2 via connectors.

[0243] The control circuit board 1600 can transmit digital video data corresponding to a left-eye image optimized for the user's left eye to a first display device 20_1, and can transmit digital video data corresponding to a right-eye image optimized for the user's right eye to a second display device 20_2. In an alternative embodiment, the control circuit board 1600 can transmit the same digital video data to both the first display device 20_1 and the second display device 20_2.

[0244] The display device housing 1100 is used to house the first display device 20_1, the second display device 20_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 11 and Figure 12 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately configured, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0245] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0246] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned on the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can be as follows: Figure 13 The image shown is provided with eyeglass frames instead of a headband 1300.

[0247] Figure 13 This is a schematic perspective view illustrating another embodiment of a head-mounted display.

[0248] Reference Figure 13 The head-mounted display 1000_1 in the embodiment may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 in the embodiment may include a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0249] The display device housing 1200_1 can accommodate the display device 20_3, the optical component 1060, and the optical path changing component 1070. The image displayed in the display device 20_3 can be magnified by the optical component 1060 and, after the optical path of the image is changed by the optical path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image—a combination of the virtual image displayed in the display device 20_3 and the real image seen through the right eye lens 1020—through their right eye.

[0250] Figure 13 The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but this disclosure is not limited thereto. In an embodiment, for example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in this case, the image displayed on the display device 20_3 can be provided to the user's left eye. In an alternative embodiment, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 20_3 through both the left and right eyes.

[0251] Figure 14 This is a schematic diagram illustrating an embodiment of a deposition apparatus.

[0252] Reference Figure 14 The deposition apparatus 2000 in the embodiments can be used to form a deposition material layer on the substrate 3000. In the embodiments, for example, on the display panel 100 (see reference 100) Figure 3 In the manufacturing process of the backplane substrate 3000, the deposition equipment 2000 in the embodiment can be used to form a light-emitting layer on the backplane substrate 3000 (or also referred to as the substrate). In the embodiment, for example, as Figure 9 As shown, a semiconductor backplane (SBP) and a light-emitting element backplane (EBP) can be disposed on a backplane substrate 3000, and a reflective electrode (RL) and interlayer insulating films (INS10 and INS11) can be disposed on the light-emitting element backplane (EBP). An electrode pattern (e.g., a first electrode AND serving as an anode electrode) and a pixel defining film (PDL) defining an opening exposing the first electrode AND can be disposed on an eleventh interlayer insulating film (INS11), and the first electrode AND can be electrically connected to the reflective electrode RL through a tenth via (VA10). In one embodiment, the deposition apparatus 2000 can form a first light-emitting layer on the first electrode AND in a first emission region EA1. In another embodiment, the deposition apparatus 2000 can form a second light-emitting layer on the first electrode AND in a second emission region EA2. As another example, the deposition apparatus 2000 can form a third light-emitting layer on the first electrode AND in a third emission region EA3.

[0253] The deposition apparatus 2000 may include a deposition source 2200 for providing vapor deposition material to a backing substrate 3000, a substrate chuck 2300 for supporting the backing substrate 3000 facing the deposition source 2200, and a mask chuck 2400 disposed between the deposition source 2200 and the substrate chuck 2300 to support a deposition mask 4000 facing the backing substrate 3000. The deposition source 2200, substrate chuck 2300, and mask chuck 2400 may be disposed in a process chamber (or evaporation chamber) 2100.

[0254] The process chamber 2100 may have an internal space, and the deposition process for forming a deposition material layer on the backplane substrate 3000 can be performed within the internal space of the process chamber 2100. The process chamber 2100 may be connected to a vacuum pump (not shown), and a vacuum atmosphere may be generated within the internal space of the process chamber 2100 by the vacuum pump. An opening (not shown) for loading / unloading the backplane substrate 3000 and the deposition mask 4000 may be provided on a wall of the process chamber 2100, and this opening may be opened and closed by a gate valve (not shown).

[0255] A deposition source 2200 can be disposed in a process chamber 2100, and deposition material can be stored in the deposition source 2200. The deposition source 2200 can evaporate deposition material, such as organic, inorganic, or conductive material, toward a backplane substrate 3000, and the evaporated deposition material can be deposited on the backplane substrate 3000 through a deposition mask 4000. In an embodiment, for example, the deposition source 2200 can evaporate an organic light-emitting material for forming a light-emitting layer on the backplane substrate 3000, and a heater (not shown) for evaporating the organic light-emitting material can be provided. The evaporated organic light-emitting material can be deposited on an electrode pattern on the backplane substrate 3000 through the deposition mask 4000, thereby forming a light-emitting layer on the electrode pattern of the backplane substrate 3000. Figure 14 As shown, the deposition source 2200 can be disposed on the central portion of the bottom surface of the process chamber 2100, but the deposition source 2200 can be moved horizontally by a separate actuator (not shown).

[0256] The substrate chuck 2300 can be disposed above the deposition source 2200 and can support the backplate substrate 3000 such that the backplate substrate 3000 faces the deposition source 2200. In an embodiment, for example, the substrate chuck 2300 can be an electrostatic chuck that uses electrostatic force to hold the rear surface of the backplate substrate 3000. Specifically, an electrode pattern (e.g., a first electrode AND) can be disposed on the front surface of the backplate substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplate substrate 3000 such that the front surface of the backplate substrate 3000 faces downward, i.e., facing the deposition source 2200.

[0257] Multiple lifting fingers 2350 for loading the backplane substrate 3000 onto the substrate chuck 2300 can be arranged in the process chamber 2100. The lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be vertically moved by finger actuators 2360, respectively. In an embodiment, for example, three or four lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved in a third direction (DR3) by the finger actuators 2360.

[0258] The backplate base 3000 can be loaded into the process chamber 2100 by a transfer robot (not shown) and can be transferred from the transfer robot to the lifting finger 2350 below the base chuck 2300. In this case, the rear surface of the backplate base 3000 can face the bottom surface of the base chuck 2300, and the lifting finger 2350 can support the front edge portion of the backplate base 3000. The finger actuator 2360 can raise the lifting finger 2350, bringing the backplate base 3000 close to (adjacent to) the bottom surface of the base chuck 2300, and the rear surface of the backplate base 3000 can be held on the bottom surface of the base chuck 2300 by electrostatic force.

[0259] Finger actuators 2360 may be disposed on the upper cover of process chamber 2100 and may be connected to lifting fingers 2350 via drive shafts 2362 extending vertically through the upper cover of process chamber 2100. Finger actuators 2360 may vertically move lifting fingers 2350 to load or unload backplane substrate 3000. Additionally, finger actuators 2360 may rotate lifting fingers 2350 relative to each of the plurality of drive shafts 2362. In an embodiment, for example, finger actuators 2360 may rotate lifting fingers 2350 such that the ends of lifting fingers 2350 do not overlap with substrate chuck 2300 and mask chuck 2400, thereby enabling vertical movement of lifting fingers 2350. Additionally, the finger actuator 2360 can rotate to lift the finger 2350 such that the end of the lifting finger 2350 overlaps with the edge portion of the backplate base 3000 to support the edge portion of the backplate base 3000.

[0260] The deposition mask 4000 can be loaded into the process chamber 2100 by a transfer robot and can be transferred over the mask chuck 2400 onto the lifting finger 2350. An edge portion of the deposition mask 4000 can be positioned on the end of the lifting finger 2350, and the finger driver 2360 can lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. In this case, a recess (not shown) into which the end of the lifting finger 2350 is inserted can be provided at the edge portion of the mask chuck 2400, and the finger driver 2360 can rotate the lifting finger 2350 such that the lifting finger 2350 does not overlap with the mask chuck 2400 after the deposition mask 4000 is loaded onto the mask chuck 2400.

[0261] The mask chuck 2400 can support the edge portion of the deposition mask 4000. In an embodiment, for example, the mask chuck 2400 can be an electrostatic chuck configured to hold the edge portion of the deposition mask 4000 using electrostatic force. Specifically, the mask chuck 2400 can define a circular opening to expose the deposition mask 4000 toward the deposition source 2200. In an embodiment, for example, the mask chuck 2400 can have a disk shape or a quadrilateral plate shape with a circular opening.

[0262] The deposition apparatus 2000 may include chuck drivers for adjusting the position and orientation of the backplane substrate 3000 and the deposition mask 4000. In embodiments, for example, the deposition apparatus 2000 may include a substrate chuck driver 2500 for moving the substrate chuck 2300 and a mask chuck driver 2600 for moving the mask chuck 2400.

[0263] The base chuck driver 2500 can move the base chuck 2300 in a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplane base 3000. In this case, the first direction DR1 can be a first horizontal direction, the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1, and the third direction DR3 can be a vertical direction. In an embodiment, for example, the first direction DR1, the second direction DR2, and the third direction DR3 can be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0264] The base chuck actuator 2500 can rotate the base chuck 2300 about the Z-axis to adjust the azimuth angle of the backplate base 3000, that is, the angle at which the backplate base 3000 is held on the bottom surface of the base chuck 2300. Furthermore, the base chuck actuator 2500 can rotate the base chuck 2300 about the X-axis and also about the Y-axis to adjust the tilt of the backplate base 3000. In an embodiment, for example, the base chuck actuator 2500 may include a hexapod actuator 2510 that provides movement in six degrees of freedom (X, Y, Z, θx, θy, and θz).

[0265] The base chuck driver 2500 may include a base stage 2520 on which a hexapod actuator 2510 is disposed (e.g., mounted) and a second actuator 2530 connected to the base stage 2520. The base stage 2520 may be horizontally disposed in the process chamber 2100, and the second actuator 2530 may be disposed above the process chamber 2100. The second actuator 2530 may be connected to the base stage 2520 via a plurality of drive shafts 2532 extending in a third direction DR3 (i.e., vertical direction) through the top cover of the process chamber 2100, and the second actuator 2530 may move the base stage 2520 in the direction of the central axis of the hexapod actuator 2510 (i.e., vertical direction). In embodiments, for example, the second actuator 2530 may be configured using a brushless DC (“DC”) motor, a linear motor, or a direct drive (“DD”) motor, and the height of the base chuck 2300 may be adjusted for loading or unloading the backplane base 3000.

[0266] The hexa-legged actuator 2510 may include a first platform connected to the base chuck 2300, a second platform disposed (e.g., mounted) to the base stage 2520, and six sub-actuators disposed between the first and second platforms. In embodiments, for example, the six sub-actuators may each be configured using a brushless DC motor, a voice coil linear motor, a stepper motor, a DD motor, or a servo motor, and may move and rotate the first platform to adjust the horizontal position, vertical position, azimuth angle, and tilt of the backplate base 3000.

[0267] The mask chuck driver 2600 can move and rotate the mask chuck 2400 to adjust the horizontal position and azimuth angle of the deposition mask 4000 (i.e., the angle at which the deposition mask 4000 is positioned on the mask chuck 2400). The mask chuck driver 2600 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and rotate the mask chuck 2400 relative to its central axis. In embodiments, for example, the mask chuck driver 2600 can move the mask chuck 2400 in a first direction DR1 (X-axis direction) and a second direction DR2 (Y-axis direction), and can rotate the mask chuck 2400 relative to a third direction DR3 (Z-axis direction). The mask chuck driver 2600 may include, for example, a piezoelectric actuator 2610 providing motion with three degrees of freedom (X, Y, and θz). The piezoelectric actuator 2610 can define an opening that communicates with the circular opening of the mask chuck 2400.

[0268] The mask chuck driver 2600 may also include a mask stage 2620 horizontally disposed in the process chamber 2100 and supporting the piezoelectric actuator 2610. In embodiments, for example, the mask stage 2620 may define an opening communicating with the opening of the piezoelectric actuator 2610 and may be supported by a plurality of pillars 2622 connected to a top cover of the process chamber 2100.

[0269] Figure 15 It is shown Figure 14 A schematic bottom view of the backplate base shown.

[0270] Reference Figure 15 The back panel base 3000 may include multiple display unit areas 3010 and scribe lines 3020 disposed between the display unit areas 3010. For example... Figure 15 As shown, the display unit area 3010 can be arranged in a matrix along the first direction DR1 and the second direction DR2, and can be individualized into the display panel 100 by a cutting process after the display manufacturing process is completed (see reference). Figure 3 In an embodiment, for example, the first direction DR1 may be a first horizontal direction, and the second direction DR2 may be a second horizontal direction perpendicular to the first direction DR1. Additionally, each of the plurality of display unit areas 3010 may have, for example, as shown in the example... Figure 15 The quadrilateral shape shown.

[0271] In an embodiment, for example, each of the plurality of display unit areas 3010 may include, for example, Figure 9The diagram shows a semiconductor backplane SBP, a light-emitting element backplane EBP disposed on the semiconductor backplane SBP, a reflective electrode RL disposed on the light-emitting element backplane EBP, and interlayer insulating films INS10 and INS11. Additionally, each of the plurality of display unit regions 3010 may include a plurality of electrode patterns (e.g., a plurality of first electrodes AND disposed on the eleventh interlayer insulating film INS11), and the first electrodes AND can be connected to the reflective electrode RL through a plurality of tenth vias VA10. In this case, the electrode patterns of the display unit regions 3010 can be arranged on the front surface of the backplane substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplane substrate 3000 such that the electrode patterns of the display unit regions 3010 face downwards, i.e., facing the deposition source 2200.

[0272] Figure 16 It is shown Figure 14 A schematic plan view of the deposition mask shown. Figure 17 It is shown Figure 16 A schematic enlarged plan view of the mask unit area shown. Figure 18 It is along Figure 17 The diagram shows a schematic cross-section taken by line I2-I2'.

[0273] Reference Figures 16 to 18 The deposition mask 4000 may include a backing substrate 3000 (see reference). Figure 15 The display unit area 3010 (refer to) Figure 15 The corresponding mask unit area 4310 and the scribing area 3020 corresponding to the backplate substrate 3000 (refer to) Figure 15 The corresponding grid area 4320. Each of the plurality of mask unit areas 4310 can define a first electrode AND (refer to) that exposes the backplane substrate 3000 during the deposition process. Figure 9 The deposition mask 4000 may include a mask substrate 4100, an intermediate inorganic film 4200 disposed on the mask substrate 4100, and a film 4300 disposed on the intermediate inorganic film 4200. In this case, the film 4300 may include a plurality of mask unit regions 4310 and a grid region 4320 surrounding the mask unit regions 4310, and each of the plurality of mask unit regions 4310 may define a plurality of pixel openings 4312.

[0274] The mask substrate 4100 may define unit openings 4110 corresponding to the mask unit regions 4310, and may include rib regions 4120 defining the unit openings 4110. The intermediate inorganic film 4200 may define intermediate openings 4210 respectively arranged on the unit openings 4110. In this case, the mask unit regions 4310 of the film 4300 may be arranged above the intermediate openings 4210, and the pixel openings 4312 of the film 4300 may communicate with the unit openings 4110 through the intermediate openings 4210.

[0275] In an embodiment, the mask unit region 4310 of the diaphragm 4300 can face the deposition source 2200 (see reference) through the unit opening 4110 of the mask substrate 4100 and the intermediate opening 4210 of the intermediate inorganic membrane 4200. Figure 14 The pixel opening 4312 can be formed to penetrate the mask unit area 4310. In this case, when performing the deposition process, the vapor deposition material provided from the deposition source 2200 can be deposited on the first electrode AND of the backplane substrate 3000 through the unit opening 4110, the intermediate opening 4210 and the pixel opening 4312.

[0276] like Figure 16 As shown, mask unit regions 4310 can be arranged in a matrix along a first direction DR1 and a second direction DR2. In an embodiment, for example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. For example, mask unit regions 4310 can have the following characteristics: Figure 16 The quadrilateral shape shown, and the pixel opening 4312 can be arranged with the first emission region EA1 (see reference). Figure 9 ), second launch area EA2 (refer to) Figure 9 ) and the third launch area EA3 (refer to Figure 9 The first electrode of any one of them corresponds to AND.

[0277] The mask substrate 4100 may include monocrystalline silicon. In an embodiment, for example, a monocrystalline silicon substrate having a thickness in the range of about 700 micrometers (μm) to about 800 μm (e.g., about 775 μm) may be used as the mask substrate 4100.

[0278] Intermediate inorganic film 4200 and film 4300 may be disposed on the front surface of mask substrate 4100, and second intermediate inorganic film 4400 and rear inorganic film 4500 may be disposed on the rear surface of mask substrate 4100. In an embodiment, for example, second intermediate inorganic film 4400 may be disposed on the rear surface of mask substrate 4100, and rear inorganic film 4500 may be disposed on second intermediate inorganic film 4400. Second intermediate inorganic film 4400 and rear inorganic film 4500 may define a second intermediate opening 4410 and a rear opening 4510 respectively communicating with unit opening 4110, and rear inorganic film 4500 may be used as an etching mask in an etching process for defining unit opening 4110. In this case, mask unit region 4310 may be exposed toward deposition source 2200 through intermediate opening 4210, unit opening 4110, second intermediate opening 4410 and rear opening 4510.

[0279] In an embodiment, the diaphragm 4300 may comprise a material having etch selectivity relative to the intermediate inorganic film 4200 and the mask substrate 4100. In an embodiment, for example, the intermediate inorganic film 4200 may comprise silicon oxide (SiO2). x Furthermore, the diaphragm 4300 may include silicon nitride (SiN). x In an embodiment, the intermediate inorganic film 4200 may comprise the same material as the second intermediate inorganic film 4400, and the film sheet 4300 may comprise the same material as the post-inorganic film 4500. In an embodiment, for example, the intermediate inorganic film 4200 and the second intermediate inorganic film 4400 may be formed simultaneously by a thermal oxidation process, and the film sheet 4300 and the post-inorganic film 4500 may be formed simultaneously by a chemical vapor deposition (“CVD”) process.

[0280] The pixel opening 4312 of the film 4300 can be defined by an anisotropic etching process (e.g., reactive ion etching (“RIE”) process). In an embodiment, for example, after forming a photoresist pattern on the film 4300 that exposes the portion to define the pixel opening 4312, a RIE process using the photoresist pattern as an etching mask can be performed to define the pixel opening 4312 that exposes the intermediate inorganic film 4200. In this case, the pixel opening 4312 can be defined to penetrate the film 4300, and the intermediate inorganic film 4200 can be used as an etch stop film in the RIE process.

[0281] The second intermediate opening 4410 and the rear opening 4510 can be defined by an anisotropic etching process (e.g., a RIE process). In an embodiment, for example, after forming a photoresist pattern on the rear inorganic film 4500 that exposes the portion that will define the rear opening 4510, a RIE process using the photoresist pattern as an etching mask can be performed to define the second intermediate opening 4410 and the rear opening 4510 that expose the rear surface of the mask substrate 4100.

[0282] The unit opening 4110 of the mask substrate 4100 can be defined as exposing the intermediate inorganic film 4200 using an anisotropic etching process that employs a second intermediate inorganic film 4400 and a post-inorganic film 4500 as an etching mask. In embodiments, for example, a monocrystalline silicon substrate can be used as the mask substrate 4100, and the unit opening 4110 can be defined by a wet etching process using an etchant such as a tetramethylammonium hydroxide (“TMAH”) solution or a potassium hydroxide (“KOH”) solution. In this case, the monocrystalline silicon substrate used as the mask substrate 4100... <100> The crystal orientation can be a third orientation DR3, and therefore, the unit opening 4110 can have a width that gradually decreases from the rear surface of the mask substrate 4100 toward the front surface of the mask substrate 4100 by a wet etching process. In an embodiment, for example, the inner surface of the unit opening 4110 can have an inclination of approximately 54.74° relative to the rear surface of the mask substrate 4100.

[0283] In another embodiment, the unit opening 4110 of the mask substrate 4100 can be defined by a deep DRIE process or a low-temperature etching process. In this case, the unit opening 4110 can extend on the third-direction DR3 and can have a constant width.

[0284] The intermediate opening 4210 of the intermediate inorganic film 4200 can be defined by a wet etching process after defining the unit opening 4110 of the mask substrate 4100. In an embodiment, for example, when the intermediate inorganic film 4200 comprises silicon oxide (SiO2), x When the intermediate opening 4210 is defined, it can be defined by a wet etching process using an etchant such as a buffer oxide etchant (“BOE”) or diluted hydrofluoric acid (“HF”). As a result, the pixel opening 4312 of the film 4300 can be connected to the unit opening 4110 of the mask substrate 4100 through the intermediate opening 4210 of the intermediate inorganic film 4200.

[0285] In another embodiment, the second intermediate inorganic film 4400 can be omitted. In this case, the rear inorganic film 4500 can be disposed on the rear surface of the mask substrate 4100. Additionally, the intermediate inorganic film 4200 can be formed by a thermal oxidation process or a CVD process, and the rear inorganic film 4500 can be formed simultaneously with the film 4300 or separately from the film 4300. As another example, both the intermediate inorganic film 4200 and the second intermediate inorganic film 4400 can be omitted. In this case, the film 4300 can be disposed on the front surface of the mask substrate 4100, and the rear inorganic film 4500 can be disposed on the rear surface of the mask substrate 4100. Additionally, the rear inorganic film 4500 can be formed simultaneously with the film 4300 or separately from the film 4300.

[0286] Figure 19 It is shown Figure 14 The diagram shows a schematic cross-sectional view of the base chuck and mask chuck. Figure 20 It is shown Figure 19 A schematic plan view of the mask chuck shown.

[0287] Reference Figures 14 to 16 , Figure 19 and Figure 20 The deposition apparatus 2000 in the embodiment may further include a grid support 2410 for supporting the mask unit area 4310 and the grid area 4320 of the deposition mask 4000. In the embodiment, for example, the grid support 2410 may include a rib area 4120 for supporting the mask substrate 4100 (see reference). Figure 18 The mask base 2400 includes a mesh plate 2412, a support ring 2414 extending downward from the edge portion of the mesh plate 2412, and a flange 2416 surrounding the lower portion of the support ring 2414. In an embodiment, for example, the mesh plate 2412 may have a disk shape and may define an opening 2418 corresponding to a unit opening 4110 of the mask base 4100. In this case, the mesh plate 2412 and the support ring 2414 may be disposed in the mask chuck 2400, and the mask chuck 2400 may be disposed on the flange 2416. Furthermore, the flange 2416 of the mesh support 2410 may be disposed on the piezoelectric actuator 2610 of the mask chuck driver 2600.

[0288] After the backplane substrate 3000 and the deposition mask 4000 are mounted onto the substrate chuck 2300 and the mask chuck 2400, respectively, the substrate chuck driver 2500 can position the backplane substrate 3000 onto the deposition mask 4000. In an embodiment, for example, a second actuator 2530 can lower the substrate chuck 2300 so that the backplane substrate 3000 is close to (adjacent to) the deposition mask 4000. A hexapod actuator 2510 can adjust the gap between the backplane substrate 3000 and the deposition mask 4000, and can adjust the tilt of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400.

[0289] In an embodiment, the deposition apparatus 2000 may further include a plurality of gap sensors 2700 for measuring the gap between the substrate chuck 2300 and the mask chuck 2400. In an embodiment, for example, the plurality of gap sensors 2700 for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 may be arranged on an edge portion of the substrate chuck 2300, and the gap sensors 2700 may measure the distance to the mask chuck 2400 via through-holes 2310 penetrating the edge portion of the substrate chuck 2300.

[0290] The hexapod actuator 2510 can adjust the parallelism between the base chuck 2300 and the mask chuck 2400 based on measurements from the gap sensor 2700. In an embodiment, for example, the hexapod actuator 2510 can adjust the height of the base chuck 2300 to a first height such that the gap between the backplate substrate 3000 and the deposition mask 4000 becomes several hundred μm (e.g., approximately 100 μm to approximately 200 μm), and can adjust the tilt of the base chuck 2300 based on measurements from the gap sensor 2700. In an embodiment, for example, a capacitive proximity sensor or a confocal sensor can be used as the gap sensor 2700, and the hexapod actuator 2510 can adjust the parallelism between the base chuck 2300 and the mask chuck 2400 by adjusting the tilt of the base chuck 2300. As a result, the parallelism between the backplate substrate 3000 supported by the base chuck 2300 and the deposition mask 4000 supported by the mask chuck 2400 can be adjusted.

[0291] In an embodiment, at least one first measurement electrode 3100 may be disposed on a backplane substrate 3000, and at least one second measurement electrode 4600 corresponding to the first measurement electrode 3100 on the backplane substrate 3000 may be disposed on a deposition mask 4000. In an embodiment, for example, as Figure 15 As shown, four first measuring electrodes 3100 can be arranged on the backplate substrate 3000, and as... Figure 16As shown, four second measurement electrodes 4600 can be arranged on the deposition mask 4000. However, the number of first measurement electrodes 3100 and the number of second measurement electrodes 4600 can be varied, and the scope of this disclosure is not limited thereto.

[0292] In an embodiment, when the backplane substrate 3000 is disposed on the deposition mask 4000, a capacitor may be formed between the backplane substrate 3000 and the deposition mask 4000. In an embodiment, for example, a capacitor 3500 (see reference 3500) includes a first measurement electrode 3100 and a second measurement electrode 4600. Figure 24 and Figure 25 The backplane substrate 3000 and the deposition mask 4000 can be formed between the backplane substrate 3000 and the deposition mask 4000. In an embodiment, the backplane substrate 3000 and the deposition mask 4000 can be aligned with each other based on the capacitance between the first measurement electrode 3100 and the second measurement electrode 4600.

[0293] In an embodiment, such as Figure 15 As shown, the first measurement electrode 3100 can be disposed on the scribing area 3020 of the backplane substrate 3000. In an embodiment, for example, the first measurement electrode 3100 can be disposed on the pixel defining film PDL (see reference) of the backplane substrate 3000. Figure 9 The first measuring electrode 3100 may be a conductive material such as a metal, metal oxide, or metal nitride. In embodiments, for example, the first measuring electrode 3100 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or transparent conductive oxide containing any of them. In embodiments, for example, the first measuring electrode 3100 may include aluminum (Al) or a transparent conductive oxide such as ITO, ZnO, or IZO. Furthermore, for example, each of the plurality of first measuring electrodes 3100 may have a quadrilateral shape (e.g., a rectangular shape), a circular shape, or a strip shape extending in a first direction DR1 or a second direction DR2 in a planar view.

[0294] The first contact pad 3110 may be disposed on an edge portion of the backplane substrate 3000, and the first measuring electrode 3100 and the first contact pad 3110 may be connected to each other via a first connecting line 3120. In an embodiment, for example, the first connecting line 3120 may extend along a scribing area 3020 of the backplane substrate 3000. The first contact pad 3110 and the first connecting line 3120 may comprise the same material as the first measuring electrode 3100. In an embodiment, for example, the first contact pad 3110 and the first connecting line 3120 may be formed simultaneously with the first measuring electrode 3100.

[0295] In one embodiment, for example, a conductive material layer (not shown) may be formed on a pixel-defining film (PDL), and the first measurement electrode 3100, the first contact pad 3110, and the first interconnect 3120 may be formed on the PDL by patterning the conductive material layer. The conductive material layer may be patterned using photolithography and anisotropic etching processes. In another embodiment, the first measurement electrode 3100, the first contact pad 3110, and the first interconnect 3120 may be formed using a damascene process.

[0296] In another embodiment, the first measuring electrode 3100, the first contact pad 3110, and the first connection line 3120 may include an image light-emitting element LE (see reference). Figure 9 The first electrode AND (refer to) Figure 9 The material is the same as that used for the light-emitting element LE. In an embodiment, for example, the first measuring electrode 3100, the first contact pad 3110, and the first connecting line 3120 may be formed simultaneously with the first electrode AND of the light-emitting element LE. In this case, a pixel defining film PDL may be disposed on the first measuring electrode 3100, the first contact pad 3110, and the first connecting line 3120, and may define an opening (not shown) exposing the first contact pad 3110.

[0297] In an embodiment, such as Figure 16 As shown, a second measurement electrode 4600 corresponding to the first measurement electrode 3100 can be disposed on the deposition mask 4000. The position of the second measurement electrode 4600 on the deposition mask 4000 can be the same as the position of the first measurement electrode 3100 on the backplane substrate 3000. In an embodiment, for example, the second measurement electrode 4600 can be disposed on the grid region 4320 of the deposition mask 4000 to correspond to the first measurement electrode 3100 respectively, and can have a thickness of tens of nm to hundreds of nm.

[0298] The second measuring electrode 4600 may include a conductive material such as a metal, metal oxide, or metal nitride. In embodiments, for example, the second measuring electrode 4600 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or transparent conductive oxide containing any of them. In embodiments, for example, the second measuring electrode 4600 may include aluminum (Al) or a transparent conductive oxide such as ITO, ZnO, or IZO. Furthermore, the second measuring electrode 4600 may have the same shape and area as the first measuring electrode 3100. In embodiments, for example, each of the plurality of second measuring electrodes 4600 may have a quadrilateral shape (e.g., a rectangular shape), a circular shape, or a strip shape extending in the first direction DR1 or the second direction DR2 in a planar view.

[0299] The second contact pad 4610 may be disposed on an edge portion of the deposition mask 4000, and the second measurement electrode 4600 and the second contact pad 4610 may be connected to each other via a second connection line 4620. In an embodiment, for example, the second connection line 4620 may extend along a grid region 4320 of the deposition mask 4000. The second contact pad 4610 and the second connection line 4620 may comprise the same material as the second measurement electrode 4600. In an embodiment, for example, the second contact pad 4610 and the second connection line 4620 may be formed simultaneously with the second measurement electrode 4600.

[0300] In an embodiment, for example, a conductive material layer (not shown) may be formed on the film 4300 (see reference). Figure 18 The second measuring electrode 4600, the second contact pad 4610, and the second connection line 4620 can be formed on the film 4300 by patterning a conductive material layer. The conductive material layer can be patterned by photolithography and anisotropic etching processes. In another embodiment, the second measuring electrode 4600, the second contact pad 4610, and the second connection line 4620 can be formed by an inlay process.

[0301] In another embodiment, the second measuring electrode 4600, the second contact pad 4610, and the second connecting line 4620 may be disposed on the intermediate inorganic film 4200. In this embodiment, for example, a conductive material layer (not shown) may be formed on the intermediate inorganic film 4200, and the second measuring electrode 4600, the second contact pad 4610, and the second connecting line 4620 may be formed on the intermediate inorganic film 4200 by patterning the conductive material layer. In this case, a diaphragm 4300 may be disposed on the second measuring electrode 4600, the second contact pad 4610, the second connecting line 4620, and the intermediate inorganic film 4200.

[0302] Reference Figure 19 and Figure 20 The deposition apparatus 2000 may also include a sensor 2800 (or a capacitance sensor) for measuring the capacitance between the first measuring electrode 3100 and the second measuring electrode 4600. In an embodiment, for example, the sensor 2800 may be disposed in a mask chuck 2400 and may be electrically connected to the first contact pad 3110 and the second contact pad 4610.

[0303] Figure 21 It is shown Figure 19 and Figure 20 The diagram shows a schematic enlarged cross-sectional view of the sensor. Figure 22 It is shown Figure 21 The diagram shows a schematic enlarged cross-sectional view of the through opening. Figure 23 It is shown Figure 21 A schematic enlarged cross-sectional view of the contact opening shown.

[0304] Reference Figures 19 to 23 The slot 2420 into which the sensor 2800 is inserted may be located at the edge portion of the mask chuck 2400. In an embodiment, the sensor 2800 may include a first probe pin 2810 for connection to a first measuring electrode 3100 and a second probe pin 2820 for connection to a second measuring electrode 4600. Furthermore, the deposition mask 4000 may define a through opening 4010 into which the first probe pin 2810 is inserted and a contact opening 4020 into which the second probe pin 2820 is inserted. In an embodiment, for example, the deposition mask 4000 may be placed on the mask chuck 2400 such that the through opening 4010 and the contact opening 4020 are defined on the sensor 2800, and the first probe pin 2810 and the second probe pin 2820 may be inserted into the through opening 4010 and the contact opening 4020, respectively.

[0305] The through-opening 4010 can penetrate the edge portion of the deposition mask 4000. When the backplane substrate 3000 is disposed on the deposition mask 4000, the first probe pin 2810 can pass through the through-opening 4010 to contact the first contact pad 3110 of the backplane substrate 3000, so that the first measuring electrode 3100 and the sensor 2800 can be electrically connected to each other. The through-opening 4010 can penetrate the rear inorganic film 4500, the second intermediate inorganic film 4400, the mask substrate 4100, the intermediate inorganic film 4200, and the diaphragm 4300 of the deposition mask 4000. In an embodiment, for example, as Figure 22As shown, the through opening 4010 can define a first through opening 4520 penetrating the inorganic membrane 4500, a second through opening 4420 penetrating the second intermediate inorganic membrane 4400, a third through opening 4130 penetrating the mask substrate 4100, a fourth through opening 4220 penetrating the intermediate inorganic membrane 4200, and a fifth through opening 4330 penetrating the membrane 4300. In an embodiment, for example, combined with Figure 18 The fifth through opening 4330 can be defined simultaneously with the pixel opening 4312, and the first through opening 4520 and the second through opening 4420 can be defined simultaneously with the rear opening 4510 and the second intermediate opening 4410. The third through opening 4130 can be defined simultaneously with the unit opening 4110, and the fourth through opening 4220 can be defined simultaneously with the intermediate opening 4210.

[0306] In another embodiment, although not shown, the through-hole 4010 may be pre-provided at the monocrystalline silicon substrate serving as the mask substrate 4100. In an embodiment, for example, the through-hole 4010 may be pre-defined by a laser dicing process when the monocrystalline silicon substrate is in a bare wafer state. In another embodiment, the through-hole 4010 may be defined by a laser dicing process after the deposition mask 4000 has been fabricated. In another embodiment, although not shown, instead of the through-hole 4010, a recess (not shown) may be defined at a side portion of the deposition mask 4000 by a laser dicing process.

[0307] Contact opening 4020 may be defined adjacent to through opening 4010. Contact opening 4020 may penetrate the post-inorganic film 4500, the second intermediate inorganic film 4400, the mask substrate 4100, and the intermediate inorganic film 4200 of deposition mask 4000, and may expose film 4300 and second contact pad 4610. In embodiments, for example, as Figure 23 As shown, the contact opening 4020 may include a first contact opening 4530 penetrating the inorganic membrane 4500, a second contact opening 4430 penetrating the second intermediate inorganic membrane 4400, a third contact opening 4140 penetrating the mask substrate 4100, and a fourth contact opening 4230 penetrating the intermediate inorganic membrane 4200. In an embodiment, for example, combined with Figure 18 The first contact opening 4530 and the second contact opening 4430 may be defined simultaneously with the rear opening 4510 and the second intermediate opening 4410. The third contact opening 4140 may be defined simultaneously with the unit opening 4110, and the fourth contact opening 4230 may be defined simultaneously with the intermediate opening 4210.

[0308] In an embodiment, the diaphragm 4300 may define a pad opening 4340. In an embodiment, for example, the pad opening 4340 may be defined by an anisotropic etching process such as RIE to expose the intermediate inorganic film 4200, and a conductive material layer for forming the second contact pad 4610 may be formed to fill the pad opening 4340. The conductive material layer may be patterned such that the second contact pad 4610 is disposed on the pad opening 4340, and the contact opening 4020 may be defined to expose the second contact pad 4610. In an embodiment, for example, after forming the second contact pad 4610, a first contact opening 4530, a second contact opening 4430, a third contact opening 4140, and a fourth contact opening 4230 may be defined sequentially.

[0309] In one embodiment, the deposition mask 4000 can be placed on the mask chuck 2400 such that the second probe pin 2820 is inserted into the contact opening 4020. In this case, the second probe pin 2820 can contact the second contact pad 4610 exposed through the contact opening 4020, so that the second measuring electrode 4600 and the sensor 2800 can be electrically connected to each other.

[0310] In an embodiment, such as Figure 20 and Figure 21 As shown, the sensor 2800 has a strip shape extending in the second direction DR2, but the shape of the sensor 2800 can be varied, and the scope of this disclosure is not limited to the shape of the sensor 2800.

[0311] In an embodiment, for example, after adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 to a second height, such that the gap between the backplate substrate 3000 and the deposition mask 4000 becomes tens of μm, for example, approximately 10 μm to approximately 50 μm. In an embodiment, for example, the hexapod actuator 2510 can adjust the height of the backplate substrate 3000, such that the gap between the first measuring electrode 3100 and the second measuring electrode 4600 becomes tens of μm, for example, approximately 10 μm to approximately 50 μm.

[0312] In an embodiment, after the height of the base chuck 2300 is adjusted to the second height, the parallelism between the base chuck 2300 and the mask chuck 2400 can be adjusted a second time. In an embodiment, for example, although not shown, a plurality of second gap sensors (not shown) can be arranged on the edge portion of the base chuck 2300, and the second gap sensors can measure the distance to the mask chuck 2400 through through-holes penetrating the edge portion of the base chuck 2300. The hexapod actuator 2510 can adjust the tilt of the base chuck 2300 based on the measurements of the second gap sensors, allowing for a second adjustment of the parallelism between the base chuck 2300 and the mask chuck 2400. In this case, the second gap sensor can have a higher resolution than the gap sensor 2700. In an embodiment, for example, a capacitive proximity sensor can be used as the gap sensor 2700, and a confocal sensor can be used as the second gap sensor. By adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 as described above, the parallelism between the backing substrate 3000 and the deposition mask 4000 can be adjusted more precisely.

[0313] Figure 24 and Figure 25 It is shown Figure 15 and Figure 16 The diagram shows the first and second measuring electrodes facing each other.

[0314] Reference Figure 24 and Figure 25 When the backplane substrate 3000 is disposed on the deposition mask 4000 as described above, the first measurement electrode 3100 and the second measurement electrode 4600 can face each other, thereby forming a capacitor 3500 including the first measurement electrode 3100 and the second measurement electrode 4600 between the backplane substrate 3000 and the deposition mask 4000. When the first measurement electrode 3100 and the second measurement electrode 4600 face each other, the capacitance between the first measurement electrode 3100 and the second measurement electrode 4600 can be proportional to the area of ​​the first measurement electrode 3100 and the second measurement electrode 4600 facing each other. In an embodiment, for example, as Figure 24 As shown, when the first measuring electrode 3100 and the second measuring electrode 4600 are misaligned on the third-direction DR3, the capacitance between the first measuring electrode 3100 and the second measuring electrode 4600 may decrease, and as... Figure 25 As shown, when the first measuring electrode 3100 and the second measuring electrode 4600 are aligned with each other on the third-direction DR3, the capacitance between the first measuring electrode 3100 and the second measuring electrode 4600 can be increased.

[0315] In an embodiment, the capacitance (capacitance value) between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured to align the backplane substrate 3000 and the deposition mask 4000 with each other. Furthermore, the azimuth and position of the backplane substrate 3000 and / or the deposition mask 4000 can be adjusted to maximize the capacitance (capacitance value) between the first measuring electrode 3100 and the second measuring electrode 4600, thereby aligning the backplane substrate 3000 and the deposition mask 4000 with each other. In an embodiment, for example, combined with... Figure 14 The hexapod actuator 2510 can rotate and horizontally move the base chuck 2300, maximizing the capacitance between the first measuring electrode 3100 and the second measuring electrode 4600. In another embodiment, the piezoelectric actuator 2610 can rotate and horizontally move the mask chuck 2400, maximizing the capacitance between the first measuring electrode 3100 and the second measuring electrode 4600.

[0316] In some embodiments, for example, the gap between the backplane substrate 3000 and the deposition mask 4000 can remain constant while aligning them together. In some embodiments, for example, the height of the substrate chuck 2300 (i.e., the position of the substrate chuck 2300 on the third-direction DR3) can remain constant while aligning the backplane substrate 3000 and the deposition mask 4000 together.

[0317] Figures 26 to 29 It shows the use Figure 15 and Figure 16 The diagram shows a schematic plan view of the method by which the first and second measuring electrodes align the backplane substrate and the deposition mask with each other.

[0318] Reference Figures 26 to 29 In one embodiment, the first measuring electrode 3100 and the second measuring electrode 4600 may each have a square shape and may have the same area (or size). In another embodiment, the first measuring electrode 3100 and the second measuring electrode 4600 may each have a circular shape and may have the same area (or size). In the embodiment, as... Figure 26 As shown, when the first measuring electrode 3100 and the second measuring electrode 4600 are not aligned with each other on the third-direction DR3 (i.e., when the first measuring electrode 3100 and the second measuring electrode 4600 partially overlap each other on the third-direction DR3), the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 may be different from each other.

[0319] In an embodiment, such as Figure 27 As shown and combined Figure 14The hexapod actuator 2510 can rotate the substrate chuck 2300 such that the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become all equal, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000. In an embodiment, for example, when the azimuth angle of the backplane substrate 3000 becomes equal to the azimuth angle of the deposition mask 4000, all areas of overlap between the first measuring electrode 3100 and the second measuring electrode 4600 on the third-direction DR3 can become identical, and therefore, all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 can become identical.

[0320] In an embodiment, the deposition apparatus 2000 may include a controller 2900 (see reference) for controlling the operation of a substrate chuck 2300, a mask chuck 2400, a substrate chuck driver 2500, or a mask chuck driver 2600, etc. Figure 14 In an embodiment, for example, it may be provided by sensor 2800 (see reference). Figure 19 The capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 is measured, and the controller 2900 can control the operation of the substrate chuck driver 2500 and / or the mask chuck driver 2600 based on the capacitance value measured by the sensor 2800. In an embodiment, the substrate chuck driver 2500 and the mask chuck driver 2600 can be collectively referred to as chuck drivers.

[0321] In an embodiment, for example, the hexapod actuator 2510 can rotate the substrate chuck 2300 in a clockwise or counterclockwise direction, and the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. While rotating the substrate chuck 2300, all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 can change, and the controller 2900 can detect the azimuth angle of the substrate chuck 2300 when all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become equal. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 such that the substrate chuck 2300 has the detected azimuth angle, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0322] In an embodiment, such as Figure 28 and Figure 29 As shown, the hexapod actuator 2510 can move the substrate chuck 2300 in the first direction DR1 and the second direction DR2, such that all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum, in order to perform position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0323] In an embodiment, for example, such as Figure 28 As shown, the hexapod actuator 2510 can move the substrate chuck 2300 in the first direction DR1, and the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. While moving the substrate chuck 2300 in the first direction DR1, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can change, and the controller 2900 can detect the first-direction position of the substrate chuck 2300 where all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 so that the substrate chuck 2300 is moved to the detected first-direction position, thereby enabling alignment of the first-direction position between the backplane substrate 3000 and the deposition mask 4000.

[0324] In addition, such as Figure 29 As shown, the hexapod actuator 2510 can move the substrate chuck 2300 in the second direction DR2, and the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. While moving the substrate chuck 2300 in the second direction DR2, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can change, and the controller 2900 can detect the second-direction position of the substrate chuck 2300 where all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 so that the substrate chuck 2300 is moved to the detected second-direction position, thereby enabling second-direction position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0325] In another embodiment, the piezoelectric actuator 2610 can rotate the mask chuck 2400 such that the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become all equal, to perform azimuth alignment between the backplane substrate 3000 and the deposition mask 4000. Furthermore, the piezoelectric actuator 2610 can move the mask chuck 2400 in a first direction DR1 and a second direction DR2 such that all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum, to perform positional alignment between the backplane substrate 3000 and the deposition mask 4000. In this case, the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800, and the operation of the piezoelectric actuator 2610 can be controlled by the controller 2900.

[0326] In another embodiment, azimuth alignment and position alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed by a hexapod actuator 2510 and a piezoelectric actuator 2610. In this embodiment, for example, the hexapod actuator 2510 can rotate the substrate chuck 2300, and simultaneously, the piezoelectric actuator 2610 can move the mask chuck 2400. In this case, the controller 2900 can detect the azimuth of the backplane substrate 3000 and the position of the deposition mask 4000 when all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum. In an alternative embodiment, the hexapod actuator 2510 can move the substrate chuck 2300, and simultaneously, the piezoelectric actuator 2610 can rotate the mask chuck 2400. In this case, the controller 2900 can detect the position of the backplane substrate 3000 and the azimuth of the deposition mask 4000 when all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum.

[0327] Furthermore, as described above, after performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000, positional alignment between the backplane substrate 3000 and the deposition mask 4000 is performed. However, unlike the above, azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed after performing positional alignment between the backplane substrate 3000 and the deposition mask 4000.

[0328] In an embodiment, for example, the hexapod actuator 2510 can move the substrate chuck 2300 in a first direction DR1 and a second direction DR2, and the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. While moving the substrate chuck 2300 in the first direction DR1 and the second direction DR2, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can change, and the controller 2900 can detect the position of the substrate chuck 2300 when the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become all equal. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 so that the substrate chuck 2300 is moved to the detected position, thereby performing alignment between the backplane substrate 3000 and the deposition mask 4000.

[0329] Subsequently, the hexapod actuator 2510 can rotate the substrate chuck 2300 in a clockwise or counterclockwise direction, and the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. While rotating the substrate chuck 2300, all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 can change, and the controller 2900 can detect the azimuth angle of the substrate chuck 2300 when the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 becomes the maximum. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 so that the substrate chuck 2300 has the detected azimuth angle, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0330] In another embodiment, positional alignment and azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed by a mask chuck driver 2600. In another embodiment, for example, positional alignment and azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed sequentially by a piezoelectric actuator 2610.

[0331] Figure 30 It is shown Figure 15 A schematic bottom view of another embodiment of the backplate substrate shown. Figure 31 It is shown Figure 16 A schematic plan view of another embodiment of the deposition mask shown.

[0332] Reference Figure 30 The backplate substrate 3000 may include at least one first measuring electrode 3200 and at least one third measuring electrode 3230. In an embodiment, for example, the backplate substrate 3000 may include a first measuring electrode 3200 extending in a first direction DR1 and disposed on a scribing area 3020, and a third measuring electrode 3230 extending in a second direction DR2 and disposed on the scribing area 3020. As shown, the backplate substrate 3000 includes two first measuring electrodes 3200 and two third measuring electrodes 3230, but the number of first measuring electrodes 3200 and third measuring electrodes 3230 may be varied, and the scope of this disclosure is not limited thereto.

[0333] The backplane substrate 3000 may include a first contact pad 3210, a third contact pad 3240, a first connection line 3220, and a third connection line 3250. In an embodiment, for example, the first contact pad 3210 and the third contact pad 3240 may be disposed on an edge portion of the backplane substrate 3000. The first connection line 3220 may be disposed on a scribing area 3020 and may connect the first measuring electrode 3200 and the first contact pad 3210. The third connection line 3250 may be disposed on the scribing area 3020 and may connect the third measuring electrode 3230 and the third contact pad 3240.

[0334] In the embodiment, apart from the first measuring electrode 3200 and the third measuring electrode 3230, the first contact pad 3210 and the third contact pad 3240, and the first connection line 3220 and the third connection line 3250, the remaining (other) components of the backplane substrate 3000 are the same as those described above. Figure 15 The components described are essentially the same, so detailed descriptions of them will be omitted.

[0335] Reference Figure 31 The deposition mask 4000 may include at least one second measurement electrode 4700 and at least one fourth measurement electrode 4730. In an embodiment, for example, the deposition mask 4000 may include a second measurement electrode 4700 corresponding to a first measurement electrode 3200 and a fourth measurement electrode 4730 corresponding to a third measurement electrode 3230.

[0336] The second measurement electrode 4700 may be arranged at the same position as the first measurement electrode 3200 in a plan view, and may have the same shape and size as the first measurement electrode 3200. In an embodiment, for example, the second measurement electrode 4700 may be arranged on the grid area 4320 of the deposition mask 4000, and may have a quadrilateral shape (e.g., a rectangular shape) or a strip shape extending in the first direction DR1. The fourth measurement electrode 4730 may be arranged at the same position as the third measurement electrode 3230 in a plan view, and may have the same shape and size as the third measurement electrode 3230. In an embodiment, for example, the fourth measurement electrode 4730 may be arranged on the grid area 4320 of the deposition mask 4000, and may have a quadrilateral shape (e.g., a rectangular shape) or a strip shape extending in the second direction DR2. As shown, the deposition mask 4000 includes two second measurement electrodes 4700 and two fourth measurement electrodes 4730, but the number of second measurement electrodes 4700 and fourth measurement electrodes 4730 may be varied, and the scope of this disclosure is not limited thereto.

[0337] The deposition mask 4000 may include a second contact pad 4710, a fourth contact pad 4740, a second interconnect 4720, and a fourth interconnect 4750. In an embodiment, for example, the second contact pad 4710 and the fourth contact pad 4740 may be arranged on an edge portion of the deposition mask 4000. The second interconnect 4720 may be arranged on a grid area 4320 and may connect the second measurement electrode 4700 and the second contact pad 4710. The fourth interconnect 4750 may be arranged on a grid area 4320 and may connect the fourth measurement electrode 4730 and the fourth contact pad 4740.

[0338] In this embodiment, apart from the second measuring electrode 4700 and the fourth measuring electrode 4730, the second contact pad 4710 and the fourth contact pad 4740, and the second connection line 4720 and the fourth connection line 4750, the remaining (other) components of the deposition mask 4000 are the same as those described above. Figures 16 to 18 The components described are essentially the same, so detailed descriptions of them will be omitted.

[0339] Figure 32 It is shown Figure 20 A schematic plan view of another embodiment of the sensor shown.

[0340] Reference Figure 32 The deposition apparatus 2000 may include a first sensor 2830 for measuring the capacitance between a first measuring electrode 3200 and a second measuring electrode 4700, and a second sensor 2840 for measuring the capacitance between a third measuring electrode 3230 and a fourth measuring electrode 4730. In an embodiment, for example, the first sensor 2830 and the second sensor 2840 may be disposed in a mask chuck 2400, and for this purpose, slots into which the first sensor 2830 and the second sensor 2840 are respectively inserted may be provided at the edge portion of the mask chuck 2400.

[0341] The first sensor 2830 may include a first probe pin 2832 connected to a first contact pad 3210 and a second probe pin 2834 connected to a second contact pad 4710, and the deposition mask 4000 may define a first through opening 4030 through which the first probe pin 2832 passes and a first contact opening 4040 through which the second probe pin 2834 is inserted. The second sensor 2840 may include a third probe pin 2842 connected to a third contact pad 3240 and a fourth probe pin 2844 connected to a fourth contact pad 4740, and the deposition mask 4000 may define a second through opening 4032 through which the third probe pin 2842 passes and a second contact opening 4042 through which the fourth probe pin 2844 is inserted.

[0342] In the embodiment, each of the first sensor 2830 and the second sensor 2840 is referenced above. Figure 20 The sensor 2800 described is substantially the same, therefore a detailed description thereof will be omitted. Each of the first through opening 4030 and the second through opening 4032 is the same as described above. Figure 21 and Figure 22 The described through opening 4010 is substantially the same, therefore a detailed description thereof will be omitted. Additionally, each of the first contact opening 4040 and the second contact opening 4042 is the same as described above. Figure 21 and Figure 23 The described contact opening 4020 is essentially the same, so a detailed description of it will be omitted.

[0343] In another embodiment, although not shown, a sensor (not shown) can be used to measure the capacitance between the first measuring electrode 3200 and the second measuring electrode 4700, and the capacitance between the third measuring electrode 3230 and the fourth measuring electrode 4730. In this case, the sensor may include a first probe pin 2832 connected to the first contact pad 3210, a second probe pin 2834 connected to the second contact pad 4710, a third probe pin 2842 connected to the third contact pad 3240, and a fourth probe pin 2844 connected to the fourth contact pad 4740. Furthermore, the deposition mask 4000 may define a through-opening (not shown) through which the first probe pin 2832 and the third probe pin 2842 pass, and a contact opening (not shown) through which the second probe pin 2834 and the fourth probe pin 2844 are inserted.

[0344] Figures 33 to 36 It shows the use Figure 30 and Figure 31 The diagram shows a schematic plan view of a method by which the first, second, third, and fourth measuring electrodes align the backplane substrate and the deposition mask with each other.

[0345] Reference Figure 33 When the first measuring electrode 3200 and the second measuring electrode 4700 are misaligned with each other on the third-direction DR3, and when the third measuring electrode 3230 and the fourth measuring electrode 4730 are misaligned with each other on the third-direction DR3, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700 and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730 can be different from each other.

[0346] Reference Figure 34 and combined Figure 14The hexapod actuator 2510 can rotate the substrate chuck 2300, making the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700 equal, and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730 equal, to perform azimuth alignment between the backplane substrate 3000 and the deposition mask 4000. At this time, the capacitance value between the first measuring electrode 3200 and the second measuring electrode 4700 may differ from the capacitance value between the third measuring electrode 3230 and the fourth measuring electrode 4730.

[0347] In an embodiment, for example, when the azimuth angle of the backplane substrate 3000 becomes equal to the azimuth angle of the deposition mask 4000, the overlapping areas of the first measuring electrode 3200 and the second measuring electrode 4700 on the third-direction DR3 can become equal, and the overlapping areas of the third measuring electrode 3230 and the fourth measuring electrode 4730 on the third-direction DR3 can also become equal. Therefore, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700 can become equal, and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730 can also become equal.

[0348] In this embodiment, the capacitance value between the first measuring electrode 3200 and the second measuring electrode 4700 can be measured by the first sensor 2830, and the capacitance value between the third measuring electrode 3230 and the fourth measuring electrode 4730 can be measured by the second sensor 2840. The controller 2900 can control the operation of the hexapod actuator 2510 based on the capacitance values ​​measured by the first sensor 2830 and the second sensor 2840.

[0349] In an embodiment, for example, the hexapod actuator 2510 can rotate the substrate chuck 2300 in a clockwise or counterclockwise direction. While rotating the substrate chuck 2300, the capacitance value between the first measuring electrode 3200 and the second measuring electrode 4700 can be measured by the first sensor 2830, and the capacitance value between the third measuring electrode 3230 and the fourth measuring electrode 4730 can be measured by the second sensor 2840. The controller 2900 can detect the azimuth angle of the substrate chuck 2300 when the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700 become equal, and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730 become equal. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 such that the substrate chuck 2300 has the detected azimuth angle, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0350] In an embodiment, such as Figure 35 and Figure 36As shown, the hexapod actuator 2510 can move the substrate chuck 2300 in the first direction DR1 and the second direction DR2 such that all capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, as well as all capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730, become maximized to perform position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0351] In an embodiment, for example, such as Figure 35 As shown, the hexapod actuator 2510 can move the substrate chuck 2300 in the first direction DR1. While moving the substrate chuck 2300 in the first direction DR1, the capacitance value between the first measuring electrode 3200 and the second measuring electrode 4700 can be measured by the first sensor 2830, and the capacitance value between the third measuring electrode 3230 and the fourth measuring electrode 4730 can be measured by the second sensor 2840. The controller 2900 can detect the first direction position of the substrate chuck 2300 where all capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, as well as all capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730, are maximized. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500, causing the substrate chuck 2300 to be moved to the detected first direction position, thereby enabling alignment of the first direction position between the backplane substrate 3000 and the deposition mask 4000.

[0352] In addition, such as Figure 36 As shown, the hexapod actuator 2510 can move the substrate chuck 2300 in the second direction DR2. While moving the substrate chuck 2300 in the second direction DR2, the capacitance value between the first measuring electrode 3200 and the second measuring electrode 4700 can be measured by the first sensor 2830, and the capacitance value between the third measuring electrode 3230 and the fourth measuring electrode 4730 can be measured by the second sensor 2840. The controller 2900 can detect the second-direction position of the substrate chuck 2300 where all capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, as well as all capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730, are maximized. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500, causing the substrate chuck 2300 to be moved to the detected second-direction position, thereby enabling second-direction position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0353] In another embodiment, azimuth alignment and position alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed by the mask chuck driver 2600. In this case, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, can be measured by the first sensor 2830 and the second sensor 2840, respectively, and the controller 2900 can control the operation of the piezoelectric actuator 2610 based on the capacitance values ​​measured by the first sensor 2830 and the second sensor 2840.

[0354] In another embodiment, azimuth alignment and position alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed by a hexapod actuator 2510 and a piezoelectric actuator 2610. In this embodiment, for example, the hexapod actuator 2510 can rotate the substrate chuck 2300, and simultaneously, the piezoelectric actuator 2610 can move the mask chuck 2400. In this case, the controller 2900 can detect the azimuth of the backplane substrate 3000 and the position of the deposition mask 4000 where all capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and all capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730, become the largest. In an alternative embodiment, the hexapod actuator 2510 can move the substrate chuck 2300, and simultaneously, the piezoelectric actuator 2610 can rotate the mask chuck 2400. In this case, the controller 2900 can detect the position of the backplane substrate 3000 and the azimuth angle of the deposition mask 4000, where all capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, as well as between the third measuring electrode 3230 and the fourth measuring electrode 4730, become the largest.

[0355] Furthermore, as described above, after performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000, positional alignment between the backplane substrate 3000 and the deposition mask 4000 is performed. However, unlike the above, azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed after performing positional alignment between the backplane substrate 3000 and the deposition mask 4000.

[0356] In an embodiment, for example, the hexapod actuator 2510 can move the base chuck 2300 in the first direction DR1 and the second direction DR2, and can measure the capacitance value between the first measuring electrode 3200 and the second measuring electrode 4700, and the capacitance value between the third measuring electrode 3230 and the fourth measuring electrode 4730, through the first sensor 2830 and the second sensor 2840. While moving the base chuck 2300 in the first direction DR1 and the second direction DR2, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730, can change, and the controller 2900 can detect the position of the base chuck 2300 when the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700 become equal, and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730 become equal. In addition, the controller 2900 can control the operation of the substrate chuck driver 2500 so that the substrate chuck 2300 is moved to the detected position, thereby performing position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0357] Next, the hexapod actuator 2510 can rotate the base chuck 2300 clockwise or counterclockwise, and can measure the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, via the first sensor 2830 and the second sensor 2840. While rotating the base chuck 2300, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, can change, and the controller 2900 can detect the azimuth angle of the base chuck 2300 where all capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, become the largest. In addition, the controller 2900 can control the operation of the substrate chuck driver 2500 so that the substrate chuck 2300 has a detected azimuth angle, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0358] In another embodiment, positional alignment and azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed by a mask chuck driver 2600. In another embodiment, for example, positional alignment and azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed sequentially by a piezoelectric actuator 2610.

[0359] Figure 37 It is shown Figure 15A schematic bottom view of another embodiment of the backplate substrate shown. Figure 38 It is shown Figure 16 A schematic plan view of another embodiment of the deposition mask shown.

[0360] Reference Figure 37 The backplate substrate 3000 may include a first measuring electrode 3300 and at least one third measuring electrode 3330. In an embodiment, for example, the backplate substrate 3000 may include a first measuring electrode 3300 disposed on an edge portion and having an annular shape, and a third measuring electrode 3330 disposed on a scribing area 3020. As shown, the backplate substrate 3000 includes two third measuring electrodes 3330, but the number of third measuring electrodes 3330 may vary, and the scope of this disclosure is not limited thereto.

[0361] The backplane substrate 3000 may include a first contact pad 3310, a third contact pad 3340, a first connection line 3320, and a third connection line 3350. In an embodiment, for example, the first contact pad 3310 and the third contact pad 3340 may be disposed on an edge portion of the backplane substrate 3000. The first connection line 3320 may connect the first measuring electrode 3300 and the first contact pad 3310. The third connection line 3350 may be disposed on a scribing area 3020 and may connect the third measuring electrode 3330 and the third contact pad 3340.

[0362] In the embodiment, apart from the first measuring electrode 3300 and the third measuring electrode 3330, the first contact pad 3310 and the third contact pad 3340, and the first connection line 3320 and the third connection line 3350, the remaining (other) components of the backplane substrate 3000 are the same as those described above. Figure 15 The components described are essentially the same, so detailed descriptions of them will be omitted.

[0363] Reference Figure 38 The deposition mask 4000 may include a second measurement electrode 4800 and at least one fourth measurement electrode 4830. In an embodiment, for example, the deposition mask 4000 may include a second measurement electrode 4800 having an annular shape corresponding to the annular shape of the first measurement electrode 3300 and a fourth measurement electrode 4830 corresponding to the third measurement electrode 3330.

[0364] The second measurement electrode 4800 may be positioned at the same location as the first measurement electrode 3300 in a plan view, and may have the same shape and size as the first measurement electrode 3300. In an embodiment, for example, the second measurement electrode 4800 may be disposed on an edge portion of the deposition mask 4000 and may have an annular shape. The fourth measurement electrode 4830 may be positioned at the same location as the third measurement electrode 3330 in a plan view, and may have the same shape and size as the third measurement electrode 3330. In an embodiment, for example, the fourth measurement electrode 4830 may be arranged on a grid area 4320 of the deposition mask 4000 and may have a circular, square, quadrilateral (e.g., rectangular) or strip shape in a plan view. As shown, the deposition mask 4000 includes two fourth measurement electrodes 4830, but the number of fourth measurement electrodes 4830 may be varied, and the scope of this disclosure is not limited thereto.

[0365] The deposition mask 4000 may include a second contact pad 4810, a fourth contact pad 4840, a second interconnect 4820, and a fourth interconnect 4850. In an embodiment, for example, the second contact pad 4810 and the fourth contact pad 4840 may be arranged on an edge portion of the deposition mask 4000. The second interconnect 4820 may connect the second measurement electrode 4800 and the second contact pad 4810. The fourth interconnect 4850 may be arranged on the grid area 4320 and may connect the fourth measurement electrode 4830 and the fourth contact pad 4840.

[0366] In this embodiment, apart from the second measuring electrode 4800 and the fourth measuring electrode 4830, the second contact pad 4810 and the fourth contact pad 4840, and the second connection line 4820 and the fourth connection line 4850, the remaining (other) components of the deposition mask 4000 are the same as those described above. Figures 16 to 18 The components described are essentially the same, so detailed descriptions of them will be omitted.

[0367] In an embodiment, the deposition apparatus 2000 may further include sensors (not shown) for measuring the capacitance between the first measuring electrode 3300 and the second measuring electrode 4800, and the capacitance between the third measuring electrode 3330 and the fourth measuring electrode 4830. The sensors may include a first probe pin connected to a first contact pad 3310, a second probe pin connected to a second contact pad 4810, a third probe pin connected to a third contact pad 3340, and a fourth probe pin connected to a fourth contact pad 4840. Furthermore, the deposition mask 4000 may define a through opening 4050 through which the first and third probe pins pass, and a contact opening 4060 through which the second and fourth probe pins are inserted. The first, second, third, and fourth probe pins are referenced above. Figures 21 to 23 The probe pins described are similar, so a detailed description of them will be omitted.

[0368] In another embodiment, the deposition apparatus 2000 may include a first sensor (not shown) for measuring the capacitance between a first measuring electrode 3300 and a second measuring electrode 4800, and a second sensor (not shown) for measuring the capacitance between a third measuring electrode 3330 and a fourth measuring electrode 4830. The first and second sensors may be configured to... (referring to above) Figure 32 The first sensor 2830 and the second sensor 2840 are substantially the same, so a detailed description of the first sensor and the second sensor will be omitted.

[0369] In the embodiments, combined with Figure 14 After the backplate substrate 3000 is placed on the deposition mask 4000, positional alignment between the backplate substrate 3000 and the deposition mask 4000 can be performed. In an embodiment, for example, the hexapod actuator 2510 can move the substrate chuck 2300 in a first direction DR1 and a second direction DR2, such that the capacitance value between the first measuring electrode 3300 and the second measuring electrode 4800 becomes maximum. The capacitance value between the first measuring electrode 3300 and the second measuring electrode 4800 can be measured by a sensor or a first sensor, and the controller 2900 can control the operation of the hexapod actuator 2510 based on the capacitance value between the first measuring electrode 3300 and the second measuring electrode 4800.

[0370] After performing positional alignment between the backplane substrate 3000 and the deposition mask 4000, azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. In an embodiment, for example, the hexapod actuator 2510 can rotate the substrate chuck 2300 such that the capacitance value between the third measuring electrode 3330 and the fourth measuring electrode 4830 becomes maximum. The capacitance value between the third measuring electrode 3330 and the fourth measuring electrode 4830 can be measured by a sensor or a second sensor, and the controller 2900 can control the operation of the hexapod actuator 2510 based on the capacitance value between the third measuring electrode 3330 and the fourth measuring electrode 4830. In this case, since each of the first measuring electrode 3300 and the second measuring electrode 4800 has an annular shape, the capacitance value between the first measuring electrode 3300 and the second measuring electrode 4800 can remain constant while performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0371] Return to reference Figure 14For example, as described above, after the backplane substrate 3000 and the deposition mask 4000 are aligned with each other, the hexapod actuator 2510 can adjust the gap between the backplane substrate 3000 and the deposition mask 4000. In an embodiment, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes approximately a few μm, for example, approximately 3 μm to approximately 7 μm.

[0372] In another embodiment, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 so that the backplate substrate 3000 is in close contact with the deposition mask 4000. In this embodiment, the height of the substrate chuck 2300 can be adjusted so that the first measurement electrode 3300 and the second measurement electrode 4800 are in contact with each other. In this case, all the first measurement electrodes 3300 can be electrically connected to the second measurement electrode 4800. However, when any of the first measurement electrodes 3300 is not electrically connected to the corresponding second measurement electrode 4800, it can be determined that warping has occurred in the deposition mask 4000, in which case the controller 2900 can stop the deposition process.

[0373] As described above, after adjusting the gap between the backplane substrate 3000 and the deposition mask 4000, the deposition source 2200 can provide vapor-phase deposited material toward the deposition mask 4000, and the vapor-phase deposited material can be deposited on the backplane substrate 3000 through the pixel opening 4312 of the deposition mask 4000. In an embodiment, for example, the deposition source 2200 can evaporate organic material for forming a light-emitting layer on the backplane substrate 3000, and the evaporated organic material can be deposited on the electrode pattern of the backplane substrate 3000 through the pixel opening 4312 of the deposition mask 4000.

[0374] Figure 39 This is a flowchart illustrating an embodiment of the deposition method according to the present disclosure.

[0375] Reference Figure 39 In operation S100, a capacitor 3500 can be formed between the backplane substrate 3000 and the deposition mask 4000 (see reference). Figure 24 and Figure 25 In an embodiment, during operation S110, a first measuring electrode 3100 (see reference) can be fabricated. Figure 15 In operation S120, the backplate substrate 3000 can be fabricated to include at least one second measuring electrode 4600 (refer to...). Figure 16The deposition mask 4000 is used, and in operation S130, a backplane substrate 3000 can be placed on the deposition mask 4000 such that at least one first measurement electrode 3100 and at least one second measurement electrode 4600 face each other. Therefore, at least one capacitor 3500 including at least one first measurement electrode 3100 and at least one second measurement electrode 4600 can be formed between the backplane substrate 3000 and the deposition mask 4000.

[0376] In an embodiment, for example, as referred to above... Figure 15 As described above, multiple first measuring electrodes 3100 can be arranged on the backplate substrate 3000, and as referred to above. Figure 16 Multiple second measurement electrodes 4600 can be arranged on the deposition mask 4000, each corresponding to a plurality of first measurement electrodes 3100. (Refer to the above text) Figure 14 The backplane substrate 3000 and deposition mask 4000 can be arranged such that the first measurement electrode 3100 and the second measurement electrode 4600 face each other via the substrate chuck 2300, the mask chuck 2400, the substrate chuck driver 2500, and the mask chuck driver 2600, thereby achieving the desired effect. Figure 24 and Figure 25 The capacitor 3500 shown can be formed including a first measuring electrode 3100 and a second measuring electrode 4600.

[0377] although Figure 39 Not shown, but the deposition method in the embodiments may further include the step of adjusting the parallelism between the backing substrate 3000 and the deposition mask 4000. In the embodiments, for example, as referred to above... Figure 19 The gap sensor 2700 can be used to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400, thereby adjusting the parallelism between the backplate substrate 3000 and the deposition mask 4000.

[0378] Reference Figure 39 In operation S200, the capacitance of the capacitor 3500 formed between the backplane substrate 3000 and the deposition mask 4000 can be measured. In an embodiment, for example, the backplane substrate 3000 and / or the deposition mask 4000 can be moved using a substrate chuck driver 2500 and / or a mask chuck driver 2600, and a sensor 2800 (see [link to documentation]) can be used simultaneously with the movement of the backplane substrate 3000 and / or the deposition mask 4000. Figures 19 to 23The capacitance between the first measuring electrode 3100 and the second measuring electrode 4600 is measured. In an embodiment, for example, the backplane substrate 3000 or the deposition mask 4000 can be rotated by the substrate chuck driver 2500 or the mask chuck driver 2600, and the backplane substrate 3000 or the deposition mask 4000 can be moved by the substrate chuck driver 2500 or the mask chuck driver 2600. At this time, the gap between the backplane substrate 3000 and the deposition mask 4000 can remain constant.

[0379] In this embodiment, while the backplane substrate 3000 or deposition mask 4000 is rotated by the substrate chuck driver 2500 or the mask chuck driver 2600, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. Furthermore, while the backplane substrate 3000 or deposition mask 4000 is moved in the first direction DR1 and the second direction DR2 by the substrate chuck driver 2500 or the mask chuck driver 2600, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. At this time, the gap between the backplane substrate 3000 and the deposition mask 4000 can remain constant. That is, the backplane substrate 3000 and the deposition mask 4000 do not move in the third direction DR3.

[0380] In operation S300, the backplane substrate 3000 and the deposition mask 4000 can be aligned with each other based on the capacitance of the capacitor 3500 measured by the sensor 2800. In an embodiment, for example, the substrate chuck driver 2500 and / or the mask chuck driver 2600 can move the backplane substrate 3000 and / or the deposition mask 4000 such that the capacitance of the capacitor 3500 is maximized, thereby aligning the backplane substrate 3000 and the deposition mask 4000 with each other. In an embodiment, for example, the position and angle of the backplane substrate 3000 or the deposition mask 4000 can be adjusted such that the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 is maximized, thereby aligning the backplane substrate 3000 and the deposition mask 4000 with each other.

[0381] In an embodiment, the first measuring electrode 3100 and the second measuring electrode 4600 may have the same shape and the same size. In an embodiment, as referred to above... Figure 26 and Figure 27The substrate chuck driver 2500 or mask chuck driver 2600 can rotate the backplane substrate 3000 or the deposition mask 4000. While rotating the backplane substrate 3000 or the deposition mask 4000, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. The azimuth angle of the backplane substrate 3000 or the deposition mask 4000 when the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become all equal can be detected by the controller 2900. The operation of the substrate chuck driver 2500 or the mask chuck driver 2600 can be controlled by the controller 2900 so that the backplane substrate 3000 or the deposition mask 4000 has the detected azimuth angle, thereby performing azimuth angle alignment between the backplane substrate 3000 and the deposition mask 4000.

[0382] In addition, as mentioned above Figure 28 and Figure 29 The substrate chuck driver 2500 or mask chuck driver 2600 can move the backplane substrate 3000 or deposition mask 4000 in the first direction DR1 and the second direction DR2. While moving the backplane substrate 3000 or deposition mask 4000, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. The position of the backplane substrate 3000 or deposition mask 4000 where all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum can be detected by the controller 2900. The operation of the substrate chuck driver 2500 or mask chuck driver 2600 can be controlled by the controller 2900 to move the backplane substrate 3000 or deposition mask 4000 to the detected position, thereby performing position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0383] In another embodiment, after performing positional alignment between the backplane substrate 3000 and the deposition mask 4000, azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. In this embodiment, the substrate chuck driver 2500 or the mask chuck driver 2600 can move the backplane substrate 3000 or the deposition mask 4000 in a first direction DR1 and a second direction DR2. While moving the backplane substrate 3000 or the deposition mask 4000, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. The position of the backplane substrate 3000 or the deposition mask 4000 when the capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become all equal can be detected by the controller 2900. The operation of the substrate chuck driver 2500 or the mask chuck driver 2600 can be controlled by the controller 2900 to move the backplane substrate 3000 or the deposition mask 4000 to the detected position, thereby performing position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0384] Subsequently, the substrate chuck driver 2500 or the mask chuck driver 2600 can rotate the backplane substrate 3000 or the deposition mask 4000. While rotating the backplane substrate 3000 or the deposition mask 4000, the capacitance value between the first measuring electrode 3100 and the second measuring electrode 4600 can be measured by the sensor 2800. The azimuth angle of the backplane substrate 3000 or the deposition mask 4000 where all capacitance values ​​between the first measuring electrode 3100 and the second measuring electrode 4600 become maximum can be detected by the controller 2900. The operation of the substrate chuck driver 2500 or the mask chuck driver 2600 can be controlled by the controller 2900 so that the backplane substrate 3000 or the deposition mask 4000 has the detected azimuth angle, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0385] In the embodiments, as referred to above Figure 30 and Figure 31 The backplane substrate 3000 may include a first measurement electrode 3200 extending in a first direction DR1 and a third measurement electrode 3230 extending in a second direction DR2, and the deposition mask 4000 may include a second measurement electrode 4700 extending in the first direction DR1 and a fourth measurement electrode 4730 extending in the second direction DR2.

[0386] In embodiments, for example, the substrate chuck driver 2500 or the mask chuck driver 2600 can rotate the backplane substrate 3000 or the deposition mask 4000. While rotating the backplane substrate 3000 or the deposition mask 4000, a first sensor 2830 (see reference) can be used. Figure 32) and the second sensor 2840 (reference) Figure 32 The capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, are measured. The controller 2900 can detect the azimuth angle of the backplane substrate 3000 or the deposition mask 4000 when the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and the capacitance values ​​between the third measuring electrode 3230 and the fourth measuring electrode 4730, become equal. The controller 2900 can control the operation of the substrate chuck driver 2500 or the mask chuck driver 2600 so that the backplane substrate 3000 or the deposition mask 4000 has the detected azimuth angle, thereby performing azimuth angle alignment between the backplane substrate 3000 and the deposition mask 4000.

[0387] Subsequently, the substrate chuck driver 2500 or the mask chuck driver 2600 can move the backplane substrate 3000 or the deposition mask 4000 in the first direction DR1 and the second direction DR2. While moving the backplane substrate 3000 or the deposition mask 4000, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, can be measured by the first sensor 2830 and the second sensor 2840. The position of the backplane substrate 3000 or the deposition mask 4000 when the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, all become maximum and equal can be detected by the controller 2900. The operation of the substrate chuck driver 2500 or the mask chuck driver 2600 can be controlled by the controller 2900 to move the backplane substrate 3000 or the deposition mask 4000 to the detected position, thereby performing position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0388] In another embodiment, after performing positional alignment between the backplane substrate 3000 and the deposition mask 4000, azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. A substrate chuck driver 2500 or a mask chuck driver 2600 can move the backplane substrate 3000 or the deposition mask 4000 in a first direction DR1 and a second direction DR2. While moving the backplane substrate 3000 or the deposition mask 4000, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, can be measured by the first sensor 2830 and the second sensor 2840. The position of the backplane substrate 3000 or the deposition mask 4000 when the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700 and the third measuring electrode 3230 and the fourth measuring electrode 4730 become equal can be detected by the controller 2900. The operation of the substrate chuck driver 2500 or the mask chuck driver 2600 can be controlled by the controller 2900 to move the backplane substrate 3000 or the deposition mask 4000 to the detected position, thereby performing position alignment between the backplane substrate 3000 and the deposition mask 4000.

[0389] Subsequently, the substrate chuck driver 2500 or the mask chuck driver 2600 can rotate the backplane substrate 3000 or the deposition mask 4000. While rotating the backplane substrate 3000 or the deposition mask 4000, the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, can be measured by the first sensor 2830 and the second sensor 2840. The azimuth angle of the backplane substrate 3000 or the deposition mask 4000 can be detected by the controller 2900 when the capacitance values ​​between the first measuring electrode 3200 and the second measuring electrode 4700, and between the third measuring electrode 3230 and the fourth measuring electrode 4730, all become maximum and all become equal. The operation of the substrate chuck driver 2500 or the mask chuck driver 2600 can be controlled by the controller 2900 to give the backplane substrate 3000 or the deposition mask 4000 a detected azimuth angle, thereby performing azimuth alignment between the backplane substrate 3000 and the deposition mask 4000.

[0390] In the embodiments, as referred to above Figure 37 and Figure 38 The backplane substrate 3000 may include a first measuring electrode 3300 and a third measuring electrode 3330 having an annular shape, and the deposition mask 4000 may include a second measuring electrode 4800 having an annular shape and corresponding to the first measuring electrode 3300 and a fourth measuring electrode 4830 corresponding to the third measuring electrode 3330.

[0391] In an embodiment, for example, after performing positional alignment between the backplane substrate 3000 and the deposition mask 4000, azimuth alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. The substrate chuck driver 2500 or the mask chuck driver 2600 can move the backplane substrate 3000 or the deposition mask 4000 in a first direction DR1 and a second direction DR2. The controller 2900 can detect the position of the backplane substrate 3000 or the deposition mask 4000 where the capacitance value between the first measuring electrode 3300 and the second measuring electrode 4800 becomes maximum. Furthermore, the controller 2900 can control the operation of the substrate chuck driver 2500 or the mask chuck driver 2600 such that the backplane substrate 3000 or the deposition mask 4000 is moved to the detected position, thereby performing positional alignment between the backplane substrate 3000 and the deposition mask 4000.

[0392] Subsequently, the substrate chuck driver 2500 or the mask chuck driver 2600 can rotate the backplane substrate 3000 or the deposition mask 4000. The controller 2900 can detect the azimuth angle of the backplane substrate 3000 or the deposition mask 4000 where the capacitance value between the third measurement electrode 3330 and the fourth measurement electrode 4830 becomes the largest. In addition, the controller 2900 can control the operation of the substrate chuck driver 2500 or the mask chuck driver 2600 so that the backplane substrate 3000 or the deposition mask 4000 has the detected azimuth angle, thereby performing azimuth angle alignment between the backplane substrate 3000 and the deposition mask 4000.

[0393] As described above, after the backing substrate 3000 and the deposition mask 4000 are aligned with each other, in operation S400, deposition material can be provided onto the backing substrate 3000 through the deposition mask 4000, thereby forming a deposition material layer on the backing substrate 3000. In an embodiment, for example, a deposition source 2200 (see...) Figure 14 Organic materials used to form a light-emitting layer on the backplane substrate 3000 can be evaporated, and the evaporated organic materials can be deposited through pixel openings 4312 of the deposition mask 4000 (see reference). Figure 18 Electrode patterns are deposited on a 3000-inch backplate substrate.

[0394] Through the embodiments of this disclosure as described above, alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed based on the capacitance between them. As a result, the high-resolution camera and illumination device used for detecting the universal alignment key can be removed (not used), thereby significantly reducing the cost of the display panel 100 (see reference 100). Figure 9 ), display device 20 (refer to) Figure 3 ) or electronic device 10 (refer to Figure 1Manufacturing costs of items such as )

[0395] This disclosure should not be construed as limiting itself to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and complete, and will fully convey the concept of this disclosure to those skilled in the art.

[0396] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of this disclosure as defined by the appended claims.

Claims

1. A deposition method, wherein, The deposition method includes: Prepare a substrate including at least one first measuring electrode; Prepare a deposition mask including at least one second measuring electrode; The substrate is placed on the deposition mask such that the at least one first measuring electrode and the at least one second measuring electrode face each other; Measure the capacitance between the at least one first measuring electrode and the at least one second measuring electrode; The substrate and the deposition mask are aligned with each other based on the measured capacitance; and The deposition material is provided onto the substrate through the deposition mask to form a deposition material layer on the substrate.

2. The deposition method according to claim 1, wherein, The measurement of the capacitance includes: Rotate the substrate or the deposition mask; While rotating the substrate or the deposition mask, a first capacitance value is measured between the at least one first measuring electrode and the at least one second measuring electrode; While maintaining a constant gap between the substrate and the deposition mask, move the substrate or the deposition mask; and While moving the substrate or the deposition mask, a second capacitance value is measured between the at least one first measuring electrode and the at least one second measuring electrode.

3. The deposition method according to claim 1, wherein, The step of aligning the substrate and the deposition mask with each other includes: The position and angle of the substrate or the deposition mask are adjusted in such a way that the capacitance between the at least one first measuring electrode and the at least one second measuring electrode becomes maximum.

4. The deposition method according to claim 1, wherein, The substrate includes a plurality of first measurement electrodes. The deposition mask includes multiple second measurement electrodes. The substrate is placed on the deposition mask with the plurality of first measurement electrodes facing the plurality of second measurement electrodes respectively, and The plurality of first measuring electrodes and the plurality of second measuring electrodes have the same shape.

5. The deposition method according to claim 4, wherein, The measurement of the capacitance includes: Rotate the substrate or the deposition mask; and While rotating the substrate or the deposition mask, multiple first capacitance values ​​are measured between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and The step of aligning the substrate and the deposition mask with each other includes: Detect the azimuth angle of the substrate or the deposition mask; and Adjust the azimuth angle of the substrate or the deposition mask so that the plurality of first capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes become all equal.

6. The deposition method according to claim 5, wherein, The measurement of the capacitance also includes: While maintaining a constant gap between the substrate and the deposition mask, move the substrate or the deposition mask; and While moving the substrate or the deposition mask, multiple second capacitance values ​​are measured between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and The step of aligning the substrate and the deposition mask with each other also includes: Detecting the position of the substrate or the deposition mask; and The substrate or the deposition mask is moved such that the plurality of second capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes are all maximized.

7. The deposition method according to claim 4, wherein, The measurement of the capacitance includes: While maintaining a constant gap between the substrate and the deposition mask, move the substrate or the deposition mask; and While moving the substrate or the deposition mask, multiple first capacitance values ​​are measured between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and The step of aligning the substrate and the deposition mask with each other includes: Detecting the position of the substrate or the deposition mask; and The substrate or the deposition mask is moved such that the plurality of first capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes become all equal.

8. The deposition method according to claim 7, wherein, The measurement of the capacitance also includes: Rotate the substrate or the deposition mask; and While rotating the substrate or the deposition mask, multiple second capacitance values ​​are measured between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and The step of aligning the substrate and the deposition mask with each other also includes: Detect the azimuth angle of the substrate or the deposition mask; and The azimuth angle of the substrate or the deposition mask is adjusted such that the plurality of second capacitance values ​​between the plurality of first measuring electrodes and the plurality of second measuring electrodes are all maximized.

9. The deposition method according to claim 1, wherein, The substrate includes multiple first measuring electrodes and multiple third measuring electrodes. The deposition mask includes multiple second measurement electrodes and multiple fourth measurement electrodes. The substrate is placed on the deposition mask such that the plurality of first measurement electrodes face the plurality of second measurement electrodes respectively, and the plurality of third measurement electrodes face the plurality of fourth measurement electrodes respectively. The plurality of first measuring electrodes and the plurality of second measuring electrodes extend in a first direction, and The plurality of third measuring electrodes and the plurality of fourth measuring electrodes extend in a second direction perpendicular to the first direction.

10. The deposition method according to claim 9, wherein, The measurement of the capacitance includes: Rotate the substrate or the deposition mask; and While rotating the substrate or the deposition mask, multiple first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and multiple second capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes are measured, and aligning the substrate and the deposition mask with each other includes: Detect the azimuth angle of the substrate or the deposition mask; and The azimuth angle of the substrate or the deposition mask is adjusted such that the plurality of first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes become equal to each other, and the plurality of second capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes become equal to each other.

11. The deposition method according to claim 10, wherein, The measurement of the capacitance also includes: While maintaining a constant gap between the substrate and the deposition mask, move the substrate or the deposition mask; and While moving the substrate or the deposition mask, multiple third capacitance values ​​are measured between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and multiple fourth capacitance values ​​are measured between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes. Aligning the substrate and the deposition mask with each other further includes: Detecting the position of the substrate or the deposition mask; and The substrate or the deposition mask is moved such that the plurality of third capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and the plurality of fourth capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes, all become maximum and all become equal.

12. The deposition method according to claim 9, wherein, The measurement of the capacitance includes: While maintaining a constant gap between the substrate and the deposition mask, move the substrate or the deposition mask; and While moving the substrate or the deposition mask, multiple first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and multiple second capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes are measured, and aligning the substrate and the deposition mask with each other includes: Detecting the position of the substrate or the deposition mask; and The substrate or the deposition mask is moved such that the plurality of first capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes become equal to each other, and the plurality of second capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes become equal to each other.

13. The deposition method according to claim 12, wherein, The measurement of the capacitance also includes: Rotate the substrate or the deposition mask; and While rotating the substrate or the deposition mask, multiple third capacitance values ​​are measured between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and multiple fourth capacitance values ​​are measured between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes. Aligning the substrate and the deposition mask with each other further includes: Detect the azimuth angle of the substrate or the deposition mask; and The azimuth angle of the substrate or the deposition mask is adjusted such that the plurality of third capacitance values ​​between the plurality of first measurement electrodes and the plurality of second measurement electrodes, and the plurality of fourth capacitance values ​​between the plurality of third measurement electrodes and the plurality of fourth measurement electrodes, all become maximum and all become equal.

14. The deposition method according to claim 1, wherein, The substrate includes a first measuring electrode and at least one third measuring electrode. The deposition mask includes a second measurement electrode and at least one fourth measurement electrode. The substrate is placed on the deposition mask with the first measurement electrode facing the second measurement electrode and the at least one third measurement electrode facing the at least one fourth measurement electrode. The first measuring electrode and the second measuring electrode have the same annular shape, and The at least one third measuring electrode and the at least one fourth measuring electrode have the same shape.

15. The deposition method according to claim 1, wherein, The deposition method further includes adjusting the parallelism between the substrate and the deposition mask.

16. A deposition apparatus, wherein, The deposition apparatus includes: Deposition source, providing depositional materials; A substrate chuck is disposed above the deposition source and supports a substrate including at least one first measuring electrode; A mask chuck is disposed between the deposition source and the substrate chuck and supports a deposition mask including at least one second measuring electrode; The sensor measures the capacitance between the at least one first measuring electrode and the at least one second measuring electrode; and A chuck driver aligns the substrate and the deposition mask with each other based on the capacitance measured by the sensor.

17. The deposition apparatus according to claim 16, wherein, The substrate further includes at least one first contact pad and at least one first connection line connecting the at least one first measuring electrode to the at least one first contact pad. The deposition mask further includes at least one second contact pad and at least one second connection line connecting the at least one second measurement electrode to the at least one second contact pad, and The sensor includes at least one first probe pin connected to the at least one first contact pad and at least one second probe pin connected to the at least one second contact pad.

18. The deposition apparatus according to claim 16 or 17, wherein, The chuck driver moves the substrate chuck or the mask chuck in such a way that the capacitance between the at least one first measuring electrode and the at least one second measuring electrode becomes maximum, and aligns the substrate and the deposition mask with each other.

19. An electronic device, wherein, The electronic device includes: The display panel includes: The substrate includes at least one first measuring electrode; and The light-emitting layer is formed on the substrate by a deposition apparatus according to any one of claims 16 to 18.

20. The electronic device according to claim 19, wherein, The electronic device also includes at least one of a processor, a memory, and a power module.

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