Chip screening system and method

Abstract

This application discloses a chip screening system and method. The chip is a light-emitting diode (LED) chip. The chip screening system includes a test backplane and a data acquisition device. The test backplane includes a first driving circuit, a second driving circuit, and multiple receiving areas. Each receiving area includes a first connection portion and a second connection portion. The first driving circuit is connected to the first connection portion via a first trace, and the second driving circuit is connected to the second connection portion via a second trace. The first and second connection portions are respectively used to connect the anode and cathode of the LED chip. The data acquisition device is used to acquire the optical parameters of the LED chip. According to the chip screening system and method provided in this application, batch chip screening can be achieved, improving the efficiency and accuracy of chip yield screening.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a chip screening system and method. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for the display effect of display panels.

[0003] However, the related technologies suffer from low efficiency and accuracy in yield detection of LED chips. Summary of the Invention

[0004] This application provides a chip screening system and method that enables batch chip screening, improving the efficiency and accuracy of chip yield screening.

[0005] In a first aspect, embodiments of this application provide a chip screening system, wherein the chip is a light-emitting diode chip, and the chip screening system includes: The test backplane includes a first driving circuit, a second driving circuit, and multiple receiving areas. Each receiving area includes a first connection part and a second connection part. The first driving circuit is connected to the first connection part through a first trace, and the second driving circuit is connected to the second connection part through a second trace. The first connection part and the second connection part are respectively used to connect the anode and cathode of the light-emitting diode chip. A data acquisition device used to acquire the optical parameters of a light-emitting diode (LED) chip.

[0006] Based on the same inventive concept, in a second aspect, embodiments of this application also provide a chip screening method, applied to a chip screening system as described in any embodiment of the first aspect, the method comprising: Place the LED chip in the receiving area, and make the anode and cathode of the LED chip contact the first connection part and the second connection part, respectively; The first driving circuit and the second driving circuit apply voltages to the anode and cathode of the LED chip respectively to light up the LED chip. The optical parameters of the light-emitting diode chip are acquired using a data acquisition device.

[0007] According to the chip screening system and method provided in this application, the chip is a light-emitting diode (LED) chip. The chip screening system includes a test backplane and a data acquisition device. The test backplane includes a first driving circuit, a second driving circuit, and multiple receiving areas. A first connection portion and a second connection portion in the receiving areas are respectively connected to the anode and cathode of the LED chip. The first driving circuit is connected to the first connection portion through a first trace to adjust the anode voltage of the LED chip, and the second driving circuit is connected to the second connection portion through a second trace to adjust the cathode voltage of the LED chip. By controlling the anode and cathode voltages of the LED chips in the multiple receiving areas through the first and second driving circuits respectively, the LED chip currently being tested can be accurately lit. Combined with the design of multiple receiving areas, batch chip screening is realized, improving the efficiency and accuracy of chip yield screening. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This is a schematic diagram of a chip screening system provided in an embodiment of this application; Figure 2 This is a schematic diagram of a accommodating area in the chip screening system provided in this application embodiment; Figure 3 This is a top view of the receiving area in the chip screening system provided in this application embodiment; Figure 4 This is a schematic diagram of a transparent cover plate in the chip screening system provided in this application embodiment; Figure 5 This is another structural schematic diagram of the transparent cover plate in the chip screening system provided in the embodiments of this application; Figure 6 This is another structural schematic diagram of the chip screening system provided in the embodiments of this application; Figure 7 This is a schematic flowchart of a chip screening method provided in an embodiment of this application; Figure 8 This is another schematic flowchart of the chip screening method provided in the embodiments of this application; Figure 9 This is another schematic flowchart of the chip screening method provided in the embodiments of this application; Figure 10 This is another schematic flowchart of the chip screening method provided in the embodiments of this application. Detailed Implementation

[0010] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0011] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0012] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0013] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0014] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: Yield testing for mass-transfer Micro LED chips is a challenging problem in the industry.

[0015] Electroluminescence point-by-point testing methods are inefficient and pose a risk of damaging the chip. Specifically, these methods require applying electrical contact via a probe station, which results in low testing efficiency, easy damage to chip electrodes, uneven contact pressure, and an inability to output chip electrical parameters in batches.

[0016] Photoluminescence testing can only obtain the optical properties of materials and cannot obtain the overall electrical properties of the chip. Therefore, photoluminescence testing is used for material screening and cannot output the chip's electrical parameters. Specifically, photoluminescence testing mainly uses light to excite the chip to generate electron-hole pairs, generate charge carriers, and emit radiative recombination light. It can only reflect the properties of the material itself and cannot reflect the overall electrical performance of the chip.

[0017] Meanwhile, the related technologies also have the problem of difficulty in synchronizing electrical excitation (such as the traditional electroluminescence point-by-point testing method) and optical acquisition (such as photoluminescence testing).

[0018] Based on this, embodiments of this application provide a chip screening system and method, which realizes the screening of batch chips and improves the efficiency and accuracy of chip yield screening.

[0019] The chip screening system provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the structure of a chip screening system provided in an embodiment of this application, as shown below. Figure 1 As shown, the chip is a light-emitting diode chip, and the chip screening system 100 may include a test backplane 10 and a data acquisition device 20.

[0021] The test backplane 10 may include a first driving circuit 11, a second driving circuit 12, and multiple receiving areas 13. Each receiving area 13 includes a first connection portion 131 and a second connection portion 132. The first driving circuit 11 is connected to the first connection portion 131 via a first trace 14, and the second driving circuit 12 is connected to the second connection portion 132 via a second trace 15. The first connection portion 131 and the second connection portion 132 are respectively used to connect the anode and cathode of the light-emitting diode chip 200. For example, the first connection portion 131 is used to connect the anode of the light-emitting diode chip 200, and the second connection portion 132 is used to connect the cathode of the light-emitting diode chip 200.

[0022] The first driving circuit 11 and the second driving circuit 12 are circuits that apply voltages to the anode and cathode of the LED chip 200. For example, the first driving circuit 11 applies a voltage of 3V or 0V to the anode of the LED chip 200, and the second driving circuit 12 applies a voltage of 3V or 0V to the cathode of the LED chip 200. If 3V is applied to the anode and 0V to the cathode, the LED chip 200 is allowed to be lit; if 0V is applied to both the anode and cathode, or vice versa, the LED chip 200 is not allowed to be lit. Of course, in other embodiments, the voltages output by the first driving circuit 11 and the second driving circuit 12 can also be set to other values. For example, the first driving circuit 11 outputs PVDD or 0V, and the second driving circuit 12 outputs PVEE or 0V, wherein PVDD-PVEE needs to be greater than the turn-on voltage of the LED chip, and PVDD-0V needs to be less than the turn-on voltage of the LED chip. In other words, the first driving circuit 11 and the second driving circuit 12 can control whether any one of the LED chips 200 in the display panel can be lit. For example, for an m-row, n-column array of LED chips 200, the first driving circuit 11 applies a voltage to the anode of the LED chip 200, and the second driving circuit 12 applies a voltage to the cathode of the LED chip 200. The LED chip 200 is only allowed to be lit when the voltage difference between the anode and cathode of the LED chip 200 is greater than or equal to the turn-on voltage of the LED chip 200. If the voltage difference between the anode and cathode of the LED chip 200 is less than the turn-on voltage, the LED chip 200 is not allowed to be lit. Therefore, the first driving circuit 11 and the second driving circuit 12 are mainly used to control the magnitude of the voltage difference between the anode and cathode of each LED chip 200 to select which LED chip 200(s) to test at the current moment, thereby accurately lighting the LED chip 200 currently being tested.

[0023] For example, the first connection portion 131 and the second connection portion 132 are two metal solder joints within the receiving area 13. The first driving circuit 11 can be connected to the first connection portion 131 via the first trace 14 to adjust the anode voltage of the light-emitting diode chip 200, and the second driving circuit 12 can be connected to the second connection portion 132 via the second trace 15 to adjust the cathode voltage of the light-emitting diode chip 200.

[0024] The acquisition device 20 is used to acquire the optical parameters of the light-emitting diode chip 200.

[0025] For example, the acquisition device 20 may include a camera and a processor. The data processing is performed by the processor. The camera feeds back the high-precision photos it acquires to the processor, which extracts optical parameter information to screen whether the light-emitting diode chip 200 is of good quality.

[0026] For example, optical parameters may include information such as wavelength, brightness, and chromaticity.

[0027] In other words, the test backplane 10 is used to drive the LED chip 200 to emit light, and the acquisition device 20 is used to collect optical parameter information for yield screening.

[0028] In one example, the test backplane 10 integrates pixel circuitry (such as an active matrix circuit) to illuminate LED chips 200. The first driving circuit 11 and the second driving circuit 12 primarily control whether each LED chip 200 can be illuminated by the pixel circuitry by controlling the voltage difference across the LED chips 200. Alternatively, in other embodiments, the test backplane 10 may integrate passive matrix circuitry (passive driving circuitry does not have pixel circuitry, only row and column scan lines, and has row and column driving circuitry) to illuminate LED chips 200. The first driving circuit 11 and the second driving circuit 12 primarily control whether each LED chip 200 can be illuminated by the passive matrix circuitry by controlling the voltage difference across the LED chips 200.

[0029] The chip screening system 100 of this application embodiment uses a light-emitting diode (LED) chip 200. The chip screening system 100 may include a test backplane 10 and a data acquisition device 20. The test backplane 10 may include a first driving circuit 11, a second driving circuit 12, and multiple receiving areas 13. A first connection portion 131 and a second connection portion 132 in the receiving areas 13 are respectively connected to the anode and cathode of the LED chip 200. The first driving circuit 11 is connected to the first connection portion 131 through a first trace 14 to adjust the anode voltage of the LED chip 200. The second driving circuit 12 is connected to the second connection portion 132 through a second trace 15 to adjust the cathode voltage of the LED chip 200. By controlling the anode and cathode voltages of the LED chips 200 in the multiple receiving areas 13 through the first driving circuit 11 and the second driving circuit 12, the LED chip 200 currently being tested can be accurately lit. Combined with the design of multiple receiving areas 13, batch chip screening is realized, improving the efficiency and accuracy of chip yield screening.

[0030] In some embodiments, see [link to relevant documentation]. Figure 1Multiple receiving areas 13 are arranged in rows and columns, with X representing the row direction and Y representing the column direction. The first connecting part 131 of multiple receiving areas 13 in the same row is connected to the same first routing line 14, and the second connecting part 132 of multiple receiving areas 13 in the same column is connected to the same second routing line 15.

[0031] In this embodiment, the first connection portions 131 in the same row share a first trace 14, and the second connection portions 132 in the same column share a second trace 15. This structure can reduce the number of traces, as each connection portion does not need to be individually connected to the drive circuit, but is connected through a shared trace, thereby simplifying the trace structure.

[0032] In some embodiments, see [link to relevant documentation]. Figure 1 The first connection portion 131 of the multiple receiving areas 13 in different rows is connected to different first traces 14, the second connection portion 132 of the multiple receiving areas 13 in different columns is connected to different second traces 15, and the different first traces 14 are connected to different output terminals of the first driving circuit 11, and the different second traces 15 are connected to different output terminals of the second driving circuit 12.

[0033] The first routing line 14 extends along the row direction, and the second routing line 15 extends along the column direction.

[0034] Different first traces 14 connect to different output terminals of the first driving circuit 11, and different second traces 15 connect to different output terminals of the second driving circuit 12, enabling independent control of each accommodating area 13. For example, by controlling the outputs of the first driving circuit 11 and the second driving circuit 12, LED chips 200 can be lit individually or in batches (e.g., row by row or column by column) for batch screening. The principle of lighting up LED chips 200 individually or in batches (e.g., row by row or column by column) is as follows: Individual Illumination Mechanism: Taking a 3×3 LED chip matrix as an example, to illuminate the LED chip in the 2nd row and 3rd column, the first driving circuit 11 applies a high level (e.g., 3V) to the first trace 14 corresponding to the 2nd row, and the second driving circuit 12 applies a low level (e.g., 0V) to the second trace 15 corresponding to the 3rd column. Simultaneously, 0V is applied to the other traces, and 3V is applied to the other column traces. At this time, only the LED chip at the intersection of the 2nd row and 3rd column is illuminated because the anode-cathode voltage difference reaches the LED chip's turn-on voltage. The remaining LED chips cannot be illuminated due to reverse voltage bias or insufficient voltage difference, thus achieving precise positioning testing of a single chip.

[0035] Row-by-row illumination mechanism: During row-by-row scanning, the first driving circuit 11 applies a high level (e.g., 3V) to the first trace 14 corresponding to the first row, and a low level (e.g., 0V) to the remaining rows. The second driving circuit 12 applies a low level (e.g., 0V) to the second trace 15 corresponding to all columns, causing all LED chips in the first row to light up simultaneously. Subsequently, the first driving circuit 11 applies a high level (e.g., 3V) to the first trace 14 corresponding to the second row, and a low level (e.g., 0V) to the remaining rows. The second driving circuit 12 applies a low level (e.g., 0V) to the second trace 15 corresponding to all columns, causing all LED chips in the second row to light up simultaneously. This process is repeated to complete row-by-row illumination. The column-by-column illumination mechanism is similar to the row-by-row mechanism and will not be described further here.

[0036] Therefore, by controlling the independent voltage of the row / column traces, it can support both precise single-point testing and rapid batch screening.

[0037] In one example, the first trace 14 and the second trace 15 are located on different metal layers, which avoids cross-interference between the traces. The first trace 14 is connected to the first connection portion 131 via a vertical connecting line, and the vertical connecting line and the first trace 14 are on the same film layer. The second trace 15 is connected to the second connection portion 132 via a horizontal connecting line, and the horizontal connecting line and the second trace 15 are on the same film layer, eliminating the need for via design and simplifying the manufacturing process.

[0038] In this embodiment, the connection parts of different rows / columns are connected to independent traces and connected to different ports of the driving circuit, supporting individual lighting (precise positioning of a single chip) and batch operations (such as scanning row by row / column by column). Combined with the simplified process design of different metal layer isolation traces to avoid cross interference and the connection lines of the same film layer without vias, the manufacturing complexity is reduced and the efficiency of batch chip screening is improved.

[0039] In some embodiments, such as Figure 2 As shown, the receiving area 13 includes a recess 133, and a first connecting portion 131 and a second connecting portion 132 are located on the bottom surface of the recess 133.

[0040] See also Figure 2 200_R is a red-emitting LED chip, 200_G is a green-emitting LED chip, and 200_B is a blue-emitting LED chip. In one example, yield screening can be performed on a pixel-by-pixel basis (one pixel includes one red-emitting LED chip 200_R, one green-emitting LED chip 200_G, and one blue-emitting LED chip 200_B). First, a single pixel is illuminated to collect its optical parameters. If the optical parameters of that pixel do not meet the requirements, then the individual LED chips within that pixel are inspected separately, thereby improving the efficiency of yield screening.

[0041] In one example, the recess 133 may include recesses of various shapes, such as circles, rectangles, etc.

[0042] In another example, the shape of the recess 133 can match the shape of the light-emitting diode chip 200, for example, the recess shape of the recess 133 is rectangular.

[0043] In this embodiment, the bottom surface of the recessed portion integrates the first and second connecting portions. Combined with the recessed design that adapts to the chip shape, such as a rectangle, it can ensure the accurate positioning of the light-emitting diode chip and avoid test offset. It also supports pixel-level testing (such as RGB three-color chip combination), which can quickly screen the overall yield of pixels. If a pixel is abnormal, then the single-color chip is specifically tested, which improves the screening efficiency. Therefore, while improving the positional accuracy and test stability, it optimizes the efficiency and accuracy of batch chip yield screening.

[0044] In some embodiments, such as Figure 3 As shown, Figure 3 The top view of the recessed portion 133 shows that the surface of the recessed portion 133, excluding the first connecting portion 131 and the second connecting portion 132, includes a light-shielding layer 134.

[0045] For example, the light-shielding layer 134 includes black photoresist. The surface of the recessed portion 133, except for the first connecting portion 131 and the second connecting portion 132, is coated with black photoresist. The black photoresist has a light-shielding function and can prevent crosstalk between light-emitting diode chips.

[0046] In one example, the surface of the test backplane 10, excluding the first connection portion 131 and the second connection portion 132, includes a light-shielding layer 134. For example, the surface of the test backplane 10, excluding the first connection portion 131 and the second connection portion 132, is coated with black photoresist, which can further prevent crosstalk between light-emitting diode chips.

[0047] This application embodiment effectively blocks crosstalk between adjacent LED chips by using a light-shielding function, significantly improving the measurement accuracy of chip optical parameters (such as wavelength, brightness, and chromaticity) by the acquisition device, ensuring the accuracy of synchronous testing of "electrical excitation-optical acquisition", and avoiding misjudgment caused by light interference, thus providing more reliable optical data support for batch chip yield screening.

[0048] In some embodiments, see [link to relevant documentation]. Figure 2 The depth of the recess 133 is less than the thickness of the LED chip 200.

[0049] In one example, the chip screening system also includes a transparent cover plate to cover the LED chip. The depth of the recess is less than the thickness of the LED chip but does not exceed a certain threshold, ensuring that the transparent cover plate can directly and uniformly press against the chip surface while avoiding light interference. In other words, a portion of the top of the LED chip is exposed, allowing the cover plate to press against the LED chip and apply pressure evenly.

[0050] This application embodiment uses a recessed portion with a depth less than the thickness of the LED chip to expose the top part of the chip, ensuring that the transparent cover can directly and evenly press the chip surface. By applying uniform pressure, stable contact between each chip and the connection part is ensured during batch testing.

[0051] In some embodiments, such as Figure 4 As shown, the chip screening system 100 may also include a transparent cover plate 30.

[0052] A transparent cover plate 30 is used to cover the light-emitting diode chip 200.

[0053] Figure 4 The arrow in the image indicates downward pressure.

[0054] For example, see [link to previous article] Figure 4 The LED chip 200 can be placed in the receiving area 13 of the test backplate 10, covered with a transparent cover plate 30, and pressure is applied to form an electrical contact. The pixel circuit scans the LED chip 200 line by line to perform electrical and optical screening.

[0055] In this embodiment, the transparent cover plate 30 can achieve uniform pressure application, so that the anode and cathode pins of the light-emitting diode chip 200 make uniform electrical contact with the first connection part and the second connection part, thereby improving the accuracy and reliability of the test.

[0056] In some embodiments, such as Figure 5 As shown, the transparent cover 30 includes an adhesive layer 40 on the side facing the test backplate.

[0057] In other words, the transparent cover 30 is coated with an adhesive substance.

[0058] In this embodiment, the transparent cover 30 is coated with an adhesive substance on the side facing the test backplate. This not only ensures the uniformity of electrical contact during the testing phase, but also serves as a temporary carrier to quickly transfer the LED chips 200 in batches to the final backplate, thus shortening the production cycle.

[0059] In some embodiments, such as Figure 6 As shown, the test backplate 10 and / or transparent cover plate 30 may include alignment marks 50.

[0060] For example, the final backplane also includes alignment marks 50. The alignment marks are used to align the test backplane 10, the transparent cover 30, and the final backplane, simplifying the positioning process, ensuring accurate chip positioning during testing, and improving the transfer efficiency of batch chips.

[0061] The alignment mark 50 can be any shape, such as a circle, triangle, or cross. This embodiment of the application does not limit the shape of the alignment mark. The number of alignment marks 50 can be set to one or more, which can be set according to actual needs (alignment accuracy requirements), for example, 3 or 4. This embodiment of the application does not limit the number of alignment marks 50.

[0062] In this embodiment, the test backplane and the transparent cover can be aligned using the alignment mark 40, which improves the efficiency and accuracy of the test. After the test, the transparent cover can be aligned with the alignment mark 50 of the final backplane, thereby quickly transferring the LED chips in batches to the final backplane, which improves the positioning accuracy and reliability of the "test-transfer" process.

[0063] In some embodiments, the transparent cover plate 30 may include a sapphire substrate.

[0064] The transparent cover is made of high-strength, high-transmittance materials, such as sapphire.

[0065] In one example, the chip is illuminated by the first and second driving circuits to obtain electrical information. Simultaneously, a high-precision camera is placed above the sapphire transparent cover plate in conjunction with a spectrometer to obtain the chip's optical parameters, realizing the synchronous acquisition of the chip's electrical and optical data. Based on the software output, the positioning coordinates of all chips on the test backplane are obtained to complete the data report for each chip.

[0066] In this embodiment, a transparent cover plate 30 is made of sapphire. The sapphire cover plate, with its high strength, can withstand uniform pressure without deformation, ensuring stable electrical contact between the LED chip and the test backplane, and avoiding poor local contact. Its high light transmittance allows a high-precision camera and spectrometer to accurately capture the chip's optical parameters, and, in conjunction with the driving circuit, synchronously acquire electrical data, achieving simultaneous acquisition and precise positioning of both electrical and optical parameters. Combined with the software's function of automatically generating chip coordinates and data reports, the accuracy and efficiency of chip testing are improved.

[0067] Based on the same inventive concept, such as Figure 7 As shown, this application embodiment also provides a chip screening method, applied to the chip screening system 100 of any of the above embodiments, the method may include steps S110 to S130.

[0068] S110, the light-emitting diode chip 200 is placed in the receiving area 13, and the anode and cathode of the light-emitting diode chip 200 are respectively in contact with the first connecting part 131 and the second connecting part 132.

[0069] S120, voltages are applied to the anode and cathode of the LED chip 200 through the first driving circuit 11 and the second driving circuit 12 respectively, so as to light up the LED chip 200.

[0070] S130, the optical parameters of the light-emitting diode chip 200 are acquired through the acquisition device 20.

[0071] In one example, the process of the chip screening system 100 screening the yield of the light-emitting diode chip 200 is as follows: the light-emitting diode chip 200 is placed in the test backplane groove with a passive matrix or active matrix driving circuit, and the power supply and synchronous acquisition method of line-by-line scanning is adopted to realize the synchronous acquisition of the chip's electrical and optical properties.

[0072] According to the chip screening method provided in this application, the chip is a light-emitting diode (LED) chip, and the chip screening system includes a test backplane and a data acquisition device. The test backplane includes a first driving circuit, a second driving circuit, and multiple receiving areas. A first connection portion and a second connection portion in the receiving areas are respectively connected to the anode and cathode of the LED chip. The first driving circuit is connected to the first connection portion through a first trace to adjust the anode voltage of the LED chip, and the second driving circuit is connected to the second connection portion through a second trace to adjust the cathode voltage of the LED chip. By controlling the anode and cathode voltages of the LED chips in the multiple receiving areas through the first and second driving circuits respectively, the LED chip currently being tested can be accurately lit. Combined with the design of multiple receiving areas, batch chip screening is realized, improving the efficiency and accuracy of chip yield screening.

[0073] In some embodiments, such as Figure 8 As shown, before acquiring the optical parameters of the light-emitting diode chip through the acquisition device, the method may further include step S140.

[0074] S140 uses a transparent cover plate to cover the light-emitting diode chip.

[0075] In this embodiment, the transparent cover plate can uniformly apply pressure to cover the LED chip, ensuring a stable electrical contact between the chip and the test backplane, avoiding test errors caused by poor local contact. Its transparency does not hinder the acquisition of optical parameters during the pressure application process, improving the efficiency and accuracy of batch chip screening.

[0076] In some embodiments, such as Figure 9 As shown, the method may further include step S150.

[0077] S150 uses a transparent cover to transfer the light-emitting diode chip to the driver backplane to obtain the display panel.

[0078] The embodiments of this application use a transparent cover plate (such as a transparent cover plate with an adhesive layer on the side facing the test back plate) to not only apply pressure evenly and achieve uniform electrical contact of the light-emitting diode chip, but also to serve as a temporary carrier to quickly transfer batches of light-emitting diode chips to the final back plate.

[0079] In some embodiments, such as Figure 10 As shown, multiple accommodating areas are arranged in rows and columns; step S120 applies voltage to the anode and cathode of the light-emitting diode chip through the first driving circuit and the second driving circuit respectively to light up the light-emitting diode chip, and may include step S121.

[0080] S121, voltages are applied to the anode and cathode of the LED chip through the first driving circuit and the second driving circuit respectively, so as to light up the LED chip one by one.

[0081] The principle that allows a single LED chip to be lit is as follows: when a positive voltage of 3V is applied to the m-th row, 0V to the n-th column, and 0V to the other rows and 3V to the other columns, only (m, n) is in a forward bias (that is, the voltage difference across the LED chip is greater than the turn-on voltage). The LED chip at (m, n) is turned on, so the current can be measured. At this time, a high-speed camera captures the light emitted by the LED chip at (m, n), thereby obtaining the wavelength, brightness, and chromaticity, thus achieving rapid contact screening of wafer-level chips.

[0082] The embodiments of this application can apply voltages to the anode and cathode of the light-emitting diode chip through the first driving circuit and the second driving circuit respectively, which can precisely control the voltage difference across each light-emitting diode chip, and can test each light-emitting diode chip individually to ensure independent and accurate measurement of electrical and optical parameters.

[0083] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip screening system, characterized in that, The chip is a light-emitting diode chip, and the chip screening system includes: The test backplane includes a first driving circuit, a second driving circuit, and multiple receiving areas. Each receiving area includes a first connection portion and a second connection portion. The first driving circuit is connected to the first connection portion via a first trace, and the second driving circuit is connected to the second connection portion via a second trace. The first connection portion and the second connection portion are respectively used to connect the anode and cathode of the light-emitting diode chip. A data acquisition device is used to acquire the optical parameters of the light-emitting diode chip.

2. The chip screening system according to claim 1, characterized in that, The plurality of receiving areas are arranged in rows and columns. The first connecting portions of the plurality of receiving areas in the same row are connected to the same first routing line, and the second connecting portions of the plurality of receiving areas in the same column are connected to the same second routing line.

3. The chip screening system according to claim 2, characterized in that, The first connection portions of the multiple accommodating areas in different rows are connected to different first traces, the second connection portions of the multiple accommodating areas in different columns are connected to different second traces, and different first traces are connected to different output terminals of the first driving circuit, and different second traces are connected to different output terminals of the second driving circuit.

4. The chip screening system according to claim 1, characterized in that, The receiving area includes a recess, and the first connecting portion and the second connecting portion are located on the bottom surface of the recess.

5. The chip screening system according to claim 4, characterized in that, The surface of the recessed portion, excluding the first connecting portion and the second connecting portion, includes a light-shielding layer.

6. The chip screening system according to claim 4, characterized in that, The depth of the recess is less than the thickness of the light-emitting diode chip.

7. The chip screening system according to claim 1, characterized in that, The chip screening system also includes: A transparent cover plate is used to cover the light-emitting diode chip.

8. The chip screening system according to claim 7, characterized in that, The side of the cover plate facing the test back plate includes an adhesive layer.

9. The chip screening system according to claim 7, characterized in that, The test backplate and / or the transparent cover plate include alignment marks.

10. The chip screening system according to claim 7, characterized in that, The transparent cover plate includes a sapphire substrate.

11. A chip screening method, characterized in that, The method, applied to the chip screening system as described in any one of claims 1 to 10, comprises: The light-emitting diode chip is placed in the receiving area, and the anode and cathode of the light-emitting diode chip are respectively in contact with the first connection part and the second connection part; The first driving circuit and the second driving circuit apply voltages to the anode and cathode of the light-emitting diode chip respectively to light up the light-emitting diode chip; The optical parameters of the light-emitting diode chip are acquired through the acquisition device.

12. The chip screening method according to claim 11, characterized in that, Before acquiring the optical parameters of the light-emitting diode chip through the acquisition device, the method further includes: The light-emitting diode chip is covered with a transparent cover plate.

13. The chip screening method according to claim 12, characterized in that, Also includes: The light-emitting diode chip is transferred to the driving backplate using the transparent cover plate to obtain the display panel.

14. The chip screening method according to claim 11, characterized in that, The plurality of receiving areas are arranged in rows and columns; the step of applying voltages to the anode and cathode of the light-emitting diode chip through the first driving circuit and the second driving circuit respectively to light up the light-emitting diode chip includes: The first driving circuit and the second driving circuit apply voltages to the anode and cathode of the light-emitting diode chip respectively, so as to light up the light-emitting diode chip one by one.

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