Synchrotron Radiation Detection Electronic System

Abstract

This invention relates to a synchrotron radiation detection electronics system, comprising a base plate, a first core plate, and a second core plate, both mounted on the base plate and connected to it. The base plate includes an energy spectrum data acquisition module and an image data acquisition module. The energy spectrum data acquisition module acquires energy spectrum data and sends the acquired digitized energy spectrum data to the first core plate. The image data acquisition module acquires digitized image data and sends it to the first core plate. The first core plate performs deep inference on the digitized energy spectrum data or digitized image data and sends the deep-inferred digitized energy spectrum data or digitized image data to the second core plate. The second core plate performs standardization processing on the deep-inferred digitized energy spectrum data or digitized image data and sends the standardized digitized energy spectrum data or digitized image data to a host computer.

Description

Technical Field

[0001] This invention relates to the field of synchrotron radiation detection technology, and more specifically to a synchrotron radiation detection electronic system. Background Technology

[0002] With the continuous improvement of synchrotron radiation source brightness and the increasing complexity of experiments, modern photonics research has placed higher demands on synchrotron radiation detection electronics systems:

[0003] High-resolution energy dispersive spectroscopy (EDS) requires semiconductor detectors to achieve high energy resolution at high count rates (>500 kcps). However, hardware dead time and signal overlap effects can lead to severe pulse buildup. Traditional rejection methods may discard up to 80% of the signal, especially in experiments with low element concentrations or high background levels, easily causing fluorescence signal overload and severely affecting the reliability of experimental data.

[0004] High-speed image processing requirements: In applications such as CT tomography, in-situ mechanical characterization, structural dynamics evolution, and multidimensional spectrum-image joint experiments, two-dimensional detectors generate several gigabytes of raw image data per second. This data needs to be preprocessed, denoised, feature extracted, and reconstructed in real time within a millisecond timescale.

[0005] In existing technologies, energy spectrum detection and image detection require their own dedicated electronic systems, which are difficult to meet the requirements of high energy spectrum resolution and high image throughput. Summary of the Invention

[0006] The purpose of this invention is to provide a synchrotron radiation detection electronics system that can process both energy spectrum detection data and image detection data, and can meet the requirements of high energy spectrum resolution and high image throughput.

[0007] To achieve the above objectives, the present invention provides a synchrotron radiation detection electronics system, comprising a base plate, a first core plate, and a second core plate, both disposed on the base plate and connected to it. The base plate includes an energy spectrum data acquisition module and an image data acquisition module. The energy spectrum data acquisition module acquires energy spectrum data and sends the acquired digitized energy spectrum data to the first core plate. The image data acquisition module acquires digitized image data and sends it to the first core plate. The first core plate performs deep inference on the digitized energy spectrum data or the digitized image data and sends the deep-inferred digitized energy spectrum data or digitized image data to the second core plate. The second core plate performs standardization processing on the deep-inferred digitized energy spectrum data or digitized image data and sends the standardized digitized energy spectrum data or digitized image data to a host computer.

[0008] Optionally, the energy spectrum data acquisition module includes a front-end signal conditioning circuit, an analog-to-digital converter, and a high-speed communication interface. The front-end signal conditioning circuit is used to receive the raw analog energy spectrum data output by the energy spectrum detector and perform gain matching, bandwidth limiting, noise suppression, and waveform shaping on the raw analog energy spectrum data to obtain conditioned analog energy spectrum data. The conditioned analog energy spectrum data is sent to the analog-to-digital converter, which is used to convert the conditioned analog energy spectrum data into digital energy spectrum data. The high-speed communication interface is used to send the digital energy spectrum data to the first core board.

[0009] Optionally, the image data acquisition module includes a first Ethernet interface and a second Ethernet interface. The first Ethernet interface is used for system control, synchronization triggering, and status feedback, and the second Ethernet interface is used to transmit the digitized image data to the first core board in a low-latency manner.

[0010] Optionally, the baseboard is further configured to uniformly distribute sampling clock, synchronization trigger, and time stamp signals to the first core board and the second core board, so that the baseboard, the first core board, and the second core board can operate collaboratively under the same clock domain or deterministic cross-clock domain conditions.

[0011] Optionally, the baseboard also integrates USB, JTAG, UART, EMMC, and clock domain power management modules.

[0012] Optionally, a deep learning inference framework is deployed on the first core board. The deep learning inference framework is used to execute an energy spectrum data inference model and an image data inference model. The energy spectrum data inference model is used to perform deep inference on the digitized energy spectrum data to obtain deep-inferred digitized energy spectrum data. The image data inference model is used to perform deep inference on the digitized image data to obtain deep-inferred digitized image data.

[0013] Optionally, both the energy spectrum data inference model and the image data inference model are pre-trained deep learning models; the digitized energy spectrum data is a digitized pulse signal, and the energy spectrum data inference model is used to perform pulse stacking identification, amplitude recovery, and energy spectrum reconstruction operations on the digitized pulse signal; the image data inference model is used to perform noise reduction, flat field correction, edge enhancement, and image reconstruction operations on the digitized image data.

[0014] Optionally, the first core board is an FPGA, NPU, or SoC.

[0015] Optionally, the first core board is configured with a model parameter storage system and a cache structure for permanently storing the parameters of the energy spectrum data inference model and the image data inference model.

[0016] Optionally, the second core board includes a high-performance processor. When the synchrotron radiation detection electronics system acquires energy spectrum data, the high-performance processor causes the first core board to load the energy spectrum data inference model. When the synchrotron radiation detection electronics system acquires energy spectrum data, the high-performance processor causes the first core board to load the image data inference model. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a synchrotron radiation detection electronics system according to an embodiment of the present invention. Detailed Implementation

[0018] The preferred embodiments of the present invention are given below with reference to the accompanying drawings and described in detail.

[0019] like Figure 1As shown, this embodiment of the invention provides a synchrotron radiation detection electronics system, which includes a base plate 100, a first core plate 200, and a second core plate 300. The first core plate 200 and the second core plate 300 are disposed on the base plate 100 and connected to the first core plate 200 and the second core plate 300. The first core plate 200 is connected to the second core plate 300. The base plate 100 includes an energy spectrum data acquisition module 110 and an image data acquisition module 120. The energy spectrum data acquisition module 110 is used to acquire energy spectrum data and send the acquired digitized energy spectrum data to the first core plate 200. The image data acquisition module 120 is used to acquire... The system digitizes image data and sends it to the first core board 200. The first core board 200 performs deep inference on the digitized energy spectrum data or image data and sends the deep-inferred digitized energy spectrum data or digitized image data to the second core board 300. The second core board 300 performs standardization processing (including format conversion, packet processing, adding indexes and timestamps, etc.) on the deep-inferred digitized energy spectrum data or digitized image data and sends the standardized digitized energy spectrum data or digitized image data to the host computer (not shown in the figure). The host computer is used for real-time display, storage or feedback control of the data.

[0020] The energy spectrum data acquisition module 110 includes a front-end signal conditioning circuit 121, an analog-to-digital converter (ADC) 122, and a high-speed communication interface 123. The front-end signal conditioning circuit 121 receives the raw analog energy spectrum data (e.g., analog charge signal or photoelectric signal) output from the energy spectrum detector and performs gain matching, bandwidth limiting, noise suppression, and waveform shaping on the raw analog energy spectrum data to ensure that its dynamic range, signal-to-noise ratio, and spectral characteristics meet the input requirements of the subsequent ADC 122. The conditioned analog energy spectrum data is then fed into the ADC 122, which converts the conditioned analog energy spectrum data into digital energy spectrum data. The high-speed communication interface 123 transmits the digital energy spectrum data to the first core board 200. For example, the ADC 122 can be a high-speed ADC with a 14-16 bit resolution and an 80-250 MSPS sampling rate to meet the dual requirements of time resolution and dynamic range for synchrotron radiation energy spectrum data under high count rate conditions. The high-speed communication interface 123 can be an Aurora or a high-speed SerDes interface, used to achieve low-latency transmission of energy spectrum data. By conditioning the raw analog energy spectrum data through the front-end signal conditioning circuit 121, a stable and clearly characterized input waveform can be provided to the first core board 200, laying the necessary signal foundation for its effective inference of energy spectrum data.

[0021] The image data acquisition module 120 may include a first Ethernet interface 121 and a second Ethernet interface 122. Both the first Ethernet interface 121 and the second Ethernet interface 122 can be used to transmit digitized image data to the first core board 200 in a low-latency manner. The first Ethernet interface 121 can also be used for system control, synchronization triggering, and status feedback. The digitized image data is a data stream detected by the image detector. This data stream is typically a high-speed frame sequence, pixel array data, or multi-channel triggered readout results. The baseboard 100 can receive the digitized image data from the image detector through the first Ethernet interface 121 and / or the second Ethernet interface 122. The first core board 200 performs preliminary buffering and protocol parsing on the digitized image data.

[0022] The baseboard 100 simultaneously distributes sampling clock, synchronization trigger, and time stamp signals to other modules of the electronics system to ensure that the baseboard 100, the first core board 200, and the second core board 300 operate collaboratively under the same clock domain or deterministic cross-clock domain conditions, thereby meeting the stringent requirements of synchrotron radiation experiments for time consistency and deterministic timing. The baseboard 100 can also integrate structured interfaces such as PCIe, FMC, or VPX for inter-board interconnection and system expansion. The baseboard 100 can also integrate auxiliary modules such as USB, JTAG (Joint Test Action Group), UART (Universal Asynchronous Receiver / Transmitter), EMMC (Embedded Multimedia Card), clock, and power management for system debugging, configuration management, and power supply and control of the core boards, thereby ensuring the stable operation of the entire electronics system.

[0023] Through the above design, the base plate 100 can not only adapt to the different requirements of different types of detectors in terms of signal shape, bandwidth and real-time performance, but also provide a high-bandwidth, low-latency and timing-controllable digital data entry for the subsequent first core board 100.

[0024] The first core board 200 is a key hardware unit for realizing core functions such as intelligent recognition of energy spectrum data and image reconstruction. Specifically, the first core board 200 deploys a deep learning inference framework, which is used to execute energy spectrum data inference models and image data inference models. The energy spectrum data inference model performs deep inference on digitized energy spectrum data to obtain deeply inferred digitized energy spectrum data, while the image data inference model performs deep inference on digitized image data to obtain deeply inferred digitized image data. Both the energy spectrum data inference model and the image data inference model are pre-trained deep learning models. Through these deep learning models, high-speed real-time processing of energy spectrum data and image data can be achieved. Digitized energy spectrum data is typically a digitized pulse signal. The energy spectrum data inference model performs operations such as pulse stacking recognition, amplitude recovery, and energy spectrum reconstruction on the digitized pulse signal. The image data inference model implements functions such as image denoising, flat-field correction, edge enhancement, and real-time image reconstruction.

[0025] For example, the energy spectrum data inference model can be a Transformer, TCN (Temporal Convolutional Network) or an equivalent temporal neural network model, while the image data inference model can be a two-dimensional neural network such as Vision Transformer (ViT) or CNN (Convolutional Neural Network).

[0026] The first core board 200 can be a heterogeneous computing platform such as FPGA (Field Programmable Gate Array), NPU (Neural Processing Unit) or SoC (System-on-a-Chip). By deploying machine learning models on it, electronic systems can achieve real-time inference capabilities at the microsecond to millisecond level.

[0027] By mapping machine learning model inference computation to a parallelized, pipelined hardware data path, this invention significantly reduces inference latency and enables complex energy spectrum and image processing tasks that originally relied on backend GPUs or offline servers to be completed in real time within the electronics system.

[0028] To support the updability and efficient operation of deep learning models, the First Core Board 200 can be configured with a comprehensive model parameter storage system and high-speed cache structure. Volatile storage modules (such as FLASH or solid-state drives) are used to permanently store the weights, structure definitions, and model version information of the deep learning model, ensuring that the model state is maintained even after power failure. This facilitates rapid model switching or upgrades under different experimental conditions. Simultaneously, the First Core Board 200 can also be configured with a large-capacity, high-bandwidth DDR4 cache to store intermediate feature maps, input buffers, weight caches, and control instructions during inference. This caching mechanism effectively improves the continuity and stability of data processing, ensuring that the deep learning inference network maintains high throughput in real-time scenarios and reduces latency caused by external storage access.

[0029] After receiving digital signals (which may be digitized energy spectrum data or digitized image data) from the baseboard 100, the first core board 200 performs necessary preprocessing operations on them, such as baseline drift correction, amplitude normalization, noise filtering, and time alignment, to ensure that the input data meets the feature requirements of the deep learning network. After preprocessing, the data is sent to the corresponding deep learning inference network, where heterogeneous computing units perform computational tasks such as stacking recognition, energy spectrum recovery, or image reconstruction in a hardware-accelerated manner. After the inference process is completed, the first core board 200 sends the inferred data to the second core board 300 in a structured data format.

[0030] Through the above architecture and process, the first core board 200 realizes full-process hardware acceleration capabilities from data preprocessing and deep learning inference to result output, enabling the present invention to provide stable, real-time, and high-precision intelligent signal analysis performance in synchrotron radiation experimental environments with high count rates and high data volumes. It is the core module for the present invention to realize deep learning electronics functions.

[0031] The second core board 300 is the management center of the electronic system of this invention. It is an important component for realizing system operation coordination, data organization, and interaction with the host computer. It runs a general operating system, such as Linux, to provide flexible software management capabilities, driver support, and network communication capabilities. Through high-speed connection with the first core board 200 and the baseboard 100, it realizes data scheduling, status management, and communication control of the entire system. It is a key module for the stable operation and intelligent expansion of the deep learning electronic system. Its main functions include the following three aspects:

[0032] In terms of task scheduling and system management, the second core board 300 manages and coordinates the deep learning inference tasks executed by the first core board 200 through a scheduler within the operating system. Specifically, the second core board 300 is responsible for monitoring the data acquisition status of the baseboard 100, determining when to trigger deep learning inference, which type of deep learning inference to trigger, how to allocate computing resources, and whether new model parameters need to be loaded. Simultaneously, the second core board 300 is also responsible for system-level event response, including device initialization, model updates, error detection, anomaly recovery, and parameter synchronization, ensuring a stable, efficient, and controllable working state between the baseboard 100, the first core board 200, and the host computer. In high-load scenarios such as synchrotron radiation experiments, the task scheduling capability of the second core board 300 can effectively avoid system bottlenecks and data congestion, thereby ensuring the real-time performance and reliability of the entire electronic system.

[0033] In terms of data management, the second core board 300 is responsible for tasks such as caching, encapsulating, and verifying the integrity of the inference data. After the second core board 300 completes deep learning inference, the data is first received by the second core board 300 and enters the high-speed cache, where it performs standardization operations such as format conversion, packet processing, adding indexes and timestamps, etc., to facilitate recognition and processing by the host computer. In addition, the second core board 300 also has short-term data storage capabilities, which can temporarily store and buffer data under high-speed detection or high instantaneous network load to maintain the continuous operation of the system. The second core board 300 also performs checksum or fragment verification on the data before uploading through the data integrity verification module to ensure that the uploaded energy spectrum data or image data is error-free and without loss.

[0034] In terms of communication functionality, the second core board 300 uploads data to the host computer system via a high-speed bus interface or a 10GbE Ethernet interface, achieving high-throughput and low-latency data transmission capabilities. For two-dimensional image detectors, due to the large number of output images and high frame rates, the second core board 300 can support real-time transmission of large-scale image frame sequences; for energy spectrum detectors, due to the compact pulse recognition results, the second core board 300 can achieve low-latency energy spectrum data upload at almost millisecond or even microsecond levels. In applications requiring real-time feedback, such as synchrotron radiation experiments, the high-speed communication capability of the second core board 300 can significantly improve experimental efficiency and response speed.

[0035] The second core board 300 primarily includes a high-performance processor, DDR4 cache, and non-volatile storage modules such as FLASH or SSD. The high-performance processor is responsible for running the operating system, executing schedulers, and managing tasks. The DDR4 cache is used for temporarily caching deep learning inference results, system cache data, and communication buffer queues. The FLASH or SSD storage modules are used to store deep learning models, device configuration files, and historical experimental data, enabling the system to have self-updating capabilities and long-term data management capabilities.

[0036] The workflow of the electronic system according to an embodiment of the present invention is described in detail below:

[0037] First, the acquisition mode of the electronic system is determined based on actual usage. When acquiring data from a synchrotron radiation energy spectrum detector, it is in energy spectrum detection mode; when acquiring data from an image sensor, it is in image detection mode. In energy spectrum detection mode, the baseboard 100 acquires the energy spectrum data output by the energy spectrum detector through the energy spectrum data acquisition module 110, obtaining digitized energy spectrum data. This digitized energy spectrum data is then transmitted at high speed to the first core board 200. The second core board 300, based on the energy spectrum detection mode, controls the first core board 200 to load the energy spectrum data inference model and uses this model to infer the digitized energy spectrum data, obtaining inferred digitized energy spectrum data. This inferred data is then transmitted to the second core board 300. The second core board 300 encapsulates the inferred digitized energy spectrum data according to the host computer's acquisition format and adds auxiliary information such as timestamps, serial numbers, and energy scales. Finally, the data is uploaded to the host computer via high-speed Ethernet or other communication buses for real-time viewing by the user. When the detector count rate increases significantly, signal characteristics change, or the accuracy of the traditional model is insufficient, users can retrain a new stacking recognition model on a host computer or external GPU platform and refresh the updated model parameters to the first core board 200, thereby continuously optimizing system performance without replacing hardware and achieving continuous model evolution capability. In image detection mode, the baseboard 100 receives digitized image data from the image detector via a 10GbE high-speed Ethernet interface and sends it to the first core board 200 with low latency. The second core board 300 controls the first core board 200 to load the image data inference model and uses the image data inference model to infer the digitized image data, obtaining the inferred digitized image data. The second core board 300 then encapsulates the inferred digitized image data according to the host computer's acquisition format and adds auxiliary information such as timestamps, serial numbers, and energy scales. Subsequently, the data is output to the host computer in real time as a data stream through the high-speed communication module, ensuring that the host computer can receive high-resolution image data with extremely low latency. For experimental scenarios that require long-term recording or large-scale image sequences, the second core board 300 can also use its storage module to temporarily store the image data locally, enabling breakpoint resume or post-experiment processing.

[0038] To ensure the sufficiency of the disclosure of this invention, several alternative implementation schemes are also proposed. For example, the Transformer model in energy spectrum processing can be replaced with LSTM, TCN, or a one-dimensional convolutional neural network; the image processing network can be replaced with ResNet, U-Net, or a lightweight MobileNet structure; the baseboard ADC can adopt the JESD204B / C interface standard; the inter-board communication method can be expanded from independent board interconnection to PCIe slot form; the number of core boards in the system can also be expanded to a multi-board parallel structure to support larger-scale data throughput. Each module of this invention adopts a replaceable and scalable design, enabling the system to adapt to different detection tasks, different experimental station environments, and different bandwidth requirements.

[0039] The synchrotron radiation detection electronics system of this invention, through a design concept of functional layering and interface decoupling, constructs a three-layer hardware architecture consisting of a baseboard 100, a first core board 200, and a second core board 300. Data acquisition, deep learning inference, and system management functions are mapped to different boards, and coordinated operation is achieved through a unified high-speed interconnect and deterministic timing control mechanism. This ensures real-time performance and stability while enabling real-time processing of both energy spectrum and image detection modes on the same hardware platform. This invention completes energy spectrum and image data processing on the first core board 200, significantly shortening the data processing link and reducing the overall system bandwidth and computational pressure. This achieves unified, efficient, and real-time processing of energy spectrum detection and two-dimensional image detection under high-throughput synchrotron radiation conditions. Therefore, the system architecture proposed in this invention not only meets the requirements of synchrotron radiation experiments for high count rate, high throughput, and low latency, but also provides a sustainable and scalable deep learning electronics foundation for future detectors with higher energy resolution and larger pixel scale.

[0040] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. Various variations can be made to the above embodiments of the present invention. That is, all simple and equivalent changes and modifications made based on the claims and description of this invention fall within the protection scope of the claims of this patent. All aspects not described in detail in this invention are conventional technical content.

Claims

1. A synchrotron radiation detection electronics system, characterized in that, The system includes a base plate, a first core plate, and a second core plate, both of which are mounted on the base plate and connected to each other. The base plate includes an energy spectrum data acquisition module and an image data acquisition module. The energy spectrum data acquisition module acquires energy spectrum data and sends the acquired digitized energy spectrum data to the first core plate. The image data acquisition module acquires digitized image data and sends the digitized image data to the first core plate. The first core plate performs deep inference on the digitized energy spectrum data or the digitized image data and sends the deep-inferred digitized energy spectrum data or digitized image data to the second core plate. The second core plate performs standardization processing on the deep-inferred digitized energy spectrum data or digitized image data and sends the standardized digitized energy spectrum data or digitized image data to a host computer.

2. The synchrotron radiation detection electronics system according to claim 1, characterized in that, The energy spectrum data acquisition module includes a front-end signal conditioning circuit, an analog-to-digital converter, and a high-speed communication interface. The front-end signal conditioning circuit receives the raw analog energy spectrum data output by the energy spectrum detector and performs gain matching, bandwidth limiting, noise suppression, and waveform shaping on the raw analog energy spectrum data to obtain conditioned analog energy spectrum data. The conditioned analog energy spectrum data is sent to the analog-to-digital converter, which converts the conditioned analog energy spectrum data into digital energy spectrum data. The high-speed communication interface is used to send the digital energy spectrum data to the first core board.

3. The synchrotron radiation detection electronics system according to claim 1, characterized in that, The image data acquisition module includes a first Ethernet interface and a second Ethernet interface. The first Ethernet interface is used for system control, synchronization triggering, and status feedback. The second Ethernet interface is used to transmit the digitized image data to the first core board in a low-latency manner.

4. The synchrotron radiation detection electronics system according to claim 1, characterized in that, The baseboard is also configured to uniformly distribute sampling clock, synchronization trigger and time stamp signals to the first core board and the second core board, so that the baseboard, the first core board and the second core board can operate collaboratively under the same clock domain or deterministic cross-clock domain conditions.

5. The synchrotron radiation detection electronics system according to claim 1, characterized in that, The baseboard also integrates USB, JTAG, UART, EMMC, and clock domain power management modules.

6. The synchrotron radiation detection electronics system according to claim 1, characterized in that, The first core board is equipped with a deep learning inference framework, which is used to execute an energy spectrum data inference model and an image data inference model. The energy spectrum data inference model is used to perform deep inference on the digitized energy spectrum data to obtain deep-inferred digitized energy spectrum data, and the image data inference model is used to perform deep inference on the digitized image data to obtain deep-inferred digitized image data.

7. The synchrotron radiation detection electronics system according to claim 6, characterized in that, Both the energy spectrum data inference model and the image data inference model are pre-trained deep learning models; the digital energy spectrum data is a digital pulse signal, and the energy spectrum data inference model is used to perform pulse stacking recognition, amplitude recovery, and energy spectrum reconstruction operations on the digital pulse signal; the image data inference model is used to perform noise reduction, flat field correction, edge enhancement, and image reconstruction operations on the digital image data.

8. The synchrotron radiation detection electronics system according to claim 1, characterized in that, The first core board is an FPGA, NPU, or SoC.

9. The synchrotron radiation detection electronics system according to claim 7, characterized in that, The first core board is equipped with a model parameter storage system and a high-speed cache structure for permanently storing the parameters of the energy spectrum data inference model and the image data inference model.

10. The synchrotron radiation detection electronics system according to claim 7, characterized in that, The second core board includes a high-performance processor. When the synchrotron radiation detection electronics system acquires energy spectrum data, the high-performance processor causes the first core board to load the energy spectrum data inference model. When the synchrotron radiation detection electronics system acquires energy spectrum data, the high-performance processor causes the first core board to load the image data inference model.

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