Methods, apparatuses, electronic devices, and storage media for processing address access signals

Abstract

This application relates to the field of memory access technology, and discloses a method, apparatus, electronic device, and storage medium for processing address access signals. The method for processing address access signals includes: configuring and generating a page height cache region in volatile memory; configuring at least one mapping register according to the page height cache region, such that the mapping register corresponds one-to-one with the page height cache pages; when it is determined that the address access signal is an access to non-volatile memory, traversing all configured mapping registers and determining whether the first page number of one of them is the same as the page number accessed by the address access signal; if not, keeping the page number accessed by the address access signal unchanged; if it is, remapping the page number accessed by the address access signal to the second page number stored in the matched mapping register. The address access signal processing method according to the embodiments of this application can optimize time overhead when processing address access signals.

Description

Technical Field

[0001] This application relates to the field of memory access technology, and in particular to a method, apparatus, electronic device, and storage medium for processing address access signals. Background Technology

[0002] In chip architecture, non-volatile memory (NDRAM) serves as the core carrier of data storage, requiring frequent read, write, and erase operations. This high-intensity interaction can easily lead to reliability degradation of NDRAM, thus necessitating proactive control mechanisms to mitigate these risks. Related technologies employ a purely software-based approach to reduce the read / write frequency of NDRAM. Specifically, this involves creating a page cache region within the volatile memory and managing this region entirely through software. When processing address access signals, this software-based management of the page cache region performs clock logic checks before generating a result, resulting in increased clock latency. Summary of the Invention

[0003] This application provides a method, apparatus, electronic device, and storage medium for processing address access signals, which can optimize time overhead when processing address access signals.

[0004] In a first aspect, embodiments of this application provide a method for processing address access signals, comprising: configuring and generating a page high cache region in volatile memory, the page high cache region including at least one page high cache page, the page high cache page being matched with a portion of data pages in non-volatile memory and configured to be mutually data synchronized; configuring at least one mapping register according to the page high cache region, such that the mapping register corresponds one-to-one with the page high cache page, and each mapping register stores mapping information corresponding to one page high cache page and the matched data page, the mapping information including a first page number of the data page and a second page number of the page high cache page; when it is determined that the address access signal is an access to the non-volatile memory, traversing all the configured mapping registers, determining whether the first page number of one of them is the same as the access page number of the address access signal; if not, keeping the access page number of the address access signal unchanged; if it is, remapping the access page number of the address access signal to the second page number stored in the mapping register that is matched.

[0005] According to some of the foregoing embodiments of the first aspect of this application, configuring and generating a page cache region in volatile memory includes: configuring a page cache configuration register such that the page cache configuration register stores page cache configuration information; and configuring the volatile memory based on the page cache configuration information to generate a page cache region.

[0006] According to some of the foregoing embodiments of the first aspect of this application, the page cache configuration register includes a start address register and a page number register; configuring the page cache configuration register to store page cache configuration information includes: configuring the start address register to store page cache start address information; configuring the page number register to store the total number of page cache pages, wherein storing the page cache configuration information includes the page cache start address information and the total number of page cache pages.

[0007] According to some of the foregoing embodiments of the first aspect of this application, the step of configuring the page cache region in volatile memory based on the page cache configuration information and generating a page cache region includes: determining the starting address of the page cache region in the volatile memory based on the page cache start address information; and allocating the cache of the volatile memory based on the total number of page cache pages starting from the starting address to obtain the page cache region.

[0008] According to some of the foregoing embodiments of the first aspect of this application, the method for processing address access signals further includes: in response to an update of the page cache region, configuring and updating the mapping register according to the updated page cache region, such that the updated mapping register corresponds one-to-one with the updated page cache page.

[0009] According to some of the foregoing embodiments of the first aspect of this application, before the step of traversing all the configured mapping registers and determining whether the first page number of one of them is the same as the access page number of the address access signal when determining that the address access signal is an access to the non-volatile memory, the method for processing the address access signal further includes: determining whether the address access signal is an access to the non-volatile memory; if not, keeping the access page number of the address access signal unchanged.

[0010] Secondly, embodiments of this application provide an address access signal processing apparatus, comprising: a page cache control module configured to configure and generate a page cache region in volatile memory, the page cache region including at least one page cache page, the page cache page matching a portion of data pages in non-volatile memory and configured to be mutually data synchronized; and a mapping register control module electrically connected to the page cache control module, the mapping register control module being configured to configure at least one mapping register according to the page cache region, such that the mapping register corresponds one-to-one with the page cache page, and each mapping register stores a corresponding... The mapping information between the page-high cached page and the matching data page includes a first page number of the data page and a second page number of the page-high cached page. The address access signal processing module is configured to, when determining that the address access signal is an access to the non-volatile memory, traverse all configured mapping registers and determine whether the first page number of one of them is the same as the access page number of the address access signal; if not, keep the access page number of the address access signal unchanged; if it is, remap the access page number of the address access signal to the second page number stored in the matched mapping register.

[0011] According to some embodiments of the second aspect of this application, the address access signal processing apparatus further includes: a start address register configuration module electrically connected to the page cache control module, the start address register configuration module being configured to configure the start address register such that the start address register stores page cache start address information; a page number register configuration module electrically connected to the page cache control module, the page number register configuration module being configured to configure the page number register such that the page number register stores the total number of page cache pages; the page cache control module being configured to: determine the start address of the page cache region in the volatile memory based on the page cache start address information; and allocate cache in the volatile memory starting from the start address based on the total number of page cache pages to obtain the page cache region.

[0012] Thirdly, embodiments of this application provide an electronic device, the electronic device including a memory and a processor, the memory being communicatively connected to the processor, the memory storing instructions, and the processor calling the instructions in the memory to cause the electronic device to execute an address access signal processing method according to any of the foregoing embodiments of the first aspect of this application.

[0013] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed by a processor, implement a method for processing address access signals according to any of the foregoing embodiments of the first aspect of this application.

[0014] According to the address access signal processing method of this application embodiment, a page high cache region is configured and generated in volatile memory. The page high cache region includes at least one page high cache page, which is matched with a portion of data pages in non-volatile memory and configured to be mutually data synchronized. At least one mapping register is configured according to the page high cache region, such that the mapping register corresponds one-to-one with the page high cache page, and each mapping register stores mapping information corresponding to a page high cache page and a matched data page. The mapping information includes the first page number of the data page and the second page number of the page high cache page. When it is determined that the address access signal is an access to non-volatile memory, all configured mapping registers are traversed to determine whether the first page number of one of them is the same as the access page number of the address access signal. If it is not hit, the access page number of the address access signal remains unchanged. If it is hit, the access page number of the address access signal is remapped to the second page number stored in the hit mapping register. On the one hand, the above scheme uses a hardware mapping register to store the relevant mapping information of the page high cache region, replacing the scheme that manages the page high cache region using a purely software approach, thereby optimizing the usage of volatile memory. On the other hand, when processing address access signals, the comparison logic that iterates through all configured mapping registers for comparison is implemented based on combinational logic rather than clock logic. Therefore, processing address access signals does not require additional clock cycles. The current clock cycle in which the processor issues the address access signal can be used to process the address access signal (e.g., remapping the page number accessed by the address access signal to the second page number stored in the hit mapping register). Therefore, the above scheme can optimize the time overhead when processing address access signals. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0016] Figure 1 This is a flowchart illustrating one embodiment of the address access signal processing method according to this application; Figure 2 This is a schematic diagram of the structure of a volatile memory when a page high cache region is generated by configuring the volatile memory based on page high cache configuration information in one embodiment of the address access signal processing method according to this application. Figure 3 This is a schematic diagram of one embodiment of the address access signal processing apparatus according to this application; Figure 4 This is a schematic diagram of the hardware structure of an embodiment of the electronic device of this application. Detailed Implementation

[0017] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0018] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0019] This application provides a method for processing an address access signal. This method is applied, for example, in a system-on-a-chip (SoC), where the address access signal is generated and emitted by a processor. Figure 1 This is a flowchart illustrating one embodiment of the address access signal processing method according to this application. The address access signal processing method includes steps S110 to S150.

[0020] In step S110, a page cache region is configured and generated in the volatile memory (i.e., random access memory, RAM). The page cache region includes at least one page cache page, which matches a portion of the data pages in the non-volatile memory (NVM) and is configured to be mutually data synchronized.

[0021] In some embodiments, the steps of configuring and generating a page cache region in volatile memory described above may include: configuring a page cache configuration register such that the page cache configuration register stores page cache configuration information; and configuring the volatile memory based on the page cache configuration information to generate a page cache region.

[0022] In some embodiments, the page cache configuration register includes a start address register and a page number register. In this case, configuring the page cache configuration register to store page cache configuration information may include: configuring the start address register to store page cache start address information; and configuring the page number register to store the total number of pages in the page cache, wherein the stored page cache configuration information includes the page cache start address information and the total number of pages in the page cache.

[0023] Figure 2 This is a schematic diagram of the volatile memory structure when configuring a page cache region in volatile memory based on page cache configuration information in one embodiment of the address access signal processing method according to this application. In this embodiment, configuring a page cache region in volatile memory based on page cache configuration information includes: determining the starting address of the page cache region in volatile memory based on page cache start address information; and allocating cache in volatile memory based on the total number of page cache pages, starting from the starting address, to obtain the page cache region.

[0024] Because a page high cache region is configured in the volatile memory, when erasing or writing to non-volatile memory, the data to be written for one page is first written to the page high cache region and not written to the non-volatile memory yet. When erasing or writing this page multiple times, the page high cache region is updated first, and after the application completes the operation, the non-volatile memory is updated once (that is, the corresponding data page in the non-volatile memory is synchronized with the page high cache region).

[0025] like Figure 1 In step S120, at least one mapping register is configured according to the page height cache region, such that the mapping register corresponds one-to-one with the page height cache page, and each mapping register stores mapping information between a corresponding page height cache page and a matching data page. The mapping information includes the first page number of the data page and the second page number of the page height cache page. In this embodiment, the first page number and the second page number are both logical page numbers.

[0026] In this embodiment, the mapping registers correspond one-to-one with the page height cache pages. Specifically, the number of valid mapping registers is equal to the number of page height cache pages in the configured page height cache region. The first mapping register corresponds to the page height cache page of the first page in the page height cache region, the second mapping register corresponds to the page height cache page of the second page in the page height cache region, and so on.

[0027] In step S130, when it is determined that the address access signal is an access to non-volatile memory, all configured mapping registers are traversed to determine whether the first page number of one of them is the same as the access page number of the address access signal.

[0028] like Figure 1If the access is not successful, in step S140, the access page number of the address access signal remains unchanged.

[0029] like Figure 1 If a hit occurs, in step S150, the access page number of the address access signal is remapped to the second page number stored in the hit mapping register, so that the address access signal is remapped to an access to the page high buffer region.

[0030] In some embodiments, prior to step S130, the method for processing the address access signal further includes step 160.

[0031] In step S160, it is determined whether the address access signal is for accessing non-volatile memory. If not, in step S170, the page number accessed by the address access signal remains unchanged.

[0032] Optionally, in some embodiments, the method for processing the address access signal further includes: in response to an update of the page high cache region, configuring and updating the mapping register according to the updated page high cache region, so that the updated mapping register corresponds one-to-one with the updated page high cache page.

[0033] In the above embodiments, configurable registers are provided in the hardware system for software use, specifically a mapping register and a page cache configuration register. The page cache configuration register includes a start address register and a page number register. The start address register and the page number register are used to store the page cache start address information and the total number of page cache pages, respectively, so that the software can allocate the desired page cache area in volatile memory and reduce the occupation of volatile memory.

[0034] According to the address access signal processing method of this application embodiment, a page high cache region is configured and generated in volatile memory. The page high cache region includes at least one page high cache page, which is matched with a portion of data pages in non-volatile memory and configured to be mutually data synchronized. At least one mapping register is configured according to the page high cache region, such that the mapping register corresponds one-to-one with the page high cache page, and each mapping register stores mapping information corresponding to a page high cache page and a matched data page. The mapping information includes the first page number of the data page and the second page number of the page high cache page. When it is determined that the address access signal is an access to non-volatile memory, all configured mapping registers are traversed to determine whether the first page number of one of them is the same as the access page number of the address access signal. If it is not hit, the access page number of the address access signal remains unchanged. If it is hit, the access page number of the address access signal is remapped to the second page number stored in the hit mapping register. On the one hand, the above scheme uses a hardware mapping register to store the relevant mapping information of the page high cache region, replacing the scheme that manages the page high cache region using a purely software approach, thereby optimizing the usage of volatile memory. On the other hand, when processing address access signals, the comparison logic that iterates through all configured mapping registers for comparison is implemented based on combinational logic rather than clock logic. Therefore, processing address access signals does not require additional clock cycles. The current clock cycle in which the processor issues the address access signal can be used to process the address access signal (e.g., remapping the page number accessed by the address access signal to the second page number stored in the hit mapping register). Therefore, the above scheme can optimize the time overhead when processing address access signals.

[0035] This application also provides an address access signal processing apparatus, which is applied, for example, in a system-on-a-chip (SoC). The address access signal is generated and emitted by, for example, a processor. In this embodiment, the address access signal processing apparatus can be integrated into the processor or can be independently located outside the processor.

[0036] Figure 3 This is a schematic diagram of one embodiment of the address access signal processing apparatus according to this application. The address access signal processing apparatus includes a page height buffer control module 110, a mapping register control module 120, and an address access signal processing module 130.

[0037] Page cache control module 110 is configured to configure and generate a page cache region in volatile memory. The page cache region includes at least one page cache page, which matches a portion of data pages in non-volatile memory and is configured to be mutually data-synchronized. Page cache control module 110 can communicate with volatile memory.

[0038] The mapping register control module 120 is electrically connected to the page height cache control module 110. The mapping register control module 120 is configured to configure at least one mapping register according to the page height cache region, such that the mapping register corresponds one-to-one with the page height cache page, and each mapping register stores mapping information corresponding to a page height cache page and a matching data page. The mapping information includes the first page number of the data page and the second page number of the page height cache page.

[0039] The address access signal processing module 130 is capable of receiving address access signals. The address access signal processing module 130 can communicate with the processor, volatile memory, and non-volatile memory. The address access signal processing module 130 is configured to, upon determining that the address access signal is an access to non-volatile memory, traverse all configured mapping registers and determine if the first page number of one of them is the same as the access page number of the address access signal; if not, the access page number of the address access signal remains unchanged; if it is, the access page number of the address access signal is remapped to the second page number stored in the matched mapping register.

[0040] According to the address access signal processing apparatus of the present application embodiment, the page height cache control module 110 configures and generates a page height cache region in volatile memory. The page height cache region includes at least one page height cache page. The page height cache page matches a portion of the data pages in non-volatile memory and is configured to be mutually data-synchronized. The mapping register control module 120 configures at least one mapping register according to the page height cache region, such that the mapping register corresponds one-to-one with the page height cache page, and each mapping register stores mapping information corresponding to a page height cache page and a matching data page. The mapping information includes the first page number of the data page and the second page number of the page height cache page. When the address access signal processing module 130 determines that the address access signal is an access to non-volatile memory, it traverses all configured mapping registers and determines whether the first page number of one of them is the same as the access page number of the address access signal. If it does not match, the access page number of the address access signal remains unchanged. If it matches, the access page number of the address access signal is remapped to the second page number stored in the matched mapping register. On the one hand, the above scheme uses a hardware mapping register to store the relevant mapping information of the page high cache region, replacing the scheme that manages the page high cache region using a purely software approach, thereby optimizing the usage of volatile memory. On the other hand, when processing address access signals, the comparison logic that iterates through all configured mapping registers for comparison is implemented based on combinational logic rather than clock logic. Therefore, processing address access signals does not require additional clock cycles. The current clock cycle in which the processor issues the address access signal can be used to process the address access signal (e.g., remapping the page number accessed by the address access signal to the second page number stored in the hit mapping register). Therefore, the above scheme can optimize the time overhead when processing address access signals.

[0041] In some embodiments, the address access signal processing apparatus further includes a start address register configuration module 140 and a page number register configuration module 150.

[0042] The start address register configuration module 140 is electrically connected to the page height cache control module 110. The start address register configuration module 140 is configured to configure the start address register so that the start address register stores the page height cache start address information.

[0043] Page number register configuration module 150 is electrically connected to page height cache control module 110. Page number register configuration module 150 is configured to configure the page number register so that the page number register stores the total number of pages in the page height cache.

[0044] In some embodiments, the page cache control module 110 is configured to: determine the starting address of the page cache region in the volatile memory based on the page cache start address information; and allocate cache in the volatile memory based on the total number of page cache pages, starting from the starting address, to obtain the page cache region.

[0045] In the above embodiments, configurable registers are provided in the hardware system for software use, specifically a mapping register and a page cache configuration register. The page cache configuration register includes a start address register and a page number register. The start address register and the page number register are used to store the page cache start address information and the total number of page cache pages, respectively. The start address register configuration module 140 is configured to configure the start address register so that it stores the page cache start address information, and the page number register configuration module 150 is configured to configure the page number register so that it stores the total number of page cache pages. Therefore, the desired page cache area can be allocated in volatile memory, while reducing the occupation of volatile memory.

[0046] This application also provides an electronic device. Figure 4 This is a schematic diagram of the hardware structure of an embodiment of the electronic device of this application. The electronic device includes a memory 910 and a processor 920. The memory 910 and the processor 920 are communicatively connected. The memory 910 stores instructions. The processor 920 calls the instructions in the memory 910, causing the electronic device to execute the address access signal processing method according to any of the foregoing embodiments of this application.

[0047] The method for processing address access signals includes: configuring and generating a page cache region in volatile memory, the page cache region including at least one page cache page, the page cache page matching a portion of data pages in non-volatile memory and configured to be mutually data synchronized; configuring at least one mapping register according to the page cache region, such that the mapping register corresponds one-to-one with the page cache page, and each mapping register stores mapping information corresponding to a page cache page and a matching data page, the mapping information including the first page number of the data page and the second page number of the page cache page; when it is determined that the address access signal is an access to non-volatile memory, traversing all configured mapping registers, and determining whether the first page number of one of them is the same as the access page number of the address access signal; if not, keeping the access page number of the address access signal unchanged; if it is, remapping the access page number of the address access signal to the second page number stored in the matched mapping register.

[0048] Specifically, the processor 920 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0049] Memory 910 may include a large-capacity memory for data or instructions. For example, and not limitingly, memory 910 may include a hard disk drive (HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 910 may include removable or non-removable (or fixed) media. Where appropriate, memory 910 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 910 may be the non-volatile memory described above. In a particular embodiment, memory 910 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0050] In one example, the control device may also include a communication interface 930 and a bus 940. The processor 920, memory 910, and communication interface 930 are connected via the bus 940 and communicate with each other.

[0051] The communication interface 930 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0052] Bus 940 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 940 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0053] Furthermore, in conjunction with the address access signal processing method in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores instructions that, when executed by a processor, implement the address access signal processing method of any of the foregoing embodiments of this application.

[0054] The method for processing address access signals includes: configuring and generating a page cache region in volatile memory, the page cache region including at least one page cache page, the page cache page matching a portion of data pages in non-volatile memory and configured to be mutually data synchronized; configuring at least one mapping register according to the page cache region, such that the mapping register corresponds one-to-one with the page cache page, and each mapping register stores mapping information corresponding to a page cache page and a matching data page, the mapping information including the first page number of the data page and the second page number of the page cache page; when it is determined that the address access signal is an access to non-volatile memory, traversing all configured mapping registers, and determining whether the first page number of one of them is the same as the access page number of the address access signal; if not, keeping the access page number of the address access signal unchanged; if it is, remapping the access page number of the address access signal to the second page number stored in the matched mapping register.

[0055] This application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0056] The functional blocks shown in the above block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0057] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for processing address access signals, characterized in that, include: A page cache region is configured and generated in volatile memory, the page cache region including at least one page cache page, the page cache page being matched with a portion of data pages in non-volatile memory and configured to be mutually data synchronized; At least one mapping register is configured according to the page height buffer region such that the mapping register corresponds one-to-one with the page height buffer page, and each mapping register stores mapping information corresponding to a page height buffer page and a matching data page, the mapping information including the first page number of the data page and the second page number of the page height buffer page; When it is determined that the address access signal is an access to the non-volatile memory, all the configured mapping registers are traversed to determine whether the first page number of one of them is the same as the access page number of the address access signal; If the access is not successful, the access page number of the address access signal remains unchanged; If a hit occurs, the access page number of the address access signal is remapped to the second page number stored in the hit mapping register.

2. The method for processing address access signals according to claim 1, characterized in that, The configuration and generation of page height buffer regions in volatile memory includes: Configure the page cache configuration register so that it stores page cache configuration information; Based on the page cache configuration information, a page cache region is generated in the volatile memory.

3. The method for processing address access signals according to claim 2, characterized in that, The page height cache configuration register includes a start address register and a page number register; The configuration of the page cache configuration register, which stores page cache configuration information, includes: Configure the start address register such that it stores page high cache start address information; The page number register is configured to store the total number of pages in the page cache. The stored page cache configuration information includes the page cache start address information and the total number of pages in the page cache.

4. The method for processing address access signals according to claim 3, characterized in that, The step of configuring the page cache region in volatile memory based on the page cache configuration information includes: The starting address of the page cache region is determined in the volatile memory based on the page cache start address information. Starting from the starting address, the cache of the volatile memory is allocated based on the total number of pages in the page cache to obtain the page cache region.

5. The method for processing address access signals according to claim 1, characterized in that, Also includes: In response to an update of the page cache region, the mapping register is configured and updated according to the updated page cache region, so that the updated mapping register corresponds one-to-one with the updated page cache page.

6. The method for processing address access signals according to claim 1, characterized in that, Before the step of traversing all configured mapping registers and determining whether the first page number of one of them is the same as the page number accessed by the address access signal when determining that the address access signal is an access to the non-volatile memory, the method for processing the address access signal further includes: Determine whether the address access signal is an access to the non-volatile memory. If not, keep the accessed page number of the address access signal unchanged.

7. A processing apparatus for address access signals, characterized in that, include: The page height cache control module is configured to configure and generate a page height cache region in volatile memory, the page height cache region including at least one page height cache page, the page height cache page being matched with a portion of data pages in non-volatile memory and configured to be mutually data synchronized; A mapping register control module is electrically connected to the page height buffer control module. The mapping register control module is configured to configure at least one mapping register according to the page height buffer region, such that the mapping register corresponds one-to-one with the page height buffer page, and each mapping register stores mapping information corresponding to one page height buffer page and the matching data page. The mapping information includes the first page number of the data page and the second page number of the page height buffer page. The address access signal processing module is configured to, when determining that the address access signal is an access to the non-volatile memory, traverse all the configured mapping registers and determine whether the first page number of one of them is the same as the access page number of the address access signal; if not, keep the access page number of the address access signal unchanged. If a hit occurs, the access page number of the address access signal is remapped to the second page number stored in the hit mapping register.

8. The address access signal processing apparatus according to claim 7, characterized in that, Also includes: The start address register configuration module is electrically connected to the page height cache control module. The start address register configuration module is configured to configure the start address register so that the start address register stores page height cache start address information. The page number register configuration module is electrically connected to the page height cache control module. The page number register configuration module is configured to configure the page number register so that the page number register stores the total number of pages in the page height cache. The page height cache control module is configured to: determine the starting address of the page height cache region in the volatile memory based on the page height cache start address information; Starting from the starting address, the cache of the volatile memory is allocated based on the total number of pages in the page cache to obtain the page cache region.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory being communicatively connected to the processor, and the memory storing instructions. The processor invokes the instructions in the memory, causing the electronic device to execute the address access signal processing method according to any one of claims 1 to 6.

10. A computer-readable storage medium storing instructions thereon, characterized in that, When the instruction is executed by the processor, it implements the method for processing address access signals according to any one of claims 1 to 6.

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