Read-write cache verification method, electronic device, computer readable storage medium and program product
By combining white-box and black-box verification methods, the problem of insufficient simulation of cache behavior in chip design verification in existing technologies is solved, enabling more accurate read and write cache verification and expanding the applicable verification scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-02-09
- Publication Date
- 2026-06-02
AI Technical Summary
In existing chip design verification methods, black-box models cannot fully simulate cache behavior, while white-box models cannot accurately verify the same errors, resulting in insufficient verification accuracy.
A verification method combining white-box and black-box models is adopted. By acquiring the request response result and response reference result of the design module under test in each clock cycle, and comparing them with the output reference results of the bus function model and the black-box model in turn, the read and write cache is verified.
It improves the correctness and comprehensiveness of chip design verification, can accurately identify and correct errors when they occur in the white-box model, shortens the verification cycle, and improves the overall verification efficiency.
Smart Images
Figure CN122133573A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design verification technology, and in particular to a read / write cache verification method, electronic device, computer-readable storage medium, and computer program product. Background Technology
[0002] Currently, the commonly used chip design verification methods mainly include two types: black-box model verification and white-box model verification.
[0003] Black-box model verification verifies the design under test (DUT) by comparing the reference output of the black-box model with the actual output of the DUT. However, since black-box models use the output of a C language model as a reference, they have almost no timing information and cannot fully simulate the caching behavior of the DUT. Therefore, they cannot verify the correctness of the intermediate results of the DUT.
[0004] White-box model verification verifies the design under test (DUT) by comparing the real-time reference output of the white-box model with the actual real-time output of the DUT. However, the white-box model uses the Universal Verification Methodology (UVM) output as the reference result, which requires implementation based on the DUT's Register Transfer Level (RTL) code. If the white-box model and the DUT contain the same error, verification becomes impossible.
[0005] Therefore, there is an urgent need for a method that can verify the correctness of the data. Summary of the Invention
[0006] Therefore, it is necessary to provide a read / write cache verification method, electronic device, computer-readable storage medium, and computer program product that can improve the verification correctness in response to the above-mentioned technical problems.
[0007] Firstly, this application provides a read / write cache verification method, including:
[0008] Obtain an input request, send the input request to the design under test module, and obtain the request response result corresponding to the input request generated by the design under test module in each clock cycle according to a preset hardware description language;
[0009] The input request is forwarded to the white-box model, and the response reference result corresponding to the input request is obtained by the white-box model in each clock cycle according to the hardware description language;
[0010] By comparing the request-response result with the response reference result in each clock cycle, the white-box verification result is obtained.
[0011] The input request is forwarded to the black box model, and the output reference result corresponding to the input request is obtained by the black box model based on the preset read and write cache logic.
[0012] Obtain the request processing result output by the design module under test corresponding to the input request, compare the request processing result with the output reference result, and obtain the black-box verification result;
[0013] By comparing the white-box verification results with the black-box verification results, the read-write cache verification results of the design module under test are obtained.
[0014] In one embodiment, after sequentially comparing the request-response result with the response reference result in each clock cycle to obtain the white-box verification result, the method further includes:
[0015] If the white-box verification result is passed, and the input request includes a bypass write request with bypass attributes, the bypass write data and bypass write address output by the design under test module corresponding to the bypass write request are sampled using the bus function model.
[0016] Using the bus function model, the bypass write data is merged with the corresponding data stored in the internal memory according to the bypass write address to generate a bypass write merging result. The bypass write merging result includes bypass merged data and the corresponding bypass write address.
[0017] The step of forwarding the input request to the black-box model and obtaining the output reference result corresponding to the input request, which is output by the black-box model based on a preset read-write cache logic, includes:
[0018] The bypass write request is forwarded to the black box model, and the output reference result corresponding to the bypass write request is obtained by the black box model based on the read and write cache logic. The output reference result includes the reference merged data and the reference write address corresponding to the bypass write request.
[0019] The step of obtaining the request processing result corresponding to the input request output by the design module under test, comparing the request processing result with the output reference result, and obtaining the black-box verification result includes:
[0020] The bypass write merging result is obtained as the request processing result;
[0021] The black-box verification result is obtained by comparing the bypass write address in the request processing result with the reference write address in the output reference result, and by comparing the bypass merged data in the request processing result with the reference merged data in the output reference result.
[0022] In one embodiment, the method further includes:
[0023] When the input request includes a cache write request, the design under test module uses the cache write address corresponding to the cache write request to write the cache write data corresponding to the cache write request into the cache memory.
[0024] The cache write request is forwarded to the black box model, which uses the black box model to generate merged reference data corresponding to the cache write request based on the read-write cache logic, and adds the cache reference address corresponding to the cache write request to the reference address queue.
[0025] Upon receiving a flush request, the bus function model is used to sample the cache write data evicted from the cache memory and the corresponding cache write address. The cache write data is then merged with the corresponding data stored in the internal memory according to the cache write address to generate cache write merge data. Each cache write address is then added to the flush address queue in sequence.
[0026] The flushing request is forwarded to the black box model, and the output reference result corresponding to the flushing request is obtained by the black box model based on the read-write cache logic. The output reference result includes cache reference addresses taken out one by one from the reference address queue and the merged reference data corresponding to the cache reference address.
[0027] The step of obtaining the request processing result corresponding to the input request output by the design module under test, comparing the request processing result with the output reference result, and obtaining the black-box verification result includes:
[0028] The request processing result is obtained by sequentially combining each cache write address in the flush address queue with the corresponding cache write merge data;
[0029] The black-box verification result is obtained by comparing the cache write merged data in the request processing result with the merged reference data in the output reference result, and the cache write address in the request processing result with the cache reference address in the output reference result.
[0030] In one embodiment, forwarding the input request to the black-box model and obtaining the output reference result corresponding to the input request output by the black-box model based on a preset read-write cache logic further includes:
[0031] When the input request includes a cache read request, the black-box model outputs a reference result corresponding to the cache read request based on a preset read-write cache logic. The reference result includes reference read data and reference read address corresponding to the cache read request.
[0032] The step of obtaining the request processing result corresponding to the input request output by the design module under test, comparing the request processing result with the output reference result, and obtaining the black-box verification result includes:
[0033] When the input request includes a cache read request, the cache read data and cache read address obtained by the design module under test corresponding to the cache read request are combined to obtain the request processing result;
[0034] The black-box verification result is obtained by comparing the reference read address in the output reference result with the cache read address in the request processing result, and by comparing the reference read data in the output reference result with the cache read data in the request processing result.
[0035] In one embodiment, the method further includes:
[0036] Forward the cache read request to the public memory module;
[0037] Use the public memory module to query whether data is stored at the cache read address corresponding to the cache read request;
[0038] If no data is stored at the cache read address corresponding to the cache read request, the initial data stored at the cache read address is generated using the common memory module, and the initial data is written to the cache read address in the bus function model and the black box model.
[0039] In one embodiment, the step of sequentially comparing the request-response result with the response reference result within each clock cycle to obtain the white-box verification result includes:
[0040] If the request response result and the response reference result are consistent in each clock cycle, the white-box verification result is considered passed.
[0041] In one embodiment, comparing the white-box verification results with the black-box verification results to obtain the read / write cache verification results of the design module under test includes:
[0042] If the white-box verification result is inconsistent with the black-box verification result, the read-write cache verification result indicates that the read-write cache logic of the design module under test has an error.
[0043] Secondly, this application also provides an electronic device. The electronic device includes an input driver, a design-under-test module, a monitor, a white-box model, a black-box model, a white-box comparison module, a black-box comparison module, and a binding verification module;
[0044] The input driver is used to generate an input request and send the input request to the design under test module;
[0045] The design-under-test module is used to process the input request and generate a request response result corresponding to the input request in each clock cycle according to a preset hardware description language.
[0046] The monitor is used to monitor the input requests of the design under test module and forward the input requests to the white-box model and the black-box model;
[0047] The white-box model is used to output a response reference result corresponding to the input request in each clock cycle according to the hardware description language.
[0048] The white-box comparison module is used to obtain the request-response result of the design module under test in each clock cycle and the response reference result of the white-box model in each clock cycle, and compare the request-response result and the response reference result in each clock cycle to obtain the white-box verification result.
[0049] The black-box model is used to output a reference result corresponding to the input request based on a preset read / write cache logic.
[0050] The black-box comparison module is used to obtain the request processing result corresponding to the input request output by the design module under test and the output reference result output by the black-box model, and compare the request processing result with the output reference result to obtain the black-box verification result.
[0051] The combined verification module is used to compare the white-box verification results with the black-box verification results to obtain the read-write cache verification results of the design module under test.
[0052] Thirdly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the read-write cache verification method described in any of the embodiments of the first aspect.
[0053] Fourthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the read / write cache verification method described in any of the embodiments of the first aspect.
[0054] The aforementioned read / write cache verification method, electronic device, computer-readable storage medium, and computer program product obtain the request-response results corresponding to the input request generated by the design under test (DUT) module in each clock cycle according to a preset hardware description language. They then utilize a white-box model to generate response reference results corresponding to the input request in each clock cycle according to the DUT module's hardware description language. By sequentially comparing the DUT module's request-response results in each clock cycle with the white-box model's response reference results, they obtain white-box verification results. This verifies whether the DUT module executes according to the preset hardware description language in each clock cycle, thereby verifying the intermediate results and timing of the DUT module's read / write cache. Meanwhile, the above-mentioned read-write cache verification method also obtains the request processing result corresponding to the input request from the final output of the design module under test. It uses a black-box model to output the reference result corresponding to the input request based on the preset read-write cache logic. The black-box verification result is obtained by comparing the request processing result of the design module under test with the output reference result of the black-box model. The read-write cache verification result of the design module under test is obtained by comparing the white-box verification result with the black-box verification result. This not only verifies whether the request processing result of the design module under test is correct, but also avoids the problem of not being able to accurately verify the design module under test when the design module under test and the white-box model have the same error, thus improving the correctness of the read-write cache verification method. Attached Figure Description
[0055] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0056] Figure 1 A structural block diagram of an electronic device 100 in one embodiment Figure 1 ;
[0057] Figure 2 This is a flowchart illustrating a read / write cache verification method in one embodiment;
[0058] Figure 3 This is a flowchart illustrating the bypass write function verification steps in one embodiment;
[0059] Figure 4A This is a schematic diagram of the bypass write data storage step in one embodiment. Figure 1 ;
[0060] Figure 4B A schematic diagram of the bypass write data storage step in another embodiment. Figure 2 ;
[0061] Figure 4C A schematic diagram of the bypass write data storage step in another embodiment. Figure 3 ;
[0062] Figure 5 This is a flowchart illustrating the flushing function verification steps in one embodiment;
[0063] Figure 6 This is a flowchart illustrating the verification steps of the cache read function in one embodiment;
[0064] Figure 7 This is a flowchart illustrating the initial data generation steps in one embodiment;
[0065] Figure 8 Structural block diagram of electronic device 100 in another embodiment Figure 2 . Detailed Implementation
[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0067] It should be noted that the terms "comprising" and "having," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusion. The term "and / or" as used in this application refers to one of the embodiments or any combination of multiple embodiments. The data involved in this application (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data that have been fully authorized by the parties, and the collection, use, and processing of related data must comply with relevant regulations.
[0068] The read / write cache verification method provided in this application embodiment can be applied to, for example... Figure 1 The electronic device 100 shown may include, but is not limited to, an input driver 102, a monitor 104, a design under test module 106, a white-box model 108, a black-box model 110, a white-box comparison module 112, a black-box comparison module 114, and a combination verification module 116.
[0069] The input driver 102, also known as input_driver, can be used to generate input requests and send them to the design-under-test module 106.
[0070] The design under test (DUT) module 106 can be used to process input requests sent by the input driver 102 and generate a request response result corresponding to the input request in each clock cycle according to a preset hardware description language, such as Register-Transfer Level (RTL).
[0071] Monitor 104, also known as monitor, can be used to monitor the input requests of the design under test module 106 and forward the input requests of the design under test module 106 to the white box model 108 and the black box model 110.
[0072] The white-box model 108 can be used to implement the same timing operations as the design under test (DUT) 106 using the Universal Verification Methodology (UVM) model and the hardware description language of the DUT 106: outputting a response reference result corresponding to the input request of the DUT 106 in each clock cycle.
[0073] The white-box comparison module 112, also known as the white-box checker, can be used to obtain the request-response results of the design module under test 106 in each clock cycle and the response reference results of the white-box model 108 in each clock cycle in real time. The request-response results and response reference results in each clock cycle are compared sequentially to obtain the white-box verification results.
[0074] The black-box model 110 can be an end-to-end model that only records input data and does not implement high-speed buffer storage. The black-box model 110 can be used to output reference results corresponding to the input requests of the design-under-test module 106 based on a preset read-write cache logic using a C language model.
[0075] The black-box comparison module 114, also known as the black-box checker, can be used to obtain the request processing result corresponding to the input request output by the design module under test 106 and the output reference result output by the black-box model 110, compare the request processing result with the output reference result, and obtain the black-box verification result.
[0076] The verification module 116 can be used to compare the white-box verification results with the black-box verification results to obtain the read-write cache verification results of the design module 106 under test.
[0077] The aforementioned electronic device 100, based on the deployment of a white-box model 108 and a white-box comparison module 112 for white-box verification of the design module 106 under test, adds a black-box model 110 and a black-box comparison module 114 for black-box verification of the design module 106 under test. By deploying a combined verification module 116 to compare the white-box verification results output by the white-box comparison module 112 and the black-box verification results output by the black-box comparison module 114, it can not only use the white-box verification results to determine whether the request-response results of the design module 106 under test are correct in each clock cycle, but also use the comparison of the black-box verification results and the white-box verification results to identify situations where the white-box model 108 and the design module 106 under test have the same error, thereby improving the correctness and comprehensiveness of the read-write cache verification results.
[0078] In one exemplary embodiment, such as Figure 2 As shown, a read / write cache verification method is provided, which is applied to... Figure 1 Taking electronic device 100 as an example, the explanation includes the following steps S202 to S212. Wherein:
[0079] Step S202: Obtain the input request, send the input request to the design under test module, and obtain the request response result corresponding to the input request generated by the design under test module in each clock cycle according to the preset hardware description language.
[0080] The hardware description language may include a register-transfer level (RTL) description language that implements high-speed cache storage.
[0081] For example, the electronic device 100 can acquire the input request generated by the input driver 102 and send the input request to the design under test (DUT) module 106 for processing. It can also acquire the request response result corresponding to the input request generated by the DUT module 106 in each clock cycle according to a preset hardware description language.
[0082] Optionally, in some implementations, during the first clock cycle, the design-under-test (DUT) module 106 can perform a parsing operation on the input request according to the hardware description language, obtaining the write address or read address corresponding to the input request as the request response result for the first clock cycle. During the second clock cycle, the DUT module 106 can perform a data query operation according to the hardware description language: querying the data at the write address or read address corresponding to the input request in its internal cache memory (also known as Cache) as the request response result for the second clock cycle. During the third clock cycle, the DUT module 106 can perform a cache write operation according to the hardware description language, writing the data to be written in the input request to the write address in the cache memory as the request response result for the third clock cycle; or, it can perform a cache read operation to read the data at the read address in the cache memory as the request response result for the third clock cycle.
[0083] Step S204: Forward the input request to the white-box model and obtain the response reference result corresponding to the input request output by the white-box model in each clock cycle according to the hardware description language.
[0084] For example, electronic device 100 can monitor input requests from design-under-test module 106 via monitor 104 and forward the input requests to white-box model 108. It can then obtain the response reference results corresponding to the input requests output by white-box model 108 in each clock cycle according to the hardware description language of design-under-test module 106.
[0085] Optionally, in some implementations, during the first clock cycle, the white-box model 108 can perform a parsing operation on the input request according to a hardware description language, obtaining the write address or read address corresponding to the input request as the response reference result for the first clock cycle. During the second clock cycle, the white-box model 108 can perform a data query operation according to a hardware description language: querying the data at the write address or read address corresponding to the input request in its internal cache memory (also known as Cache) as the response reference result for the second clock cycle. During the third clock cycle, the white-box model 108 can perform a cache write operation according to a hardware description language, writing the data to be written in the input request to the write address in the cache memory as the response reference result for the third clock cycle; or, it can perform a cache read operation to read the data at the read address in the cache memory as the response reference result for the third clock cycle.
[0086] Step S206: Compare the request response results with the response reference results in each clock cycle to obtain the white-box verification results.
[0087] For example, the electronic device 100 can use the white-box comparison module 112 to obtain the request response results generated by the design-under-test module 106 and the response reference results generated by the white-box model 108 in real time within each clock cycle, and compare the request response results with the response reference results within the same clock cycle. If the request response results and response reference results within the same clock cycle are consistent, the white-box verification result for the current clock cycle is considered passed. Otherwise, the white-box verification result for the current clock cycle is considered failed.
[0088] Step S208: Forward the input request to the black box model and obtain the output reference result corresponding to the input request, which is output by the black box model based on the preset read and write cache logic.
[0089] Among them, the read-write cache logic can be used to characterize the data processing logic when the design module under test 106 implements the high-speed cache storage function under ideal conditions without deviation or error.
[0090] For example, electronic device 100 can monitor input requests from design-under-test module 106 via monitor 104 and forward the input requests to black-box model 110. It then obtains the output reference result from black-box model 110 after processing the input request based on preset read / write caching logic.
[0091] Step S210: Obtain the request processing result corresponding to the input request output by the design module under test, compare the request processing result with the output reference result, and obtain the black-box verification result.
[0092] For example, the electronic device 100 can use the black-box comparison module 114 to obtain the request processing result corresponding to the input request finally output by the design under test module 106, and the output reference result corresponding to the input request output by the black-box model 110. If the request processing result of the design under test module 106 is consistent with the output reference result output by the black-box model 110, the black-box verification result is passed. Otherwise, the black-box verification result is failed.
[0093] Step S212: Compare the white-box verification results with the black-box verification results to obtain the read-write cache verification results of the design module under test.
[0094] For example, the electronic device 100 can use the combined verification module 116 to compare the white-box verification result output by the white-box comparison module 112 with the black-box verification result output by the black-box comparison module 114. If the white-box verification result and the black-box verification result are consistent, the read-write cache verification result of the design module under test is obtained as passed. Otherwise, the read-write cache verification result is obtained as failed.
[0095] In the above-mentioned read / write cache verification method, the request-response results generated by the design module under test (DUT) in each clock cycle according to the preset hardware description language are obtained. The white-box model generates the response reference results corresponding to the input requests in each clock cycle according to the hardware description language of the DUT. The request-response results of the DUT in each clock cycle are compared with the response reference results of the white-box model to obtain the white-box verification results. This method can verify whether the DUT executes according to the preset hardware description language in each clock cycle, and realize the verification of the intermediate results of the read / write cache of the DUT and the timing of the read / write cache. Meanwhile, the above-mentioned read-write cache verification method also obtains the request processing result corresponding to the input request from the final output of the design module under test. It uses a black-box model to output the reference result corresponding to the input request based on the preset read-write cache logic. The black-box verification result is obtained by comparing the request processing result of the design module under test with the output reference result of the black-box model. The read-write cache verification result of the design module under test is obtained by comparing the white-box verification result with the black-box verification result. This not only verifies whether the request processing result of the design module under test is correct, but also avoids the problem of not being able to accurately verify the design module under test when the design module under test and the white-box model have the same error, thus improving the correctness of the read-write cache verification method.
[0096] Furthermore, since the white-box model and the black-box model work independently, the above-mentioned read-write cache verification method can also quickly develop an end-to-end black-box model to perform simple path verification of the design module under test in the early stage of verification. At the same time, the white-box model can be developed in parallel, thereby solving the problem of long white-box model development cycle and improving overall verification efficiency.
[0097] In an exemplary embodiment, the input request of the design under test (DUT) 106 may include a bypass write request with a bypass attribute. A bypass write request with a bypass attribute (also known as a bypass) can be used to characterize a write request that does not need to be cached in the internal cache memory of the DUT 106, but is instead written directly to a subsequent memory. Since the bypass write request does not need to be cached in the internal cache memory of the DUT 106, a bus function model can be deployed to simulate the implementation of the subsequent module of the DUT 106, using the internal memory of the bus function model as the subsequent memory for processing bypass write requests. Furthermore, the bypass write request processing function of the DUT 106 can be verified by comparing the bus function model with the black-box model 110.
[0098] like Figure 3 As shown, the read / write bypass verification method provided in this application may further include the following steps S302 to S310. Wherein:
[0099] In step S302, if the white-box verification result is passed and the input request includes a bypass write request with bypass attributes, the bypass write data and bypass write address output by the design under test module corresponding to the bypass write request are sampled using the bus function model.
[0100] Among them, the Bus Function Model (BFM) can be used to simulate the implementation of the subsequent modules of the design under test module 106, and has internal memory (also known as bfm_mem).
[0101] For example, when the input request includes a bypass write request with bypass attributes, the electronic device 100 can use the design-under-test (DUT) module 106 to parse the bypass write request with bypass attributes according to a preset hardware description language, obtain the bypass write data and bypass write address corresponding to the bypass write request, and output the bypass write data and bypass write address. If the white-box verification result is successful and the input request includes a bypass write request with bypass attributes, the bus function model of the DUT module 106's subsequent stage is used to sample the bypass write data and bypass write address output by the DUT module 106 corresponding to the bypass write request via the bus.
[0102] Step S304: Using the bus function model, the bypass write data is merged with the corresponding data stored in the internal memory according to the bypass write address to generate a bypass write merging result. The bypass write merging result includes the bypass merged data and the corresponding bypass write address.
[0103] Alternatively, in some implementations, such as Figure 4A As shown, the bypass write address output by the design-under-test module 106 is (1,1) and the bypass write data is (AAA). An internal memory 402 is deployed in the bus function model 400. Data (aaa) is stored at address (1,1) in the internal memory 402 that matches the bypass write address (1,1). The bus function model 400 can then use the bypass write data (AAA) corresponding to the bypass write address (1,1) to overwrite the original data (aaa) stored at address (1,1) in the internal memory 402, thereby obtaining the bypass write merged data (AAA) corresponding to the bypass write address (1,1). Optionally, in some other embodiments, if no data is stored at address (1,1) in the internal memory 402, the bypass write data (AAA) can be directly written at address (1,1) as the corresponding bypass write merged data.
[0104] Alternatively, in other embodiments, such as Figure 4BAs shown, the bypass write address output by the design under test module 106 is (1,1) and the bypass write data is (___AAA). That is, the first three bits of the bypass write data are empty. An internal memory 402 is deployed in the bus function model 400. Data (bbb___) is stored at address (1,1) in the internal memory 402 that matches the bypass write address (1,1). That is, the last three bits stored at address (1,1) in the internal memory 402 are empty. Therefore, the bus function model 400 can merge the bypass write data (___AAA) corresponding to the bypass write address (1,1) with the original data (bbb___) stored at address (1,1) in the internal memory 402. This results in the bypass merged data stored at the bypass write address (1,1) in the internal memory 402 being (bbbAAA).
[0105] Alternatively, in other embodiments, such as Figure 4C As shown, the bypass write address output by the design under test module 106 is (1,1) and the bypass write data is (___AAA). That is, the first three bits of the bypass write data are empty. An internal memory 402 is deployed in the bus function model 400. Data (bbba__) is stored at address (1,1) in the internal memory 402 that matches the bypass write address (1,1). That is, the last two bits stored at address (1,1) in the internal memory 402 are empty. Therefore, the bus function model 400 can merge the bypass write data (___AAA) corresponding to the bypass write address (1,1) with the original data (bbba__) stored at address (1,1) in the internal memory 402, and use the third bit 'A' in the bypass write data to overwrite the original stored third bit data 'a'. This makes the bypass merged data stored at the bypass write address (1,1) in the internal memory 402 (bbbAAA).
[0106] Step S306: Forward the bypass write request to the black box model and obtain the output reference result corresponding to the bypass write request output by the black box model based on the read-write cache logic. The output reference result includes the reference merged data and reference write address corresponding to the bypass write request.
[0107] For example, electronic device 100 can use monitor 104 to forward bypass write requests with bypass attributes to black-box model 110. The black-box model 110 obtains the data merging result when executing the bypass write request under ideal conditions without deviation or error, based on the read-write cache logic output, as its output reference result. The output reference result may include reference merged data (the data carried in the bypass write request merged with the corresponding data stored in the subsequent memory) and its corresponding reference write address.
[0108] Step S308: Obtain the bypass write merge result as the request processing result.
[0109] Step S310: Compare the bypass write address in the request processing result with the reference write address in the output reference result, and compare the bypass merged data in the request processing result with the reference merged data in the output reference result to obtain the black-box verification result.
[0110] For example, electronic device 100 can obtain the bypass write merging result of the bus function model as the request processing result and output the request processing result to black-box comparison module 114. Black-box comparison module 114 compares whether the bypass write address in the request processing result is consistent with the reference write address in the output reference result, and whether the bypass merged data in the request processing result is consistent with the reference merged data in the output reference result. If the bypass write address and the reference write address are consistent, and the bypass write data and the reference merged data are consistent, the black-box verification result is passed. Otherwise, the black-box verification result is failed.
[0111] In this embodiment, the bypass write address and bypass write data corresponding to the bypass write request with bypass attribute output by the design under test (DUT) are sampled using the bus functional model. The bus functional model then merges the bypass write data with the corresponding data stored in the internal memory based on the bypass write address, generating a bypass write merging result carrying the bypass merged data and its corresponding bypass write address. During black-box verification, the reference merged data output by the black-box model is compared with the bypass write merging result, and the reference write address output by the black-box model is compared with the bypass write address. This allows the bus functional model to simulate the request processing result of the DUT for the bypass write request with bypass attribute, and by combining the output reference result of the black-box model, a dual comparison of address and data is performed to verify whether the bypass write request processing function of the DUT 106 is implemented correctly, thereby expanding the applicable scenarios of the verification method.
[0112] In one exemplary embodiment, such as Figure 5 As shown, the read / write cache verification method provided in this application may further include the following steps S502 to S512. Wherein:
[0113] In step S502, if the input request includes a cache write request, the design under test module writes the cache write data corresponding to the cache write request to the cache write memory based on the cache write address corresponding to the cache write request.
[0114] Step S504: Forward the cache write request to the black box model, use the black box model to generate merged reference data corresponding to the cache write request based on the read and write cache logic, and add the cache reference address corresponding to the cache write request to the reference address queue.
[0115] For example, the design-under-test (DUT) module 106 may have a cache memory internally deployed. When an input request includes a cache write request, the electronic device 100 can use the DUT module 106 to parse the cache write request based on a preset hardware description language to obtain the cache write address and cache write data corresponding to the cache write request. The DUT module 106 then writes the cache write data to the address in its internal cache memory that matches the cache write address. Similarly, the cache write request can be forwarded to the black-box model 110, which processes the cache write request based on read-write cache logic, parses it to obtain the cache reference address and merged reference data corresponding to the cache write request, adds the cache reference address to the reference address queue, and establishes a correspondence between the cache reference address and the merged reference data.
[0116] In step S506, upon receiving a flush request, the bus function model is used to sample the cache write data evicted from the cache memory and the corresponding cache write address. The cache write data is then merged with the corresponding data stored in the internal memory according to the cache write address to generate cache write merge data. Each cache write address is then added to the flush address queue in sequence.
[0117] The flush request, also known as a flush request, can be used to evict write data from all addresses in the cache memory.
[0118] For example, upon receiving a flush request, the cache memory will proactively evict stored cached write data. Therefore, the bus function model of the subsequent stage of the design under test module 106 can be used to sample the output of the cache memory via the bus to obtain the cached write data evicted from the cache memory and the corresponding cached write address. Referring to the above-described method for generating bypass merged data, the bus function model is used to merge the cached write data with the corresponding data stored in the internal memory according to the cached write address to generate cached write merged data, and each cached write address is sequentially added to the flush address queue (i.e., the flush queue, an address queue used for black-box comparison).
[0119] Step S508: Forward the flush request to the black box model and obtain the output reference result corresponding to the flush request based on the read-write cache logic output by the black box model. The output reference result includes the cache reference address taken out one by one from the reference address queue and the merged reference data corresponding to the cache reference address.
[0120] For example, electronic device 100 can forward the flush request to black-box model 110. Black-box model 110 processes the flush request based on read / write cache logic, retrieving each cached reference address sequentially from the reference address queue according to the address order, and determining the merged reference data corresponding to each cached reference address. Each time a cached reference address is retrieved, it is combined with its corresponding merged reference data as the current output reference result. The output reference results corresponding to each cached reference address are then sent to black-box comparison module 114 sequentially according to the address order in the reference address queue.
[0121] Step S510: Sequentially combine each cache write address in the flush address queue with the corresponding cache write merge data to obtain the request processing result.
[0122] For example, the electronic device 100 can sequentially retrieve the cache write data corresponding to each cache write address according to the address order of each cache write address in the flush address queue. Furthermore, each time cache write data is retrieved, the current cache write address is combined with the cache write merge data to obtain the request processing result. The request processing result is then sent to the black-box comparison module 114.
[0123] Step S512: Compare the cache write merged data in the request processing result with the merged reference data in the output reference result, and compare the cache write address in the request processing result with the cache reference address in the output reference result to obtain the black-box verification result.
[0124] For example, the electronic device 100 can utilize the black-box comparison module 114 to perform the following operations sequentially, according to the order of the cache write address in the received request processing result and the cache reference address in the output reference result: comparing whether the cache write merged data in the request processing result and the merged reference data in the output reference result are consistent, and comparing whether the cache write address in the request processing result and the cache reference address in the output reference result are consistent. If the cache write merged data and the merged reference data are consistent, and the cache write address and the cache reference address are consistent, the black-box verification result is passed. Otherwise, the black-box verification result is failed.
[0125] In this embodiment, when the output request includes a cache write request, the design under test (DUT) module stores the cache write data into its internal cache memory based on the cache write address. A black-box model is used to determine the cache reference address and cache write data based on the read / write cache logic. When the output request includes a flush request, a bus function model is used to write the cache write data at each cache write address evicted from the cache memory into its internal memory to generate cache write merge data. A black-box model is used to output each cache reference address and its corresponding cache write data sequentially. The cache reference address is compared with the cache write address, and the merged reference data is compared with the cache write merge data to obtain the black-box verification result. This enables the verification of the cache write function and flush function of the DUT module, thereby expanding the applicable scenarios of the verification method.
[0126] In one exemplary embodiment, such as Figure 6 As shown, the read / write cache verification method provided in this application may further include the following steps S602 to S606. Wherein:
[0127] Step S602: If the input request includes a cache read request, obtain the output reference result corresponding to the cache read request output by the black box model based on the preset read-write cache logic. The output reference result includes the reference read data and reference read address corresponding to the cache read request.
[0128] For example, when the input request includes a cache read request, the electronic device 100 can use the black-box model 110 to parse the read-write cache logic to obtain the reference read address corresponding to the cache read request, and obtain the reference read data based on the reference read address. The combination of the reference read data and the reference read address is sent as the output reference result to the black-box comparison module 114.
[0129] Step S604: If the input request includes a cache read request, combine the cache read data and cache read address obtained by the design module under test corresponding to the cache read request to obtain the request processing result.
[0130] For example, when the input request includes a cache read request, the electronic device 100 can use the design-under-test module 106 to parse the cache read request based on a hardware description language to obtain the cache read address. Based on the cache read address, the cache read data corresponding to the cache read request is obtained, and the combination of the cache read address and the cache read data is sent as the request processing result to the black-box comparison module 114.
[0131] Step S606: Compare the reference read address in the output reference result with the cache read address in the request processing result, and compare the reference read data in the output reference result with the cache read data in the request processing result to obtain the black-box verification result.
[0132] For example, the electronic device 100 can use the black-box comparison module 114 to compare whether the cache read address and the reference read address are consistent, and to compare whether the cache read data and the reference read data are consistent. If the cache read address and the reference read address are consistent, and the cache read data and the reference read data are consistent, the black-box verification result is passed. Otherwise, the black-box verification result is failed.
[0133] Optionally, in other embodiments, the design-under-test module 106 may also send the cached read data as the request processing result of the cached read request to the black-box comparison module 114. Correspondingly, the black-box model 110 may send the reference read data as the output reference result to the black-box comparison module 114. The black-box comparison module 114 compares whether the cached read data and the reference read data are consistent. If the cached read data and the reference read data are consistent, the black-box verification result is "passed". Otherwise, the black-box verification result is "failed".
[0134] In this embodiment, by comparing the reference read address with the cache read address and comparing the reference read data with the cache read data when the input request includes a cache read request, the black-box verification result can be obtained, thereby verifying the cache read function of the design module under test and expanding the applicable scenarios of the verification method.
[0135] In one exemplary embodiment, such as Figure 7 As shown, the read / write cache verification method provided in this application may further include steps S702 to S706. Wherein:
[0136] Step S702: Forward the cache read request to the common memory module.
[0137] Step S704: Use the common memory module to query whether data is stored at the cache read address corresponding to the cache read request.
[0138] Step S706: If no data is stored at the cache read address corresponding to the cache read request, the initial data stored at the cache read address is generated using the common memory module, and the initial data is written to the cache read address in the bus function model and the black box model.
[0139] The common memory module, also known as common_mem, is used to provide initial data generation functions for the design-under-test module 106, the white-box model 108, and the black-box model 110. Optionally, in some implementations, the initial data can be randomly generated, or it can be generated default values (such as 0, 1, etc.).
[0140] For example, when the input driver 102 generates a cache read request, the electronic device 100 can forward the cache read request to the common memory module. The common memory module parses the cache read address corresponding to the cache read request and checks whether data is stored at that address. If no data is stored at the cache read address, the common memory module generates the initial data stored at the cache read address and writes it to the cache read address in both the bus function model and the black-box model 110. This allows the design-under-test module 106 and the white-box model 108 to read the corresponding initial data from the cache read address in the bus function model, while the black-box model 110 can also obtain the initial data from the cache read address.
[0141] In this embodiment, by generating initial data using the common memory module for cache read requests where no data is stored at the cache read address, and providing the initial data to the bus function model and the black box model, it is possible to avoid the data read by the design under test module, the white box model, and the black box model at the same address being different, thereby improving the feasibility of verification.
[0142] In an exemplary embodiment, step S206 includes: if the request response result and the response reference result are consistent in each clock cycle, the white-box verification result is obtained as passed.
[0143] In this embodiment, obtaining a pass result for white-box verification using the above method can improve the accuracy of verification.
[0144] In an exemplary embodiment, step S210 includes: if the white-box verification result and the black-box verification result are inconsistent, the read-write cache verification result is that the read-write cache logic of the design module under test has an error.
[0145] In this embodiment, by using the above method to determine that the read-write cache logic of the design module under test has errors, the problem of not being able to verify correctly when the white-box model and the design module under test have the same errors can be avoided, thereby improving the robustness and correctness of the verification method.
[0146] In one exemplary embodiment, such as Figure 8 As shown, a result block diagram of an electronic device 100 is also provided, including: an input driver 102, a monitor 104, a design-under-test module 106, a white-box model 108, a black-box model 110, a white-box comparison module 112, a black-box comparison module 114, a combination verification module 116, a bus function model 400, and a common memory module 802.
[0147] For example, when the input request is a cache read request, if no data is stored at the cache read address corresponding to the cache read request, the common memory module 802 can be used to generate initial data and write it to the cache read address in the bus function model and the black box model 110. The white box comparison module 112 can compare the cache read address and cache read data of the design under test module 106 with the white box model 108 to obtain the white box verification result. If the white box verification result is passed, the cache read address and cache read data of the design under test module 106 are sent to the black box comparison module 114 for consistency comparison with the reference read address and reference read data of the black box model 110 to obtain the black box verification result.
[0148] If the white-box alignment passes and the input request is a bypass write request with bypass attributes, the bus functional model 400 can sample the bypass write data and bypass write address corresponding to the bypass write request output by the design-under-test module 106. The bypass write data is then merged with the corresponding data stored in the internal memory according to the bypass write address to generate a bypass write merge result. During black-box verification, the bus functional model 400 sends the bypass write merge result carrying the bypass write address and bypass write merge data to the black-box alignment module 114. The black-box alignment module 114 compares the bypass write address and bypass write merge data with the reference write address and reference merge data of the black-box model 110 to obtain the black-box verification result.
[0149] When the input request is a cache write request, the design-under-test (DUT) module 106 can write the cache write data corresponding to the cache write request into its internal cache memory based on the cache write address corresponding to the cache write request. The white-box comparison module 112 compares the cache write address and cache write data of the DUT module 106 with the cache write address and cache write data in the response reference result of the white-box model 108 to obtain the white-box comparison result. The bus function model 400 samples the cache write address and cache write data output by the DUT module 106, and referring to the above-mentioned bypass write merging result generation method, merges the cache write data with the corresponding data stored in the internal memory according to the cache write address to generate cache write merged data. Simultaneously, the cache write request is forwarded to the black-box model 110 to obtain the merged reference data corresponding to the cache write request generated by the black-box model 110 based on the read-write cache logic, and adds the cache reference address corresponding to the cache write request to the reference address queue. At this time, since the data is stored in the internal cache memory of the DUT module 106, black-box verification cannot be performed until a flush request is obtained.
[0150] When the input request is a flush request, the bus function model 400 samples the cache write data evicted from the cache memory and the corresponding cache write address. Referring to the aforementioned method for generating cache write merge data, the cache write data is merged with the corresponding data stored in internal memory according to the cache write address, generating the cache write merge data at this time. Each cache write address is then added sequentially to the flush address queue. Simultaneously, the flush request is forwarded to the black-box model 110, obtaining the output reference result corresponding to the flush request. The output reference result includes the cache reference addresses retrieved one by one from the reference address queue and the merged reference data corresponding to the cache reference addresses. During black-box verification, the bus function model 400 sends the cache write address and cache write merge data to the black-box comparison module 114. The black-box comparison module 114 compares the cache write address and cache write merge data with the cache reference address and merged reference data of the black-box model 110 to obtain the black-box verification result.
[0151] If the white-box verification results are consistent with the black-box verification results, the read-write cache verification result is "passed". Otherwise, the read-write cache verification result indicates that there is an error in the read-write cache logic of the design module under test.
[0152] The aforementioned electronic devices, by adding a third-party black-box model comparison to the white-box comparison, can additionally verify the cache read function, cache write function, flush function, and bypass write function, ensuring that the design module under test does not have the same errors as the white-box model, thus improving the accuracy of verification.
[0153] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.
[0154] Each module in the aforementioned electronic device 100 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the electronic device 100 in hardware form, or stored in the memory of the electronic device 100 in software form, so that the processor can call and execute the operations corresponding to each module.
[0155] Those skilled in the art will understand that Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device 100 to which the present application is applied. The specific electronic device 100 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0156] In one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described method embodiments.
[0157] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0158] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0160] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A read / write cache verification method, characterized in that, The method includes: Obtain an input request, send the input request to the design under test module, and obtain the request response result corresponding to the input request generated by the design under test module in each clock cycle according to a preset hardware description language; The input request is forwarded to the white-box model, and the response reference result corresponding to the input request is obtained by the white-box model in each clock cycle according to the hardware description language; By comparing the request-response result with the response reference result in each clock cycle, the white-box verification result is obtained. The input request is forwarded to the black box model, and the output reference result corresponding to the input request is obtained by the black box model based on the preset read and write cache logic. Obtain the request processing result output by the design module under test corresponding to the input request, compare the request processing result with the output reference result, and obtain the black-box verification result; By comparing the white-box verification results with the black-box verification results, the read-write cache verification results of the design module under test are obtained.
2. The method according to claim 1, characterized in that, After sequentially comparing the request-response result with the response reference result within each clock cycle to obtain the white-box verification result, the method further includes: If the white-box verification result is passed, and the input request includes a bypass write request with bypass attributes, the bypass write data and bypass write address output by the design under test module corresponding to the bypass write request are sampled using the bus function model. Using the bus function model, the bypass write data is merged with the corresponding data stored in the internal memory according to the bypass write address to generate a bypass write merging result. The bypass write merging result includes bypass merged data and the corresponding bypass write address. The step of forwarding the input request to the black-box model and obtaining the output reference result corresponding to the input request, which is output by the black-box model based on a preset read-write cache logic, includes: The bypass write request is forwarded to the black box model, and the output reference result corresponding to the bypass write request is obtained by the black box model based on the read and write cache logic. The output reference result includes the reference merged data and the reference write address corresponding to the bypass write request. The step of obtaining the request processing result corresponding to the input request output by the design module under test, comparing the request processing result with the output reference result, and obtaining the black-box verification result includes: The bypass write merging result is obtained as the request processing result; The black-box verification result is obtained by comparing the bypass write address in the request processing result with the reference write address in the output reference result, and by comparing the bypass merged data in the request processing result with the reference merged data in the output reference result.
3. The method according to claim 1, characterized in that, The method further includes: When the input request includes a cache write request, the design under test module uses the cache write address corresponding to the cache write request to write the cache write data corresponding to the cache write request into the cache memory. The cache write request is forwarded to the black box model, which uses the black box model to generate merged reference data corresponding to the cache write request based on the read-write cache logic, and adds the cache reference address corresponding to the cache write request to the reference address queue. Upon receiving a flush request, the bus function model is used to sample the cache write data evicted from the cache memory and the corresponding cache write address. The cache write data is then merged with the corresponding data stored in the internal memory according to the cache write address to generate cache write merge data. Each cache write address is then added to the flush address queue in sequence. The flushing request is forwarded to the black box model, and the output reference result corresponding to the flushing request is obtained by the black box model based on the read-write cache logic. The output reference result includes cache reference addresses taken out one by one from the reference address queue and the merged reference data corresponding to the cache reference address. The step of obtaining the request processing result corresponding to the input request output by the design module under test, comparing the request processing result with the output reference result, and obtaining the black-box verification result includes: The request processing result is obtained by sequentially combining each cache write address in the flush address queue with the corresponding cache write merge data; The black-box verification result is obtained by comparing the cache write merged data in the request processing result with the merged reference data in the output reference result, and the cache write address in the request processing result with the cache reference address in the output reference result.
4. The method according to claim 1, characterized in that, The step of forwarding the input request to the black-box model and obtaining the output reference result corresponding to the input request output by the black-box model based on a preset read-write cache logic further includes: When the input request includes a cache read request, the black-box model outputs a reference result corresponding to the cache read request based on a preset read-write cache logic. The reference result includes reference read data and reference read address corresponding to the cache read request. The step of obtaining the request processing result corresponding to the input request output by the design module under test, comparing the request processing result with the output reference result, and obtaining the black-box verification result includes: When the input request includes a cache read request, the cache read data and cache read address obtained by the design module under test corresponding to the cache read request are combined to obtain the request processing result; The black-box verification result is obtained by comparing the reference read address in the output reference result with the cache read address in the request processing result, and by comparing the reference read data in the output reference result with the cache read data in the request processing result.
5. The method according to claim 4, characterized in that, The method further includes: Forward the cache read request to the public memory module; Use the public memory module to query whether data is stored at the cache read address corresponding to the cache read request; If no data is stored at the cache read address corresponding to the cache read request, the initial data stored at the cache read address is generated using the common memory module, and the initial data is written to the cache read address in the bus function model and the black box model.
6. The method according to claim 1, characterized in that, The step of sequentially comparing the request-response result with the response reference result within each clock cycle to obtain the white-box verification result includes: If the request response result and the response reference result are consistent in each clock cycle, the white-box verification result is considered passed.
7. The method according to claim 1, characterized in that, The comparison of the white-box verification results with the black-box verification results yields the read / write cache verification results of the design module under test, including: If the white-box verification result is inconsistent with the black-box verification result, the read-write cache verification result indicates that the read-write cache logic of the design module under test has an error.
8. An electronic device, characterized in that, The electronic device includes an input driver, a design-under-test module, a monitor, a white-box model, a black-box model, a white-box comparison module, a black-box comparison module, and a combined verification module; The input driver is used to generate an input request and send the input request to the design under test module; The design-under-test module is used to process the input request and generate a request response result corresponding to the input request in each clock cycle according to a preset hardware description language. The monitor is used to monitor the input requests of the design under test module and forward the input requests to the white-box model and the black-box model; The white-box model is used to output a response reference result corresponding to the input request in each clock cycle according to the hardware description language. The white-box comparison module is used to obtain the request-response result of the design module under test in each clock cycle and the response reference result of the white-box model in each clock cycle, and compare the request-response result and the response reference result in each clock cycle to obtain the white-box verification result. The black-box model is used to output a reference result corresponding to the input request based on a preset read / write cache logic. The black-box comparison module is used to obtain the request processing result corresponding to the input request output by the design module under test and the output reference result output by the black-box model, and compare the request processing result with the output reference result to obtain the black-box verification result. The combined verification module is used to compare the white-box verification results with the black-box verification results to obtain the read-write cache verification results of the design module under test.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.