Storage systems that support edge computing

Abstract

This invention relates to a memory system supporting edge computing. A semiconductor substrate with multiple rows of memory transistors is provided, each row divided into multiple transistor pairs, with each pair of transistors in each pair sharing a common source. The common sources of all transistor pairs in the same row are set at the same potential as a common-source line, and all drains of all transistor pairs in the same row are set at the same potential as a common-source line. The array of multiple rows of memory transistors is mapped as a carrier of a weight matrix for a neural network. The weights of the two transistors in each pair are adjusted by their respective threshold voltages. Input data from the neural network to each row of memory transistors is input as pulse signals to the respective control gates of the column of memory transistors, and the magnitude of the input data is adjusted by changing the pulse width of the pulse signals.

Description

Technical Field

[0001] This invention primarily relates to the technical field of data storage, and more specifically, to a storage system in the field of data storage that supports edge computing. Background Technology

[0002] Edge computing, as a branch of artificial intelligence, typically has unique applications in terms of high reliability, strong computing power, ease of deployment, and miniaturization. Mass-produced flash memory can serve as a medium for edge computing, allowing flash memory cells to function as discrete devices or integrating them and the processor onto the same chip based on the same or different process nodes. This flexibility perfectly matches the needs of edge computing. Weight values ​​can be pre-edited in the flash memory to configure neural networks for edge computing. The challenges of providing easily cut or expanded neural network weight matrices under compatible semiconductor process conditions, and constructing flash memory cells with high cell density for neural networks, are key aspects of edge computing storage systems. Summary of the Invention

[0003] This application discloses a storage system supporting edge computing (also referred to as a storage device or storage apparatus supporting edge computing), comprising: a semiconductor substrate with multiple rows of storage transistors arranged thereon, each row of storage transistors being divided into multiple transistor pairs, and each pair of storage transistors in each transistor pair having a common source, the common source of each pair of transistors in the same row of storage transistors being set at the same potential as a common source line, and all drains of all pairs of transistors in the same row of storage transistors being set at the same potential as a common source line, and an array having multiple rows of storage transistors being mapped to a weight matrix of a neural network; multiple trenches formed on the semiconductor substrate, each trench being filled with an outer insulating layer, a control gate layer, an interlayer insulating layer, a floating gate layer, a gate insulating layer, and a semiconductor material in the direction from the sidewall to the center; a doped region of a second conductivity type at the top of the semiconductor material with a first conductivity type at the center of any trench being regarded as the drain of the first transistor in the transistor pair, a doped region of a second conductivity type at the bottom of the semiconductor material being regarded as the drain of the second transistor in the transistor pair, and a doped region of a second conductivity type in the region of the semiconductor material between the top and the bottom being regarded as the common source of the two transistors in the transistor pair; A gate isolation layer separating the control gate layer of each trench and a floating gate isolation layer separating the floating gate layer of each trench are used. The upper part of the control gate layer is regarded as the control gate of the first one, and the lower part of the control gate layer is regarded as the control gate of the second one. The upper part of the floating gate layer is regarded as the floating gate of the first one, and the lower part of the floating gate layer is regarded as the floating gate of the second one. The weight of the two in each transistor pair is adjusted by their respective threshold voltages.

[0004] The aforementioned storage system supporting edge computing is characterized in that: the input data of the neural network to each column of storage transistors is input to the control gate of each column of storage transistors in the form of pulse signals, and the size of the input data is adjusted by changing the pulse width of the pulse signals, so as to collect the output data of the neural network at the column of storage transistors by collecting the source line charge of each column of storage transistors.

[0005] In the aforementioned memory system, the first and second conductivity types are P and N conductivity types, respectively, or the first and second conductivity types are N and P conductivity types, respectively. In the aforementioned memory system, both the gate isolation layer and the floating gate isolation layer in each trench overlap with the doped region within the trench, which is considered as a common source, in a direction perpendicular to the trench.

[0006] The aforementioned memory system supporting edge computing is characterized in that it includes multiple parallel top interconnect strips disposed on the front side of a semiconductor substrate. The top interconnect strips are electrically insulated from the semiconductor substrate through an upper insulating layer covering the upper surface of the semiconductor substrate. A series of trenches corresponding to the same column of memory transistors overlap with a corresponding top interconnect strip, and the doped region at the top of each series of trenches corresponding to the same column of memory transistors and a top interconnect strip used as a bit line that overlaps with the series of trenches are electrically connected.

[0007] The aforementioned memory system supporting edge computing is characterized by: including multiple parallel bottom interconnect strips disposed on the back side of a semiconductor substrate, the bottom interconnect strips being electrically insulated from the semiconductor substrate by a lower insulating layer covering the lower surface of the semiconductor substrate, a series of trenches corresponding to the same column of memory transistors overlapping with a corresponding bottom interconnect strip, and the doped region at the bottom of each series of trenches corresponding to the same column of memory transistors being electrically contacted with a bottom interconnect strip used as a bit line that overlaps with the series of trenches. It also includes: a top insulating layer covering each top interconnect strip and multiple top metal strips, with each top metal strip corresponding to a top interconnect strip. Each top metal strip is isolated from and overlaps with a top interconnect strip through the top insulating layer below it. The doped regions inside each of the series of trenches corresponding to the same column of storage transistors, which are regarded as common sources, are electrically connected to a top metal strip used as a source line that overlaps with the series of trenches. A via is formed in the semiconductor material of each trench, extending downward from the top of the trench to the doped region regarded as the common source. The via penetrates the top insulating layer and the top interconnect strip, and its sidewalls are covered with an insulating barrier layer. The conductor filled in the via electrically contacts the top metal strip above the trench and electrically connects the common source in the trench to the top metal strip.

[0008] The aforementioned storage system supporting edge computing is characterized by: including a bottom insulating layer covering each bottom interconnect strip and multiple side-by-side bottom metal strips, the multiple bottom metal strips and the multiple bottom interconnect strips corresponding one-to-one, each bottom metal strip being isolated from and overlapping with a bottom interconnect strip through the bottom insulating layer above it, and the doped regions inside each of the series of trenches corresponding to the same column of storage transistors, which are regarded as common sources, are electrically connected to a bottom metal strip used as a source line that overlaps with the series of trenches; Each trench has a via formed in its semiconductor material, extending upwards from the bottom of the trench to a doped region considered as a common source. The via penetrates the bottom insulating layer and the bottom interconnect strip, and its sidewalls are covered with an insulating barrier layer. The conductors filling the vias electrically contact the bottom metal strip below the trench, electrically connecting the common source in the trench to the bottom metal strip.

[0009] The aforementioned memory system supporting edge computing: In the array, the trenches belonging to multiple transistor pairs in the same column are arranged along the same vertical line of the semiconductor substrate, and the trenches belonging to multiple transistor pairs in different columns but with the same column number are arranged along the same row line of the semiconductor substrate.

[0010] The aforementioned memory system supporting edge computing: wherein in the trenches corresponding to pairs of transistors on the same row, the control gates of the first transistors within each pair are electrically connected to each other, and the control gates of the second transistors within each pair are electrically connected; the threshold voltages of the first transistors on the same row are modulated differently, and the threshold voltages of the second transistors on the same row are modulated differently; or In a row of trenches corresponding to a pair of transistors on the same row line, the control gates of the first transistors within each pair are configured not to be connected to each other, and the control gates of the second transistors within each pair are configured not to be connected. The threshold voltages of the first transistors on the same row line are modulated to be the same or different, and the threshold voltages of the second transistors on the same row line are modulated to be the same or different.

[0011] In the aforementioned memory system: in a row of trenches corresponding to transistor pairs on the same row line: the control gates of the first transistors within each pair are electrically connected to each other, and the control gates of the second transistors within each pair are electrically connected to each other; the threshold voltages of the first transistors on the same row line are modulated differently, and the threshold voltages of the second transistors on the same row line are modulated differently; in a row of trenches corresponding to transistor pairs on the same row line: the control gates of the first transistors within each pair are synchronously controlled, and the control gates of the second transistors within each pair are synchronously controlled, but the control gates of the first transistors within each pair and the control gates of the second transistors within each pair are asynchronously controlled.

[0012] In the aforementioned memory system: in a row of trenches corresponding to transistor pairs on the same row line: the control gates of the first transistors within each pair are configured not to be connected to each other, and the control gates of the second transistors within each pair are configured not to be connected to each other; the threshold voltages of the first transistors on the same row line are modulated to be the same or different, and the threshold voltages of the second transistors on the same row line are modulated to be the same or different; in a row of trenches corresponding to transistor pairs on the same row line: the control gates of the first transistors within each pair are configured to be asynchronously controlled, and the control gates of the second transistors within each pair are configured to be asynchronously controlled, and simultaneously the control gates of the first transistors within each pair and the control gates of the second transistors within each pair are configured to be asynchronously controlled.

[0013] In the field of edge computing, unlike the application scenarios of graphics processing units (GPUs), edge computing, due to factors such as device miniaturization, heat dissipation, cost, and the limited power consumption of portable devices, makes processors specifically designed to accelerate neural networks, such as NPUs or KPUs, a better choice. In particular, some edge computing scenarios focus more on inference than training, so the flash memory-based storage systems, devices, or storage devices suitable for edge computing, as discussed in this paper, are the preferred option. When flash memory cells are discrete devices, they can work with external processors to coordinate the execution of neural network operations. The advantage of flash memory cells as discrete devices is that they can flexibly expand the matrix size. For example, the flash memory storage devices in this paper can expand and reduce the number of devices in the planar direction (two-dimensional direction) of the substrate (such as a circuit board) to match a reasonable matrix size, or multiple layers of flash memory can be stacked together (three-dimensional direction). Furthermore, there are various options for integrating flash memory cells and processors into the same chip under existing process conditions, such as fabricating flash memory and processors on the same semiconductor substrate, or fabricating isolated flash memory and isolated processors into the same package, which also allows for two-dimensional or three-dimensional expansion. These models provide easily cut or expandable neural network weight matrices for edge computing, thereby enabling the construction of flash memory computing units with high cell density for neural networks. High cell density means greater computing power per unit substrate area. Attached Figure Description

[0014] To make the objectives, features, and advantages described above more easily understood, the following detailed description of specific embodiments is provided in conjunction with the accompanying drawings. After reading the following description and referring to the accompanying drawings, the features and advantages of this application will become apparent.

[0015] Figure 1 It is based on flash memory and selects local transistor circuit topology to display the neural network weight carrier.

[0016] Figure 2 It shows a cross-sectional view of a transistor in a trench on a semiconductor substrate and a top view of the top interconnect strips side by side.

[0017] Figure 3 It is a series of trenches corresponding to the same column of storage transistors and the transistor circuit topology.

[0018] Figure 4 The input data is delivered to the control gate of each storage transistor in the form of pulse signals.

[0019] Figure 5 It shows a cross-sectional view of a transistor in a trench on a semiconductor substrate and a top view of the top metal strip side by side. Detailed Implementation

[0020] The technical solutions disclosed in this application will be clearly and completely described below with reference to specific embodiments. However, the described embodiments are only the embodiments used for description and illustration in this application and not all of the embodiments.

[0021] See Figure 1 This application will now be explained based on the illustrated NOR flash memory array. The principle involves forming a floating gate, capable of storing charges such as electrons, between the source (S) and drain (D) of the storage transistor and on the semiconductor in the current conduction path. The floating gate is encased within a silicon oxide insulator. Above the floating gate is a select / control gate that controls the conduction current between the source and drain. The charges, such as electrons, in the floating gate do not disappear when power is lost, making flash memory a non-volatile memory. A write operation involves applying a positive voltage to the control gate, causing charges, such as electrons, to pass through the insulating layer into the floating gate. An erase operation is the opposite; applying a positive voltage to the substrate causes electrons to be extracted from the floating gate, thus erasing the data. Data operations in flash memory are prior art and will not be described separately here.

[0022] See Figure 1 In flash memory, the gates of transistors in each row are connected to a common word line, the drains of transistors in each column are connected to a common bit line, and the sources of transistors in each column are connected to a common source line. Alternatively, each transistor in the same row may have its own independent word line instead of being connected to a common word line. In the diagram, word lines not truncated by cross symbols indicate that transistors in the same row are connected to a common word line, such as G1 / GN. Word lines truncated by cross symbols indicate that the gates of transistors in the same row operate independently instead of being connected to a common word line, such as G2 / G(N-1). This example uses several word lines such as G1-GN (N>1), source lines S1-SM, and bit lines B1-BM (M>1) as examples.

[0023] See Figure 1 Here's an example of a word line configuration: the gates of the transistors in the first row are connected to word line G1, the gates of the transistors in the second row are connected to word line G2, and the gates of the transistors in the Nth row are connected to word line GN. For simplicity, more omitted rows are not shown repeatedly in the diagram. The total N rows of transistors are considered as a matrix of N×M elements. The first column of transistors includes T11-T1N, the second column includes T21-T2N, and the Mth column includes TM1-TMN. Alternatively, the gates of transistors T11-TM1 in the first row can be individually controlled and operated independently without being connected to each other; or the gates of transistors T12-TM2 in the second row can be individually controlled and operated independently without being connected to each other; and so on, the gates of transistors T1N-TMN in the Nth row can be individually controlled and operated independently without being connected to each other.

[0024] See Figure 1 The optional bit lines are as follows: the drains of the transistors in the first column are connected to bit line B1, the drains of the transistors in the second column are connected to bit line B2, and the drains of the transistors in the Mth column are connected to bit line BM. For simplicity, more columns are omitted and not shown repeatedly in the figure. The total of M columns of transistors are considered as a matrix of M×N elements.

[0025] See Figure 1 Optional source line examples: the sources of the transistors in the first column are connected to source line S1, the sources of the transistors in the second column are connected to source line S2, and the sources of the transistors in the Mth column are connected to source line SM. For simplicity, more omitted columns are not shown repeatedly in the figure. The total of M columns of transistors are considered as a matrix of M×N elements.

[0026] See Figure 1 The storage transistor array serves as the carrier of the weight matrix of the neural network. The input data of the neural network is sent to the respective gates or bit lines G1-GN of the storage transistors, and the output data of the neural network is simultaneously extracted from the series of source lines S1-SM of the storage transistor array. As shown in the figure, the weight of any transistor in the storage transistor array is determined by its threshold voltage V. TH Adjustments are made accordingly. The weight matrix of the neural network is configured based on this, and the figure shows M×N weight values. If you attempt to configure a series of bias values ​​for the neural network, you will need to use an additional row of storage transistors, and add one storage transistor to each column. Each additional storage transistor in each column serves as a bias value provider, for a total of M bias transistors.

[0027] See Figure 1 In the first column, gates G1-GN serve as inputs and source line S1 serves as output. Figure 1 Flash memory is considered the physical carrier for implementing the weights of neural networks. To illustrate the specific implementation process, a matrix Max with M×N elements is designed to associate and map with the flash memory. The first column stores the gates G1-GN of each transistor as input examples, and the other columns can be similarly stored. For example, the gates of each transistor in the second column are used as inputs, and the source line S2 is used as the output of the second column. The Mth column stores the gates of each transistor as inputs, and the source line SM is used as the output of the Mth column.

[0028] See Figure 2The inputs to gates G1-GN are represented by the vector Max_in = [I1*t1, I2*t2, ..., IN*tn]. For ease of representation, the input values ​​of gate G1 are mapped to I1*t1 = X1, the input values ​​of gate G2 are mapped to I2*t2 = X2, and similarly, the input values ​​of gate G3 are mapped to I3*t3 = X3, and the input values ​​of gate GN are mapped to IN*tn = X1. N Here, the output current or sink current of each source line is IS1 to ISM, respectively. For example, the output current of source line SM is ISM. The current of T1N is injected into source line S1 in pulse form for a time of tn, that is, the current IN is injected during the time period tn. The current of T11 is injected into source line S1 in pulse form for a time of t1, that is, the current I1 is injected during the time period t1. The current of T12 is injected into source line S1 in pulse form for a time of t2, that is, the current I2 is injected during the time period t2. The current of T13 is similar, injected into source line S1 in pulse form for a time of t3, that is, the current I3 is injected during the time period t3. And so on, and a pulse signal is applied to the control gate or word line, with the effective width of the pulse being time t.

[0029] See Figure 1 The output of source line S1-SM is represented by the vector Max_out = [QIS1, QIS2, ..., QISM]. For ease of representation, the output of source line S1 needs to be mapped to Y1, the output of source line S2 to Y2, the output of source line S3 to Y3, ..., and the output of source line SM needs to be mapped to Y... M QIS1 is the charge or quantity gained by source line S1 under the condition of current IS1, which charges the capacitor at source line S1. QIS2 is the charge or quantity gained by source line S2 under the condition of current IS2, which charges the capacitor at source line S2. QISM is the charge or quantity gained by source line SM under the condition of current ISM, for example, ISM charges the capacitor at source line SM. The currents of the first transistor to the Nth transistor in the first column are I1 to IN respectively, and IS1 is the sum of I1 to IN.

[0030] See Figure 1 This flash memory is intended to demonstrate a rough computational function of implementing a neural network, expressed by the following formula. Essentially, this process is a detailed example of simulating a flash memory as a computational unit or a computational unit-like unit. Using Y1, Y2, and Y... M Examples of these will be used to illustrate the spirit of the invention and the calculation process described in this paper.

[0031] See Figure 1 This example uses vector-matrix multiplication to demonstrate the general operation process involving arrays. The principle of vector-matrix representation of flash memory performing local data processing of neural networks is roughly as follows.

[0032] See Figure 1 Predetermine X1 to X N For the input layer of the neural network (the input is a pulse signal delivered from the control gate of each column of storage transistors), Y1 to Y... N This represents the relative output layer of the neural network (the output data at that column of storage transistors is extracted by collecting the source line charge of each column of storage transistors). Thus, the flash memory completes a complete vector operation from the input layer to the output layer, which is significantly different from the operation of a traditional von Neumann computer. This is because the operation only requires measuring the charge of each source line S1-SM; individual multiplications and additions do not need to be performed individually. The final result can be fully represented by the charge of the source lines S1-SM at once, making it a form of analog computation. Traditional von Neumann computers must execute all multiplications and additions individually, making a single, simultaneous operation impossible.

[0033] See Figure 1 For matrix Max, the gate of the first transistor in the first column is connected to word line G1, the gate of the second transistor in the first column is connected to word line G2, and the gate of the Nth transistor in the first column is connected to word line GN. The transistors in the first column are mapped to weights T11-T1N in the weight matrix, denoted as W. 11 W 12 W 13 ...W 1N In the weighting matrix, the second column of transistors, T21-T2N, are each mapped to a weight denoted as W. 21 W 22 W 23 ...W 2N Let the weights mapped to the transistors in the Mth column of the weight matrix be W, specifically TM1-TMN. M1 W M2 W M3 ...W MN Therefore, each storage transistor is configured with a corresponding weight value that contributes to the matrix Max participating in the neural network. Thus, how to map the weights to the transistors is a key problem that needs to be solved. This will be discussed in more detail later in this article.

[0034] See Figure 1 This explains the relationship between the current, threshold voltage, and applied voltage of a storage transistor. The transistor threshold voltage is V. THThe process parameter K=μCW / L, which is related to the manufacturing process, belongs to the existing technology of transistors. For example, W / L in the parameter is the aspect ratio of the transistor. For memory transistors with a given fabrication process and size, the process parameter K is almost a constant. The voltage V between the gate and source... GS and the voltage V between the drain and source of the transistor DS It can satisfy K(V) GS -V TH V DS =I. When a transistor operates in the linear or bipolar junction region, I is the current flowing between the drain and source of the transistor. In this paper, the current I of a single transistor is multiplied, and the output currents I of a single column of transistors are accumulated (e.g., I1 to IN are added in the first column), which is equivalent to matrix multiplication and accumulation calculation.

[0035] See Figure 1 The first column contains bit line B1 and source line S1: the current I1 of the first transistor can be calculated and denoted as K(V). GS11 -V TH11 V DS11 =I1. Following the same current formula, the current I2 of the second transistor can be calculated and written as K(V). GS12 -V TH12 V DS12 =I2, Nth transistor current K (V) GS1N -V TH1N V DS1N =IN. The voltage between the gate and source of the first transistor is V. GS11 The voltage between the drain and source is V. DS11 Threshold voltage is V TH11 The voltage between the gate and source of the second transistor is V. GS12 The voltage between the drain and source is V. DS12 Threshold voltage is V TH12 The voltage between the gate and source of the Nth transistor is V. GS1N and the drain-source voltage is V DS1N Threshold voltage is V TH1N The current characteristics of the storage transistors in other columns are similar to those of T11, T12, and T1N, and will not be repeated here. The weight of each storage transistor can be adjusted by its respective threshold voltage. If transistors in the same column share a common bit line and a common source line, the voltage between their drain and source can be the same, such as allowing V... DS11 and V DS12 and V DS1N They can be the same.

[0036] See Figure 1At bit line B1 and source line S1 in the first column: the source currents of the first to Nth transistors all flow to the common source line S1 of this column of transistors. The charge on source line S1 is QIS1. The charge can be integrated with the currents I1 to IN using a known capacitor (note the non-parasitic capacitance). For example, a capacitor of known capacitance can be placed on the source line to charge the source line S1 with the currents I1 to IN, and the charge is QIS1. For example, in the example shown in the figure, a capacitor C can be placed on the source line S1 (the same applies to S2 to SM). The figure is only for illustration, but in practice, capacitors are often placed on the source lines S1 to SM and combined with operational amplifiers. For example, a known capacitor is connected to the positive input terminal of the operational amplifier, and the negative input terminal of the operational amplifier can be connected to the reference ground terminal. Then, a signal such as the output voltage value is provided at the output terminal of the operational amplifier, that is, the charge is converted into a sampleable voltage value. Sampling can be performed using existing techniques.

[0037] See Figure 1 At bit line B1 and source line S1 in the first column: This indicates the location of the first transistor if W is defined. 11 With K(V) GS11 -V TH11 V DS11 To ensure a proportional or equal relationship, the charge flowing through the first transistor and onto the common source line S1 of the transistors in that column can be expressed as Q11 = I1 * t1. At the location of the second transistor, if W is defined... 12 With K(V) GS12 -V TH12 V DS12 To ensure a proportional or equal relationship, the charge flowing through the second transistor and onto the common source line S1 of the same column of transistors can be expressed as Q12 = I2 * t2. And at the location of the third transistor, if W is defined... 13 With K(V) GS13 -V TH13 V DS13 To ensure a proportional or equal relationship, the charge flowing through the third transistor and onto the common source line S1 of that column of transistors can be expressed as Q13 = I3 * t3. And if W is defined at the location of the Nth transistor... 1N With K(V) GS1N -V TH1N V DS1N To ensure a proportional or equal relationship, the amount of charge flowing through the Nth transistor and towards the common source line S1 of that column of transistors is expressed as Q1N = IN * tn. QIS1 is the sum of Q11 to Q1N.

[0038] See Figure 1At bit line B1 and source line S1 in the first column: the charge QIS1 on source line S1 can be expressed as charge addition after the aforementioned transformation (Y1=QIS1 can also be defined). The prerequisite is the source current convergence characteristics of the transistors in the first column, which is equivalent to the multiplication and accumulation calculation algorithm of vector matrix multiplication.

[0039] See Figure 1 At bit line B2 and source line S2 in the second column: the charge QIS2 on source line S2 can be expressed as charge addition after a similar transformation (Y2=QIS2 can also be defined). The current merging on the charge QIS2 on source line S2, i.e., charge addition, is basically similar to that on source line S1, so it will not be repeated. Note that the gate turn-on times t1 to tn of the second column of storage transistors can be the same as or different from those of the first column of storage transistors. The input data from the neural network to the second column of storage transistors T21-T2N is input to the control gate of each storage transistor in the column in the form of pulse signals, and the magnitude of the input data is adjusted by changing the pulse width of the pulse signals. The weights W of the second column of storage transistors are determined by their respective weights. 21 -W 2N The process of obtaining QIS2 and the gate turn-on time can be referred to QIS1. The main difference between them is that they belong to different columns (first column / second column) and allow different weights to be set for different columns.

[0040] See Figure 1 The bit line BM2 and source line SM of the Mth column transistor: The charge QISM of the source line SM can be expressed as follows after formula transformation (Y can also be defined) M =QISM). The current merging, or charge addition, pattern on the source line SM is basically similar to that of the source line S1, so it will not be repeated. The gate turn-on times t1 to tn of the Mth column storage transistors can be the same as or different from those of the first column transistors. The input data from the neural network to the Mth column storage transistors TM1-TMN is input to the control gate of each storage transistor in that column in the form of pulse signals, and the magnitude of the input data is adjusted by changing the pulse width of the pulse signals. The weights W of the Mth column storage transistors are determined by their respective weights. M1 -W MN The process of obtaining QISM by specifying the gate turn-on time can be referenced in QIS1. The main difference between them is that they belong to different columns (first column / Mth column) and allow different weights to be set for different columns.

[0041] See Figure 1This design allows flash memory (M×N array) cells to be discrete devices, and also allows flash memory cells and the CPU to be integrated onto the same chip based on the same or different process nodes. Flash memory with accelerated neural networks (such as NPU or KPU) can be integrated with processors of various architectures (such as RISC-V or ARM) into the same chip, such as into the same chip or package, which is very suitable for edge computing chips. It can also be easily installed in small devices. This is ideal for edge applications such as factory visual quality inspection, drone inspection or intelligent robots, voice recognition and interaction, image recognition, and large-scale model deployment. The flash memory in this design, compatible with existing semiconductor processes, is an excellent solution for edge computing due to its high reliability, strong computing power, ease of deployment, multi-form array expansion, and broad processor architecture adaptability.

[0042] See Figure 2 Flash memory can be implemented based on storage devices that support edge computing, as illustrated in the diagram. These edge computing-enabled storage systems or devices (components) or storage equipment (devices) include semiconductor substrates. The lower diagram in this figure shows a longitudinal cross-section of the semiconductor substrate, while the upper diagram shows a transverse cross-section.

[0043] See Figure 2Multiple trenches 11, 12...1L are formed on a semiconductor substrate. L is a positive integer. The trenches are filled with an outer insulating layer, a control gate layer, an interlayer insulating layer, a floating gate layer, a gate insulating layer, and semiconductor material in the direction from the sidewalls to the center. Trench 11 is filled with an outer insulating layer 122, a control gate layer, an interlayer insulating layer 121, a floating gate layer, a gate insulating layer 120, and semiconductor material in the direction from the surrounding sidewalls to the center (i.e., from the outside to the inside). The outer insulating layer 122, the interlayer insulating layer 121, and the gate insulating layer 120 can be single insulating layers or insulating composite layers, commonly silicon oxide layers or silicon nitride layers, or combinations thereof. The control gate layer and the floating gate layer are commonly made of polysilicon, and the control gate layer is divided into an upper part a and a lower part c by a gate isolation layer 131. The floating gate layer is divided into an upper part b and a lower part d by a floating gate isolation layer 132. Polysilicon is filled into the trench, then etched back to retain the lower part c as shown in the figure, and then a gate isolation layer 131, such as oxide, is formed above the lower part c. Then, polysilicon is filled again to form the upper part a. The same applies to b and d. The context indicates that each column of storage transistors is divided into multiple transistor couples, and each trench can be configured with the first transistor (the first) and the second transistor (the second). A doped region 111 of the semiconductor material with a first conductivity type at the center of trench 11, doped with a second conductivity type, is considered the drain of the first transistor in the pair; a doped region 115 of the semiconductor material with a second conductivity type at the bottom is considered the drain of the second transistor in the pair; and a doped region 113 of the semiconductor material located between the top and bottom of the top and bottom is considered the common source of both transistors in the pair. For transistor pairs T11 and T12: the doped region 111 at the top of the semiconductor material at the center of trench 11 is considered the drain of the first transistor T11; the doped region 115 at the bottom of the semiconductor material is considered the drain of the second transistor T12; and the doped region 113, located in the region of the semiconductor material between the top and bottom, which is doped with a second conductivity type, is considered the common source of both T11 and T12. The conductivity type of the semiconductor material filling the center of trench 11 can be the same as or opposite to that of the semiconductor substrate. Trench 12 is similar to trench 11.

[0044] See Figure 2For trench 11, there is a gate isolation layer 131 separating the control gate layer of trench 11 and a floating gate isolation layer 132 separating the floating gate layer of trench 11. The upper part a of the control gate layer is regarded as the control gate of the first T11, and the lower part c of the control gate layer is regarded as the control gate of the second T12. As shown, the control gate layer is separated or divided into upper part a and lower part c by the gate isolation layer 131. Correspondingly, the upper part b of the floating gate layer is regarded as the floating gate of the first T11, and the lower part d of the floating gate layer is regarded as the floating gate of the second T12. As shown, the floating gate layer is separated or divided into upper part b and lower part d by the floating gate isolation layer 132. The weight of the first transistor in the first column of storage transistors relative to both T11 and T12 is determined by their respective threshold voltage V. TH11 V TH12 To make adjustments.

[0045] See Figure 2 In trench 11, T11 is a control gate, i.e., a, which can operate T11 to turn it off or off, while the latter, i.e., b, stores charge in T11.

[0046] See Figure 2 In trench 11, T12 is a control gate (c) and a floating gate (d). The former, T12, acts as a control gate and can control whether T12 is turned off or not, while the latter, T12, stores charge.

[0047] See Figure 2The trench 12 is filled with an outer insulating layer 122, a control gate layer, an interlayer insulating layer 121, a floating gate layer, a gate insulating layer 120, and a semiconductor material, respectively, in the direction from the sidewall to the center (from the outside to the inside). Similarly, the outer insulating layer 122, the interlayer insulating layer 121, and the gate insulating layer 120 can be a single insulating layer or an insulating composite layer, and can be silicon oxide layers, silicon nitride layers, or combinations thereof. The control gate layer and the floating gate layer are conventionally made of polysilicon, and the control gate layer is divided into an upper part a and a lower part c by a gate isolation layer 131. The floating gate layer is divided into an upper part b and a lower part d by a floating gate isolation layer 132. Polysilicon is filled into the trench, then etched back, retaining the lower part c as shown in the figure, and then the gate isolation layer 131, such as an oxide layer, is formed above the lower part c. Then, polysilicon is filled again to form the upper part a. The same process is repeated for b and d. The context indicates that each column of storage transistors is divided into multiple transistor couples, and each trench can be configured with the first transistor (the first) and the second transistor (the second). The first transistor in the transistor couple can be called the upper transistor, and the second transistor can be called the lower transistor. A doped region 111 of the semiconductor material at the center of trench 12, having a first conductivity type, is doped with a second conductivity type and considered as the drain of the first transistor in the pair; a doped region 115 of the semiconductor material at the bottom of the pair is doped with a second conductivity type and considered as the drain of the second transistor in the pair; and a doped region 113 of the semiconductor material located between the top and bottom of ... The conductivity type of the semiconductor material filling the center of trench 12 can be the same as or opposite to that of the semiconductor substrate. Trench 13-1L is similar to trench 12.

[0048] See Figure 2 For trench 12, there is a gate isolation layer 131 separating the control gate layer of trench 12 and a floating gate isolation layer 132 separating the floating gate layer of trench 12. The upper part a of the control gate layer is regarded as the control gate of the first T13, and the lower part c of the control gate layer is regarded as the control gate of the second T14. As shown, the control gate layer is separated or divided into upper part a and lower part c by the gate isolation layer 131. Correspondingly, the upper part b of the floating gate layer is regarded as the floating gate of the first T13, and the lower part d of the floating gate layer is regarded as the floating gate of the second T14. As shown, the floating gate layer is separated or divided into upper part b and lower part d by the floating gate isolation layer 132. The weight of the second transistor in the first column of storage transistors relative to both T13 and T14 is determined by their respective threshold voltage V.TH13 V TH14 To make adjustments.

[0049] See Figure 2 In trench 12, T13 is a control gate, i.e., a, which can control whether T13 is turned off or not, while the latter, i.e., b, stores charge in T13.

[0050] See Figure 2 In trench 11, T14 is a control gate (c) and a floating gate (d). The former, T14, acts as a control gate and can control whether T14 is turned off or not, while the latter, T14, stores charge.

[0051] See Figure 2 In this example, trench 11 houses the first transistor pair (T11 and T12) of the first column of transistors (including B1 and S1). Similarly, trench 12 houses the second transistor pair (T13 and T14) of the first column of transistors (including B1 and S1). Trench 13 houses the third transistor pair (T15 and T16) of the first column of transistors (including B1 and S1). The other transistor pairs in the first column (including B1 and S1) follow the same pattern. The top view above shows multiple columns of memory transistors. The labels 11, 12…1L in both the top and bottom views refer to a series of trenches corresponding to the first column of memory transistors. The bottom view is a vertical cross-section or sectional view of the first column of the multiple columns of memory transistors.

[0052] See Figure 2 A storage system, component, or electronic device supporting edge computing includes a semiconductor substrate with multiple rows of storage transistors arranged in it. Each row of storage transistors is divided into multiple transistor pairs, and each pair of storage transistors in each pair has a common source. The common source of each pair of transistors in the same row is set at the same potential as a common source line, and all drains of all pairs of transistors in the same row are set at the same potential as a common source line. The array with multiple rows of storage transistors is mapped as a carrier of the weight matrix of a neural network. Figure 1 and Figure 2 .

[0053] See Figure 2The first column of storage transistors, such as T11-T1N, is divided into multiple transistor pairs: the first transistor pair, such as T11 and T12, has a common source, such as the doped region 113 of trench 11, located at trench 11; the second transistor pair, such as T13 and T14, has a common source, such as the doped region 113 of trench 12, located at trench 12; the third transistor pair, such as T15 and T16, has a common source, such as the doped region 113 of trench 13, located at trench 13. This pattern continues, with each column of storage transistors divided into multiple transistor pairs, and each pair of storage transistors in a pair sharing a common source. The second, third, and Mth columns of storage transistors are similarly divided.

[0054] See Figure 2 The common sources of transistor pairs such as T11 and T12, T13 and T14, T15 and T16, etc., are set to the same potential as the common sources within trenches 11-1L (i.e., the doped regions 113 of each trench). Equipotentiality means that their voltage levels are the same, that is, the potentials of the doped regions 113 in each trench 11-1L are equal. The common sources of all transistor pairs in the first column of storage transistors, such as T11-T1N, are set to the same potential as the common source line S1. The common sources of all transistor pairs in the second column of storage transistors, such as T21-T2N, are set to the same potential as the common source line S2. The common sources of all transistor pairs in the third column of storage transistors, such as T31-T3N, are set to the same potential as the common source line S3. The common sources of all transistor pairs in the Mth column of storage transistors, such as TM1-TMN, are set to the same potential as the common source line SM. In other words, the common sources of all transistor pairs in the same column of storage transistors are set to the same potential as the common source line.

[0055] See Figure 2 In the first column of transistor pairs, such as T11 and T12, T13 and T14, T15 and T16, all drains are co-located on line B1 and at the same potential. In the first transistor pair T11-T12, the drain of T11 is electrically connected to the top interconnect 101. For the drain of T11, the top doped region 111 of the semiconductor material within trench 11, i.e., the drain, preferably maintains an ohmic electrical contact with the top interconnect 101. In the second transistor pair T13-T14, the drain of T13 is electrically connected to the top interconnect 101. For the drain of T13, the top doped region 111 of the semiconductor material within trench 12, i.e., the drain, also maintains an ohmic electrical contact with the top interconnect 101. The drain of the third transistor (T15) in T15-T16 is electrically connected to the top interconnect 101. For the drain of T15, the top doped region 111 of the semiconductor material within trench 13 (i.e., the drain) also maintains an ohmic electrical contact with the top interconnect 101. The drains of the other transistors in trenches 11-1L corresponding to the first column of transistors, such as the doped regions 111 in each trench, are all electrically connected to the top interconnect 101, which is considered bit line B1.

[0056] See Figure 2 In the first column of transistor pairs, such as T11 and T12, T13 and T14, T15 and T16, all drains are co-located on line B1 and at the same potential. For the first transistor pair T11-T12, the drain of T12 is electrically connected to the bottom interconnect 201. For the drain of T12, the bottom doped region 115 of the semiconductor material within trench 11, i.e., the drain, preferably maintains an ohmic electrical contact with the bottom interconnect 201. Similarly, for the second transistor pair T13-T14, the drain of T14 is electrically connected to the bottom interconnect 201. For the drain of T14, the bottom doped region 115 of the semiconductor material within trench 12, i.e., the drain, also maintains an ohmic electrical contact with the bottom interconnect 201. The drain of the third transistor, T16 (T15-T16), is electrically connected to the bottom interconnect 201. For the drain of T16, the bottom doped region 115 of the semiconductor material within trench 13, i.e., the drain, also maintains an ohmic electrical contact with the bottom interconnect 201. The drains of the other transistors in trenches 11-1L corresponding to the first column of transistors, such as the doped regions 115 in each trench, are also connected to the bottom interconnect 201, which is also considered bit line B1.

[0057] See Figure 2 Note that the top interconnect 101 on the top surface or top of the semiconductor substrate and the bottom interconnect 201 on the bottom surface or bottom of the semiconductor substrate are essentially part of bit line B1. Physically, they can be interconnected through internal metal interconnect structures such as through-silicon vias (TSVs) within the semiconductor substrate, or external connections such as wire bonding. The top interconnect 101 and the bottom interconnect 201 can also be interconnected without any form of interconnection; their equivalent interconnection can be achieved in other ways, as long as their supply voltages are equal. For example, the top interconnect 101 and the bottom interconnect 201 can use the same level of supply potential.

[0058] See Figure 2 In an optional embodiment, an array of storage transistors with multiple columns is mapped to a carrier of a weight matrix for a neural network. For example, the array of the first column T11-T1N to the Mth column TM1-TMN is mapped to a carrier of the weight matrix for the neural network, where the first column T11-T1N represents the N weights of the neural network matrix and each transistor represents a weight value; similarly, the second column T21-T2N represents the N weights of the neural network matrix and each transistor represents a weight value; and the Mth column TM1-TMN represents the N weights of the neural network matrix and each transistor represents a weight value. The weight matrix is ​​calculated as an M×N element, and the weight of each storage transistor can be determined by its threshold voltage (V). THAdjustments are made using this method. In practice, due to the requirement in this paper that each trench be configured with a transistor pair, the weights of the two transistors in the pair are typically adjusted by their respective threshold voltages.

[0059] See Figure 2 In an optional embodiment, the input data of the neural network to each column of storage transistors is input to the control gate of each column of storage transistors in the form of pulse signals, and the size of the input data is adjusted by changing the pulse width of the pulse signals, so as to collect the source line charge (such as the accumulation of charge or electrical charge) of each column of storage transistors and extract the output data of the neural network at that column of storage transistors.

[0060] See Figure 3 For example, the input data fed into the first column of storage transistors T11-T1N by the neural network is sent to the control gates of each transistor T11-T1N in the form of pulse signals. T11 receives input data by sending the pulse signal Sig1 to the control gate (G1) of transistor T11. T12 receives input data by sending the pulse signal Sig2 to the control gate (G2) of transistor T12. T13 receives input data by sending the pulse signal Sig3 to the control gate (G3) of transistor T13. T1N receives input data by sending the pulse signal SigN to the control gate (GN) of transistor T1N. As shown in the figure, the input data fed into the first column of storage transistors T11-T1N by the neural network is sent to the control gates (G1-GN) of the respective storage transistors in that column in the form of pulse signals Sig1-SigN, and the same applies to the second to the Mth columns. Thus, the output data of the neural network at the first column of storage transistors T11-T1N is obtained by collecting the charge of source line S1, such as QIS1, from the source line S1. IS1 charges the capacitor C at the source line S1 to obtain QIS1. Similarly, the output data of the neural network at the second column of storage transistors T21-T2N is obtained by collecting the charge of source line S2, such as QIS2, from the source line S2. IS2 charges the capacitor at the source line S2 to obtain QIS2.

[0061] See Figure 4The size of the input data sent to the storage transistor array by the neural network is adjusted by changing the pulse width of the pulse signal. For example, in the first column of transistors, the size of the input data at T11 is adjusted by changing the pulse width of the pulse signal Sig1 received at its gate, such as the high-level time t1 of the pulse signal. The charge flowing through this transistor and to S1 is Q11 = I1 * t1. In the first column of transistors, the size of the input data at T12 is adjusted by changing the pulse width of the pulse signal Sig2 received at its gate, such as the high-level time t2 of the pulse signal. The charge flowing through this transistor and to S1 is Q12 = I2 * t2. In the first column of transistors, the size of the input data at T13 is adjusted by changing the pulse width of the pulse signal Sig3 received at its gate, such as the high-level time t3 of the pulse signal. The charge flowing through this transistor and to S1 is Q13 = I3 * t3. In the first column of transistors, the input data magnitude at transistor T1N can be adjusted by changing the pulse width of the pulse signal SigN received at its gate, such as the high-level time tn of the pulse signal. The charge flowing through this transistor and to S1 is Q1N = IN * tn. QIS1 is the sum of Q11 to Q1N. The input data of any individual transistor in the first column can be adjusted by changing the pulse width of the pulse signal at its gate. The weight value of any individual transistor in the first column is adjusted by the threshold voltage. Similarly, the input data of any individual transistor in other columns can be adjusted by changing the pulse width of the pulse signal at its gate. The weight value of any individual transistor in other columns is adjusted by the threshold voltage.

[0062] See Figure 2 In this example, the N-type doped region 111 at the top of the P-type semiconductor material at the center of the trench is considered the drain of the first transistor in the pair, and the N-type doped region 115 at the bottom of the semiconductor material is considered the drain of the second transistor in the pair. The N-type doped region 113 in the region of the semiconductor material between the top and bottom is considered the common source of both transistors. The semiconductor substrate is either P-type or N-type. The channel region 112 of the semiconductor material is the current path for the first transistor, i.e., the upper transistor, and its current magnitude is shown in I1. The channel region 114 of the semiconductor material is the current path for the second transistor, i.e., the lower transistor, and its current magnitude is shown in I2. This example uses an NMOS transistor.

[0063] See Figure 2In this transistor pair, the P-type doped region 111 at the top of the N-type semiconductor material at the center of the trench is considered the drain of the first transistor, and the P-type doped region 115 at the bottom of the semiconductor material is considered the drain of the second transistor. The P-type doped region 113 in the region of the semiconductor material between the top and bottom is considered the common source of both transistors. The semiconductor substrate is either P-type or N-type. This example uses a PMOS transistor.

[0064] See Figure 2 The gate isolation layer 131 and the floating gate isolation layer 132 within the trench 11 overlap with the doped region 113 within the trench 11, which is considered a common source, in a direction perpendicular to the trench 11, such as the Y direction. This structure is an optional mode for establishing an effective channel. In the figure, the Z direction is along the depth of the trench 11, and the Y direction is perpendicular to the Z direction and can also be considered parallel to the plane where the semiconductor substrate or wafer is located. The Z direction represents the direction of the trench and also represents the direction perpendicular to the semiconductor substrate or wafer.

[0065] See Figure 2 In an optional embodiment, an insulating layer 103 is deposited on the upper surface of the semiconductor substrate, typically comprising a silicon oxide compound or silicon nitride insulating layer. This layer can be prepared by thermal oxidation of the semiconductor substrate, or by deposition such as chemical vapor deposition or physical vapor deposition. Figure 2 The figure above shows the planar arrangement of the upper insulating layer 103, and also includes multiple side-by-side top interconnect strips 101 disposed on the front side of the semiconductor substrate. As shown, the top interconnect strips 101 are strip-shaped structures and are arranged in parallel. The length direction of the top interconnect strips 101 is A_I, and the direction perpendicular to the length direction A_I on the plane of the semiconductor substrate or wafer is A_J. The top interconnect strips 101 are spaced apart from each other on the plane of the semiconductor substrate, that is, separated from each other in the A_J direction. The top interconnect strips 101 are electrically insulated from the semiconductor substrate by the upper insulating layer 103 covering the upper surface of the semiconductor substrate, but the top interconnect strips 101 contact the semiconductor material in the trench at the trench opening, especially contacting the doped region 111.

[0066] See Figure 2The lower figure is a vertical cross-section of the trench 11-1L corresponding to the first column of memory transistors T11-T1N, while the upper figure is a top view of multiple side-by-side top interconnect strips 101. In the upper figure, the first top interconnect strip 101 from the bottom is directly above the trench 11-1L corresponding to the first column of memory transistors T11-T1N, and the trench 11-1L drawn at its location points towards the trench 11-1L corresponding to T11-T1N. The second-to-last top interconnect strip 101 in the upper figure is directly above the top interconnect strip 101 corresponding to the second column of memory transistors T21-T2N (but without shown trenches), and the unlabeled trench drawn at its location points towards the trench corresponding to T21-T2N. In the diagram above, the third-to-last top interconnect strip 101 is directly above the trenches corresponding to the third column of memory transistors T31-T3N (but not shown). The unlabeled trenches drawn at its location point to the trenches corresponding to T31-T3N. Following the same principle, the positional relationships of the other top interconnect strips and their corresponding trenches will not be described in detail. Figure 2 The cross mark in the middle indicates groove 11-1L, etc.

[0067] See Figure 2 The series of trenches 11-1L corresponding to the first column of storage transistors T11-T1N overlaps with a corresponding top interconnect strip 101 (as shown in the last top interconnect strip in the figure above). The doped region 111 at the top of each trench 11-1L corresponding to the first column of storage transistors T11-T1N is electrically contacted with the top interconnect strip 101 used as bit line B1, which overlaps with the trenches 11-1L. The trenches 11-1L corresponding to the first column of storage transistors overlap vertically with the last top interconnect strip 101. The doped region 111 at the top of each trench 11-1L corresponding to the first column of storage transistors is in contact with this interconnect strip used as bit line B1. Furthermore, the doped region 111 is electrically contacted with the top interconnect strip 101 that overlaps with the trenches 11-1L. The series of trenches corresponding to the first column of storage transistors are used to house multiple transistor pairs divided by the first column of storage transistors.

[0068] See Figure 2The series of unshown trenches corresponding to the second column of memory transistors T21-T2N overlap with a corresponding top interconnect strip 101 (as shown in the second-to-last top interconnect strip in the diagram above). The doped region 111 at the top of each of the unshown trenches corresponding to the second column of memory transistors T21-T2N is electrically contacted by the top interconnect strip 101 used as bit line B2 that overlaps with this series of unshown trenches. The unshown trenches corresponding to the second column of memory transistors overlap vertically with the second-to-last top interconnect strip 101. The doped region 111 at the top of each of the unshown trenches corresponding to the second column of memory transistors is in contact with this interconnect strip used as bit line B2. Furthermore, the doped region 111 is electrically contacted with this top interconnect strip 101 that overlaps with the unshown trenches. The series of trenches corresponding to the second column of memory transistors are used to house multiple transistor pairs divided by the second column of memory transistors. Figure 1 .

[0069] See Figure 2 Multiple side-by-side top interconnects can be configured on the front side of the semiconductor substrate. The top interconnects are electrically insulated from the semiconductor substrate by an upper insulating layer covering the upper surface of the semiconductor substrate. A series of trenches corresponding to the same column of storage transistors overlap with a corresponding top interconnect, and the doped region at the top of each series of trenches corresponding to the same column of storage transistors and a top interconnect used as a bit line that overlaps with the series of trenches are electrically connected.

[0070] See Figure 2 In an optional embodiment, an insulating layer 203 is covered on the lower surface of the semiconductor substrate, which typically includes a silicon oxide compound or silicon nitride insulating layer. This layer can be prepared by thermal oxidation of the semiconductor substrate, or by deposition such as chemical vapor deposition or physical vapor deposition. Figure 2 The figure below shows a cross-section of the lower insulating layer 203, and also includes multiple side-by-side bottom interconnect strips 201 disposed on the back side of the semiconductor substrate. These bottom interconnect strips 201 are similarly strip-shaped structures and are arranged in parallel. The length direction of the bottom interconnect strips 201 is A_I, and the direction perpendicular to the length direction A_I on the plane of the semiconductor substrate or wafer is A_J. It can be seen that the bottom interconnect strips and the top interconnect strips are basically similar in structure, except that they are located on the back and front sides of the semiconductor substrate, respectively. The bottom interconnect strips 201 are spaced apart from each other on the plane of the semiconductor substrate, i.e., separated in the A_J direction. The bottom interconnect strips 201 are electrically insulated from the semiconductor substrate by the lower insulating layer 203 covering the lower surface of the semiconductor substrate, but the bottom interconnect strips 201 contact the semiconductor material within the trench at the trench opening, especially with the doped region 115.

[0071] See Figure 2In optional embodiments, multiple side-by-side bottom interconnect strips 201 can be configured on the lower surface or back side of the semiconductor substrate. Their layout can be referenced in the description of the top interconnect strip 101 in the upper figure. The parallel arrangement of the bottom interconnect strips and their overlap with the trenches are not detailed here. The bottom interconnect strips 201 are also electrically insulated from the semiconductor substrate by the lower insulating layer 203 covering the lower surface of the semiconductor substrate. The layout of the bottom interconnect strips 201 and the lower insulating layer 203 can be referenced in the description of the top interconnect strip 101 and the upper insulating layer 103 in the upper figure. The series of trenches 11-1L corresponding to the first column of memory transistors overlap vertically with a corresponding bottom interconnect strip 201. The doped region 115 at the bottom of each series of trenches 11-1L corresponding to the first column of memory transistors is electrically contacted with a bottom interconnect strip 201 that overlaps with the series of trenches 11-1L and serves as the bit line B1 of the first column of memory transistors. Similarly, the series of unshown trenches corresponding to the second column of memory transistors overlap vertically with another corresponding bottom interconnect strip 201. The doped region 115 at the bottom of each of the unshown trenches corresponding to the second column of memory transistors is electrically contacted with another bottom interconnect strip 201 that overlaps with this series of unshown trenches and serves as the bit line B2 of the second column of memory transistors. The series of trenches corresponding to the first column of memory transistors are used to house multiple transistor pairs divided by the first column of memory transistors. The series of trenches corresponding to the second column of memory transistors are used to house multiple transistor pairs divided by the second column of memory transistors. The same applies to the other columns.

[0072] See Figure 2 As mentioned above, regarding: the series of trenches corresponding to the first column of memory transistors overlapping with a corresponding bottom interconnect strip, the doped region at the bottom of each of the series of trenches corresponding to the first column of memory transistors, and a bottom interconnect electrical contact serving as a bit line overlapping with the series of trenches. See also: the series of trenches corresponding to the first column of memory transistors overlapping with a corresponding top interconnect strip, and the doped region at the top of each of the series of trenches corresponding to the first column of memory transistors and a top interconnect electrical contact serving as a bit line overlapping with the series of trenches. The former describes the relationship between the trenches and their bottom doped regions and the bottom interconnect strip, while the latter describes the relationship between the trenches and their top doped regions and the top interconnect strip: for an explanation of the former, see the example of the latter. Even simply flipping the semiconductor substrate to swap the front and back sides is equivalent to swapping the top and bottom interconnect strips, the upper and lower insulating layers, the top and bottom doped regions, and so on.

[0073] See Figure 2Multiple side-by-side bottom interconnects can be configured on the back side of the semiconductor substrate. The bottom interconnects are electrically insulated from the semiconductor substrate by a lower insulating layer covering the lower surface of the semiconductor substrate. A series of trenches corresponding to the same column of storage transistors overlap with a corresponding bottom interconnect, and the doped region at the bottom of each series of trenches corresponding to the same column of storage transistors is electrically contacted with a bottom interconnect used as a bit line that overlaps with the series of trenches.

[0074] See Figure 5 This includes a top insulating layer 102 covering each top interconnecting strip 101 and multiple side-by-side top metal strips 303, the top insulating layer 102 covering... Figure 2 On each of the top interconnect strips 101 in the upper middle diagram. In fact, at this time, the top insulating layer 102 can also cover the area of ​​the upper insulating layer 103 that is not covered by the top interconnect strip 101. Note that if the top insulating layer 102 does not cover the area of ​​the upper insulating layer 103 that is not covered by the top interconnect strip 101, it will not have any negative impact, because both of them can play an insulating role, and if they are made of the same material, such as silicon oxide, they will actually eventually fuse together to form a single integrated structure.

[0075] See Figure 5 ,contrast Figure 2 Multiple top metal strips 303 and multiple top interconnect strips 101 correspond one-to-one, with each top metal strip 303 isolated from a top interconnect strip 101 by a top insulating layer 102 below it. Each top metal strip 303 overlaps with the top interconnect strip 101 directly below it, separated by the top insulating layer 102. The doped regions 113 within the trenches 11-1L corresponding to the first column of memory transistors T11-T1N, which are considered common sources, are electrically connected to a top metal strip 303 serving as a source line S1 that overlaps with the trenches 11-1L. Similarly, the doped regions 113 within the trenches not shown in the second column of memory transistors T21-T2N, which are considered common sources, are electrically connected to a top metal strip 303 serving as a source line S2 that overlaps with the trenches not shown in the second column of memory transistors.

[0076] See Figure 5 ,contrast Figure 2In the first column of memory transistors T11-T1N, the doped regions 113 within each of the trenches 11-1L, which are considered as common sources, are electrically connected to the top metal strip 303 serving as the source line S1. Note that the top metal strip 303 serving as the source line S1 overlaps vertically with the trenches 11-1L. In short, the doped regions 113 within each of the trenches 11-1L in the first column of memory transistors T11-T1N, which are considered as common sources, are electrically connected to a top metal strip 303 serving as the source line S1 that overlaps with the trenches 11-1L. Similarly, in the second column of memory transistors T21-T2N, the doped regions 113 within each of the trenches not shown, which are considered as common sources, are electrically connected to a top metal strip 303 serving as the source line S2 that overlaps with the trenches not shown. The doped regions inside each of the trenches corresponding to the same column of storage transistors, which are regarded as common sources, are electrically connected to a top metal line that overlaps with the series of trenches and serves as a source line. This scheme is applicable to the first to the Mth columns of transistors.

[0077] See Figure 5 ,contrast Figure 2 Taking trench 11-1L as an example: Each trench's semiconductor material has vias 301 extending downwards from the top of the trench to the doped region 113, which is considered the common source. The vias 301 penetrate both the top insulating layer 102 and the top interconnect strip 101, and the sidewalls of the vias 301 are covered by an insulating barrier layer 302. Conductors, such as tungsten or copper, filling the vias 301 electrically contact the top metal strip 303 above the trench, thereby electrically connecting the common source doped region 113 within the trench to the top metal strip 303. The top interconnect strip 101 is typically made of copper or aluminum-silicon-copper alloys, while the top metal strip 303 is made of copper or tungsten. The conductors or plugs filling the vias 301 are prevented from diffusing through the barrier layer 302. The barrier layer can be silicon nitride or a composite layer of silicon nitride and silicon oxide. The conductors or plugs contact the doped region 113 at the bottom of the vias 301. The top metal strip 303 and the conductor or plug inside the via 301 on the front side of the semiconductor substrate can be prepared in the same process stage, such as sputtering or depositing metal materials such as copper or tungsten into the via 301 and covering 102, and then grinding or etching back the metal material.

[0078] See Figure 5In summary, the system includes a top insulating layer covering each top interconnect strip and multiple side-by-side top metal strips, with each top metal strip corresponding to a top interconnect strip. Each top metal strip is isolated from a top interconnect strip by the top insulating layer below it and overlaps with each other. The doped regions inside each of the trenches corresponding to the same column of storage transistors, which are considered as common sources, are electrically connected to a top metal strip used as a source line that overlaps with the series of trenches. A via is formed in the semiconductor material within each trench, extending downward from the top of the trench to the doped region considered as a common source. The via penetrates the top insulating layer and the top interconnect strips, and the sidewalls of the via are covered with an insulating barrier layer. The conductor filled in the via electrically contacts the top metal strip above the trench, thereby electrically connecting the common source, such as the source doped region, within the trench to the top metal strip. Figure 5 The large fork mark indicates via 301, while the small fork mark indicates via 345 connected to the control gate (a) or via 346 connected to the control gate (c).

[0079] See Figure 5 ,contrast Figure 2As previously mentioned, the bottom interconnect 201 and the top interconnect 101 are similar. This example includes a bottom insulating layer 202 covering each bottom interconnect 201 and multiple side-by-side bottom metal strips 403. Note that the bottom metal strips 403 and the top metal strips 303 have similar structures, except that the bottom interconnects 201 and 403 are located on the back side of the semiconductor substrate, while the top interconnects 101 and 303 are located on the front side. Even simply flipping the semiconductor substrate to swap the front and back sides is equivalent to swapping the top and bottom interconnects, the upper and lower insulating layers, the doped regions on the top and bottom, and so on. The relationship between the multiple bottom metal strips 403 and the multiple bottom interconnect strips 201 is similar to that between the top metal strip 303 and the top interconnect strip 101: that is, the multiple bottom metal strips 403 and the multiple bottom interconnect strips 201 correspond one-to-one, with each bottom metal strip 403 isolated from and overlapping with a bottom interconnect strip 201 through the bottom insulating layer 202 above it. Referring to the previous embodiment, the doped regions 113, which are considered as common sources, inside each of the series of trenches 11-1L corresponding to the first column of memory transistors T11-T1N are electrically connected to a bottom metal strip 403, which serves as a source line S1, and overlaps with the series of trenches 11-1L. Similarly, the doped regions 113, which are considered as common sources, inside each of the series of trenches not shown, corresponding to the second column of memory transistors T21-T2N are electrically connected to a bottom metal strip 403, which serves as a source line S2, and overlaps with the series of trenches not shown. Similarly, the doped regions inside each of the trenches corresponding to the same column of storage transistors, which are regarded as common sources, are electrically connected to a bottom metal line that overlaps with the series of trenches and serves as a source line. This scheme is applicable to the first to the Mth columns of transistors.

[0080] See Figure 5 ,contrast Figure 2Either the top metal strip 303 or the bottom metal strip 403 can be selected, or they can coexist. That is, the semiconductor material of the trench is required to have a via 301 extending downwards from the top of the trench to the doped region considered as the common source, while retaining the top metal strip 303. Alternatively, the semiconductor material of the trench is required to have a via 351 extending upwards from the bottom of the trench to the doped region considered as the common source, while retaining the bottom metal strip 403. Alternatively, the semiconductor material of the trench may have a via 301 extending downwards from the top of the trench to the doped region considered as the common source, and a via 351 extending upwards from the bottom of the trench to the doped region considered as the common source. It should be noted that in this case, the conductors within both vias 301 and 351 contact the doped region 113 at the common source doped region 113. In this case, both the top metal strip 303 and the bottom metal strip 403 are retained, and they are both considered as part of the source line S1. For example, the doped regions 113 inside each of the trenches corresponding to the first column of storage transistors, which are regarded as common sources, are electrically connected to a bottom metal strip 403 that overlaps with the trenches and serves as a source line S1. At the same time, the doped regions 113 inside each of the trenches corresponding to the first column of storage transistors, which are regarded as common sources, are electrically connected to a top metal strip 303 that overlaps with the trenches and serves as a source line S1.

[0081] See Figure 5 ,contrast Figure 2 Taking trench 11-1L as an example: Each trench's semiconductor material has vias 351 extending upwards from the bottom of the trench to the doped region 113, which is considered the common source. The vias 351 penetrate both the bottom insulating layer 202 and the bottom interconnect strip 201, and the sidewalls of the vias 351 are covered with an unlabeled insulating barrier layer. Conductors such as tungsten or copper filled within the vias 351 electrically contact the bottom metal strip 403 below the trench, thereby electrically connecting the common source doped region 113 within the trench to the bottom metal strip 403. The bottom interconnect strip 201 is typically made of copper or aluminum-silicon-copper, while the bottom metal strip 403 is made of copper or tungsten. The conductors or plugs filled within the vias 351 are prevented from diffusing by the unlabeled barrier layer, which can be silicon nitride or a composite layer of silicon nitride and silicon oxide. The conductors or plugs contact the doped region 113 at the top of the vias 351. The bottom metal strip 403 on the back side of the semiconductor substrate and the conductor or plug inside the via 351 can be prepared in the same process stage, such as sputtering or depositing a metal material such as copper or tungsten into the via 351 and covering 202, and then grinding or etching back the metal material.

[0082] See Figure 5In summary, the system includes a bottom insulating layer covering each bottom interconnect strip and multiple side-by-side bottom metal strips, with each bottom metal strip corresponding to a bottom interconnect strip (refer to the related scheme shown in the attached figure regarding the one-to-one correspondence between multiple top metal strips and multiple top interconnect strips). Each bottom metal strip is isolated from a bottom interconnect strip by the bottom insulating layer above it and overlaps with each other. The doped regions inside each of the trenches corresponding to the same column of storage transistors, which are considered as common sources, are electrically connected to a bottom metal strip used as a source line that overlaps with the series of trenches. A via is formed in the semiconductor material within each trench, extending upward from the bottom of the trench to the doped region considered as a common source. The via penetrates the bottom insulating layer and the bottom interconnect strips, and the sidewalls of the via are covered with an insulating barrier layer. The conductor filled in the via electrically contacts the bottom metal strip below the trench, thereby electrically connecting the common source, such as the source doped region, within the trench to the bottom metal strip.

[0083] See Figure 5 Note that the bottom metal strip 403 on the bottom surface or bottom of the semiconductor substrate and the top metal strip 303 on the top surface or top of the semiconductor substrate are essentially part of the source line S1. Physically, they can be interconnected through internal metal interconnect structures within the semiconductor substrate, such as through-silicon vias (TSVs), or external connections such as wire bonding. Alternatively, the bottom metal strip 403 and the top metal strip 303 can be interconnected without any form of interconnection; their equivalent interconnection can be achieved in other ways, as long as their voltage levels are equal. For example, the bottom metal strip 403 and the top metal strip 303 can use the same reference potential.

[0084] See Figure 5 As mentioned above, in comparison Figure 2 An array of multi-column storage transistors is mapped to the weight matrix of a neural network. Figure 1 In the array, the trenches to which the many transistor pairs (couples) in the first column belong, such as trench 11-1L in the figure, are arranged on the same vertical line of the semiconductor substrate. Figure 2The top interconnect strips 101 are strip-shaped structures arranged in parallel. The length direction of the top interconnect strips 101 is A_I, and the direction perpendicular to the length direction A_I on the plane of the semiconductor substrate or wafer is A_J. The vertical line is the direction of A_I and belongs to the column line or vertical axis of the array. The direction perpendicular to the vertical line on the substrate plane is the row line, which is the direction of A_J and belongs to the horizontal line or horizontal axis of the array. The trenches belonging to transistor pairs T11-T12, T13-T14, T15-T16, etc., in the first column are arranged along the same vertical line of the substrate (e.g., along the length direction of the penultimate top interconnect strip 101 in the A_I direction). Following the same arrangement principle, the trenches belonging to transistor pairs T21-T22, T23-T24, T25-T26, etc., in the second column are arranged along the same vertical line of the substrate (e.g., along the length direction of the second-to-last top interconnect strip 101 in the A_I direction). Following the same arrangement principle, the trenches belonging to transistor pairs T31-T32, T33-T34, T35-T36, etc., in the third column are arranged along the same longitudinal line of the substrate (e.g., along the length of the third-to-last top interconnect strip 101 in the A_I direction). The trenches belonging to other transistor pairs in the same column of the array are also arranged along the same longitudinal line, which will not be described in detail here.

[0085] See Figure 5 As mentioned above, in comparison Figure 2 An array of multi-column storage transistors is mapped to the weight matrix of a neural network. Figure 1 In the array, trenches belonging to transistor pairs located in different columns but having the same column position number are arranged in the same row on the semiconductor substrate. In different first, second, and third columns up to the Mth column, trenches belonging to transistor pairs with the same column position number are arranged in the same row on the semiconductor substrate: the trench belonging to transistor pair T11-T12 with column position number one in the first column is arranged in the first row; the trench belonging to transistor pair T21-T22 with column position one in the second column is arranged in the first row; the trench belonging to transistor pair T31-T32 with column position one in the third column is arranged in the first row. The first row is, for example, the first row from left to right in the A_J direction. Other transistor pairs with column position number one are also possible, and will not be elaborated further. Figure 2 The first A_J row line marked with a cross.

[0086] See Figure 5Transistor pairs with the same column number have their trenches arranged in the same row on the semiconductor substrate: the trench belonging to transistor pair T13-T14 (column number two) in the first column is arranged in the second row; the trench belonging to transistor pair T23-T24 (column number two) in the second column is arranged in the second row; and the trench belonging to transistor pair T33-T34 (column number two) in the third column is arranged in the second row. The second row is, for example, the second row from left to right in the A_J direction. Other transistor pairs with the same column number two are also acceptable, and will not be elaborated further. Figure 2 The second A_J row line marked with a cross.

[0087] See Figure 5 Transistor pairs with the same column number have their trenches arranged in the same row on the semiconductor substrate: the trench belonging to transistor pair T15-T16 (column number three) in the first column is arranged in the third row; the trench belonging to transistor pair T25-T26 (column number three) in the second column is arranged in the third row; and the trench belonging to transistor pair T35-T36 (column number three) in the third column is arranged in the third row. The third row is, for example, the third row from left to right in the A_J direction. Other transistor pairs with the same column number three can also be arranged, and will not be elaborated further. Similarly, the third A_J row is marked with a cross.

[0088] See Figure 5 In this array, multiple trenches belonging to transistor pairs in the same column are arranged along the same vertical line (also called column line or vertical axis) on the semiconductor substrate. Multiple trenches belonging to transistor pairs in different columns but with the same column number are arranged along the same row line (also called horizontal line or horizontal axis) on the semiconductor substrate. This scheme facilitates the provision of easily cut or expanded neural network weight matrices while remaining compatible with existing semiconductor process conditions, enabling the construction of flash memory with extremely high cell density for neural networks. It is worth noting that the transistor pair mode is proposed considering the requirements for source interconnection of different transistor pairs on the semiconductor substrate and minimizing the mutual interference of pulse signals. If too many transistors are fabricated in the same trench, the pulse signals of different transistors will inevitably affect each other, and source interconnection (collecting source charge while minimizing parasitic parameters) of transistors in different trenches will be a challenge.

[0089] See Figure 5 In the so-called row of trenches corresponding to the transistor pairs on the first row (such as T11-T12, T21-T22, T31-T32, etc.), for example... Figure 2In the diagram above, the trenches marked with a cross, corresponding to the first A_J row, have their respective first-order control gates (e.g., 'a') electrically connected to each other. For example, the control gates (e.g., 'a') of the first transistor pairs (T11, T21, T31, etc.) are interconnected during the fabrication process. Alternatively, conductors or plugs within via 345 can be used to wire-bond the control gates (e.g., 'c') outside the semiconductor substrate. In an alternative example, the control gates of their respective second-order counterparts are electrically connected to each other. For example, the control gates (e.g., 'c') of the second transistor pairs (T12, T22, T32, etc.) are interconnected during the fabrication process. Alternatively, conductors or plugs within via 346 can be used to wire-bond the control gates (e.g., 'c') outside the semiconductor substrate. The threshold voltages of the first transistors (T11-T12, T21-T22, T31-T32, etc.) on the same row line are modulated differently, and the threshold voltages of the second transistors (T12, T22, T32, etc.) on the same row line are also modulated differently. Since the control gates of the first transistors within each pair of transistors on the same row line are electrically connected, and the control gates of the second transistors within each pair are also electrically connected, the threshold voltages of the first transistors on the same row line are modulated differently, and the threshold voltages of the second transistors on the same row line are modulated differently. This is to ensure that the weights of the array with multiple columns of memory transistors can be adapted to the semiconductor substrate process when mapped into a neural network, and to simplify the manufacturing process. Because the control gates (a or c) of transistor pairs located on the same row of trenches share the same material and fabrication process, manufacturing them within the same process stage simplifies the process and improves gate consistency. Minimizing process differences between different control gates significantly improves the accuracy of AI weight training, which is crucial for adapting to precise memory transistor weight values ​​during wafer fabrication. Another advantage of this approach is that the control gates of the first transistor within each trench on the same row of trenches can be synchronously controlled in software, as can the control gates of the second transistor within each trench. However, the control gates of the first and second transistors within each trench are asynchronously controlled. The upper and lower parts of the control gate layer within the same trench are configured to operate asynchronously to suppress the modulation of the common source within a single trench by pulse signals from the upper and lower parts. Synchronous control during the large-scale weight matrix training stage saves significant training time. For example, this embodiment is an extremely important solution when edge computing devices or systems face limited computing power and limited hardware resources.

[0090] See Figure 5 For example, in the trench row corresponding to the transistor pairs on the second line (such as T13-T14, T23-T24, T33-T34, etc.), for instance... Figure 2 In the second row of A_J in the diagram above, the trenches marked with a cross have their respective first-order control gates (e.g., 'a') electrically connected. For example, the control gates (e.g., 'a') of the first-order transistors T13, T23, T33, etc., of a transistor pair are interconnected during the fabrication process. In an alternative example, the control gates of their respective second-order transistors are electrically connected. For example, the control gates (e.g., 'c') of the second-order transistors T14, T24, T34, etc., of a transistor pair are interconnected during the fabrication process. The threshold voltages of the first-order transistors (T13-T14, T23-T24, T33-T34, etc.) of the same row of transistors are modulated differently, and the threshold voltages of the second-order transistors (T14, T24, T34, etc.) of transistor pairs located on the same row are also modulated differently.

[0091] See Figure 5 Or, in the trench corresponding to the transistor pairs on the first row (such as T11-T12, T21-T22, T31-T32, etc.), for example... Figure 2In the first row of trenches marked with a cross (A_J) in the diagram above, the control gates (e.g., 'a') of the first transistors within each pair are not connected to each other. For example, the control gates (e.g., 'a') of the first transistors T11, T21, T31, etc., are set to be unconnected during the fabrication process. In an alternative example, the control gates of the second transistors within each pair are set to be electrically unconnected. For example, the control gates (e.g., 'c') of the second transistors T12, T22, T32, etc., are set to be unconnected during the fabrication process. At this time, the threshold voltages of the first transistors (T11-T12, T21-T22, T31-T32, etc.) of the same pair of transistors (T11-T12, T21-T22, T31-T32, etc.) are modulated to be the same or different, and the threshold voltages of the second transistors (T12, T22, T32, etc.) of the same pair of transistors on the same pair are modulated to be the same or different. In a row of trenches corresponding to transistor pairs on the same line, the control gates of the first transistor within each pair are configured to be disconnected from each other, and the control gates of the second transistor within each pair are configured to be disconnected from each other. The threshold voltages of the first transistors and the second transistors on the same line are modulated to be the same or different to implement asynchronous control. The consideration is that the control gates of the first transistors and the second transistors within each pair can be configured to be asynchronously controlled at the software operation level. Transistor pairs (T11-T12, T21-T22, T31-T32, etc.) are located on the same row, but their respective gates need to be operated individually rather than synchronously. If the input data differs significantly, and even with appropriate solutions (typically normalization) to mitigate this difference, it may still be insufficient to overcome the excessively large distance between the extreme values ​​in the weight matrix caused by the input data's variability. For example, a neural network configuration might require some transistors to have high weight values ​​and others low weight values. However, semiconductor fabrication processes face difficulties in achieving high and low threshold resolution due to the large gap between high and low weight values. In such cases, asynchronous control of the control gates of transistors on the same row is the optimal solution. In asynchronous operation, the weights of transistors belonging to the same row and the input data of each transistor are independent, providing a compromise between the neural network's input and the resolution of high and low thresholds.

[0092] See Figure 5In this example, in the trenches corresponding to the transistor pairs on the same row: the control gates of the first transistors within each pair are electrically connected, and the control gates of the second transistors within each pair are electrically connected; the threshold voltages of the first transistors on the same row are modulated differently, and the threshold voltages of the second transistors on the same row are modulated differently; in the trenches corresponding to the transistor pairs on the same row: the control gates of the first transistors within each pair are synchronously controlled, and the control gates of the second transistors within each pair are synchronously controlled, but the control gates of the first transistors within each pair and the control gates of the second transistors within each pair are asynchronously controlled. This example is explained above. The pulse signals of the control gates of the first and second transistors within the same trench can be suppressed from modulating the common source of this same trench. It is noted that modulation of the common source in the trench will unexpectedly charge the source line, especially the pulse superposition effect of the control gates of the first and the second. This is unacceptable for neural networks that are extremely sensitive to source line charge and rely on the acquisition of source line charge to obtain output data, and the output results are also significantly deviated.

[0093] See Figure 5In this example, in the trenches corresponding to transistor pairs on the same row line, the control gates of the first transistors within each pair are not connected to each other, and the control gates of the second transistors within each pair are not connected to each other. The threshold voltages of the first transistors on the same row line are modulated to be the same or different, and the threshold voltages of the second transistors on the same row line are modulated to be the same or different. Within the trenches corresponding to transistor pairs on the same row line, the control gates of the first transistors within each pair are asynchronously controlled, and the control gates of the second transistors within each pair are also asynchronously controlled. This asynchronous control suppresses the modulation of the source electrodes within the trenches. Not only are the control gates of the first and second trenches within the same trench configured to operate asynchronously (i.e., the upper and lower portions of the control gate layer within the same trench are configured to operate asynchronously), but the control gates of the first trenches in different trenches on the same row line are also configured asynchronously (i.e., the upper portions of the control gate layers of different trenches on the same row line are configured asynchronously). Furthermore, the control gates of the second trenches in different trenches on the same row line are configured asynchronously (i.e., the lower portions of the control gate layers of different trenches on the same row line are configured asynchronously). This suppresses the modulation of the common source electrode in any trench by pulse signals applied to the control gates of the first and second trenches (upper and lower portions of the control gate layer) within that trench, and also suppresses the modulation of the common source electrode in any trench by pulse signals applied to the control gates of the first or second trenches (upper and lower portions of the control gate layer) of other trenches on the same row line to which that trench belongs. The main reason is that the common source electrode is sensitive to source line charge.

[0094] The foregoing description and accompanying drawings have provided typical embodiments of specific structures for specific implementations. The above-described invention presents preferred embodiments, but these are not intended to be limiting. Various changes and modifications will undoubtedly be apparent to those skilled in the art after reading the foregoing description. Therefore, the appended claims should be considered to cover all changes and modifications that encompass the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should be considered to still fall within the intent and scope of the invention.

Claims

1. A storage system supporting edge computing, characterized in that, include: A semiconductor substrate with multiple rows of storage transistors is arranged, each row of storage transistors is divided into multiple transistor pairs and each pair of storage transistors in each transistor pair has a common source. The common source of each pair of transistors in the same row of storage transistors is set to the same potential as the common source line, and all drains of all pairs of transistors in the same row of storage transistors are set to the same potential as the common source line. The array with multiple rows of storage transistors is mapped to the carrier of the weight matrix of a neural network. Multiple trenches are formed on a semiconductor substrate. Each trench is filled with an outer insulating layer, a control gate layer, an interlayer insulating layer, a floating gate layer, a gate insulating layer, and a semiconductor material in the direction from the sidewall to the center. A doped region of a second conductivity type at the top of a semiconductor material with a first conductivity type at the center of any trench is regarded as the drain of the first transistor in the transistor pair; a doped region of a second conductivity type at the bottom of the semiconductor material is regarded as the drain of the second transistor in the transistor pair; and a doped region of a second conductivity type in the semiconductor material located between the top and the bottom is regarded as the common source of the two transistors in the transistor pair. A gate isolation layer separating the control gate layer of each trench and a floating gate isolation layer separating the floating gate layer of each trench are used. The upper part of the control gate layer is regarded as the control gate of the first one, and the lower part of the control gate layer is regarded as the control gate of the second one. The upper part of the floating gate layer is regarded as the floating gate of the first one, and the lower part of the floating gate layer is regarded as the floating gate of the second one. The weight of the two in each transistor pair is adjusted by their respective threshold voltages.

2. The storage system supporting edge computing according to claim 1, characterized in that: The neural network sends input data to each column of storage transistors in the form of pulse signals to the control gate of each column of storage transistors. The size of the input data is adjusted by changing the pulse width of the pulse signal, and the output data of the neural network at the column of storage transistors is obtained by collecting the source line charge of each column of storage transistors.

3. The storage system supporting edge computing according to claim 1, characterized in that: If the first conductivity type is P conductivity type, then the second conductivity type is N conductivity type, or vice versa, that is, if the first conductivity type is N conductivity type, then the second conductivity type is P conductivity type.

4. The storage system supporting edge computing according to claim 1, characterized in that: Both the gate isolation layer and the floating gate isolation layer in each trench overlap with the doped region within the trench, which is considered a common source, in a direction perpendicular to the trench.

5. The storage system supporting edge computing according to claim 1, characterized in that: It includes multiple side-by-side top interconnect strips disposed on the front side of a semiconductor substrate. The top interconnect strips are electrically insulated from the semiconductor substrate through an upper insulating layer covering the upper surface of the semiconductor substrate. A series of trenches corresponding to the same column of storage transistors overlap with a corresponding top interconnect strip, and the doped region at the top of each series of trenches corresponding to the same column of storage transistors and a top interconnect strip used as a bit line that overlaps with the series of trenches are electrically connected.

6. The storage system supporting edge computing according to claim 5, characterized in that: It includes multiple side-by-side bottom interconnects disposed on the back side of a semiconductor substrate. The bottom interconnects are electrically insulated from the semiconductor substrate by a lower insulating layer covering the lower surface of the semiconductor substrate. A series of trenches corresponding to the same column of storage transistors overlap with a corresponding bottom interconnect, and the doped region at the bottom of each series of trenches corresponding to the same column of storage transistors is electrically contacted with a bottom interconnect serving as a bit line that overlaps with the series of trenches.

7. The storage system supporting edge computing according to claim 6, characterized in that: It includes a top insulating layer covering each top interconnect strip and multiple side-by-side top metal strips, with each top metal strip corresponding to a top interconnect strip. Each top metal strip is isolated from and overlaps with a top interconnect strip through the top insulating layer below it. The doped regions inside each of the series of trenches corresponding to the same column of storage transistors, which are regarded as common sources, are electrically connected to a top metal strip used as a source line that overlaps with the series of trenches. Each trench has a via formed in its semiconductor material, extending downward from the top of the trench to the doped region considered as a common source. The via penetrates the top insulating layer and the top interconnect strip, and its sidewalls are covered with an insulating barrier layer. The conductors filling the vias electrically contact the top metal strip above the trench, electrically connecting the common source in the trench to the top metal strip.

8. The storage system supporting edge computing according to claim 6, characterized in that: It includes a bottom insulating layer covering each bottom interconnect strip and multiple side-by-side bottom metal strips. The multiple bottom metal strips correspond one-to-one with the multiple bottom interconnect strips. Each bottom metal strip is isolated from and overlaps with a bottom interconnect strip through the bottom insulating layer above it. The doped regions inside each of the series of trenches corresponding to the same column of storage transistors, which are regarded as common sources, are electrically connected to a bottom metal strip used as a source line that overlaps with the series of trenches. Each trench has a via formed in its semiconductor material, extending upward from the bottom of the trench to the doped region considered as a common source. The via penetrates the bottom insulating layer and the bottom interconnect strip, and its sidewalls are covered with an insulating barrier layer. The conductor filled in the via electrically contacts the bottom metal strip below the trench, electrically connecting the common source in the trench to the bottom metal strip.

9. The storage system supporting edge computing according to claim 1, characterized in that: In the array, the trenches belonging to multiple transistor pairs in the same column are arranged on the same vertical line of the semiconductor substrate, and the trenches belonging to multiple transistor pairs in different columns but with the same column number are arranged on the same row line of the semiconductor substrate.

10. The storage system supporting edge computing according to claim 9, characterized in that: In a row of trenches corresponding to pairs of transistors on the same row, the control gates of the first transistors within each pair are electrically connected to each other, and the control gates of the second transistors within each pair are electrically connected to each other. The threshold voltages of the first transistors on the same row are modulated differently, and the threshold voltages of the second transistors on the same row are modulated differently. Or In a row of trenches corresponding to a pair of transistors on the same row line, the control gates of the first transistors within each pair are configured not to be connected to each other, the control gates of the second transistors within each pair are configured not to be connected to each other, the threshold voltages of the first transistors on the same row line are modulated to be the same or different, and the threshold voltages of the second transistors on the same row line are modulated to be the same or different.

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