A memory and an electronic device

By employing pull-up and pull-down driver modules with a combined resistor network structure in the memory to adjust the resistance value to enable the transmission of PAM3 signals, the challenges of signal transmission rate and eye diagram margin are solved, and data throughput and bandwidth efficiency are improved.

CN122135755APending Publication Date: 2026-06-02JIXINTUOFANG TECHNOLOGY (SHANGHAI) CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
JIXINTUOFANG TECHNOLOGY (SHANGHAI) CO LTD
Filing Date
2026-02-02
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Designing the PAM3 signal transmission circuit in memory to improve data throughput and bandwidth efficiency presents challenges, particularly in terms of signal transmission rate and eye diagram margin.

Method used

It employs two pull-up driver modules and two pull-down driver modules, implemented using a combined resistor network structure. The resistance value is adjusted by adjusting the resistance adjustment code and calibration code to meet the requirements of signal transmission rate and eye diagram margin.

Benefits of technology

It achieves a high signal transmission rate and eye diagram margin, improving data throughput and bandwidth efficiency.

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Abstract

This disclosure provides a memory and an electronic device. The memory includes a data driving module and a data port. The data driving module is used to adjust the level value of the data port to characterize target data as a first value, a second value, or a third value. The data driving module includes a first pull-up driving module, a second pull-up driving module, a first pull-down driving module, and a second pull-down driving module. At least one of the first pull-up driving module, the second pull-up driving module, the first pull-down driving module, and the second pull-down driving module employs a combined resistor network. The combined resistor network includes an adjustment unit and a driving resistor. The adjustment unit includes multiple adjustment branches connected in parallel. The equivalent resistance of each adjustment branch is adjusted by a sub-signal of a corresponding resistance adjustment code. The driving resistor is connected to all adjustment branches in the adjustment unit, and the resistance value of the driving resistor is independent of the resistance adjustment code.
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