An easily integrated all-mos structure memristor analog circuit

Abstract

This invention discloses an easily integrated all-MOS structure memristor analog circuit, which consists of two functional modules: a current-multiplexed integrator module and an operational transconductance amplifier module. M1-M3 constitute the current-multiplexed integrator module, used to convert the input voltage to the integration control voltage and memorize the historical state of the input voltage signal; M1 and M2 form a current-multiplexed structure, and M3 acts as a MOS transistor capacitor to achieve the integration function. M4-M8 constitute the operational transconductance amplifier module, used to realize the resistive-change memory characteristic of the memristor analog circuit; M4 and M5 form a completely symmetrical current mirror structure, M6 and M7 are differential input pairs with identical structure and parameters, and M8 serves as a tail current source. This invention features a simple circuit structure that is easy to integrate, consisting of only eight MOS transistors, eliminating the need for discrete components such as operational amplifiers and multipliers, and meeting the requirements for miniaturization, low power consumption, and wide bandwidth.

Description

Technical Field

[0001] This invention relates to a CMOS analog integrated circuit with memristor characteristics, and more particularly to an easily integrated all-MOS structure memristor analog circuit. Background Technology

[0002] With the rapid development of artificial intelligence technology and the ever-increasing volume of data processing, the bottleneck problems caused by the separation of storage and computing in the traditional von Neumann architecture are becoming increasingly prominent. Frequent data transfer between storage and computing units not only leads to extremely high power consumption but also severely restricts the improvement of computing power and energy efficiency. Against this backdrop, memristors, with their unique resistive-switching memory characteristics, have become one of the important implementation solutions for in-memory computing hardware circuits.

[0003] As the fourth basic passive component in circuit theory, the core characteristic of a memristor lies in its malleable resistance. When a specific external electric field is applied to a memristor, its resistance will continuously change, and this resistance state can be maintained after the power is turned off. Furthermore, this resistance change is directional; that is, when an external electric field in the opposite direction is applied, the memristor will produce the opposite resistance change.

[0004] This characteristic of memristors perfectly matches the plasticity of biological synaptic weights, making them valuable for applications in neural network hardware implementation. Specifically, the connection strength of biological synapses changes with neuronal activity, similar to how the resistance of a memristor changes with an applied electric field. This similarity allows memristors to simulate the function of biological synapses, providing an ideal basic component for building efficient, low-power neural network hardware circuits.

[0005] Furthermore, memristors possess numerous advantages, including low power consumption, nanometer-scale size, and compatibility with standard CMOS processes. These advantages make memristor-based hardware circuit research promising and are expected to drive new breakthroughs in fields such as artificial intelligence and neuromorphic computing.

[0006] Currently, memristors are mainly implemented in the following ways: nanophysical devices, Spice models, and circuit simulators. Nanophysical devices for memristors are still primarily in the laboratory stage. For example, HP first implemented a nano-memristor using TiO2, but due to its high manufacturing cost, technical complexity, and poor product consistency, it has not yet achieved true commercialization. Memristor Spice models define device characteristics through mathematical equations or behavioral descriptions, but they are only suitable for theoretical simulation analysis and cannot be used for related hardware experimental verification. Current memristor circuit simulators are built using discrete components on breadboards or PCBs, such as operational amplifiers, current transmitters, multipliers, resistors, and capacitors. However, these simulators require many discrete components, are large in size, consume a lot of power, have complex structures, and operate at low frequencies, making them unsuitable for the practical needs of large-scale integrated circuit engineering applications.

[0007] Currently, the advantages of CMOS integrated circuits are mainly reflected in several aspects: small size and light weight; advanced technical specifications and high reliability; ease of mass production and low cost. Memristors designed using CMOS integrated circuits have advantages such as high precision, high operating frequency, low voltage and low power consumption, and small area.

[0008] Therefore, this project studies memristor analog circuits based on CMOS technology, using standard CMOS technology to design an easily integrated all-MOS structure memristor analog circuit. This results in a simple and easy-to-integrate CMOS memristor integrated circuit structure, consisting of only a few MOS transistors, eliminating the need for discrete components such as operational amplifiers and multipliers, and meeting requirements for miniaturization, low power consumption, and wide bandwidth. Summary of the Invention

[0009] The purpose of this invention is to design an easily integrated all-MOS structure memristor analog circuit. It employs CMOS technology, consists of only a small number of MOS transistors, and eliminates the need for discrete components such as operational amplifiers and multipliers, significantly reducing the number of active and passive components. The designed CMOS memristor achieves the memory characteristics of a memristor, with low power consumption and a small area, making it suitable for miniaturized integrated circuit chip design. Due to the small number of MOS transistors used, the designed CMOS memristor can operate at frequencies exceeding MHz.

[0010] This invention is achieved through the following technical solution: an easily integrated all-MOS structure memristor analog circuit, such as... Figure 1As shown, this memristor circuit consists of only eight MOS transistors: M1, M3, M4, and M5 are PMOS transistors, and M2, M6, M7, and M8 are NMOS transistors. The memristor circuit is divided into two functional modules: a first-stage current-multiplexing integrator module and a second-stage operational transconductance amplifier (OTA) module. The first-stage current-multiplexing integrator module, composed of PMOS transistors M1 and M3 and NMOS transistor M2, is used to implement the input voltage signal V. in To the integral control voltage V C The conversion completes the conversion of the input voltage signal V. in Memorizing historical states. M1 and M2 form a single-ended input, single-ended output current multiplexing structure. The gates of M1 and M2 are connected together, serving as the signal input terminal of the memristor circuit, connected to the input voltage signal V. in The drain and source of PMOS transistor M3 are both grounded, and the intrinsic gate oxide capacitance of the MOS transistor is used as the MOS transistor capacitance to achieve the integration function. The second-stage operational transconductance amplifier module is the resistive switching characteristic implementation module of the memristor circuit. It consists of PMOS transistors M4 and M5, and NMOS transistors M6, M7, and M8. The gates of M4 and M5 are connected together and connected to the drain of M4, forming a completely symmetrical 1:1 current mirror structure. M6 and M7 are a differential input pair with completely identical structure and parameters. The gate of M6 is connected to the input voltage signal V of the memristor circuit. in M7's gate is grounded, M6's drain is connected to M4's drain, and M7's drain is connected to M5's drain, serving as the output node of the memristor circuit. M8 acts as the tail current source, its drain connected to the sources of M6 and M7; M8's gate is connected to node C, receiving the control voltage V output from the first-stage current multiplexing integrator module. C .exist Figure 1 In the middle, the input voltage signal V in On one hand, it is input to the gates of M1 and M2 in the current multiplexing structure, and on the other hand, it is also input to the gate of M6 in the OTA module; the drain nodes of M1 and M2 are connected together with the gate of the MOS transistor capacitor M3 and are denoted as node C, and connected to the gate of the M8 transistor.

[0011] exist Figure 1 In the middle, when the input voltage signal V in After being input to the first-stage current multiplexing integrator module, the current multiplexing structure composed of M1 and M2 converts the input voltage into the corresponding charging and discharging current I. C The effective transconductance of M1 and M2 is enhanced by utilizing a current multiplexing structure, thereby improving the voltage-to-current conversion efficiency; the charging and discharging current I C The intrinsic gate oxide capacitor of the MOS transistor, formed by M3, is charged and discharged to control the voltage V at node C. C With input voltage signal V in The time integral is linear, thus the input voltage signal Vin The historical state is transformed into a quantifiable control voltage V C The output enables the core memory characteristic of the memristor. The input voltage signal V... in The input is given to the gate of the differential pair transistor M6 as the single-ended differential input signal of the OTA module. The control voltage V output from the first-stage current multiplexing integrator module... C The input voltage is fed to the gate of the tail current transistor M8. By modulating the gate-source voltage of M8, the total tail current of the OTA module is changed, thereby altering the transconductance of the differential pair transistors M6 and M7, ultimately achieving continuous adjustment of the total transconductance of the OTA module. Since the equivalent memristor circuit's transconductance is numerically equal to the total transconductance of the OTA module, the input voltage signal V... in Historical state corresponding control voltage V C This allows for dynamic modulation of the equivalent memristor conductance of the circuit, enabling the input current signal I of the memristor circuit to be dynamically modulated. in With input voltage signal V in The resistance-to-resistance relationship between the two varies with the input history, thus realizing the resistance-to-resistance memory characteristic of the memristor circuit.

[0012] To verify that the memristor circuit proposed in this invention theoretically possesses memristor characteristics, the equivalent memristor conductance expression of this memristor circuit is derived. Let the input voltage signal at the input terminal of the memristor circuit be V. in The input voltage signal V in It is input to the gates of M1 and M2 in the current multiplexing structure on one hand, and to the gate of M6 in the OTA structure on the other hand. Figure 1 The connection relationships in the diagram can be obtained by applying Kirchhoff's current law to node ①:

[0013] ,

[0014] The equivalent memorization expression of the circuit can be obtained by rearranging: ,

[0015] The input equivalent transconductance of the OTA module composed of M4-M8 is set as G. m1 I OUT I is the output current of the OTA module. in This represents the input current of the memristor circuit. From the above equation, it can be seen that if the total transconductance G of the OTA module can be verified... m1 The memristor characteristic of the circuit can be demonstrated by the time integral of the input voltage.

[0016] Based on the working principle of a MOSFET, the expression for the drain current of a MOSFET operating in the saturation region is as follows:

[0017] ,

[0018] The transconductance expression of a MOSFET operating in the saturation region is as follows:

[0019] ,

[0020] Where K n (or K) p ) represents the conductivity constant of the MOSFET, µ n (or µ) p C represents the carrier mobility of the MOSFET. ox V is the capacitance per unit area of ​​the gate oxide layer of the MOSFET, W and L are the channel width and length of the MOSFET, and V is the capacitance per unit area of ​​the gate oxide layer of the MOSFET. GS V is the gate-source voltage of the MOSFET. TN (or V) TP ) represents the threshold voltage of the MOSFET.

[0021] Applying Kirchhoff's current law to node ② of the OTA module's tail current, we can obtain:

[0022] ,

[0023] Among them I S The drain current of the tail current transistor M8 is i. D6 i D7 These are the drain currents of the differential pair transistors M6 and M7, respectively. Since M6 and M7 are a perfectly matched differential input pair, their drain currents are equal, i.e.:

[0024] ,

[0025] Substituting the above equation into the transconductance expression, we obtain the transconductance g of the differential pair transistors M6 and M7. m6 g m7 The expression is as follows:

[0026] ,

[0027] The derivation of the transconductance expression for the five-transistor OTA module used in this invention is based on the following operating conditions: all MOS transistors operate in the saturation region; the structures and parameters of PMOS transistors M4 and M5 are perfectly matched, forming a 1:1 current mirror; the structures and parameters of NMOS transistors M6 and M7 are perfectly matched, forming a symmetrical differential input pair. For M6, the gate is connected to a single-ended input voltage signal V. in The input configuration of M7 with its gate grounded, and the single-ended input signal V of the differential amplifier circuit. in This can be equivalent to: the input signal at the non-inverting input terminal of the differential pair transistor is V. in / 2, the inverting input terminal receives a signal of -V in / 2. That is, the gate input of M6 is V. in / 2, resulting in a current change of Δi D6That is, the change in current Δi across M4 D4 =Δi D6 M7 gate input is -V in / 2, resulting in a current change of Δi D7 Based on the current mirror principle, the current change at the drain of M4 will be replicated 1:1 to the drain of M5, i.e., Δi D5 =Δi D4 Therefore, the current transformation across M4 caused by the gate input voltage of M6 will be replicated across M5. Thus, applying Kirchhoff's current law to the output node of the OTA module (i.e., the drain connection point of M5 and M7) yields the output current I. OUT The expression is:

[0028] ,

[0029] ,

[0030] Therefore, it can be concluded that in the five-transistor OTA module of the present invention, when the differential pair transistors and the current mirror meet the matching condition, the total transconductance of the OTA module is equal to the transconductance of a single MOS transistor in the differential input pair, and the following expression can be obtained:

[0031] ,

[0032] Applying Kirchhoff's current law to the integral control node C yields the following:

[0033] ,

[0034] Therefore, the equivalent transconductance G of the current multiplexing structure formed by M1 and M2 m2 It can be represented as:

[0035] ,

[0036] The MOS capacitor composed of M3 controls the charging and discharging current I. C Integration is performed, therefore the voltage V at the integral control node C is... C The expression is:

[0037] ,

[0038] in C P Let be the capacitance value of the MOS capacitor. We can obtain:

[0039] ,

[0040] ,

[0041] As can be seen from the above equation, the first term of the proposed memristor derivative expression is the linear time-invariant part that determines the initial state of the memristor, and the second term is the linear time-varying part responsible for generating the hysteresis loop and producing the memory effect. Therefore, the proposed memristor circuit is essentially a flux-controlled memristor analog circuit, which possesses the memory characteristics of a memristor.

[0042] In addition, when the substrate of MOSFET M8 is not connected to the source, but instead uses forward substrate biasing technology, its threshold voltage V is set by an external bias voltage. TH8 At that time, the first term of the derivative function expression can achieve parametric electrical tuning.

[0043] When performing frequency response analysis, the sinusoidal voltage signal V m When sin(ωt) is input to the input terminal of the memristor circuit, the corresponding input magnetic flux can be expressed as:

[0044] ,

[0045] Substituting the above equation into formula

[0040] , the memristor circuit's memderivative function expression can be rewritten as:

[0046] ,

[0047] As can be seen, the memory effect of a memristor can be obtained using the capacitor of a MOSFET, and the memristor also exhibits frequency dependence. When the memristor's derivative function increases with frequency and capacitance value, the memristor will also exhibit resistive characteristics. Attached Figure Description

[0048] Figure 1 This is an analog circuit diagram of an easily integrated all-MOS structure memristor.

[0049] Figure 2 This is a graph showing the hysteresis loop characteristics of signals at different frequencies with a fixed sinusoidal voltage signal amplitude.

[0050] Figure 3 This is a graph showing the hysteresis loop characteristics of signals with different amplitudes at a fixed sinusoidal voltage signal frequency.

[0051] Figure 4 This is a graph showing the hysteresis loop characteristics of signals at different frequencies under a fixed square wave voltage signal amplitude.

[0052] Figure 5 This is a graph showing the hysteresis loop characteristics of signals with different amplitudes at a fixed square wave voltage signal frequency. Detailed Implementation

[0053] To make the technical solution, objectives, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0054] like Figure 1 As shown, this invention proposes an easily integrated all-MOS structure memristor analog circuit. This memristor circuit consists of eight MOS transistors: M1, M3, M4, and M5 are PMOS transistors, and M2, M6, M7, and M8 are NMOS transistors. The memristor circuit is divided into two functional modules: a first-stage current-multiplexing integrator module and a second-stage operational transconductance amplifier module. M1-M3 constitute the first-stage current-multiplexing integrator module, where M1 and M2 form a single-ended input, single-ended output current-multiplexed structure, and M3 acts as a MOS transistor capacitor to achieve the integration function. M4-M8 constitute the second-stage operational transconductance amplifier module, where M4 and M5 form a completely symmetrical current mirror structure, M6 and M7 are a differential input pair with identical structure and parameters, and M8 is the tail current source.

[0055] The first-stage current multiplexing integrator module consists of PMOS transistors M1 and M3 and an NMOS transistor M2. It is used to convert the input voltage to the integration control voltage and to memorize the historical state of the input voltage signal. The input voltage signal V... in The gates of MOSFETs M1 and M2 are connected together and denoted as node ①, serving as the signal input terminal of the proposed memristor circuit. The input voltage signal V... in On one hand, it is input to the gates of M1 and M2 in the current multiplexing structure, and on the other hand, it is also input to the gate of M6 in the operational transconductance amplifier module. The source of M1 is connected to the positive power supply voltage V. DD The source of M2 is connected to the negative power supply voltage V. SS The drains of M1 and M2 are connected to the gate of the MOS transistor capacitor M3, denoted as node C, and then connected to the gate of transistor M8 in the operational transconductance amplifier module. The drain and source of PMOS transistor M3 are both grounded.

[0056] The second-stage operational transconductance amplifier module is the module that implements the resistive switching characteristic of the memristor circuit. It consists of PMOS transistors M4 and M5, and NMOS transistors M6, M7, and M8. The sources of M4 and M5 are both connected to a positive power supply voltage V. DD The gates of M4 and M5 are connected together and then connected to the drain of M4, forming a completely symmetrical 1:1 current mirror structure. M6 and M7 are a differential input pair with identical structure and parameters. The gate of M6 is connected to the input voltage signal V of the memristor circuit. in The drain of M6 is connected to the drain of M4; the gate of M7 is grounded, and the drain of M7 is connected to the drain of M5, serving as the output node of the memristor circuit. This output node is connected to the input node ① of the memristor circuit. M8 serves as the tail current source of the operational transconductance amplifier module. The drain of M8 is connected to the sources of M6 and M7, and the source of M8 is connected to the negative power supply voltage V. SSThe gate of M8 is connected to node C, and receives the control voltage V output from the first-stage current multiplexing integrator module. C .

[0057] To verify the rationality of the aforementioned theoretical derivation of the memristor circuit, the memristor characteristics of the circuit proposed in this invention are simulated and verified. Assume the input signal is a sinusoidal voltage signal or a square wave voltage signal, and the positive power supply voltage is set to V. DD =+5V, negative power supply voltage is set to V SS =-5V, the hysteresis loop characteristics of the memristor are simulated and analyzed below.

[0058] With a fixed input sinusoidal signal amplitude of 2V, and input signal frequencies set to 1000Hz, 2000Hz, 3000Hz, and 10000Hz respectively, plot the input current signal I. in With input voltage signal V in Relationship curves, such as Figure 2 As shown in the figure. The simulation results show that under different frequency signals, the input current signal I... in With input voltage signal V in The resulting volt-ampere characteristic curves are all typical figure-eight hysteresis loop characteristic curves; with a constant input amplitude, the area of ​​the hysteresis loop gradually decreases as the input signal frequency increases. The simulation results are consistent with the law revealed by the derivation expression in the theoretical derivation.

[0059] With the frequency of the input sinusoidal signal fixed at 1000Hz, and the amplitude of the input signal set to 1.0V, 1.5V, 1.8V, and 2.0V respectively, plot the input current signal I. in With input voltage signal V in Relationship curves, such as Figure 3 As shown in the figure. The simulation results show that under different amplitude signals, the input current signal I... in With input voltage signal V in The resulting volt-ampere characteristic curves are all typical figure-eight hysteresis loop characteristic curves. With the input frequency remaining constant, the area of ​​the hysteresis loop gradually increases as the amplitude of the input signal increases, and the simulation results are consistent with the theoretical derivation.

[0060] With a fixed input square wave signal amplitude of 1V, and input signal frequencies set to 1000Hz, 5000Hz, and 20000Hz respectively, plot the input current signal I. in With input voltage signal V in Relationship curves, such as Figure 4As shown in the figure. The simulation results show that under different frequency signals, since the input signal is a square wave, the signal amplitude changes abruptly. Therefore, the simulated volt-ampere characteristic curve is no longer smooth and continuous, but it still forms an "8"-shaped hysteresis loop characteristic curve. Furthermore, with the input amplitude remaining constant, the area of ​​the hysteresis loop gradually decreases as the input signal frequency increases.

[0061] With the frequency of the input square wave signal fixed at 1000Hz, and the input signal amplitude set to 0.6V, 0.8V, and 1.0V respectively, plot the input current signal I. in With input voltage signal V in The relationship curve, the result is as follows Figure 5 As shown in the figure. The simulation results show that under different amplitude signals, the simulated volt-ampere characteristic curves all form a figure-eight hysteresis loop characteristic curve. Furthermore, with the input frequency remaining constant, the area of ​​the hysteresis loop gradually increases as the amplitude of the input signal increases. The simulation results are consistent with the theoretical derivation.

Claims

1. An easily integrated all-MOS structure memristor analog circuit, characterized in that, The proposed memristor analog circuit is divided into two functional modules: a first-stage current multiplexing integrator module and a second-stage operational transconductance amplifier module. It consists of eight MOS transistors: M1, M3, M4, and M5 are PMOS transistors, and M2, M6, M7, and M8 are NMOS transistors. M1-M3 constitute the first-stage current multiplexing integrator module, where M1 and M2 form a single-ended input and single-ended output current multiplexing structure, and M3 acts as a capacitor for the MOS transistors to achieve the integration function. M4-M8 constitute the second-stage operational transconductance amplifier module, where M4 and M5 form a completely symmetrical current mirror structure, M6 and M7 are differential input pairs with completely identical structure and parameters, and M8 is the tail current source.

2. The easily integrated all-MOS structure memristor analog circuit according to claim 1, characterized in that, The first-stage current multiplexing integrator module consists of PMOS transistors M1 and M3 and an NMOS transistor M2. It is used to convert the input voltage to the integration control voltage and to memorize the historical state of the input voltage signal; the input voltage signal V... in The gates of MOSFETs M1 and M2 are connected together and denoted as node ①, serving as the signal input terminal of the proposed memristor analog circuit; the input voltage signal V in It is also connected to the gate of M6 in the operational transconductance amplifier module; the source of M1 is connected to the positive power supply voltage V. DD The source of M2 is connected to the negative power supply voltage V. SS The drains of M1 and M2 are connected to the gate of the MOS transistor capacitor M3, denoted as node C, and connected to the gate of the operational transconductance amplifier module M8; the drain and source of the PMOS transistor M3 are both grounded.

3. The easily integrated all-MOS structure memristor analog circuit according to claim 1, characterized in that, The second-stage operational transconductance amplifier module is the module for realizing the resistive switching characteristic of the memristor analog circuit. It consists of PMOS transistors M4 and M5, and NMOS transistors M6, M7, and M8; the sources of M4 and M5 are both connected to the positive power supply voltage V. DD The gates of M4 and M5 are connected together and then connected to the drain of M4, forming a completely symmetrical current mirror structure; M6 and M7 are a differential input pair with identical structure and parameters, and the gate of M6 is connected to the input voltage signal V of the memristor analog circuit. in The drain of M6 is connected to the drain of M4; the gate of M7 is grounded, and the drain of M7 is connected to the drain of M5 and serves as the output node of the memristor analog circuit. This output node is connected to the input node ① of the memristor analog circuit; M8 serves as the tail current source of the operational transconductance amplifier module, and the drain of M8 is connected to the source of M6 and M7. The source of M8 is connected to the negative power supply voltage V. SS The gate of M8 is connected to node C, and receives the control voltage V output from the first-stage current multiplexing integrator module. C .

4. The easily integrated all-MOS structure memristor analog circuit according to claim 1, characterized in that, The current multiplexing structure composed of M1 and M2 will convert the input voltage signal V in Converted to current signal I C The current signal I C The charging and discharging integration operation is performed by using transistor M3 as a capacitor in a MOSFET, generating a signal V at node C that is analogous to the input voltage signal. in Control voltage V that is proportional to time integral C The control voltage V C The system memorizes the historical state of the input voltage signal; simultaneously, the control voltage is input to the gate of M8 in the second-stage operational transconductance amplifier module. By modulating the tail current source in the operational transconductance amplifier module, the total input transconductance of the operational transconductance amplifier module is changed, thereby dynamically controlling the equivalent memconductance of the proposed memristor analog circuit, ultimately causing the input current signal I of the memristor analog circuit to... in With input voltage signal V in The resistance-change relationship between them exhibits a nonlinear resistance-change relationship that varies with the historical state of the input voltage signal, thereby realizing the resistance-change memory characteristic of the memristor analog circuit.

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