Method, device and equipment for suppressing magnetic bias and storage medium
By sampling multiple times during the switching cycle of a single-stage converter and dynamically compensating for the duty cycle, a bias detection signal is generated and the duty cycle of the switching transistor is adjusted, thus solving the problem of bias in magnetic components and improving the stability and energy transfer efficiency of the single-stage converter.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU INOSA UNITED POWER SYST CO LTD
- Filing Date
- 2026-01-19
- Publication Date
- 2026-06-02
Smart Images
Figure CN122137214A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronics technology, and in particular to a method, apparatus, device and storage medium for suppressing bias magnetization. Background Technology
[0002] Electric vehicle on-board charging systems typically include a single-stage converter. This converter is used to convert electrical energy (e.g., converting high voltage to low voltage, AC to DC, etc.). In practice, the magnetic components (transformers) in a single-stage converter are susceptible to the DC component in the circuit, causing core bias, which leads to core saturation, increased losses, and in severe cases, overcurrent damage to the switching transistors, significantly reducing the converter's reliability and lifespan.
[0003] In related technologies, a DC blocking capacitor is typically connected in series in the magnetic component circuit. This capacitor's characteristic of "blocking DC and conducting high-frequency AC" filters out the DC component in the magnetic component circuit, thus suppressing core bias. However, in a single-stage converter, the electrical circuit of the magnetic component simultaneously contains high-frequency AC components generated by a dual active bridge (DAB) converter and low-frequency AC components generated by a power factor correction (PFC) module. The DC blocking capacitor impedes the low-frequency AC components, and in doing so, it disrupts the magnetic field balance of the magnetic component, leading to core bias.
[0004] As can be seen from the above, in related technologies, the effect of suppressing bias magnetism by using DC blocking capacitors is poor. Summary of the Invention
[0005] This application provides a method, apparatus, device, and storage medium for suppressing bias magnetism, which can achieve precise suppression of bias magnetism in the magnetic components of a single-stage converter while ensuring the smooth transmission of low-frequency AC components in the PFC module, maintain the magnetic field balance of the magnetic components, and improve the bias magnetism suppression effect and the energy transfer efficiency of the single-stage converter.
[0006] In a first aspect, this application provides a method for suppressing magnetic bias, applied to a single-stage converter, to prevent magnetic elements in the single-stage converter from becoming magnetically biased, the method comprising:
[0007] Within a single switching cycle, the bus capacitor current is sampled at least twice, with a time interval of half a switching cycle between the two samplings;
[0008] A bias detection signal is obtained based on the sampling current from at least two samplings; the bias detection signal is used to reflect the degree of bias of the magnetic elements in the single-stage converter.
[0009] A duty cycle compensation signal is generated based on the bias detection signal, and the duty cycle of the primary-side switching transistor is adjusted based on the duty cycle compensation signal to suppress the bias of the magnetic element.
[0010] In one possible implementation, obtaining the bias detection signal based on the at least two sampled currents includes:
[0011] The difference between the bus capacitance currents obtained from the two samplings is used to obtain the bias detection signal.
[0012] In one possible implementation, sampling the bus capacitor current at least twice within a single switching cycle includes:
[0013] In the first half of a single switching cycle, the bus capacitor current is sampled once;
[0014] After one sampling, the bus capacitor current is sampled again after half of the switching cycle.
[0015] In one possible implementation, generating the duty cycle compensation signal based on the bias detection signal includes:
[0016] The bias detection signal is subjected to proportional-integral processing to obtain the duty cycle compensation signal.
[0017] In one possible implementation, the primary-side switch includes a first switch and a second switch located in the first bridge arm, and a third switch and a fourth switch located in the second bridge arm; adjusting the duty cycle of the primary-side switch includes:
[0018] Adjust the duty cycle of the first switch, the second switch, the third switch, and the fourth switch; wherein the first switch and the fourth switch are in the same switching state, and the second switch and the third switch are in the same switching state.
[0019] In one possible implementation, adjusting the duty cycle of the first switch, the second switch, the third switch, and the fourth switch includes:
[0020] When the duty cycle compensation signal is greater than a preset value, the duty cycle of the first switch and the fourth switch is reduced, and the duty cycle of the second switch and the third switch is increased.
[0021] When the duty cycle compensation signal is less than or equal to the preset value, the duty cycle of the first switch and the fourth switch is increased, and the duty cycle of the second switch and the third switch is decreased.
[0022] In one possible implementation, adjusting the duty cycle of the primary-side switch according to the duty cycle compensation signal includes:
[0023] Based on the duty cycle compensation signal, update the register parameters used to provide the switch drive signal for the primary-side switch to adjust the duty cycle of the primary-side switch.
[0024] Secondly, this application provides a bias magnetization suppression device, comprising:
[0025] The sampling module is used to sample the bus capacitor current at least twice within a single switching cycle;
[0026] The processing module is used to obtain a bias detection signal based on the sampling current from at least two samplings; the bias detection signal is used to reflect the degree of bias of the magnetic elements in the single-stage converter.
[0027] The adjustment module is used to generate a duty cycle compensation signal based on the bias detection signal, and adjust the duty cycle of the primary-side switching transistor according to the duty cycle compensation signal to suppress the bias of the magnetic element.
[0028] Thirdly, this application provides a controller, including: a memory and a processor;
[0029] The memory stores computer-executed instructions;
[0030] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.
[0031] Fourthly, this application provides a vehicle, including: a vehicle body, and a controller as described in the third aspect.
[0032] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible embodiments of the first aspect.
[0033] In a sixth aspect, this application provides a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.
[0034] This application provides a method, apparatus, device, and storage medium for suppressing magnetic bias. The method includes sampling the bus capacitor current at least twice within a single switching cycle, obtaining a magnetic bias detection signal based on the sampled current, generating a duty cycle compensation signal based on this signal, and adjusting the duty cycle of the primary-side switch transistor to suppress magnetic bias in the magnetic components. In this process, by using software control logic for multiple sampling and dynamic compensation within the switching cycle, the traditional DC blocking capacitor hardware solution is replaced, fundamentally solving the core magnetic bias problem without altering the topology of the single-stage converter, significantly improving the operational stability and energy transfer efficiency of the single-stage converter. Attached Figure Description
[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0036] Figure 1 A schematic diagram illustrating the application scenarios provided in the embodiments of this application;
[0037] Figure 2 A schematic flowchart of Embodiment 1 of the bias magnetization suppression method provided in this application;
[0038] Figure 3 This is a schematic diagram showing the location of the bus capacitor current sampling points provided in the embodiments of this application;
[0039] Figure 4 A schematic flowchart of Embodiment 2 of the bias magnetization suppression method provided in this application;
[0040] Figure 5 This is a bus capacitor current sampling time diagram provided in an embodiment of this application;
[0041] Figure 6 A flowchart illustrating an example of a bias magnetization suppression method provided in this application.
[0042] Figure 7 This is a schematic diagram of the bias suppression device provided in the embodiments of this application;
[0043] Figure 8 This is a schematic diagram of the controller provided in an embodiment of this application.
[0044] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0046] With the rapid iteration of automotive power electronics technology, new energy vehicles are placing increasingly stringent requirements on the safety, power density, and overall performance of on-board power systems. Single-stage converters, with their irreplaceable advantages in electrical isolation, voltage level adaptation, and safety protection, have become a key component of core components such as on-board chargers and power battery management systems, and are widely used in the power transmission links of various new energy vehicles.
[0047] In practical applications, the magnetic components of a single-stage converter are highly susceptible to the influence of the DC component in the circuit, resulting in core bias. This phenomenon not only leads to core saturation and increased losses, but may also cause overcurrent damage to the switching transistors, significantly reducing the reliability and lifespan of the single-stage converter.
[0048] In related technologies, a DC blocking capacitor is typically connected in series in the electrical circuit of a single-stage converter. The DC blocking capacitor's characteristic of "blocking DC and conducting high-frequency AC" filters out the DC component in the magnetic component circuit, thus preventing core magnetization. However, since the topology of a single-stage converter simultaneously contains high-frequency AC components generated by the DAB converter and low-frequency AC components generated by the PFC module, directly using a DC blocking capacitor will disrupt the magnetic field balance of the magnetic components by hindering the low-frequency AC components. This will ultimately lead to magnetic core magnetization, severely affecting the operational stability of the single-stage converter.
[0049] Specifically, the capacitive reactance of the DC blocking capacitor is inversely proportional to the current frequency. For the high-frequency AC components generated by the DAB converter, the capacitive reactance of the DC blocking capacitor is extremely small, allowing for smooth conduction. However, for the low-frequency AC components generated by the PFC module, its capacitive reactance increases significantly, creating a noticeable obstacle. Due to factors such as the on-state voltage drop of the single-stage converter's switching transistors and the nonlinearity of the circuit impedance, the low-frequency AC components of the PFC inherently exhibit a slight asymmetry between the positive and negative half-cycles. When this current flows through the high-capacitive-reactance DC blocking capacitor, the capacitor voltage drop amplifies this asymmetry, causing an imbalance in the positive and negative half-cycle amplitudes of the low-frequency current flowing through the magnetic components. This unbalanced current leads to inconsistent forward and reverse magnetization of the magnetic core, disrupting the inherent magnetic field balance of the core and ultimately resulting in core bias.
[0050] Furthermore, the significant obstruction of low-frequency AC components by the DC blocking capacitor directly leads to the inefficient transfer of low-frequency energy from the PFC module to subsequent circuits, resulting in increased energy transmission link losses and significantly reducing the energy transfer efficiency of the single-stage converter.
[0051] To address the aforementioned issues, the inventors considered constructing a bias suppression mechanism that combines real-time performance and accuracy through a collaborative design of multiple samplings within the switching cycle and dynamic duty cycle compensation, thereby achieving the dual goals of core bias suppression and efficient energy transfer. Based on this, after numerous experiments, the inventors discovered that the bus capacitor current can be sampled at least twice within a single switching cycle, with a half-cycle interval between the two samplings. Based on the sampled currents from these at least two samplings, a bias detection signal reflecting the degree of magnetic bias in the single-stage converter is calculated. Finally, a corresponding duty cycle compensation signal is generated based on this bias detection signal. The duty cycle of the primary-side switching transistor is dynamically adjusted according to this compensation signal, thereby suppressing core bias by balancing the excitation current of the magnetic components and offsetting the influence of the DC component. In the above process, the bias state is sensed in real time through multiple samplings within a single switching cycle. Active bias suppression is achieved through dynamic duty cycle compensation, eliminating the need for a series DC blocking capacitor. This avoids the obstruction of low-frequency AC components by the DC blocking capacitor, ensuring efficient energy transfer from the PFC module. Furthermore, it avoids the risks of core saturation and overcurrent damage to the switching transistor, thus improving the operational stability of the single-stage converter. Based on this, this application proposes a bias suppression method to improve the suppression accuracy and energy transfer efficiency of core bias in a single-stage converter, preventing bias in the magnetic components of the single-stage converter.
[0052] Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. Please refer to [link / reference]. Figure 1 This application scenario typically uses on-board charging systems for new energy vehicles as an example, mainly comprising an AC power grid, a single-stage converter, and a power battery. The AC power grid serves as the energy input side, providing AC power to the on-board charging system; the single-stage converter is the core power conversion unit of this link, responsible for AC-to-DC rectification, voltage level adaptation, and electrical isolation; and the power battery is the energy receiving end, used to store the converted electrical energy and provide power output for the new energy vehicle.
[0053] In actual charging, the electrical energy from the AC grid is first input into the single-stage converter. After the coordinated action of its internal PFC module, DAB converter, and magnetic components, the energy is converted and finally stably transmitted to the power battery, achieving efficient charging. However, the problem of core bias occurs in the magnetic component circuit of the single-stage converter, and its suppression effect directly affects the stability and efficiency of energy transmission.
[0054] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.
[0055] Figure 2 This is a schematic flowchart illustrating an embodiment of the bias suppression method provided in this application. Please refer to [link / reference]. Figure 2 The method includes:
[0056] S201. The bus capacitor current is sampled at least twice during a single switching cycle.
[0057] The execution entity in this application embodiment can be a controller or a magnetic bias suppression device disposed in the controller. The magnetic bias suppression device can be implemented by software or by a combination of software and hardware. The magnetic bias suppression device can be a processor in the controller. For ease of understanding, the technical solution of this application will be described below using a controller as an example.
[0058] In this step, the controller can sample the bus capacitor current at least twice within a single switching cycle of the single-stage converter to obtain the corresponding current sample value.
[0059] In one specific implementation, based on the second harmonic characteristic of the bus capacitor current in a single-stage converter (the oscillation period of the bus current is twice the switching period), the bus capacitor current can be sampled once in the first half of a single switching cycle; after the first sampling, the bus capacitor current can be sampled again at the same position after half a switching cycle.
[0060] Figure 3 This is a schematic diagram showing the location of the bus capacitor current sampling points provided in an embodiment of this application. Please refer to... Figure 3 The main circuit of the single-stage converter includes multiple sets of switching bridge arms, AC side filter, DAB inductor, transformer (T), bus capacitor (Cbus), DC side filter, AC power supply (Vac) connected to the input side, and power battery voltage source (Vbatt) connected to the output side.
[0061] The multiple switching transistor bridge arms include four high-frequency fast switching transistor bridge arms (Q1 / Q2, Q3 / Q4, Q5 / Q6, Q7 / Q8) and one power frequency slow switching transistor bridge arm (Q9 / Q10). Each switching transistor bridge arm is connected in parallel with a freewheeling diode (e.g., Q1 is connected in parallel with diode D1, Q2 with diode D2, and so on up to Q10 with diode D10). The AC side filter includes inductor Lac and capacitor Cac. The DC side filter includes inductor Ldc and capacitor Cdc. The DAB inductors include inductor L1 and inductor L2.
[0062] Accordingly, the components of the DAB converter may include four sets of high-frequency fast switching bridge arms (Q1 / Q2, Q3 / Q4, Q5 / Q6, Q7 / Q8) and their parallel freewheeling diodes (D1~D8), DAB inductors (L1, L2) and transformers (T); the components of the PFC module may include one set of power frequency slow switching bridge arms (Q9 / Q10) and their parallel freewheeling diodes (D9, D10), AC side filters (Lac, Cac), and DC side filters (Ldc, Cdc).
[0063] The bus capacitor current sampling point (Ibus) is set on the connection branch of the bus capacitor (Cbus). It can sample the bus capacitor current at least twice in a single switching cycle, providing raw data for subsequent bias detection.
[0064] For example, if the switching period of a single-stage converter is Ts, the bus capacitor current can be sampled for the first time in the first half of the switching period Ts to obtain the current value I1. After an interval of half a switching period, the bus capacitor current can be sampled for the second time in the second half of the switching period to obtain the current value I2.
[0065] S202. Obtain the bias detection signal based on the sampling current from at least two samplings.
[0066] In this step, based on the collected multiple sets of bus capacitor current sampling values, a bias detection signal reflecting the degree of bias of the magnetic element can be calculated through preset calculation logic.
[0067] Among them, magnetic components refer to the core components in a single-stage converter that realize power conversion and electrical isolation, specifically including the transformer (T), whose magnetic core is the key carrier of energy transfer, and the bias magnetization phenomenon occurs on the magnetic core of the transformer.
[0068] In one specific implementation, the difference between the bus capacitance currents obtained from two samplings can be calculated to obtain the bias detection signal.
[0069] For example, the difference between current values I1 and I2 can be calculated, and the result ΔI is the bias detection signal. When the value of ΔI is zero, it indicates that the excitation current of the magnetic element in the single-stage converter is symmetrical in the positive and negative half-cycles, and the magnetic core is in a balanced state without bias. When ΔI is not zero, it indicates that there is an amplitude imbalance in the positive and negative half-cycles of the current. The larger the absolute value of the difference, the more severe the bias of the magnetic element.
[0070] S203. Generate a duty cycle compensation signal based on the bias detection signal, and adjust the duty cycle of the primary-side switching transistor according to the duty cycle compensation signal to suppress the bias of the magnetic element.
[0071] In this step, the controller can perform proportional-integral processing on the bias detection signal to obtain a duty cycle compensation signal. Based on the duty cycle compensation signal, the duty cycle of the primary-side switching transistor is adjusted to suppress the bias of the magnetic components.
[0072] For primary-side switching transistors, it can include Figure 3 The first switch Q1 and the second switch Q2 are located in the first bridge arm of the single-stage converter, and the third switch Q3 and the fourth switch Q4 are located in the second bridge arm. The switching states of the first switch Q1 and the fourth switch Q4 are consistent, and the switching states of the second switch Q2 and the third switch Q3 are consistent, thus forming a symmetrical switch driving logic.
[0073] In one specific implementation, the controller can adjust the duty cycles of the two sets of switches in opposite directions based on the magnitude of the duty cycle compensation signal: when the duty cycle compensation signal is greater than a preset value, the duty cycles of the first switch Q1 and the fourth switch Q4 are decreased, while the duty cycles of the second switch Q2 and the third switch Q3 are increased; when the duty cycle compensation signal is less than or equal to the preset value, the duty cycles of the first switch Q1 and the fourth switch Q4 are increased, while the duty cycles of the second switch Q2 and the third switch Q3 are decreased. Specifically, the controller can update the register parameters used to output the primary-side switch drive signal based on the duty cycle compensation signal. By adjusting the pulse width of the pulse width modulation (PWM) wave, the controller changes the on-time of the switch, thereby balancing the excitation current of the magnetic components, counteracting the influence of the DC component, and suppressing core bias.
[0074] In this embodiment, the bus capacitor current can be sampled at least twice within a single switching cycle of the single-stage converter. Based on the sampled current from these two samplings, a magnetization detection signal reflecting the degree of magnetization of the magnetic components is obtained. Then, a duty cycle compensation signal is generated based on this magnetization detection signal to adjust the duty cycle of the primary-side switch to suppress magnetization of the magnetic components. In this process, by using software control logic for multiple sampling, magnetization signal detection, and dynamic duty cycle compensation within the switching cycle, the DC blocking capacitor hardware solution is replaced, effectively suppressing magnetization of the magnetic components at its source. This effectively solves problems such as core saturation and overcurrent damage to the switch, significantly improving the operational stability and energy transfer efficiency of the single-stage converter.
[0075] exist Figure 2 Based on the illustrated embodiment, the following, in conjunction with Figure 4 The above-mentioned method for suppressing bias magnetism will be explained in further detail.
[0076] Figure 4 This is a schematic flowchart illustrating Embodiment 2 of the bias suppression method provided in this application. Please refer to... Figure 4 The method includes:
[0077] S401. In the first half of a single switching cycle, the bus capacitor current is sampled once.
[0078] In this step, the controller can synchronize the switching cycle clock signal of the single-stage converter, locate the start time of a single switching cycle, and then trigger the sampling action in the first half of the cycle.
[0079] Figure 5 This is a bus capacitor current sampling time diagram provided for an embodiment of this application. Please refer to... Figure 5 The total duration of the switching cycle is Ts, with the first half of the cycle being Ts / 2. The first sampling time is... The first sampling occurs within the first half of the cycle; the second sampling occurs within the second half of the cycle, specifically by superimposing the duration of the first half of the cycle. The corresponding time period, the interval between two samplings is strictly half a switching cycle, which can accurately capture the characteristics of the current during symmetrical time periods within the cycle, and the interval between two samplings is strictly half a switching cycle.
[0080] For example, if the switching period Ts of a single-stage converter is 20 microseconds (μs) and the corresponding switching frequency is 50 kilohertz (kHz), then the first half of a single switching period Ts is a time interval of 0~10μs. The controller can operate within this time interval... The bus capacitor current is sampled for the first time at a time (e.g., 3μs) to obtain the sampled current value I1. The value of current I1 can be 2A.
[0081] S402. After one sampling, the bus capacitor current is sampled again after half a switching cycle.
[0082] In this step, the controller can resample the bus capacitor current based on the timing of the first sampling, after a delay of half a switching cycle.
[0083] For example, the first sampling time The sampling time is 3μs, and after an interval of half a switching cycle (10μs), the sampling time is 13μs, which is located in the second half of the switching cycle. The controller can perform a second sampling of the bus capacitor current at 13μs to obtain the sampled current value I2. The value of current I2 can be 1.8A.
[0084] S403. Calculate the difference between the bus capacitance currents obtained from the two samplings to obtain the bias detection signal.
[0085] In this step, the controller can perform a difference calculation on the bus capacitor current values obtained from the two samplings, and use the difference in the symmetrical characteristics of the current to convert it into a bias detection signal that reflects the degree of bias of the magnetic components in the single-stage converter.
[0086] For example, the difference between the current value I1 and the current value I2 can be calculated to obtain the bias detection signal ΔI as 0.1A.
[0087] S404. Perform proportional-integral processing on the bias detection signal to obtain the duty cycle compensation signal.
[0088] In this step, the controller can use its built-in proportional-integral (PI) adjustment module to calculate the bias detection signal and generate an accurate duty cycle compensation signal.
[0089] For example, a bias detection signal ΔI of 0.1A can be input into the PI adjustment module to calculate the duty cycle compensation signal ΔD of 0.06.
[0090] S405. Based on the duty cycle compensation signal, update the register parameters used to provide the switch drive signal for the primary-side switch, so as to adjust the duty cycle of the primary-side switch and suppress the bias magnetization of the magnetic components.
[0091] In this step, the register parameters corresponding to the primary-side switch can be adjusted according to the value of the duty cycle compensation signal, thereby changing the duty cycle of the switch drive signal, balancing the excitation current of the magnetic component, and suppressing the bias of the magnetic component.
[0092] Specifically, the primary-side switching transistors may include a first switch Q1 and a second switch Q2 located in the first bridge arm, and a third switch Q3 and a fourth switch Q4 located in the second bridge arm; adjusting the duty cycle of the primary-side switching transistors may specifically include adjusting the duty cycle of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4; wherein the switching states of the first switch Q1 and the fourth switch Q4 are the same, and the switching states of the second switch Q2 and the third switch Q3 are the same.
[0093] In one optional implementation, when the duty cycle compensation signal is greater than a preset value, the duty cycle of the first switch Q1 and the fourth switch Q4 can be reduced, and the duty cycle of the second switch Q2 and the third switch Q3 can be increased; when the duty cycle compensation signal is less than or equal to the preset value, the duty cycle of the first switch Q1 and the fourth switch Q4 can be increased, and the duty cycle of the second switch Q2 and the third switch Q3 can be decreased.
[0094] The preset value can be set according to actual needs. For example, the preset value can be set to 0.
[0095] For example, if the duty cycle compensation signal ΔD is 0.06, which is greater than the preset value of 0, the duty cycle of the first switch Q1 and the fourth switch Q4 can be reduced from the initial value of 0.5 to 0.44, while the duty cycle of the second switch Q2 and the third switch Q3 can be increased from 0.5 to 0.56. By adjusting the on-time of the switches, the excitation current can be balanced, thereby achieving magnetic bias suppression.
[0096] In this embodiment, the bus capacitor current can be sampled once during the first half of a single switching cycle, and then sampled again after a half-cycle interval. The difference between the two sampled currents is used to obtain the bias detection signal, which is then processed by proportional-integral (PI) to generate a duty cycle compensation signal. Finally, the register parameters are updated to adjust the duty cycle of the primary-side switch. In the above process, by increasing the sampling of the bus capacitor current and matching the second harmonic characteristic of the bus capacitor current to complete symmetrical sampling within the switching cycle, and combining the difference operation with PI closed-loop control to generate the duty cycle compensation signal, the traditional DC blocking capacitor hardware solution is replaced. This method can accurately capture bias characteristics without additional hardware, avoiding the problem of DC blocking capacitors hindering low-frequency AC components and ensuring efficient energy transmission of the PFC module. It can also balance the excitation current by dynamically adjusting the duty cycle of the primary-side switch, suppressing the bias of magnetic components from the source and preventing magnetic saturation. At the same time, it avoids the risk of overcurrent damage to the switch, significantly improving the operational stability and energy transfer efficiency of the single-stage converter.
[0097] Figure 6 This is a flowchart illustrating an example of a bias suppression method provided in this application. Please refer to... Figure 6 ,include:
[0098] S601, Read the sampled data.
[0099] Specifically, after the single-stage converter enters the main interrupt, sampled data can be read, including two sampled current values of the bus capacitor within the same switching cycle. The main interrupt refers to a periodic interrupt event that is precisely synchronized with the switching cycle of the single-stage converter.
[0100] S602, Execute loop control and obtain duty cycle compensation signal.
[0101] Specifically, the difference between the bus capacitance currents obtained from the two samplings can be calculated to obtain the bias detection signal. The bias detection signal can then be processed by proportional-integral processing to obtain the duty cycle compensation signal.
[0102] S603. Adjust the duty cycle of the primary-side switching transistor according to the duty cycle compensation signal.
[0103] Specifically, it can be based on the operating logic that "Q1 / Q4 is turned on in the first half of a switching cycle and Q2 / Q3 is turned on in the second half of the cycle"; when the duty cycle compensation signal is greater than 0, the duty cycle of Q1 and Q4 is reduced and the duty cycle of Q2 and Q3 is increased; when the duty cycle compensation signal is less than or equal to 0, the duty cycle of Q2 and Q3 is reduced and the duty cycle of Q1 and Q4 is increased.
[0104] It should be noted that if the conduction logic within a switching cycle is that Q2 / Q3 is on in the first half of the cycle and Q1 / Q4 is on in the second half of the cycle, then the corresponding duty cycle adjustment logic needs to be reversed: when the duty cycle compensation signal is greater than 0, decrease the duty cycle of Q2 and Q3 and increase the duty cycle of Q1 and Q4; when the duty cycle compensation signal is less than or equal to 0, decrease the duty cycle of Q1 and Q4 and increase the duty cycle of Q2 and Q3.
[0105] S604, Update Register and Send Wave.
[0106] Specifically, the adjusted duty cycle parameter of the primary-side switch can be written into the register to generate a PWM drive signal that matches the duty cycle. The PWM drive signal is then output to the corresponding switch. By updating the register parameters, the drive signal can be accurately output, thereby balancing the excitation current of the magnetic components and suppressing the bias phenomenon.
[0107] Optionally, the register can refer to the comparison value register integrated inside the controller, which is used to store the threshold parameter that matches the duty cycle. The updated comparison value can be used in conjunction with the preset period register parameter inside the controller to jointly determine the pulse width of the PWM drive signal and the on-time of the switching transistor.
[0108] The example of the bias suppression method provided in this application can be referred to the technical solution shown in the above embodiment for the specific execution process. The implementation principle and beneficial effects are similar, and will not be repeated here.
[0109] Figure 7 This is a schematic diagram of the bias suppression device provided in an embodiment of this application. Please refer to... Figure 7 The bias suppression device 10 includes:
[0110] The sampling module 11 is used to sample the bus capacitor current at least twice within a single switching cycle, with the time interval between the two samplings being half a switching cycle.
[0111] Processing module 12 is used to obtain a bias detection signal based on the sampling current sampled at least twice; the bias detection signal is used to reflect the degree of bias of the magnetic elements in the single-stage converter;
[0112] The adjustment module 13 is used to generate a duty cycle compensation signal based on the bias detection signal, and adjust the duty cycle of the primary-side switching transistor according to the duty cycle compensation signal to suppress the bias of the magnetic element.
[0113] The bias suppression device provided in this application embodiment can perform the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.
[0114] In one possible implementation, the processing module 12 is specifically used for:
[0115] The difference between the bus capacitance currents obtained from the two samplings is used to obtain the bias detection signal.
[0116] In one possible implementation, the sampling module 11 is specifically used for:
[0117] In the first half of a single switching cycle, the bus capacitor current is sampled once;
[0118] After one sampling, the bus capacitor current is sampled again after half a switching cycle.
[0119] In one possible implementation, the adjustment module 13 is specifically used for:
[0120] The bias detection signal is processed by proportional-integral processing to obtain the duty cycle compensation signal.
[0121] In one possible implementation, the primary-side switching transistor includes a first switch and a second switch located in the first bridge arm, and a third switch and a fourth switch located in the second bridge arm; the adjustment module 13 is specifically used for:
[0122] Adjust the duty cycle of the first, second, third, and fourth switches; wherein the first and fourth switches are in the same switching state, and the second and third switches are in the same switching state.
[0123] In one possible implementation, the adjustment module 13 is specifically used for:
[0124] When the duty cycle compensation signal is greater than the preset value, the duty cycle of the first and fourth switches is reduced, and the duty cycle of the second and third switches is increased.
[0125] When the duty cycle compensation signal is less than or equal to the preset value, the duty cycle of the first and fourth switches is increased, and the duty cycle of the second and third switches is decreased.
[0126] In one possible implementation, the adjustment module 13 is specifically used for:
[0127] Based on the duty cycle compensation signal, update the register parameters used to provide the switch drive signal for the primary-side switch to adjust the duty cycle of the primary-side switch transistor.
[0128] The bias suppression device provided in this application embodiment can perform the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.
[0129] Figure 8 This is a schematic diagram of the controller provided in an embodiment of this application. Please refer to... Figure 8 The controller 20 includes at least one processor 21 and a memory 22. Optionally, the controller 20 also includes a communication component 23. The processor 21, the memory 22, and the communication component 23 are connected via a bus 24.
[0130] In the specific implementation process, at least one processor 21 executes computer execution instructions stored in memory 22, causing at least one processor 21 to perform the above-described method.
[0131] The specific implementation process of processor 21 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0132] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0133] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0134] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0135] This application embodiment also provides a vehicle, including a vehicle body and Figure 8 The controller shown can execute the bias suppression method in the above method embodiment to prevent the magnetic elements in the single-stage converter from becoming biased.
[0136] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0137] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.
[0138] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0139] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0140] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0141] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0142] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0143] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0144] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0145] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A method for suppressing magnetic bias, applied to a single-stage converter, to prevent magnetic elements in the single-stage converter from becoming magnetically biased, characterized in that, The method includes: Within a single switching cycle, the bus capacitor current is sampled at least twice, with a time interval of half a switching cycle between the two samplings; A bias detection signal is obtained based on the sampling current from at least two samplings; the bias detection signal is used to reflect the degree of bias of the magnetic elements in the single-stage converter. A duty cycle compensation signal is generated based on the bias detection signal, and the duty cycle of the primary-side switching transistor is adjusted based on the duty cycle compensation signal to suppress the bias of the magnetic element.
2. The method according to claim 1, characterized in that, The step of obtaining the bias detection signal based on the sampling current from at least two samplings includes: The difference between the bus capacitance currents obtained from the two samplings is used to obtain the bias detection signal.
3. The method according to claim 2, characterized in that, The step of generating a duty cycle compensation signal based on the bias detection signal includes: The bias detection signal is subjected to proportional-integral processing to obtain the duty cycle compensation signal.
4. The method according to claim 2, characterized in that, The primary-side switching transistor includes a first switch and a second switch located in the first bridge arm, and a third switch and a fourth switch located in the second bridge arm; adjusting the duty cycle of the primary-side switching transistor includes: Adjust the duty cycle of the first switch, the second switch, the third switch, and the fourth switch; wherein the first switch and the fourth switch are in the same switching state, and the second switch and the third switch are in the same switching state.
5. The method according to claim 4, characterized in that, Adjusting the duty cycle of the first switch, the second switch, the third switch, and the fourth switch includes: When the duty cycle compensation signal is greater than a preset value, the duty cycle of the first switch and the fourth switch is reduced, and the duty cycle of the second switch and the third switch is increased. When the duty cycle compensation signal is less than or equal to the preset value, the duty cycle of the first switch and the fourth switch is increased, and the duty cycle of the second switch and the third switch is decreased.
6. The method according to any one of claims 1-5, characterized in that, The step of adjusting the duty cycle of the primary-side switch transistor according to the duty cycle compensation signal includes: Based on the duty cycle compensation signal, update the register parameters used to provide the switch drive signal for the primary-side switch to adjust the duty cycle of the primary-side switch.
7. A bias magnetization suppression device, characterized in that, include: The sampling module is used to sample the bus capacitor current at least twice within a single switching cycle, with the time interval between the two samplings being half a switching cycle. The processing module is used to obtain a bias detection signal based on the sampling current from at least two samplings; the bias detection signal is used to reflect the degree of bias of the magnetic elements in the single-stage converter. The adjustment module is used to generate a duty cycle compensation signal based on the bias detection signal, and adjust the duty cycle of the primary-side switching transistor according to the duty cycle compensation signal to suppress the bias of the magnetic element.
8. A controller, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-6.
9. A vehicle, characterized in that, It includes the vehicle body and the controller as described in claim 8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.