Fast start relaxation oscillator and electronic device

Abstract

This invention discloses a fast-start relaxation oscillator and electronic device, relating to the field of oscillator technology. The circuit includes: a constant current source; a digital adjustment module for adjusting the current of the constant current source; a first charging circuit, with its input connected to the output of the digital adjustment module; a second charging circuit connected in parallel with the first charging circuit; a first comparator, with its positive input connected to the positive terminal of a first capacitor and its inverting input connected to a reference voltage; a second comparator, with its positive input connected to the positive terminal of a second capacitor and its inverting input connected to the reference voltage; and a transistor-level cross-coupled latch, with its input connected to the outputs of the first and second comparators, and its output connected to the controlled terminals of the first and second charging circuits. This circuit can eliminate the reset dead time problem through the alternating charging of the two capacitors.

Description

Technical Field

[0001] This invention relates to the field of oscillator technology, and in particular to a fast-start relaxation oscillator and electronic device. Background Technology

[0002] Traditional RC relaxation oscillators typically consist of a constant current source, resistors, capacitors, comparators, latches, etc., and have the following drawbacks: 1. Frequency error and temperature drift caused by comparator delay: This is the most critical defect of traditional RC oscillators. Theoretically, the comparator should flip the clock the instant the capacitor voltage reaches the threshold, but in practice, comparators have an inherent propagation delay (t). d During the delay period, the capacitor voltage continues to rise, causing the actual switching point to exceed the set threshold (overshoot), thus lengthening the oscillation period (T). real = T ideal + t d T real For the actual period, T ideal (For the ideal period). More seriously, this delay t d It is not a constant value; it is highly sensitive to temperature and supply voltage. As temperature increases, electron mobility decreases, comparator speed slows down, and delay increases, directly causing the output frequency to drift significantly with temperature, thus limiting the frequency stability of the oscillator.

[0003] 2. Temperature coefficient limitation of core passive components: In traditional RC relaxation oscillators, the RS latch, as a key logic unit connecting the comparator and the charge / discharge switch, has an inherent logic propagation delay that can cause uncontrollable overcharging of the capacitor voltage. This not only introduces systematic frequency errors, but also significantly deteriorates the temperature stability of the oscillator because the delay characteristics change with temperature, voltage and process fluctuations.

[0004] 3. The impact of comparator offset voltage: The core drawback of existing technologies in fast startup is that it is difficult to balance high precision and high speed. Although the traditional frequency-locked loop architecture and complex temperature compensation mechanism ensure frequency stability, they lead to a significant increase in circuit locking and signal processing delays. In order to pursue microsecond-level fast startup, existing solutions often have to sacrifice power consumption, increase chip area, or reduce output frequency. Furthermore, due to the long settling time of the internal bandgap reference source, the ability of high-precision oscillators to achieve stable output in a very short time is further limited.

[0005] 4. Logic Delay Bottleneck of RS Latch: Existing technology typically uses RS latches to control the switching of capacitor charging and discharging switches. RS latches consist of multiple cascaded logic gates, resulting in a relatively long signal transmission path and introducing a non-negligible fixed delay. During the initial oscillation phase or at high frequencies, this delay limits the oscillator's maximum operating frequency and introduces additional phase noise.

[0006] 5. Existing RC relaxation oscillators typically have only one capacitor. During the charging and resetting process of the capacitor, there is a "reset dead zone" problem, which limits the upper frequency limit and accuracy. Summary of the Invention

[0007] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a fast-start relaxation oscillator and electronic device that eliminates the reset dead zone problem through alternating charging of two capacitors.

[0008] In a first aspect, a fast-start relaxation oscillator according to an embodiment of the present invention includes: Constant current source; A digital adjustment module is used to adjust the current magnitude of the constant current source to change the frequency of the fast-start relaxation oscillator; The first charging circuit has its input terminal connected to the output terminal of the digital adjustment module, and is used to charge the first capacitor. The second charging circuit is connected in parallel with the first charging circuit. The second charging circuit is used to charge the second capacitor. When the first capacitor is in a charging state, the second capacitor is in a discharging reset state; when the second capacitor is in a charging state, the first capacitor is in a discharging reset state. The first comparator has its positive input terminal connected to the positive terminal of the first capacitor, and its inverting input terminal connected to a reference voltage. The second comparator has its positive input terminal connected to the positive terminal of the second capacitor, and its inverting input terminal connected to the reference voltage. A transistor-level cross-coupled latch has its input terminal connected to the output terminals of the first comparator and the second comparator, and its output terminal connected to the controlled terminals of the first charging circuit and the second charging circuit. The transistor-level cross-coupled latch is used to control the charging state of the first charging circuit and the second charging circuit.

[0009] According to some embodiments of the present invention, the digital adjustment module includes: A current replication unit is used to replicate the current of the constant current source; Multiple parallel current regulating branches, each of which is used to regulate the current of the constant current source according to a corresponding digital control signal.

[0010] According to some embodiments of the present invention, the current replication unit includes: The first NMOS transistor has its drain connected to the power supply voltage, its source connected to the constant current source, and its gate connected to the source. The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, and its source connected to the constant current source. The first PMOS transistor has its source connected to the power supply voltage, its drain connected to the drain of the second NMOS transistor, and its gate connected to the source of the second NMOS transistor. The second PMOS transistor has its source connected to the power supply voltage and its gate connected to the gate of the first PMOS transistor. The third PMOS transistor has its source connected to the drain of the second PMOS transistor, and its gate connected to the gate of the first NMOS transistor. The drain of the third PMOS transistor is used to output the output current.

[0011] According to some embodiments of the present invention, each of the current regulating branches includes: The fourth PMOS transistor has its source connected to the power supply voltage and its gate connected to the gate of the first PMOS transistor. The fifth PMOS transistor has its source connected to the drain of the fourth PMOS transistor, its gate connected to the gate of the first PMOS transistor, and its drain connected to the drain of the third PMOS transistor. The sixth PMOS transistor has its gate connected to the corresponding digital control signal, its source connected to the drain of the fourth PMOS transistor, and its drain grounded.

[0012] According to some embodiments of the present invention, the first charging circuit includes: The seventh PMOS transistor has its source connected to the output terminal of the digital adjustment module, its drain connected to the positive terminal of the first capacitor, the negative terminal of the first capacitor grounded, its gate connected to the first output terminal of the transistor-level cross-coupled latch, and its drain connected to the positive input terminal of the first comparator. The third NMOS transistor has its gate connected to the first output terminal of the transistor-level cross-coupled latch, its drain connected to the drain of the seventh PMOS transistor, and its source grounded. When the first comparator outputs a low level, the first output terminal of the transistor-level cross-coupled latch outputs a low level; when the first comparator outputs a high level, the first output terminal of the transistor-level cross-coupled latch outputs a high level.

[0013] According to some embodiments of the present invention, the second charging circuit includes: The eighth PMOS transistor has its source connected to the output terminal of the digital adjustment module, its drain connected to the positive terminal of the second capacitor, the negative terminal of the second capacitor grounded, its gate connected to the second output terminal of the transistor-level cross-coupled latch, and its drain connected to the positive input terminal of the second comparator. The fourth NMOS transistor has its gate connected to the second output terminal of the transistor-level cross-coupled latch, its drain connected to the drain of the eighth PMOS transistor, and its source grounded. When the second comparator outputs a low level, the second output terminal of the transistor-level cross-coupled latch outputs a low level; when the second comparator outputs a high level, the second output terminal of the transistor-level cross-coupled latch outputs a high level.

[0014] According to some embodiments of the present invention, the transistor-level cross-coupled latch includes: The fifth NMOS transistor has its gate connected to the output of the first comparator and its source grounded. The ninth PMOS transistor has its source connected to the power supply voltage, and its drain connected to the drain of the fifth NMOS transistor. The drain of the ninth PMOS transistor outputs a clock signal through a buffer. The tenth PMOS transistor has its source connected to the power supply voltage, its gate connected to the drain of the ninth PMOS transistor, and its gate connected to the drain of the tenth PMOS transistor. The sixth NMOS transistor has its gate connected to the output of the second comparator, its drain connected to the drain of the tenth PMOS transistor, and its source grounded. The seventh NMOS transistor has its drain connected to the drain of the tenth PMOS transistor, and its source is grounded. The eighth NMOS transistor has its gate connected to the drain of the seventh NMOS transistor, and the gate of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor. The first inverter has its input terminal connected to the drain of the sixth NMOS transistor, and its output terminal connected to the gate of the fourth NMOS transistor and the gate of the eighth PMOS transistor. The second inverter has its input terminal connected to the output terminal of the first inverter, and its output terminal connected to the gate of the third NMOS transistor and the gate of the seventh PMOS transistor.

[0015] According to some embodiments of the present invention, when the first capacitor or the second capacitor is charged, the drain of the ninth PMOS transistor and the drain of the tenth PMOS transistor are locked in complementary high and low level states.

[0016] According to some embodiments of the present invention, when the first comparator outputs a high level, the clock signal is a low level; when the first comparator outputs a low level, the clock signal is a high level.

[0017] In a second aspect, an electronic device according to an embodiment of the present invention includes the fast-start relaxation oscillator described in the first aspect embodiment.

[0018] The fast-start relaxation oscillator and electronic device according to embodiments of the present invention have at least the following beneficial effects: the digital adjustment module controls the frequency of the oscillator by changing the current magnitude. Simultaneously, a dual-capacitor alternating discharge structure is employed. When the first charging circuit charges the first capacitor, the second capacitor is in a discharge reset state. Once the voltage value of the first capacitor reaches the reference voltage connected to the first comparator, the output of the first comparator flips, immediately switching to the second charging circuit to charge the second capacitor, while the first capacitor returns to the discharge reset state. This "seamless" operation eliminates the time gap of waiting for capacitor discharge, making the oscillation frequency depend only on the constant current source current and the capacitor size, resulting in more accurate calculations and the ability to operate at higher frequencies. The biggest improvement of this structure is the elimination of the "reset dead time," thereby significantly improving frequency accuracy and speed. Furthermore, replacing the traditional RS latch with a transistor-level cross-coupled latch composed of MOS transistors achieves a smaller propagation delay, thereby improving frequency accuracy. The traditional logic gate RS latch involves multiple gate circuits (each with a delay), which introduces significant loop delay. In a relaxation oscillator, any delay will cause the capacitor charging and discharging time to exceed the theoretical threshold, resulting in a lower oscillation frequency. However, transistor-level cross-coupled latches have extremely short paths and extremely fast switching speeds, significantly reducing the delay between comparator toggling and switching action, thereby improving frequency accuracy during high-frequency oscillations.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a circuit schematic of an existing RC relaxation oscillator. Figure 2 This is a circuit schematic diagram of a fast-start relaxation oscillator according to an embodiment of this application; Figure 3 This is a circuit schematic diagram of the digital adjustment module according to an embodiment of this application; Figure 4 This is a line graph showing the effect of temperature change on the output frequency of the fast-start relaxation oscillator according to an embodiment of the present invention. Figure 5 This is a line graph showing the effect of power supply voltage changes on the output frequency of a fast-start relaxation oscillator according to an embodiment of the present invention. Figure 6 The startup time of the fast-start relaxation oscillator at different operating frequencies in embodiments of the present invention is given. Detailed Implementation

[0021] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0022] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0023] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0024] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] RC relaxation oscillators, as a common on-chip clock source, are widely used in cost- and power-sensitive fields such as the Internet of Things (IoT), biomedical chips, and smart sensors due to their simple structure, low cost, ease of integration, and lack of external components (such as inductors or crystals). Traditional RC relaxation oscillators primarily employ a voltage-mode architecture, with their core operating principle based on the charging and discharging characteristics of a first-order RC circuit. The basic circuit typically consists of a constant current source, a timing capacitor, one or two continuous-time comparators, and a digital logic module (such as an SR latch). During the operating cycle, the current source linearly charges the capacitor. When the voltage across the capacitor rises to a preset reference voltage threshold VREF, the comparator flips its output level, and the logic circuit controls a switch to rapidly discharge (reset) the capacitor or switch the charging direction.

[0026] Based on the number of comparators, traditional comparator structures are mainly divided into single-comparator structures and dual-comparator structures. The single-comparator structure compares the capacitor voltage with a single reference; the circuit is simple but sensitive to ground noise. The dual-comparator structure sets two threshold values ​​(V0 and V1). H and V L The capacitor voltage oscillates between two threshold values, exhibiting relatively strong anti-interference capability. Regardless of the structure, its theoretical oscillation frequency is primarily determined by the resistor value, capacitor value, and the comparator's threshold voltage window, typically expressed as: Where k is a constant, R is the resistance value, and C is the capacitance value.

[0027] Traditional RC relaxation oscillators, such as Figure 1 As shown, the oscillator consists of a constant current source, a resistor (not shown in the figure), a capacitor, comparator 1, comparator 2, and M. P M N It consists of an RS flip-flop. The core mechanism of this circuit is to use a constant current source to alternately charge and discharge the capacitor, generating a linear triangular wave that reciprocates between two threshold voltages (V1 and V2). Whenever the capacitor voltage reaches the upper or lower threshold, the comparator triggers the SR latch to flip, thereby controlling the switch to switch the direction of the charging and discharging circuit, forming a cyclical self-excited oscillation. The final output is a square wave signal whose frequency depends on the current magnitude, capacitance value, and threshold window width.

[0028] Traditional RC relaxation oscillators have the following drawbacks: 1. Frequency error and temperature drift caused by comparator delay: This is the most critical defect of traditional RC oscillators. Theoretically, the comparator should flip the clock the instant the capacitor voltage reaches the threshold, but in practice, comparators have an inherent propagation delay (t). d During the delay period, the capacitor voltage continues to rise, causing the actual switching point to exceed the set threshold (overshoot), thus lengthening the oscillation period (T).real = T ideal + t d T real For the actual period, T ideal (For the ideal period). More seriously, this delay t d It is not a constant value; it is highly sensitive to temperature and supply voltage. As temperature increases, electron mobility decreases, comparator speed slows down, and delay increases, directly causing the output frequency to drift significantly with temperature, thus limiting the frequency stability of the oscillator.

[0029] 2. Temperature coefficient limitation of core passive components: In traditional RC relaxation oscillators, the RS latch, as a key logic unit connecting the comparator and the charge / discharge switch, has an inherent logic propagation delay that can cause uncontrollable overcharging of the capacitor voltage. This not only introduces systematic frequency errors, but also significantly deteriorates the temperature stability of the oscillator because the delay characteristics change with temperature, voltage and process fluctuations.

[0030] 3. The impact of comparator offset voltage: The core drawback of existing technologies in fast startup is that it is difficult to balance high precision and high speed. Although the traditional frequency-locked loop architecture and complex temperature compensation mechanism ensure frequency stability, they lead to a significant increase in circuit locking and signal processing delays. In order to pursue microsecond-level fast startup, existing solutions often have to sacrifice power consumption, increase chip area, or reduce output frequency. Furthermore, due to the long settling time of the internal bandgap reference source, the ability of high-precision oscillators to achieve stable output in a very short time is further limited.

[0031] 4. Logic Delay Bottleneck of RS Latch: Existing technology typically uses RS latches to control the switching of capacitor charging and discharging switches. RS latches consist of multiple cascaded logic gates, resulting in a relatively long signal transmission path and introducing a non-negligible fixed delay. During the initial oscillation phase or at high frequencies, this delay limits the oscillator's maximum operating frequency and introduces additional phase noise.

[0032] 5. Existing RC relaxation oscillators typically have only one capacitor. During the charging and resetting process of the capacitor, there is a "reset dead zone" problem, which limits the upper frequency limit and accuracy.

[0033] To address these issues, this application provides a fast-start relaxation oscillator designed to overcome the technical bottlenecks of traditional RC oscillators, such as large frequency errors and significant temperature drift caused by comparator propagation delays and logic gate cascading, as well as the "reset dead zone" in single-capacitor structures that limits frequency limits and accuracy. By employing a dual-capacitor alternating charge-discharge structure to eliminate reset latency and using a positive feedback-based transistor-level cross-coupled latch to replace traditional logic gates, loop delay is significantly reduced. Simultaneously, a digital adjustment module is integrated to correct process deviations, thereby achieving a high-performance clock solution that combines microsecond-level fast startup capability, high frequency accuracy, and excellent temperature and power supply stability.

[0034] The fast-start relaxation oscillator and electronic device according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] On the one hand, embodiments of the present invention propose a fast-start relaxation oscillator, such as... Figure 2 As shown, the circuit includes: Constant current source 100; The digital adjustment module 200 is used to adjust the current of the constant current source 100 to change the frequency of the oscillator; The first charging circuit 300 has its input terminal connected to the output terminal of the digital adjustment module 200, and is used to charge the first capacitor C1. The second charging circuit 400 is connected in parallel with the first charging circuit 300. The second charging circuit 400 is used to charge the second capacitor C2. When the first capacitor C1 is in the charging state, the second capacitor C2 is in the discharge reset state; when the second capacitor C2 is in the charging state, the first capacitor C1 is in the discharge reset state. The first comparator COM1 has its positive input terminal connected to the positive terminal of the first capacitor C1, and its inverting input terminal connected to the reference voltage VBG. The second comparator COM2 has its positive input terminal connected to the positive terminal of the second capacitor C2, and its inverting input terminal connected to the reference voltage. The transistor-level cross-coupled latch 500 has its input terminal connected to the output terminals of the first comparator COM1 and the second comparator COM2, and its output terminal connected to the controlled terminals of the first charging circuit 300 and the second charging circuit 400. The transistor-level cross-coupled latch 500 is used to control the charging state of the first charging circuit 300 and the second charging circuit 400.

[0036] The constant current source 100 is provided by a reference circuit generated by a bandgap reference source, rather than by the oscillator itself. Therefore, this current is independent of temperature coefficients and unaffected by temperature. The digital adjustment module 200 controls the oscillator frequency by changing the current magnitude. Simultaneously, a dual-capacitor alternating discharge structure is employed. When the first charging circuit 300 charges the first capacitor C1, the second capacitor C2 is in a discharge reset state. Once the voltage of the first capacitor C1 reaches the reference voltage VBG connected to the first comparator COM1, the output of the first comparator COM1 flips, immediately switching to the second charging circuit 400 to charge the second capacitor C2, while the first capacitor C1 returns to the discharge reset state. This seamless operation eliminates the time gap waiting for capacitor discharge, making the oscillation frequency depend only on the constant current source current and capacitor size, resulting in more accurate calculations and the ability to operate at higher frequencies. The biggest improvement of this structure is the elimination of the "reset dead time," significantly improving frequency accuracy and speed. Furthermore, replacing the traditional RS latch with a transistor-level cross-coupled latch 500 composed of MOSFETs achieves a smaller propagation delay, thereby improving frequency accuracy. Traditional logic gate RS latches involve multiple gate circuits (each with a delay), introducing significant loop delay. In a relaxation oscillator, any delay will cause the capacitor charging and discharging time to exceed the theoretical threshold, resulting in a lower oscillation frequency. The transistor-level cross-coupled latch 500, however, has an extremely short path and a very fast switching speed, significantly reducing the delay between comparator toggling and switching action, thus improving frequency accuracy during high-frequency oscillation.

[0037] like Figure 3 As shown, in some embodiments of this application, the digital adjustment module 200 includes a current replication unit 210 and multiple parallel current adjustment branches 220. The current replication unit 210 replicates the current of the constant current source 100, and each current adjustment branch 220 adjusts the current of the constant current source 100 according to a corresponding digital control signal. When the constant current source 100 outputs current, it replicates the current at a certain ratio through the current replication unit 210, and then adjusts the current through the multiple current adjustment branches 220 to achieve precise current regulation.

[0038] like Figure 3As shown, in some embodiments of this application, the current replication unit 210 includes: a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, and a third PMOS transistor PM3. The drain of the first NMOS transistor NM1 is connected to the power supply voltage VDDA, the source of the first NMOS transistor NM1 is connected to the constant current source 100, and the gate of the first NMOS transistor NM1 is connected to the source of the first NMOS transistor NM1. The gate of the second NMOS transistor NM2 is connected to the gate of the first NMOS transistor NM1, and the source of the second NMOS transistor NM2 is connected to the constant current source 100. The first PMOS transistor PM1... The source of transistor PM1 is connected to the power supply voltage VDDA. The drain of the first PMOS transistor PM1 is connected to the drain of the second NMOS transistor NM2, and the gate of the first PMOS transistor PM1 is connected to the source of the second NMOS transistor NM2. The source of the second PMOS transistor PM2 is connected to the power supply voltage VDDA, and the gate of the second PMOS transistor PM2 is connected to the gate of the first PMOS transistor PM1. The source of the third PMOS transistor PM3 is connected to the drain of the second PMOS transistor PM2, and the gate of the third PMOS transistor PM3 is connected to the gate of the first NMOS transistor NM1. The drain of the third PMOS transistor PM3 is used to output the output current IOUT. NM1 is used to sample the current of the constant current source 100. NM1 and NM2 form a current mirror to replicate the current. PM1 acts as a pull-up transistor, replicating the current to the current mirror composed of PM2 and PM3.

[0039] like Figure 3As shown, in some embodiments of this application, each current regulation branch includes a fourth PMOS transistor (PM41 / PM42 / PM43 / PM44 / PM45), a fifth PMOS transistor (PM51 / PM52 / PM53 / PM54 / PM55), and a sixth PMOS transistor (PM61 / PM62 / PM63 / PM64 / PM65). The source of the fourth PMOS transistor is connected to the power supply voltage VDDA, and the gate of the fourth PMOS transistor is connected to the gate of the first PMOS transistor PM1. The source of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor PM1, and the drain of the fifth PMOS transistor is connected to the drain of the third PMOS transistor PM3. The gate of the sixth PMOS transistor is connected to the corresponding digital control signal, the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the sixth PMOS transistor is grounded. This example illustrates five parallel current regulation branches. Taking the first current regulation branch as an example, it includes PM41, PM51, and PM61. The source of PM41 is connected to the power supply voltage VDDA, and the gate of PM41 is connected to the gate of the first PMOS transistor PM1. The source of PM51 is connected to the drain of PM41, the gate of PM51 is connected to the gate of the first PMOS transistor PM1, and the drain of PM51 is connected to the drain of the third PMOS transistor PM3. The gate of PM61 is connected to the corresponding digital control signal (X_OSC_ICTL). <4> The source of PM61 is connected to the drain of PM41, and the drain of PM61 is grounded. When X_OSC_ICTL <4> When the signal is low, PM61 is turned on, drawing some current from PM41. This reduces the current flowing into PM51, thus decreasing IOUT. The other current regulation branches operate on the same principle, controlled by the digital control signal X_OSC_ICTL. <3> X_OSC_ICTL <2> X_OSC_ICTL <1> X_OSC_ICTL <0> The conduction states of PM62, PM63, PM64, and PM65 can be controlled separately, thereby regulating the current flowing through PM52, PM53, PM54, and PM55.

[0040] To achieve high-precision adjustment of the oscillation frequency, the digital adjustment module 200 of this application employs a 5-bit digitally controlled current adjustment branch. This circuit is essentially a common-source, common-gate current mirror array with switch control. Current Mirroring: The constant current source 100, in conjunction with NM1 / NM2 and PM1 / PM2 / PM3, generates a basic bias voltage, causing the PMOS transistors (such as PM41, PM42, PM43, PM44, and PM45) at the top of each current adjustment branch to act as constant current sources, replicating the reference current. Digital Switching: The circuit contains five parallel current adjustment branches, each controlled by the digital signal X_OSC_ICTL<4:0>. Each branch has its own control logic (driving switches via buffers, such as PM61, PM62, PM63, PM64, and PM65). When a control bit is valid, the corresponding switch activates, turning on the common-source cascode transistors (such as PM51, PM52, PM53, PM54, and PM55) of that branch, allowing current to flow to the output IOUT. Conversely, if the control bit is invalid, the branch is turned off and does not contribute current. By changing the 5-bit verification code <4:0>, the current flowing to the oscillator core can be linearly increased or decreased, thereby finely adjusting the oscillation frequency. This embodiment uses 5 channels; more control words can be added if more precise adjustment is required.

[0041] The digital adjustment module 200 has the following advantages: 1. Calibrate process deviations (Process Trimming): This is the primary function of the circuit. During chip manufacturing, the actual values ​​of resistors and capacitors typically exhibit a process variation of ±10% to 20%, leading to inaccurate frequencies from the oscillator. This digital adjustment module 200 allows for current correction during the chip's factory testing (CP / FT) phase by "burning fuses" or configuring registers, calibrating the frequency to the target value (e.g., a precise 10MHz), significantly improving the yield and frequency accuracy of the finished product.

[0042] 2. High output impedance and high power supply rejection ratio (High PSRR): The circuit employs a common-source, common-gate structure, which has a higher output impedance compared to a single-transistor current source. This means that the output current IOUT varies very little with the output voltage (i.e., the voltage across the oscillator capacitor), ensuring the charging current remains constant throughout the cycle. This improves the oscillator's linearity and enhances its resistance to power supply noise.

[0043] 3. Good monotonicity: By using the method of adding parallel current branches, the adjustment curve is guaranteed to be monotonic (i.e., adding digital code will always increase or keep the current constant, and there will be no reversal), which makes the frequency calibration algorithm easier to implement.

[0044] like Figure 2 As shown, in some embodiments of this application, the first charging circuit 300 includes a seventh PMOS transistor PM7 and a third NMOS transistor NM3. The source of the seventh PMOS transistor PM7 is connected to the output terminal of the digital adjustment module 200, the drain of the seventh PMOS transistor PM7 is connected to the positive terminal of the first capacitor C1, the negative terminal of the first capacitor C1 is grounded, the gate of the seventh PMOS transistor PM7 is connected to the first output terminal of the transistor-level cross-coupled latch 500, and the drain of the seventh PMOS transistor PM7 is connected to the positive input terminal of the first comparator COM1. The gate of the third NMOS transistor NM3 is connected to the first output terminal of the transistor-level cross-coupled latch 500, the drain of the third NMOS transistor NM3 is connected to the drain of the seventh PMOS transistor PM7, and the source of the third NMOS transistor NM3 is grounded. When the first capacitor C1 is charged until the voltage at the non-inverting input of the first comparator COM1 is greater than the reference voltage VBG, the output of the first comparator COM1 outputs a high-level pulse. At this time, the first output of the transistor-level cross-coupled latch 500 will output a high level, which turns on the third NMOS transistor NM3 and turns off the seventh PMOS transistor. The first capacitor C1 stops charging and enters the discharge reset state.

[0045] like Figure 2 As shown, in some embodiments of this application, the second charging circuit includes an eighth PMOS transistor PM8 and a fourth NMOS transistor NM4. The source of the eighth PMOS transistor PM8 is connected to the output terminal of the digital adjustment module 200, the drain of the eighth PMOS transistor PM8 is connected to the positive terminal of the second capacitor C2, the negative terminal of the second capacitor C2 is grounded, the gate of the eighth PMOS transistor PM8 is connected to the second output terminal of the transistor-level cross-coupled latch 500, and the drain of the eighth PMOS transistor PM8 is connected to the positive input terminal of the second comparator COM2. The gate of the fourth NMOS transistor NM4 is connected to the second output terminal of the transistor-level cross-coupled latch 500, the drain of the fourth NMOS transistor NM4 is connected to the drain of the eighth PMOS transistor PM8, and the source of the fourth NMOS transistor NM4 is grounded. When the second capacitor C2 is charged until the voltage at the non-inverting input of the second comparator COM2 exceeds the reference voltage VBG, the output of the second comparator COM2 outputs a high-level pulse. At this time, the second output of the transistor-level cross-coupled latch 500 outputs a high level, causing the fourth NMOS transistor NM4 to conduct and the eighth PMOS transistor to turn off. The second capacitor C2 stops charging and enters a discharge reset state. It should be noted that the output signals at the first and second outputs of the transistor-level cross-coupled latch are opposite in level.

[0046] like Figure 2 As shown, in some embodiments of this application, the transistor-level cross-coupled latch 500 includes: a fifth NMOS transistor NM5, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a first inverter A2, and a second inverter A3. The gate of the fifth NMOS transistor NM5 is connected to the output of the first comparator COM1, and the source of the fifth NMOS transistor NM5 is grounded. The source of the ninth PMOS transistor PM9 is connected to the power supply voltage VDDA, and the drain of the ninth PMOS transistor PM9 is connected to the drain of the fifth NMOS transistor NM5. The drain of the ninth PMOS transistor PM9 outputs a clock signal CLK through buffer A1. The source of the tenth PMOS transistor PM10 is connected to the power supply voltage VDDA, and the gate of the tenth PMOS transistor PM10 is connected to the drain of the ninth PMOS transistor PM9. The gate of the ninth PMOS transistor PM9 is connected to the drain of the tenth PMOS transistor PM10. The sixth NMOS transistor NM6... The gate of the sixth NMOS transistor NM6 is connected to the output of the second comparator COM2. The drain of the sixth NMOS transistor NM6 is connected to the drain of the tenth PMOS transistor PM10, and the source of the sixth NMOS transistor NM6 is grounded. The drain of the seventh NMOS transistor NM7 is connected to the drain of the tenth PMOS transistor PM10, and the source of the seventh NMOS transistor NM7 is grounded. The gate of the eighth NMOS transistor NM8 is connected to the drain of the seventh NMOS transistor NM7, and the gate of the seventh NMOS transistor NM7 is connected to the drain of the eighth NMOS transistor NM8. The drain of the eighth NMOS transistor NM8 is connected to the drain of the ninth PMOS transistor PM9; the input of the first inverter A2 is connected to the drain of the sixth NMOS transistor NM6, and the output of the first inverter A2 is connected to the gate of the fourth NMOS transistor NM4 and the gate of the eighth PMOS transistor PM8; the input of the second inverter A3 is connected to the output of the first inverter A2, and the output of the second inverter A3 is connected to the gate of the third NMOS transistor NM3 and the gate of the seventh PMOS transistor PM7.

[0047] The transistor-level cross-coupled latch 500 of this application replaces the traditional RS latch with a combination of MOS transistors. This circuit is a static latch structure based on a positive feedback mechanism. Its core consists of two back-to-back cross-coupled inverters composed of PM9 and PM10, and NM7 and NM8, forming a bistable circuit that can lock nodes A and B in complementary high and low level states. NM5 and NM6 serve as pull-down driver transistors for input, corresponding to set (high level) and reset (low level) functions, respectively.

[0048] The process of CLK outputting a low level begins at the end of the charging process of the first capacitor C1. At this time, since the voltage at the positive input terminal of the first comparator COM1 is less than the reference voltage VBG at the inverting input terminal, the first comparator COM1 outputs a low level. At this time, NM5 is cut off, node A is VDD, and node B is maintained at a steady state of 0V by NM6. PM9 conducts, locking point A at the power supply level. When the voltage on the plate of the first capacitor C1 rises linearly and just exceeds the reference voltage VBG, the output of the first comparator COM1 flips, and its output jumps instantaneously from 0V to VDD, thereby triggering NM5 to conduct. NM5 begins to forcibly pull down node A, causing the voltage at node A to initially drop from VDD. As the voltage at point A drops, PM10, which was originally cut off, begins to conduct, injecting current into node B, causing the voltage at node B to rise from 0V. The rise in node B voltage directly causes PM5, which was originally maintaining a high level at point A, to quickly turn off, simultaneously waking up pull-down transistor NM8. At this point, NM8 and the initial trigger transistor NM5 work together to pull node A down even more strongly, causing the voltage at node A to drop to 0V instantaneously. The complete zeroing of point A, in turn, causes PM10 to strongly conduct and NM7 to completely turn off, resulting in node B being rapidly pulled up and locked at VDD. At this point, buffer A1 follows the drop in node A, and CLK finally outputs a low level. Finally, point B, now VDD, outputs a high level through the first inverter A2 and the second inverter A3, turning off PM7 and turning on NM3, discharging the first capacitor C1 to 0V. Simultaneously, point B, now VDD, outputs a low level through the first inverter A2, turning on PM8 and turning off NM4, charging the second capacitor C2 and starting the next cycle.

[0049] The process of CLK outputting a high level begins at the end of the charging period of the second capacitor C2. At this time, the steady state of the circuit is that node A is 0V, node B is maintained at VDD by PM10, and NM8 is conducting, locking point A to ground. When the voltage on the plate of C2 rises linearly and just exceeds the reference voltage VBG, the second comparator COM2 flips, and its output voltage jumps instantaneously from 0V to VDD, which directly triggers NM6 to conduct. NM6 forcibly discharges the charge of node B to ground, causing the voltage of node B to drop from VDD. When the voltage drop at point B causes PM9 to meet the turn-on condition, the previously off PM9 instantly conducts, and current surges into node A, causing the voltage of node A to rise rapidly from 0V. The rise in voltage at node A not only rapidly turns off PM10, which maintains a high level at point B, but also turns on pull-down transistor NM7. NM7 and NM6 work together to rapidly pull the voltage at node B down to a complete 0V. The 0V at point B, in turn, causes PM9 to conduct strongly and NM8 to turn off completely. At this point, node A loses all pull-down resistance, instantly surges to VDD and locks in. Buffer A1 senses the high level at point A and outputs VDD via CLK. Subsequently, point B, now at 0V, outputs a high level through the first inverter A2, turning on NM4 and turning off PM8, instantly discharging the second capacitor C2 to 0V. The output of the second comparator COM2 also returns to 0V, ending the pulse.

[0050] In relaxation oscillator design, the comparator output typically drives a latch directly to control the charge / discharge switch. Compared to traditional RS latches composed of standard NAND or NOR logic gates, using… Figure 2 The transistor-level cross-coupled latch 500 shown has the following significant advantages: 1. Reduced propagation delay (improved frequency accuracy): Traditional logic gate RS latches involve multiple stages of gate circuits (each stage has a delay), which introduces significant loop delay. In relaxation oscillators, any delay will cause the capacitor charging and discharging time to exceed the theoretical threshold, resulting in a lower oscillation frequency. This structure has an extremely short path and a very fast switching speed, which can significantly reduce the delay between the comparator's flip and the switching action, thereby improving the frequency accuracy during high-frequency oscillation.

[0051] 2. Steep Output Edges and Rail-to-Rail Swing: This structure utilizes positive feedback to accelerate the switching, resulting in a very steep rising / falling edge of the output waveform. Simultaneously, it provides a full-swing voltage from power supply to ground. This is crucial for driving the reset switch inside the oscillator, as the high gate voltage ensures the switch operates in the deep linear region, minimizing and stabilizing the on-resistance RON, guaranteeing complete discharge.

[0052] 3. Naturally Complementary Outputs (No Additional Inverter Required): Nodes A and B of this circuit are naturally complementary signals. In many oscillator designs, one signal may be needed to control a discharge switch, while another signal outputs to a subsequent counter or clock tree. Using this structure, two signals with opposite phases can be directly obtained, avoiding the phase difference and additional delay caused by adding an inverter at the output.

[0053] 4. Improved driving capability and level conversion function: If the output drive capability of the front-end comparator is weak, or if the comparator operates in a low voltage domain (such as the core voltage), while the oscillator switch requires high voltage drive, this structure can also function as a level shifter. Even when driven by weak or low voltage signals, the NM5 / NM6 can trigger the subsequent stage to generate a high-drive power domain output.

[0054] The fast-start relaxation oscillator disclosed in this application aims to address the technical bottlenecks of traditional RC oscillators, such as large frequency errors and significant temperature drift caused by comparator propagation delay and logic gate cascading, as well as the "reset dead zone" in single-capacitor structures that limits the upper frequency limit and accuracy. By employing a dual-capacitor alternating charge-discharge structure to eliminate reset latency and using a transistor-level cross-coupled latch based on positive feedback to replace traditional logic gates, loop delay is significantly reduced. Simultaneously, a digital adjustment module is integrated to correct process deviations, thereby achieving a high-performance clock solution that combines microsecond-level fast start-up capability, high frequency accuracy, and excellent temperature and power supply stability.

[0055] To verify the adjustment accuracy of the digital adjustment module, several gears were selected for verification. The verification results are shown in Table 1.

[0056] Table 1: Control word adjustment accuracy test (X_OSC_ICTL<4:0>, TT, 25℃) At 25°C, as shown in Table 2 and Figure 5 As shown. However, with the adjustments made in this application, the target frequency can be relocked at each process corner. In the structure of this application, temperature changes have a very small impact on the output frequency, with a maximum change rate of 1.19% compared to 27°C, as shown in Table 3 and... Figure 4 As shown, the maximum rate of frequency change after a power supply voltage change is only 0.01% compared to a power supply voltage of 3.3V. Figure 5 As shown.

[0057]

[0058] Table 2: Output 8MHz control word settings (25℃)

[0059] Table 3: Effect of temperature change on frequency (28 levels, TT) Circuit startup time, such as Figure 6 As shown in the figure, it can be seen that the oscillator can reach the normal operating frequency in less than 6µs under different process angles.

[0060] On the other hand, embodiments of this application also provide an electronic device, including a fast-start relaxation oscillator as described in the first aspect embodiment.

[0061] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A fast-start relaxation oscillator, characterized in that, include: Constant current source; The digital regulation module includes a current replication unit and multiple parallel current regulation branches; The first charging circuit has its input terminal connected to the output terminal of the digital adjustment module, and is used to charge the first capacitor. The second charging circuit is connected in parallel with the first charging circuit, and the second charging circuit is used to charge the second capacitor; when the first capacitor is in the charging state, the second capacitor is in the discharge reset state; when the second capacitor is in the charging state, the first capacitor is in the discharge reset state. The first comparator has its positive input terminal connected to the positive terminal of the first capacitor, and its inverting input terminal connected to a reference voltage. The second comparator has its positive input terminal connected to the positive terminal of the second capacitor, and its inverting input terminal connected to the reference voltage. A transistor-level cross-coupled latch has its input terminal connected to the output terminals of the first comparator and the second comparator, and its output terminal connected to the controlled terminals of the first charging circuit and the second charging circuit. The transistor-level cross-coupled latch is used to control the charging state of the first charging circuit and the second charging circuit. The current replication unit includes: The first NMOS transistor has its drain connected to the power supply voltage, its source connected to the constant current source, and its gate connected to the source of the first NMOS transistor. The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, and its source connected to the constant current source. The first PMOS transistor has its source connected to the power supply voltage, its drain connected to the drain of the second NMOS transistor, and its gate connected to the source of the second NMOS transistor. The second PMOS transistor has its source connected to the power supply voltage and its gate connected to the gate of the first PMOS transistor. The third PMOS transistor has its source connected to the drain of the second PMOS transistor and its gate connected to the gate of the first NMOS transistor. The drain is used to output the output current.

2. The fast-start relaxation oscillator according to claim 1, characterized in that, Each of the current regulation branches includes: The fourth PMOS transistor has its source connected to the power supply voltage and its gate connected to the gate of the first PMOS transistor. The fifth PMOS transistor has its source connected to the drain of the fourth PMOS transistor, its gate connected to the gate of the first PMOS transistor, and its drain connected to the drain of the third PMOS transistor. The sixth PMOS transistor has its gate connected to the corresponding digital control signal, its source connected to the drain of the fourth PMOS transistor, and its drain grounded.

3. The fast-start relaxation oscillator according to claim 1, characterized in that, The first charging circuit includes: The seventh PMOS transistor has its source connected to the output terminal of the digital adjustment module, its drain connected to the positive terminal of the first capacitor, the negative terminal of the first capacitor grounded, its gate connected to the first output terminal of the transistor-level cross-coupled latch, and its drain connected to the positive input terminal of the first comparator. The third NMOS transistor has its gate connected to the first output terminal of the transistor-level cross-coupled latch, its drain connected to the drain of the seventh PMOS transistor, and its source grounded.

4. The fast-start relaxation oscillator according to claim 3, characterized in that, The second charging circuit includes: The eighth PMOS transistor has its source connected to the output terminal of the digital adjustment module, its drain connected to the positive terminal of the second capacitor, the negative terminal of the second capacitor grounded, its gate connected to the second output terminal of the transistor-level cross-coupled latch, and its drain connected to the positive input terminal of the second comparator. The fourth NMOS transistor has its gate connected to the second output terminal of the transistor-level cross-coupled latch, its drain connected to the drain of the eighth PMOS transistor, and its source grounded; wherein the outputs of the first and second output terminals of the transistor-level cross-coupled latch are opposite.

5. The fast-start relaxation oscillator according to claim 4, characterized in that, The transistor-level cross-coupled latch includes: The fifth NMOS transistor has its gate connected to the output of the first comparator and its source grounded. The ninth PMOS transistor has its source connected to the power supply voltage, and its drain connected to the drain of the fifth NMOS transistor. The drain of the ninth PMOS transistor outputs a clock signal through a buffer. The tenth PMOS transistor has its source connected to the power supply voltage, its gate connected to the drain of the ninth PMOS transistor, and its gate connected to the drain of the tenth PMOS transistor. The sixth NMOS transistor has its gate connected to the output of the second comparator, its drain connected to the drain of the tenth PMOS transistor, and its source grounded. The seventh NMOS transistor has its drain connected to the drain of the tenth PMOS transistor, and its source is grounded. The eighth NMOS transistor has its gate connected to the drain of the seventh NMOS transistor, and the gate of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor. The first inverter has its input terminal connected to the drain of the sixth NMOS transistor, and its output terminal connected to the gate of the fourth NMOS transistor and the gate of the eighth PMOS transistor. The second inverter has its input terminal connected to the output terminal of the first inverter, and its output terminal connected to the gate of the third NMOS transistor and the gate of the seventh PMOS transistor.

6. The fast-start relaxation oscillator according to claim 5, characterized in that, When the first capacitor or the second capacitor is charged, the drain of the ninth PMOS transistor and the drain of the tenth PMOS transistor are locked in complementary high and low level states.

7. The fast-start relaxation oscillator according to claim 5, characterized in that, When the first comparator outputs a high level, the clock signal is low; when the first comparator outputs a low level, the clock signal is high.

8. An electronic device, characterized in that, Includes the fast-start relaxation oscillator as described in any one of claims 1-7.

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