On-chip transformer coupled differential single-pole double-throw switch circuit and radio frequency integrated circuit

Abstract

This invention provides an on-chip transformer-coupled differential single-pole double-throw switch circuit and an RF integrated circuit, belonging to the field of RF integrated circuits. The differential common port is coupled to the first differential throw ports L_P and L_N, and the second differential throw ports R_P and R_N, respectively. The first switch network includes switch elements D1 and D2, with the anodes of D1 and D2 connected to L_N and L_P, respectively. The cathodes of D1 and D2 are connected together and then connected to the output of a first CMOS inverter. The input of the first CMOS inverter is the input signal SW_L. The second switch network includes switch elements D3 and D4, with the anodes of D3 and D4 connected to R_N and R_P, respectively. The cathodes of D3 and D4 are connected together and then connected to the output of a second CMOS inverter. The input of the second CMOS inverter is the input signal SW_R. This invention solves the problems of limited switching linearity, high insertion loss, insufficient isolation, and large chip area.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and in particular to on-chip transformer-coupled differential single-pole double-throw (SPDT) switching circuits and radio frequency integrated circuits. Background Technology

[0002] With the rapid development of fifth-generation mobile communication technology and millimeter-wave technology, the performance requirements of RF front-end systems for switching circuits are becoming increasingly stringent. In the millimeter-wave band (30GHz~100GHz), traditional single-ended switching circuits face many technical challenges: (1) the parasitic parameter effects of semiconductor devices increase significantly at high frequencies, leading to deterioration of insertion loss; (2) the isolation of traditional structures is difficult to meet system specifications in the millimeter-wave band; (3) the common-mode interference suppression capability is insufficient, affecting the anti-interference performance and signal integrity of the system.

[0003] Differential structures have been widely used in millimeter-wave systems due to their excellent common-mode rejection capability and anti-interference performance. However, existing differential switching circuits have the following shortcomings: (1) They mostly use multi-level stacked transistor structures as switching elements, resulting in a large chip area, which is not conducive to high-density integration; (2) They require complex bias networks and control logic, which increases the design difficulty and power consumption; (3) The transformer coupling efficiency drops significantly in the millimeter-wave band, which restricts the overall performance of the switch; (4) The isolation between the control signal and the radio frequency signal is insufficient, which poses a risk of signal leakage.

[0004] In the prior art, the Chinese invention patent application CN111525917A, entitled "A Broadband Single-Pole Single-Throw Switch and Single-Pole Multi-Throw Switch Based on a Transformer", uses a broadband matching network composed of a transformer and parallel switching transistors, combined with a quarter-wavelength transmission line to achieve impedance transformation, and achieves good switching performance in the broadband range; however, the switch adopts a single-ended structure, has limited common-mode rejection capability, and mainly relies on transistors as switching elements. The linearity and power handling capability in the millimeter-wave high-frequency band are limited by the characteristics of the transistors themselves. The Chinese invention patent application CN120856122A, entitled "RF Switch Chip," adopts a differential structure. Compared with a single-ended port, the differential port has better common-mode rejection capability and anti-interference performance. However, the shortcomings of this switch are: (1) It relies on NMOS transistors as switching elements and operates by switching the channel on and off. In the millimeter-wave high-frequency band, the linearity and power handling capability are limited by the characteristics of the transistor itself; (2) When applied to high-frequency millimeter waves, its inductor parasitic capacitance will lead to a limitation of the self-resonant frequency, and the transistor turn-off capacitance is large, which leads to the deterioration of network bandwidth and matching characteristics in the millimeter-wave band, which in turn leads to a decrease in transformer coupling efficiency and restricts the overall performance of the switch; (3) It relies on gate resistors (RG1, RG2) to achieve AC / DC isolation. In the high-frequency millimeter-wave band, the gate parasitic capacitance of the transistor and the gate resistor constitute a low-pass filter, but some RF signals may still be coupled to the control terminal through the gate-drain / gate-source parasitic capacitance, and the high-frequency leakage risk is relatively high.

[0005] Therefore, there is an urgent need for a millimeter-wave differential SPDT switching circuit that combines low insertion loss, high isolation, high linearity, strong common-mode rejection capability, and compact chip area. Summary of the Invention

[0006] The technical problem to be solved by this invention is: how to solve the problems of limited linearity capability, high insertion loss in the high-frequency band, insufficient isolation and large chip area of ​​existing millimeter-wave switches.

[0007] This invention solves the above-mentioned technical problems through the following technical solution: an on-chip transformer-coupled differential single-pole double-throw switch circuit, comprising:

[0008] The differential common port is coupled to the first differential throwing port L_P, L_N and the second differential throwing port R_P, R_N respectively through a transformer coupling network; The first switching network includes switching elements D1 and D2. The anodes of switching elements D1 and D2 are connected to the first differential throwing ports L_N and L_P, respectively. The cathodes of switching elements D1 and D2 are connected to the output terminal of the first CMOS inverter. The input terminal of the first CMOS inverter receives the control signal SW_L. The second switching network includes switching elements D3 and D4. The anodes of switching elements D3 and D4 are connected to the second differential throwing ports R_N and R_P, respectively. The cathodes of switching elements D3 and D4 are connected together and then connected to the output terminal of the second CMOS inverter. The input terminal of the second CMOS inverter receives the control signal SW_R. The control signals SW_L and SW_R are complementary logic level signals.

[0009] This invention achieves the selection and switching of two RF paths through complementary logic control signals SW_L and SW_R. The transformer simultaneously performs impedance transformation and signal coupling functions, eliminating the need for additional impedance matching networks and multi-stage stacked transistor structures, thus reducing chip area by more than 40%. RF signal transmission is achieved through transformer magnetic coupling, combined with low on-resistance switching elements, resulting in low insertion loss in the millimeter-wave band. Utilizing the high impedance characteristics of the switching elements under reverse bias and the inherent port isolation capability of the transformer, the isolation between control signals and RF signals is improved, effectively suppressing crosstalk between transmitted and received signals. The transformer is a passive device, introducing no nonlinear distortion. The switching elements operate in the linear region under both forward bias and reverse bias, improving the linearity of the switching circuit.

[0010] Preferably, when the control signal SW_L is low and the control signal SW_R is high, the RF path between the differential common port and the first differential throwing port is turned on, and the RF path between the differential common port and the second differential throwing port is turned off; when the control signal SW_L is high and the control signal SW_R is low, the RF path between the differential common port and the first differential throwing port is turned off, and the RF path between the differential common port and the second differential throwing port is turned on.

[0011] This invention uses complementary logic control signals SW_L and SW_R to switch between two radio frequency paths, ensuring that only one radio frequency path is on at any given time, while the other path is reliably off, thus avoiding energy splitting and crosstalk between ports caused by signals being fed into two ports simultaneously.

[0012] Preferably, the switching elements D1, D2, D3, and D4 are diodes, bipolar transistors with base-collector short circuits, or NMOS transistors with gate-drain short circuits. The diodes are Schottky barrier diodes or PIN diodes. The diode switch operates in the linear region when forward-biased on or reverse-biased off, with an input 1dB compression point (IP1dB) ≥15dBm, meeting the requirements of large-signal applications. Utilizing the high impedance characteristics of the diode under reverse bias and the inherent port isolation capability of the transformer, the turn-off port isolation is ≥25dB, effectively suppressing crosstalk between transmitted and received signals. The transformer magnetic coupling combined with the low on-resistance diode switch structure achieves an insertion loss ≤2dB in the millimeter-wave band, significantly superior to traditional multi-stage stacked transistor switches.

[0013] Preferably, the transformer coupling network includes a common winding, a transformer winding L1, and a transformer winding L2. The two ends of the common winding are connected to the differential common ports COM_P and COM_N, respectively. The transformer winding L1 is connected between the first differential throwing port L_P and the second differential throwing port R_P. The transformer winding L2 is connected between the first differential throwing port L_N and the second differential throwing port R_N.

[0014] The transformer coupling network of the present invention adopts a four-winding integrated magnetic coupling structure. The common winding directly transfers energy to the transformer windings L1 and L2 through magnetic coupling. The signal path does not depend on the series capacitor, which can reduce parasitic nodes on the signal path, so that the coupling efficiency of the transformer itself directly determines the insertion loss.

[0015] Preferably, transformer winding L1 and common winding are placed close to each other using a stacked or interdigitated structure to form a first pair of magnetically coupled transformers, and transformer winding L2 and common winding are placed close to each other using a stacked or interdigitated structure to form a second pair of magnetically coupled transformers. The coupling coefficients of the first pair of magnetically coupled transformers and the second pair of magnetically coupled transformers are the same and are greater than or equal to 0.4.

[0016] Preferably, the common windings include transformer windings L3 and L4. One end of transformer winding L3 is connected to one end of transformer winding L4, and the other end of transformer winding L3 is connected to the differential common port COM_P. The other end of transformer winding L4 is connected to the differential common port COM_N. Transformer windings L1 and L2 span the first and second differential throwing ports. Transformer windings L3 and L4 are connected in series to the differential common port, forming an integrated network for magnetic coupling signal distribution and impedance transformation. This results in a simple structural layout and significantly reduces the chip area.

[0017] Preferably, the inductance values ​​of transformer windings L1, L2, L3, and L4 range from 50pH to 500pH. The selection of the inductance values ​​for the transformer windings needs to consider both impedance matching and operating bandwidth. A larger inductance value results in stronger magnetic coupling of the transformer, but a lower self-resonant frequency; a smaller inductance value results in a wider bandwidth, but a decrease in coupling efficiency. This invention provides a range of inductance values ​​for transformer windings L1, L2, L3, and L4 that balances both coupling efficiency and bandwidth.

[0018] Preferably, the differential common port COM_P, the first differential throwing port L_P, and the second differential throwing port R_P are positive phase ports, and the differential common port COM_N, the first differential throwing port L_N, and the second differential throwing port R_N are negative phase ports. The transformer winding L1 serves as the coupling path for the positive phase differential signal, and the transformer winding L2 serves as the coupling path for the negative phase differential signal.

[0019] Preferably, the first switching network further includes an input resistor R1 and a current-limiting bias resistor R2, and the second switching network further includes an input resistor R3 and a current-limiting bias resistor R4. The cathodes of switching elements D1 and D2 are connected to one end of the current-limiting bias resistor R2, and the other end of the current-limiting bias resistor R2 is connected to the output terminal of the first CMOS inverter. The input terminal of the first CMOS inverter is connected to one end of the input resistor R1, and the other end of the input resistor R1 receives the control signal SW_L. The cathodes of switching elements D3 and D4 are connected to one end of the current-limiting bias resistor R4, and the other end of the current-limiting bias resistor R4 is connected to the output terminal of the second CMOS inverter. The other input of the second CMOS inverter is connected to one end of the input resistor R3, and the other end of the input resistor R3 receives the control signal SW_R.

[0020] Input resistor R1 limits the current flowing into the input terminal of the first CMOS inverter, and input resistor R3 limits the current flowing into the input terminal of the second CMOS inverter, protecting the gate oxide layer of the transistors. Simultaneously, it forms a low-pass filter with the gate parasitic capacitance to suppress high-frequency noise components in the control signal. Current-limiting bias resistor R2 sets appropriate forward bias currents for switching elements D1 and D2, and current-limiting bias resistor R4 sets appropriate forward bias currents for switching elements D3 and D4. At the same time, it presents high impedance in the RF path, effectively isolating the RF signal and preventing it from leaking into the control circuit. Using the first CMOS inverter to drive switching elements D1 and D2, and the second CMOS inverter to drive switching elements D3 and D4, the control link delay is extremely small, with a switching time ≤10ns, enabling fast switching.

[0021] Preferably, the resistance values ​​of input resistors R1 and R3 are in the range of 1kΩ to 100kΩ, and the resistance values ​​of current-limiting bias resistors R2 and R4 are in the range of 500Ω to 50kΩ.

[0022] When the values ​​of input resistors R1 and R3 are relatively large, high-frequency noise on the control signal can be filtered out more effectively, but the switching speed will be reduced. When the values ​​of input resistors R1 and R3 are relatively small, the switching speed is improved, but the noise suppression effect is weakened. This invention provides a range of values ​​for input resistors R1 and R3, which can balance switching speed and noise suppression effect. In addition, this invention provides a range of values ​​for current-limiting bias resistors R2 and R4, which can ensure that sufficient forward bias current is provided to the switching element while preventing radio frequency signal leakage.

[0023] Preferably, the first CMOS inverter includes an NMOS transistor M1 and a PMOS transistor M2, and the second CMOS inverter includes an NMOS transistor M3 and a PMOS transistor M4. The gates of the NMOS transistors M1 and M2 are connected and serve as the input terminal of the first CMOS inverter. The sources of the NMOS transistors M1 and M2 are connected and serve as the output terminal of the first CMOS inverter. The drain of the NMOS transistor M1 is grounded, and the drain of the PMOS transistor M2 is connected to the power supply voltage. The gates of the NMOS transistors M3 and M4 are connected and serve as the input terminal of the second CMOS inverter. The sources of the NMOS transistors M3 and M4 are connected and serve as the output terminal of the second CMOS inverter. The drain of the PMOS transistor M3 is grounded, and the drain of the NMOS transistor M4 is connected to the power supply voltage.

[0024] The present invention also provides a radio frequency integrated circuit, including an on-chip transformer-coupled differential single-pole double-throw switch circuit. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0026] Figure 1 This is a schematic diagram of an on-chip transformer-coupled differential single-pole double-throw switch circuit provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the transformer coupling network in the on-chip transformer-coupled differential single-pole double-throw switch circuit provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the first switching network in the on-chip transformer-coupled differential single-pole double-throw switch circuit provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the second switching network in the on-chip transformer-coupled differential single-pole double-throw switch circuit provided in Embodiment 1 of the present invention; In the diagram: 100 Transformer coupling network, 200 First switch network, 300 Second switch network.

[0027] The accompanying drawings have illustrated specific embodiments of the invention, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] Example 1 like Figure 1 As shown, this embodiment provides an on-chip transformer-coupled differential single-pole double-throw switch circuit, including: a transformer coupling network 100, a first switch network 200, and a second switch network 300. Differential common ports COM_P and COM_N are coupled to the first differential throw ports L_P and L_N and the second differential throw ports R_P and R_N, respectively, through the transformer coupling network 100. The differential common ports COM_P and COM_N serve as common input or output terminals for radio frequency (RF) signals. The differential common ports COM_P and COM_N are magnetically coupled to the first differential throw ports L_P and L_N and the second differential throw ports R_P and R_N, respectively, through the transformer coupling network 100. The first switching network 200 is connected between the transformer coupling network 100 and the first differential throwing ports L_P and L_N, and is used to control the on / off state of the radio frequency path between the differential common ports COM_P and COM_N and the first differential throwing ports L_P and L_N; the second switching network 300 is connected between the transformer coupling network 100 and the second differential throwing ports R_P and R_N, and is used to control the on / off state of the radio frequency path between the differential common ports COM_P and COM_N and the second differential throwing ports R_P and R_N.

[0030] See Figure 2 The transformer coupling network 100 includes a common winding, a transformer winding L1, and a transformer winding L2. The two ends of the common winding are connected to differential common ports COM_P and COM_N, respectively. Transformer winding L1 is connected between a first differential throwing port L_P and a second differential throwing port R_P. Transformer winding L2 is connected between a first differential throwing port L_N and a second differential throwing port R_N. In this embodiment, the differential common port COM_P, the first differential throwing port L_P, and the second differential throwing port R_P are positive phase ports, while the differential common port COM_N, the first differential throwing port L_N, and the second differential throwing port R_N are anti-phase ports. Transformer winding L1 serves as the coupling path for positive-phase differential signals, and transformer winding L2 serves as the coupling path for anti-phase differential signals.

[0031] In physical implementation, this invention employs a stacked or interdigitated structure on the chip to place transformer winding L1 and a common winding close together, forming a first pair of magnetically coupled transformers. Similarly, a stacked or interdigitated structure is used to place transformer winding L2 and a common winding close together on the chip, forming a second pair of magnetically coupled transformers. When differential radio frequency signals are applied to the differential common ports COM_P and COM_N, the signals are induced in transformer windings L1 and L2 respectively through the magnetic coupling of transformer windings L3 and L4, and then transmitted to the corresponding first differential throwing ports L_P and L_N or second differential throwing ports R_P and R_N. The coupling coefficients of the first and second pairs of magnetically coupled transformers are the same, and the coupling coefficient is greater than or equal to 0.4.

[0032] In this implementation, the common windings include transformer windings L3 and L4. One end of transformer winding L3 is connected to one end of transformer winding L4, and the other end of transformer winding L3 is connected to the differential common port COM_P. The other end of transformer winding L4 is connected to the differential common port COM_N. Transformer windings L3 and L4 are magnetically coupled to transformer winding L1, and transformer windings L3 and L4 are magnetically coupled to transformer winding L2, achieving radio frequency signal transmission and impedance transformation through mutual inductance. The mutual inductance coefficient between transformer windings L3 and L4 and transformer winding L1 is k1, and the mutual inductance coefficient between transformer windings L3 and L4 and transformer winding L2 is k2. Under ideal symmetry conditions, k1 = k1 = k, where k is the coupling coefficient of the transformer, and the value of the transformer coupling coefficient ranges from 0.4 to 0.8. The higher the coupling coefficient, the higher the signal transmission efficiency and the lower the insertion loss. The inductance and coupling coefficient of a transformer can be optimized by adjusting geometric parameters such as the line width, spacing, interlayer distance, and number of turns of the transformer windings. In silicon-based integrated circuits (such as SiGe BiCMOS or CMOS SOI processes), transformer windings are implemented with a thick top metal layer (such as an aluminum or copper layer) to achieve a high quality factor. The upper and lower windings are tightly coupled through a thin dielectric layer. In the millimeter-wave band, each winding typically uses a single-turn or 1.5-turn structure to reduce parasitic capacitance and ensure that the self-resonant frequency is much higher than the operating frequency.

[0033] In practical applications, the center tap connection point between transformer windings L3 and L4 can be used as a DC bias point or ground point, providing a DC path for the differential common ports COM_P and COM_N without affecting the transmission of differential RF signals. Due to the inherent DC isolation characteristics of the transformer, there is no DC path between the first differential throwing ports L_P and L_N and the differential common ports COM_P and COM_N, nor between the second differential throwing ports R_P and R_N and the differential common ports COM_P and COM_N, which is beneficial for system-level bias isolation design.

[0034] See Figure 1 The first switch network 200 is located on the left, and the second switch network 300 is located on the right. The first switch network 200 and the second switch network 300 are completely symmetrical in circuit topology and are driven by complementary logic control signals. The first switch network 200 includes switch elements D1 and D2, an input resistor R1, and a current-limiting bias resistor R2. The anode of switch element D1 is connected to the first differential throwing port L_N, and the anode of switch element D2 is connected to the first differential throwing port L_P. The cathodes of switch elements D1 and D2 are connected together and then connected to one end of the current-limiting bias resistor R2. The other end of the current-limiting bias resistor R2 is connected to the output terminal of the first CMOS inverter. The input terminal of the first CMOS inverter is connected to one end of the input resistor R1, and the other end of the input resistor R1 receives the control signal SW_L.

[0035] The second switching network 300 includes switching elements D3 and D4, an input resistor R3, and a current-limiting bias resistor R4. The anode of switching element D3 is connected to the second differential throwing port R_N, and the anode of switching element D4 is connected to the second differential throwing port R_P. The cathodes of switching elements D3 and D4 are connected together and then connected to one end of the current-limiting bias resistor R4. The other end of the current-limiting bias resistor R4 is connected to the output terminal of the second CMOS inverter. The other input of the second CMOS inverter is connected to one end of the input resistor R3, and the other end of the input resistor R3 receives the control signal SW_R. The control signals SW_L and SW_R are complementary logic level signals, meaning that at any given time, the level states of the control signals SW_L and SW_R are opposite.

[0036] When the control signal SW_L is low (SW_L=0) and the control signal SW_R is high (SW_R=1), the control signal SW_L outputs a high level after passing through the first CMOS inverter. The switching elements D1 and D2 in the first switching network 200 are reverse biased and in a cut-off state. The radio frequency path between the differential common port and the first differential throwing port is connected through the transformer magnetic coupling. The radio frequency signal can be freely transmitted between the differential common port and the first differential throwing port through the transformer coupling network 100. The control signal SW_R outputs a low level after passing through the second CMOS inverter. The switching elements D3 and D4 in the second switching network 200 are forward biased and in a conducting state. The corresponding ports of the transformer windings L1 and L2 are short-circuited to a low impedance state. The radio frequency path between the differential common port and the second differential throwing port is turned off, thereby blocking the transmission path of the radio frequency signal.

[0037] When the control signal SW_L is high (SW_L=1) and the control signal SW_R is low (SW_R=0), the control signal SW_L outputs a low level after passing through the first CMOS inverter. Switching elements D1 and D2 in the first switching network 200 are forward biased and in a conducting state, short-circuiting the corresponding ports of transformer windings L1 and L2 to a low-impedance state. The RF path between the differential common port and the first differential throwing port is turned off, thereby blocking the transmission path of the RF signal. The control signal SW_R outputs a high level after passing through the second CMOS inverter. Switching elements D3 and D4 in the second switching network 200 are reverse biased and in a cut-off state. The RF path between the differential common port and the second differential throwing port is connected through transformer magnetic coupling, allowing the RF signal to transmit freely between the differential common port and the second differential throwing port via the transformer coupling network 100.

[0038] The on-chip transformer-coupled differential single-pole double-throw switch circuit of this invention adopts a fully differential structure, which has excellent common-mode rejection, with a common-mode rejection ratio (CMRR) ≥30dB, effectively suppressing common-mode interference such as power supply noise and substrate coupling noise. It uses transformer magnetic coupling to transmit radio frequency signals, combined with low on-resistance switching elements, to achieve low insertion loss in the millimeter-wave band. When diodes are used as switching elements, the insertion loss in the millimeter-wave band is ≤2dB, which is significantly better than traditional multi-stage stacked transistor switches.

[0039] The on-chip transformer-coupled differential single-pole double-throw switch circuit of this invention utilizes the high impedance characteristics of the switching element under reverse bias and the inherent port isolation capability of the transformer to improve the isolation between the control signal and the radio frequency signal, effectively suppressing crosstalk between the transmit and receive signals. When the switching element is a diode, the isolation of the turn-off port is ≥25dB.

[0040] In the on-chip transformer-coupled differential single-pole double-throw switch circuit of this invention, the transformer is a passive device, which does not introduce nonlinear distortion. The switching element operates in the linear region when forward biased on or reverse biased off, thus improving the linearity of the switching circuit. When a diode is used as the switching element, the diode switch operates in the linear region when forward biased on or reverse biased off, with an input 1dB compression point (IP1dB) ≥ 15dBm, meeting the requirements of large-signal applications.

[0041] The on-chip transformer-coupled differential single-pole double-throw switch circuit of this invention features a simple design and low power consumption, with near-zero static power consumption and dynamic power consumption originating solely from the charging and discharging current during control signal switching. This makes it suitable for battery-powered mobile terminal applications. It eliminates the need for complex bias networks, requiring only complementary logic levels to achieve reliable switching control, thus reducing system integration complexity.

[0042] The input resistor R1 limits the current flowing into the input of the first CMOS inverter, and the input resistor R3 limits the current flowing into the input of the second CMOS inverter, protecting the transistor gate oxide layer. It also forms a low-pass filter with the gate parasitic capacitance to suppress high-frequency noise components in the control signal. The current-limiting bias resistor R2 sets a suitable forward bias current for switching elements D1 and D2, and the current-limiting bias resistor R4 sets a suitable forward bias current for switching elements D3 and D4. Simultaneously, it presents high impedance in the RF path, effectively isolating the RF signal and preventing leakage to the control circuit. By using the first CMOS inverter to drive switching elements D1 and D2, and the second CMOS inverter to drive switching elements D3 and D4, the control link delay is extremely small, with a switching time ≤10ns, enabling fast switching.

[0043] Switching elements D1, D2, D3, and D4 are diodes, base-collector shorted bipolar transistors, or gate-drain shorted NMOS transistors. The diodes are Schottky barrier diodes (SBDs) or PIN diodes. In this embodiment, switching elements D1, D2, D3, and D4 are Schottky barrier diodes (SBDs). Schottky barrier diodes have advantages such as low forward conduction voltage (typically 0.2V to 0.4V), extremely short reverse recovery time (picosecond level), and low junction capacitance, making them particularly suitable for millimeter-wave high-frequency switching applications. Of course, in processes without Schottky barrier diodes, PIN diodes or base-collector shorted bipolar transistors (HBTs) can be used as alternatives to Schottky barrier diodes.

[0044] In this invention, the resistance values ​​of input resistors R1 and R3 are selected in the range of 1kΩ to 100kΩ, with a preferred value of 5kΩ to 20kΩ. The resistance values ​​of input resistors R1 and R3 can be selected according to actual needs. When the resistance values ​​of input resistors R1 and R3 are larger, high-frequency noise on the control signal can be filtered out more effectively, but the switching speed will be reduced. When the resistance values ​​of input resistors R1 and R3 are smaller, it is beneficial to improve the switching speed, but the noise suppression effect is weakened.

[0045] The resistance values ​​of the current-limiting bias resistors R2 and R4 need to meet two design constraints: First, the resistance values ​​of the current-limiting bias resistors R2 and R4 should be small enough to ensure sufficient forward bias current (typically 0.5mA to 5mA) is provided to the switching element, allowing the switching element to conduct completely; second, the current-limiting bias resistors R2 and R4 should present sufficiently high impedance in the radio frequency band to prevent radio frequency signals from leaking to the first CMOS inverter and the second CMOS inverter. In this invention, the resistance values ​​of the current-limiting bias resistors R2 and R4 are selected in the range of 500Ω to 50kΩ, with a preferred value of 2kΩ to 10kΩ.

[0046] See Figure 3 and Figure 4 The first CMOS inverter includes an NMOS transistor M1 and a PMOS transistor M2, and the second CMOS inverter includes an NMOS transistor M3 and a PMOS transistor M4. The gates of NMOS transistors M1 and M2 are connected and serve as the input terminal of the first CMOS inverter. The sources of NMOS transistors M1 and M2 are connected and serve as the output terminal of the first CMOS inverter. The drain of NMOS transistor M1 is grounded, and the drain of PMOS transistor M2 is connected to the power supply voltage. The gates of NMOS transistors M3 and M4 are connected and serve as the input terminal of the second CMOS inverter. The sources of NMOS transistors M3 and M4 are connected and serve as the output terminal of the second CMOS inverter. The drain of PMOS transistor M3 is grounded, and the drain of NMOS transistor M4 is connected to the power supply voltage.

[0047] This invention allows for flexible adjustment of the connection method between the first CMOS inverter and the second CMOS inverter according to actual process and voltage requirements. Figure 3 and Figure 4 One connection method is given, but a conventional CMOS inverter connection method can also be used. The conventional CMOS inverter connection method is as follows: the gates of NMOS transistor M1 and PMOS transistor M2 are connected together to serve as the input terminal of the first CMOS inverter, and the drains of NMOS transistor M1 and PMOS transistor M2 are connected together to serve as the output terminal of the first CMOS inverter. The source of NMOS transistor M1 is grounded, and the source of PMOS transistor M2 is connected to the power supply voltage. The gates of NMOS transistor M3 and PMOS transistor M4 are connected together to serve as the input terminal of the second CMOS inverter, and the drains of NMOS transistor M3 and PMOS transistor M4 are connected together to serve as the output terminal of the second CMOS inverter. The source of PMOS transistor M3 is grounded, and the source of NMOS transistor M4 is connected to the power supply voltage.

[0048] Working principle: See below Figure 1The on-chip transformer-coupled differential single-pole double-throw switch circuit provided in this embodiment achieves the selection and switching of two radio frequency paths through complementary logic control signals SW_L and SW_R. The control signals satisfy the constraint that SW_L and SW_R are logically inverses of each other at any time, i.e., SW_L⊕SW_R=1. The two operating modes are described in detail below: Mode 1: Differential common ports COM_P and COM_N are connected to the first differential throwing ports L_P and L_N (COM... L-path is open) When the control signal SW_L=0 (low level) and the control signal SW_R=1 (high level) are set, the first CMOS inverter in the first switch network 200 outputs a high level, and the switching elements D1 and D2 are reverse biased and cut off. Since the anode of the switching element D1 is connected to the end of the transformer winding L2 near the first differential throwing port L_N, and the anode of the switching element D2 is connected to the end of the transformer winding L1 near the first differential throwing port L_P, the nodes of the transformer winding L1 near the first differential throwing port L_P and the nodes of the transformer winding L2 near the first differential throwing port L_N are both in a high impedance state. The radio frequency signal is successfully transmitted from the differential common ports COM_P and COM_N to the first differential throwing ports L_P and L_N through the transformer magnetic coupling. Simultaneously, the second CMOS inverter in the second switching network 300 outputs a low level, and switching elements D3 and D4 obtain forward bias current through the current-limiting bias resistor R4, achieving forward bias conduction and exhibiting low impedance (typically several ohms to tens of ohms). Since the anode of switching element D3 is connected to the end of transformer winding L2 near the second differential throwing port R_N, and the anode of switching element D4 is connected to the end of transformer winding L1 near the second differential throwing port R_P, at this time, switching elements D3 and D4 clamp the nodes of transformer winding L1 near the second differential throwing port R_P and the nodes of transformer winding L2 near the second differential throwing port R_N to low impedance, severely mismatching the transmission path of the radio frequency signal, and effectively blocking the transmission of the radio frequency signal to the second differential throwing ports R_P and R_N.

[0049] Mode 2: Differential common ports COM_P and COM_N are connected to the second differential throwing ports R_P and R_N (COM... R-path is open) When the control signal SW_L=1 (high level) and the control signal SW_R=0 (low level) are set, the first CMOS inverter in the first switch network 200 outputs a low level. Switching elements D1 and D2 obtain forward bias current through the current-limiting bias resistor R2, achieving forward bias conduction and presenting a low impedance (typically several ohms to tens of ohms). At this time, switching elements D1 and D2 clamp the nodes of transformer winding L1 near the first differential throwing port L_P and transformer winding L2 near the first differential throwing port L_N to a low impedance, severely mismatching the transmission path of the radio frequency signal. The transmission of the radio frequency signal to the first differential throwing ports L_P and L_N is effectively blocked. Simultaneously, the second CMOS inverter in the second switching network 300 outputs a low level, and the switching elements D3 and D4 are reverse biased and cut off. At this time, the nodes of transformer winding L1 near the second differential throwing port R_P and the nodes of transformer winding L2 near the second differential throwing port R_N are both in a high impedance state. The radio frequency signal is successfully transmitted from the differential common ports COM_P and COM_N to the second differential throwing ports R_P and R_N through the transformer magnetic coupling.

[0050] The complementary control scheme of the present invention ensures that only one RF path is on at any given time, while the other path is reliably off, thus avoiding energy splitting and inter-port crosstalk caused by signals being fed into two ports simultaneously.

[0051] The key design parameters and optimization criteria of this invention in typical millimeter-wave frequency bands (75GHz to 110GHz, i.e., W-band) are given below: (1) Transformer parameters: The inductance values ​​of transformer windings L1, L2, L3, and L4 range from 50pH to 500pH, with the preferred values ​​being 80pH to 200pH. The selection of inductance values ​​needs to consider both impedance matching and operating bandwidth: the larger the inductance value, the stronger the magnetic coupling of the transformer, but the lower the self-resonant frequency; the smaller the inductance value, the wider the bandwidth, but the lower the coupling efficiency. In W-band applications, the typical inductance of a single-turn transformer winding is approximately 100pH to 150pH.

[0052] The coupling coefficient k of the transformer directly affects the insertion loss, and k ≥ 0.5 is preferred. In SiGe BiCMOS technology, the typical coupling coefficient of a multilayer transformer composed of a top aluminum layer and a second-to-top aluminum layer is 0.5 to 0.7; the typical coupling coefficient of a planar transformer with an interdigital structure is 0.4 to 0.6.

[0053] (2) Diode parameters: The key parameters of a Schottky diode include: forward conduction resistance R on Zero-bias junction capacitance C j0 and cutoff frequency f T For W-band applications, f is required. TMuch higher than 110GHz, preferred f T ≥500GHz. Forward conduction resistance R on ≤5Ω, to reduce the impedance impact on the RF signal transmission path during conduction. Zero-bias junction capacitance C j0 ≤20fF, to reduce signal leakage in the reverse bias cutoff state.

[0054] (3) Parameters of the first and second CMOS inverters: The gate lengths of NMOS transistor M1 and PMOS transistor M2 are selected from the minimum gate lengths of the process (e.g., 130nm or 65nm). Similarly, the gate lengths of NMOS transistor M3 and PMOS transistor M4 are selected from the minimum gate lengths of the process (e.g., 130nm or 65nm) to obtain the fastest switching speed. The typical gate width of the NMOS transistor is 2μm to 10μm, and the gate width of the PMOS transistor is 2 to 3 times that of the NMOS transistor to achieve symmetrical rise / fall edge characteristics. The operating voltages of the first and second CMOS inverters are consistent with the process power supply voltage, typically 1.2V to 3.3V.

[0055] (4) Parameters of input resistors and current-limiting bias resistors: Input resistors R1 and R3 are preferably implemented using polysilicon resistors or thin-film resistors, with a resistance range of 5kΩ to 20kΩ. Current-limiting bias resistors R2 and R4 are preferably implemented using polysilicon resistors, with a resistance range of 2kΩ to 10kΩ. In the layout design, the resistors should be kept away from RF signal traces to minimize parasitic coupling effects.

[0056] The reasons for the decreased coupling efficiency of existing differential circuits in the millimeter-wave band are as follows: (1) Exacerbation of parasitic capacitance effect: As the frequency rises above 30 GHz, the parasitic capacitance between transformer windings and between windings and substrate begins to dominate the impedance characteristics. This causes the self-resonant frequency to approach the operating frequency, and the transformer no longer exhibits pure inductive behavior. The coupling energy is bypassed by the parasitic capacitance or converted into dielectric loss.

[0057] (2) Losses caused by skin effect and proximity effect: At high frequencies, the current tends to the surface of the conductor, the equivalent AC resistance increases sharply, and the ohmic loss of the conductor increases. At the same time, the proximity effect between windings further crowds out the current path, resulting in a sharp drop in the quality factor Q. Even if the magnetic coupling coefficient k remains unchanged, the effective transmission power is greatly reduced due to the low Q value.

[0058] (3) Eddy current loss on silicon substrate: In CMOS / SiGe process, there is a conductive silicon substrate under the transformer. The high-frequency alternating magnetic field will induce eddy currents in the substrate. The eddy currents generate a reverse magnetic field to cancel the original magnetic field (reducing the k value), and at the same time, the eddy currents generate Joule heat loss (reducing the Q value).

[0059] The on-chip transformer-coupled differential single-pole double-throw switch circuit provided by this invention employs a four-winding integrated magnetic coupling structure for transformer coupling 100. Transformer windings L3 and L4 serve as a common winding, directly transferring energy to transformer windings L1 and L2 via magnetic coupling, with the signal path independent of series capacitance. This structure reduces parasitic nodes on the signal path, making the transformer's coupling efficiency directly determine the insertion loss. Furthermore, the transformer windings L1, L2, L3, and L4 of this invention employ a single-turn or 1.5-turn structure. In the millimeter-wave frequency band, fewer turns result in smaller parasitic capacitance, allowing the self-resonant frequency to be pushed much higher than the operating frequency band, ensuring the transformer operates in the inductive high-efficiency region within the operating frequency band. The windings are implemented using an ultra-thick top metal layer (e.g., 3μm-6μm) achieved through SiGe BiCMOS or CMOS SOI processes. The thick metal effectively reduces the series resistance caused by the high-frequency skin effect, significantly improving the Q value (an increase in Q value is directly equivalent to an increase in coupling efficiency). Strong coupling (k≥0.5) is achieved by reducing the interlayer dielectric thickness (e.g., 1.5μm). Although the frequency increases, the problem of magnetic field dispersion caused by the shorter wavelength is offset by reducing the physical size (reducing the coil diameter), thus maintaining a high flux linkage. Finally, when a diode is used as the switching element, the diode's zero-bias junction capacitance (C) j0 The capacitance is only a few fF to a dozen fF, which is much smaller than the turn-off capacitance C of a MOSFET of the same size. off When the diode is turned off, the parasitic capacitance connected in parallel to the transformer winding is extremely small, equivalent to no load. The energy transmission of the transformer is not affected by the parasitic bypass, maintaining high coupling efficiency.

[0060] Example 2 This embodiment provides a specific implementation of an on-chip transformer-coupled differential single-pole double-throw switch circuit operating in the W-band (75GHz~110GHz). It is manufactured using a 0.13μm SiGe BiCMOS process, with a chip area of ​​0.15mm² (approximately 390μm×385μm, including pads).

[0061] The specific parameters of the transformer coupling network are as follows: each winding adopts a single-turn structure with a top 3μm thick aluminum layer; the inductance of transformer windings L1 and L2 is 120pH; the inductance of the common winding formed by transformer windings L3 and L4 is 200pH; the coupling coefficient between transformer winding L1 and the common winding, and the coupling coefficient between transformer winding L2 and the common winding are both 0.62. The linewidth of transformer windings L1, L2, L3, and L4 is 6μm, and the thickness of the interlayer dielectric is 1.5μm.

[0062] The switching elements D1, D2, D3, and D4 are Schottky barrier diodes built into the SiGe BiCMOS process, with an anode area of ​​2μm×4μm, a forward conduction resistance of approximately 3.5Ω, a zero-bias junction capacitance of approximately 8fF, and a cutoff frequency of approximately 800GHz.

[0063] The gate widths of NMOS transistor M1 in the first CMOS inverter and NMOS transistor M3 in the second CMOS inverter are 4μm and 0.13μm, respectively. The gate widths of PMOS transistor M2 in the first CMOS inverter and PMOS transistor M4 in the second CMOS inverter are 10μm and 0.13μm, respectively. The operating voltage is 1.2V. The input resistors R1 and R3 are 10kΩ, and the current-limiting bias resistors R2 and R4 are 5kΩ.

[0064] The results of this embodiment are as follows: At a center frequency of 92.5 GHz, the insertion loss of the turn-on path is 1.8 dB, and the isolation of the turn-off path is 28 dB. Within the full frequency band of 75 GHz to 110 GHz, the insertion loss is ≤2.5 dB, and the isolation is ≥22 dB. The input 1 dB compression point (IP1 dB) is approximately 16 dBm, and the third-order input cutoff point (IIP3) is approximately 26 dBm, exhibiting excellent linearity. The switching time is approximately 6 ns. The static power consumption is less than 0.1 mW.

[0065] Example 3 This embodiment provides a specific implementation of an on-chip transformer-coupled differential single-pole double-throw switch circuit operating in the Ka band (30GHz~40GHz). It is manufactured using a 65nm CMOS SOI process, with a chip area of ​​approximately 0.12mm².

[0066] The specific parameters of the transformer coupling network are as follows: each winding uses a top copper layer to achieve a 1.5-turn structure; the inductance of transformer windings L1 and L2 is 200 pH; the inductance of the common winding formed by transformer windings L3 and L4 is 360 pH; the coupling coefficient between transformer winding L1 and the common winding, and the coupling coefficient between transformer winding L2 and the common winding are both 0.55. The winding linewidth of transformer windings L1, L2, L3, and L4 is 4 μm, and the winding spacing is 3 μm.

[0067] Since it is not easy to obtain independent Schottky diodes in CMOS SOI process, in this embodiment, the switching elements D1, D2, D3, and D4 are equivalently implemented using NMOS transistors with gate-drain short circuit, with a gate width of 10μm / 65nm, an equivalent forward conduction resistance of about 5Ω, and an equivalent zero-bias junction capacitance of about 12fF.

[0068] The test results of this embodiment are as follows: At the 35GHz center frequency, the insertion loss of the conduction path is 1.2dB, and the isolation of the shutdown path is 32dB. Within the entire 30GHz–40GHz frequency band, the insertion loss is ≤1.8dB, and the isolation is ≥26dB. IP1dB is approximately 18dBm, and IIP3 is approximately 28dBm. The switching time is approximately 4ns.

[0069] Example 4 This embodiment provides a specific implementation of an on-chip transformer-coupled differential single-pole double-throw switch circuit operating in the V-band (58GHz~62GHz). It is manufactured using a 65nm CMOS process, with a chip area of ​​approximately 0.18mm².

[0070] The transformer windings adopt a single-turn structure. The inductance of transformer windings L1 and L2 is 140 pH, and the inductance of the common winding formed by transformer windings L3 and L4 is 120 pH. The coupling coefficients between transformer winding L1 and the common winding, and between transformer winding L2 and the common winding, are both 0.58. Switching elements D1, D2, D3, and D4 are implemented using the HBT base-collector junction as an equivalent PIN diode, with a forward conduction resistance of approximately 4Ω.

[0071] The test results for this embodiment at a center frequency of 60GHz are as follows: insertion loss 1.5dB, isolation 30dB, and IP1dB 17dBm. Within the full frequency band of 58GHz to 62GHz, the insertion loss is ≤2.0dB, and the isolation is ≥25dB. This is suitable for the RF front-end of 60GHz Wireless Personal Area Networks (WPANs) and short-range high-speed communication systems.

[0072] It should be noted that the on-chip transformer-coupled differential single-pole double-throw switch circuit of the present invention is not limited to the specific semiconductor process used in the above embodiments. Those skilled in the art can choose different process platforms to implement it according to actual needs. (1) In the GaAs pHEMT process, the switching elements D1, D2, D3 and D4 can be implemented by built-in Schottky diodes, and the transformer can be implemented by multi-layer metal wiring. This scheme is particularly suitable for low-noise receiver front-ends with strict requirements for noise figure.

[0073] (2) In the InP HBT process, SPDT switches with operating frequencies extended to the D band (110GHz~170GHz) or even higher frequency bands can be realized to meet the needs of terahertz communication and imaging systems.

[0074] (3) In advanced FinFET processes (such as 7nm or 5nm), the smaller chip area and lower power consumption can be achieved by replacing the diode with a FinFET transistor with a gate-drain short circuit, which is suitable for the integrated application of large-scale phased array antenna front-ends.

[0075] (4) In the printed circuit board (PCB) or low temperature co-fired ceramic (LTCC) process, the transformer can be implemented with multi-layer wiring and the diode can be a discrete packaged Schottky diode. This solution is suitable for application scenarios with low integration requirements but sensitive to cost.

[0076] Example 5 This embodiment provides a radio frequency integrated circuit, including the on-chip transformer-coupled differential single-pole double-throw switch circuit in Embodiment 1.

[0077] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An on-chip transformer-coupled differential single-pole double-throw switch circuit, characterized in that: include: The differential common port is coupled to the first differential throwing port L_P, L_N and the second differential throwing port R_P, R_N respectively through a transformer coupling network; The first switching network includes switching elements D1 and D2. The anodes of switching elements D1 and D2 are connected to the first differential throwing ports L_N and L_P, respectively. The cathodes of switching elements D1 and D2 are connected to the output terminal of the first CMOS inverter. The input terminal of the first CMOS inverter receives the control signal SW_L. The second switching network includes switching elements D3 and D4. The anodes of switching elements D3 and D4 are connected to the second differential throwing ports R_N and R_P, respectively. The cathodes of switching elements D3 and D4 are connected together and then connected to the output terminal of the second CMOS inverter. The input terminal of the second CMOS inverter receives the control signal SW_R. The control signals SW_L and SW_R are complementary logic level signals.

2. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 1, characterized in that: When the control signal SW_L is low and the control signal SW_R is high, the RF path between the differential common port and the first differential throwing port is turned on, and the RF path between the differential common port and the second differential throwing port is turned off; when the control signal SW_L is high and the control signal SW_R is low, the RF path between the differential common port and the first differential throwing port is turned off, and the RF path between the differential common port and the second differential throwing port is turned on.

3. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 1, characterized in that: Switching elements D1, D2, D3, and D4 are diodes, bipolar transistors with base-collector short circuits, or NMOS transistors with gate-drain short circuits. The diodes are Schottky barrier diodes or PIN diodes.

4. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 1, characterized in that: The transformer coupling network includes a common winding, transformer winding L1, and transformer winding L2. The two ends of the common winding are connected to the differential common ports COM_P and COM_N, respectively. Transformer winding L1 is connected between the first differential throwing port L_P and the second differential throwing port R_P. Transformer winding L2 is connected between the first differential throwing port L_N and the second differential throwing port R_N.

5. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 4, characterized in that: Transformer winding L1 and common winding are placed close to each other using a laminated or interdigitated structure to form a first pair of magnetically coupled transformers. Transformer winding L2 and common winding are placed close to each other using a laminated or interdigitated structure to form a second pair of magnetically coupled transformers. The coupling coefficients of the first pair of magnetically coupled transformers and the second pair of magnetically coupled transformers are the same and are greater than or equal to 0.

4.

6. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 4, characterized in that: The common windings include transformer windings L3 and L4. One end of transformer winding L3 is connected to one end of transformer winding L4, and the other end of transformer winding L3 is connected to the differential common port COM_P. The other end of transformer winding L4 is connected to the differential common port COM_N.

7. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 6, characterized in that: The inductance values ​​of transformer windings L1, L2, L3, and L4 range from 50pH to 500pH.

8. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 4, characterized in that: The differential common port COM_P, the first differential throwing port L_P, and the second differential throwing port R_P are positive phase ports, while the differential common port COM_N, the first differential throwing port L_N, and the second differential throwing port R_N are negative phase ports. The transformer winding L1 serves as the coupling path for the positive phase differential signal, and the transformer winding L2 serves as the coupling path for the negative phase differential signal.

9. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 1, characterized in that: The first switching network also includes an input resistor R1 and a current-limiting bias resistor R2. The second switching network also includes an input resistor R3 and a current-limiting bias resistor R4. The cathodes of switching elements D1 and D2 are connected to one end of the current-limiting bias resistor R2, and the other end of the current-limiting bias resistor R2 is connected to the output terminal of the first CMOS inverter. The input terminal of the first CMOS inverter is connected to one end of the input resistor R1, and the other end of the input resistor R1 receives the control signal SW_L. The cathodes of switching elements D3 and D4 are connected to one end of the current-limiting bias resistor R4, and the other end of the current-limiting bias resistor R4 is connected to the output terminal of the second CMOS inverter. The other input of the second CMOS inverter is connected to one end of the input resistor R3, and the other end of the input resistor R3 receives the control signal SW_R.

10. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 9, characterized in that: The resistance values ​​of input resistors R1 and R3 range from 1kΩ to 100kΩ, and the resistance values ​​of current-limiting bias resistors R2 and R4 range from 500Ω to 50kΩ.

11. The on-chip transformer-coupled differential single-pole double-throw switch circuit according to claim 1, characterized in that: The first CMOS inverter includes an NMOS transistor M1 and a PMOS transistor M2. The second CMOS inverter includes an NMOS transistor M3 and a PMOS transistor M4. The gates of NMOS transistors M1 and M2 are connected and serve as the input terminal of the first CMOS inverter. The sources of NMOS transistors M1 and M2 are connected and serve as the output terminal of the first CMOS inverter. The drain of NMOS transistor M1 is grounded, and the drain of PMOS transistor M2 is connected to the power supply voltage. The gates of NMOS transistors M3 and M4 are connected and serve as the input terminal of the second CMOS inverter. The sources of NMOS transistors M3 and M4 are connected and serve as the output terminal of the second CMOS inverter. The drain of PMOS transistor M3 is grounded, and the drain of NMOS transistor M4 is connected to the power supply voltage.

12. A radio frequency integrated circuit, characterized in that: Includes the on-chip transformer-coupled differential single-pole double-throw switch circuit as described in any one of claims 1-11.

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