Transmitter circuit with additional delay

Abstract

This invention discloses a transmitter circuit with additional delay. It generates a first transmitter output signal based on the rising and falling edges of a data input signal, and generates a second transmitter output signal by delaying the first transmitter output signal. The transmitter circuit includes a rising / falling edge converter that outputs a converted data signal, a delay logic unit that receives the converted data signal and generates a carrier signal, an AND logic gate that receives the converted data signal and the carrier signal to generate the first transmitter output signal, and a delay circuit that receives the first transmitter output signal to generate the second transmitter output signal. This invention improves the robustness of data transmission and the stability of common-mode signals. Furthermore, because the carrier signal contains a finite and definite number of pulses, it effectively reduces power consumption and electromagnetic interference.

Description

Technical Field

[0001] This invention relates to a circuit architecture for a transmitter circuit, particularly a transmitter circuit with an additional delay path. When this transmitter circuit is applied to a digital isolator module, it can not only effectively amplify the signal at the receiver input by more than two times, but also enhance the robustness of data transmission and prevent drift of the common-mode voltage signal. Background Technology

[0002] Existing isolation circuits are known to be intermediary circuits that provide voltage isolation between two communication blocks, such as a transmitter circuit (TX) and a receiver circuit (RX). These isolation circuits are generally used to eliminate unavoidable ground loops and protect high-voltage sensitive circuits. Using isolation circuits, not only is electrical insulation and signal isolation between circuits ensured, but reliable data transmission is also established between two dissimilar communication circuits, so that signals are not affected by fast transient common-mode noise. In practical applications, since common-mode noise is usually predictable and interference caused by user operation is unavoidable, isolation circuits that ensure the safety and reliability of signals during transmission naturally become indispensable intermediary circuits. Currently, it is known that in some industrial applications susceptible to voltage surges, fast transients, and high noise, isolation circuits are widely used to ensure the safety and reliability of transmitted signals.

[0003] Please see Figure 1 As shown, the disclosed prior art presents a schematic diagram of a conventional isolation circuit architecture, wherein two communication blocks, a transmitting circuit 10 and a receiving circuit 20, are each connected to a first ground voltage V. ss1 and a second grounding voltage V ss2 The isolation circuit included is designed to isolate the two ground voltages: the first ground voltage... Vss1 Second grounding voltage Vss2 To isolate. For example Figure 1 As shown in the figure, the isolation capacitor 22 is disposed between the transmitting circuit 10 and the receiving circuit 20 to provide electrical isolation. Specifically, in a conventional transmitter architecture, the transmitting circuit 10 may, for example, include a first transmitter TX_1 and a second transmitter TX_2, wherein the first transmitter TX_1 and the second transmitter TX_2 are each composed of an oscillator 11 and a mixer 12. Figure 1As shown, the data input signal DI is the input signal of the transmitting circuit 10, and generates a first transmitting output signal TXO_1 and a second transmitting output signal TXO_2 via the first transmitter TX_1 and the second transmitter TX_2, respectively. An isolation capacitor 22 is disposed between the transmitting circuit 10 and the receiving circuit 20 to couple the first transmitting output signal TXO_1 and the second transmitting output signal TXO_2 from the transmitting end to the receiving end, thereby generating a first receiving input signal RXIN_1 and a second receiving input signal RXIN_2, which are then received by the receiving circuit 20. The receiving circuit 20 includes a first receiver RX_1, a second receiver RX_2, and a mixer 21. The first receiver RX_1 receives the first receiving input signal RXIN_1, and the second receiver RX_2 receives the second receiving input signal RXIN_2. Through the mixer 21, which is electrically coupled to the first receiver RX_1 and the second receiver RX_2, an output signal RO is generated.

[0004] Please refer to this document as well. Figure 2 As shown, it is based on Figure 1 The waveforms of the data input signal DI, the first transmit output signal TXO_1 and the second transmit output signal TXO_2, the output oscillation signal OSC generated by oscillator 11, the first receive input signal RXIN_1 and the second receive input signal RXIN_2, and the output signal RO in the traditional isolated circuit architecture are shown in the diagram. Generally, the voltage level of the output signal RO usually follows the voltage level of the data input signal DI. However, as... Figure 1 As shown, it is worth noting that in traditional isolator circuit architectures, the aforementioned oscillator 11 must typically be configured at its transmitting end. In this case, as soon as the isolator circuit is powered on and operational, the oscillator 11 will continuously output an infinite pulse carrier signal, such as... Figure 2 The waveform of the output oscillation signal OSC generated by the oscillator is shown in the figure. These endless pulse signals will cause huge power consumption and serious electromagnetic interference problems. In addition, regardless of whether the data input signal DI transitions from logic state "0" to logic state "1" or from logic state "1" to logic state "0", the oscillator 11 continuously outputs an infinite pulse signal, which will make the output signals TXO_1 and TXO_2 at the transmitting end very likely to have severe signal jitter problems.

[0005] To go even further, from Figure 1As shown in the traditional isolator circuit architecture, it is clear that at least two signal transmission channels must be provided. This means that it is unavoidable to have two transmitters, TX_1 and TX_2, each matched with a receiver, RX_1 and RX_2, respectively. In this situation, the manufacturing cost and area consumption of the circuit become a major challenge. Therefore, traditional isolator circuits are insufficient and cannot be effectively and widely used in the industry.

[0006] Therefore, considering the numerous problems listed above, it is essential to adopt a multi-faceted approach. Consequently, the inventors of this invention, recognizing the potential for improvement in the aforementioned deficiencies and drawing upon years of experience in this field, through careful observation and research, and by applying theoretical principles, have proposed a novel design that effectively addresses these deficiencies. This invention provides a novel transmitter circuit architecture that eliminates the need for a traditional oscillator. This innovative transmitter circuit architecture solves many long-standing deficiencies in existing technologies, while simultaneously reducing power consumption and electromagnetic interference in the circuit. The specific architecture and implementation methods are detailed below. Summary of the Invention

[0007] To address the problems existing in the prior art, one objective of this invention is to provide a novel and highly innovative transmitter circuit that is suitable for and applicable to a digital isolator, helping to reduce its power consumption and electromagnetic interference. Therefore, the circuit architecture provided by this invention effectively solves the long-standing deficiencies of the prior art while maintaining accurate data transmission results and superior system robustness.

[0008] On the other hand, another objective of this invention is to provide a novel transmitter circuit that eliminates the need for a traditional oscillator. Instead, it replaces the oscillator used in existing technologies through an innovative circuit design. By eliminating the need for a traditional oscillator, this invention effectively eliminates the problems of excessive power consumption and electromagnetic interference inherent in previous technologies. Furthermore, the jitter problem in the output signal that may occur in the transmitter circuit is also improved.

[0009] In another aspect, another object of the present invention is to provide a transmitter circuit with additional delay. The transmitter circuit provided by the present invention is composed of: an upper and lower edge converter, a delay logic unit, an AND logic gate, and a delay circuit. By integrating these circuits with equivalent simplicity, the transmitter circuit provided by the present invention can successfully maintain relatively low circuit complexity, and therefore can be widely used in any related industry.

[0010] In view of the numerous inventive objectives of the present invention disclosed above, this invention significantly improves upon aspects that cannot be achieved or applied in existing patents or papers. Therefore, based on achieving the aforementioned inventive objectives, the present invention provides a transmitter circuit with additional delay, suitable for a digital isolator, the digital isolator including a receiver circuit and an isolation barrier electrically coupled between the transmitter circuit and the receiver circuit. The transmitter circuit provided by the present invention receives a data input signal and is electrically coupled to the isolation barrier. The transmitter circuit generates a first transmitter output signal and a second transmitter output signal based on the data input signal, wherein the second transmitter output signal is a delayed signal of the first transmitter output signal.

[0011] The isolation barrier is electrically coupled to the transmitter circuit and receives the first transmitter output signal and the second transmitter output signal. The isolation barrier generates a first isolation output signal and a second isolation output signal based on the received first transmitter output signal and second transmitter output signal.

[0012] With the circuit configuration described above, the receiver circuit is electrically coupled to the isolation barrier to receive the first isolation output signal and the second isolation output signal, so that the receiver circuit responds to the first isolation output signal and the second isolation output signal to generate a data output signal.

[0013] According to an embodiment of the present invention, the transmitter circuit generates the first transmitter output signal (TXO) based on the data input signal. The first transmitter output signal includes a first part signal and a second part signal. The transmitter circuit provided by the present invention starts generating the first part signal in response to a first transition state of the data input signal from a first logic state to a second logic state, and stops generating the first part signal while the data input signal is still in the second logic state.

[0014] Subsequently, the transmitter circuit begins generating the second partial signal in response to a second transition of the data input signal from the second logic state to the first logic state, and stops generating the second partial signal while the data input signal is still in the first logic state. According to a preferred embodiment of the invention, a first operation time of the first partial signal is different from a second operation time of the second partial signal. Furthermore, based on the periodicity of the data input signal (DI) and the voltage level of the first transmitter output signal (TXO) following the voltage level of the data input signal, the first transmitter output signal (TXO) disclosed in this invention is periodic.

[0015] In a preferred embodiment of the present invention, the transmitter circuit with additional delay provided by the present invention includes: a top-to-bottom edge converter, a delay logic unit, an AND logic gate, and a delay circuit. The top-to-bottom edge converter receives the data input signal and outputs a converted data signal in response to a rising edge and a falling edge of the data input signal. The converted data signal includes a first partition signal and a second partition signal. The top-to-bottom edge converter generates the first partition signal in response to the rising edge of the data input signal and terminates the generation of the first partition signal before the data input signal reaches the falling edge. Subsequently, the top-to-bottom edge converter generates the second partition signal in response to the falling edge of the data input signal and terminates the generation of the second partition signal before the data input signal reaches the next rising edge. Furthermore, a first operating time of the first partition signal and a second operating time of the second partition signal are different.

[0016] The delay logic unit is electrically coupled to the rising and falling edge converter to receive the converted data signal and generate a carrier signal accordingly. The carrier signal has multiple pulses between the rising and falling edges of the data input signal. According to an embodiment of the invention, the number of these multiple pulses of the carrier signal is finite and has a defined quantity.

[0017] The AND logic gate is electrically coupled to the upper and lower edge converter and the delay logic unit to receive the converted data signal and the carrier signal, and to generate the first transmitter output signal.

[0018] Subsequently, the delay circuit is electrically coupled to the AND logic gate, enabling the delay circuit to receive the first transmitter output signal, delay the first transmitter output signal, and thereby generate the second transmitter output signal.

[0019] According to an embodiment of the present invention, when the first transmitter output signal has a duty time T, the second transmitter output signal can be generated, for example, by delaying the first transmitter output signal by half a duty time (T*1 / 2).

[0020] Specifically, in one embodiment of the present invention, the delay circuit includes at least one inverting unit, which is composed of two inverters connected in series, such that the at least one inverting unit receives the first transmitter output signal, delays the first transmitter output signal, and generates the second transmitter output signal accordingly. In another embodiment of the present invention, the delay circuit may optionally include multiple inverting units, which are connected in series and receive the first transmitter output signal to generate the second transmitter output signal, thus similarly enabling the implementation of the inventive objective of the present invention.

[0021] On the other hand, according to an embodiment of the present invention, the first transition state of the data input signal from the first logic state to the second logic state is responsive to the rising edge of the data input signal. Furthermore, the second transition state of the data input signal from the second logic state to the first logic state is responsive to the falling edge of the data input signal.

[0022] Specifically, according to an embodiment of the present invention, the first portion of the first transmitter output signal has a first operating time, which is a first time interval between the transmitter circuit starting to generate the first set of pulse carriers and the transmitter circuit stopping the generation of the first set of pulse carriers. Similarly, the second portion of the first transmitter output signal has a second operating time, which is a second time interval between the transmitter circuit starting to generate the second set of pulse carriers and the transmitter circuit stopping the generation of the second set of pulse carriers. The first operating time of the first portion of the signal and the second operating time of the second portion of the signal are different.

[0023] Furthermore, the first operating time of the first portion of the first transmitter output signal (TXO) is equal to the first operating time of the first partition of the converted data signal, and the second operating time of the second portion of the first transmitter output signal (TXO) is equal to the second operating time of the second partition of the converted data signal.

[0024] According to a preferred embodiment of the present invention, the delay logic unit includes: a plurality of delay units, a plurality of multiplexers, and an OR logic gate. The plurality of delay units are connected in series to receive the converted data signal, sequentially delay the converted data signal, and output a plurality of delayed signals, wherein the signal delay time of each delay unit is one period. Each multiplexer has two input terminals and one output terminal, wherein the two input terminals are electrically coupled to both the converted data signal and the plurality of delayed signals consecutively, to generate a multiplexed signal at the output terminal. The OR logic gate receives each multiplexed signal from each output terminal of the plurality of multiplexers and generates the carrier signal accordingly.

[0025] According to an embodiment of the present invention, when the converted data signal and two consecutive signals among the plurality of delayed signals, wherein the former is a high voltage level and the latter is a low voltage level, the multiplexing signal will be converted to the high voltage level.

[0026] On the other hand, regarding the circuit configuration of the top and bottom edge converter, the present invention designs the top and bottom edge converter to include: an inverter, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, and an inverting OR gate, wherein the inverter receives the data input signal and outputs an inverted data input signal, a first input terminal of the inverting OR gate is electrically coupled to the first and second transmission gates, a second input terminal of the inverting OR gate is electrically coupled to the third and fourth transmission gates, and the first and third transmission gates are each connected to an input terminal and an output terminal of the inverter.

[0027] In this configuration, the data input signals are each delayed by a first period and a second period to control the first transmission gate and the fourth transmission gate, respectively. The inverted data input signals are each delayed by the first period and the second period to control the second transmission gate and the third transmission gate, respectively, so that the inverted gate outputs the converted data signal.

[0028] In one embodiment of the present invention, when the first period is longer than the second period, the first working time of the first partition signal of the converted data signal is longer than the second working time of the second partition signal of the converted data signal.

[0029] In another embodiment of the present invention, when the second period is longer than the first period, the second working time of the second partition signal of the converted data signal will be longer than the first working time of the first partition signal of the converted data signal.

[0030] Therefore, in summary, it can be confirmed that the present invention provides a well-designed transmitter circuit suitable for use in digital isolator architectures. This innovative circuit can be applied to transmitting circuits and has been proven to successfully minimize system power consumption and electromagnetic interference while maintaining excellent system robustness and accurate data transmission results. Thus, it is certain that, compared with the prior art, the advantages of the present invention lie in its excellent system-level control stability and its ability to maintain precise control over the isolation circuit.

[0031] Furthermore, based on the transmitter circuit with additional delay disclosed in this invention, which utilizes the delay of the first transmitter output signal (TXO) to generate a second transmitter output signal, this invention can effectively amplify the receiver input signal by more than two times. Therefore, the robustness of data transmission can also be greatly improved simultaneously. At the same time, by adopting the technical solution disclosed in this invention, the instability and drift of common-mode voltage can also be suppressed and minimized.

[0032] In summary, it is evident that the advantages and benefits of this invention include, in the application of digital isolation circuits, not only excellent system-level control stability, but also the ability to maintain precise control over the isolation circuits.

[0033] The following detailed description, through specific embodiments and accompanying drawings, will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0034] Figure 1 A schematic diagram of a conventional isolation circuit architecture in the prior art is disclosed.

[0035] Figure 2 According to Figure 1 The waveform diagram of the data input signal, the first transmitting end output signal, the second transmitting end output signal, the output oscillation signal generated by the oscillator, the first receiving end input signal, the second receiving end input signal, and the output signal in the traditional isolated circuit architecture.

[0036] Figure 3 This is a schematic diagram of the architecture of a digital isolator according to an embodiment of the present invention.

[0037] Figure 4 In accordance with the present invention Figure 3 The diagram shows the waveforms of the data input signal DI, the first transmitter output signal TXO, the second transmitter output signal TXOD, the first isolation output signal RXIN, the second isolation output signal RXIND, and the data output signal RO in the digital isolator circuit.

[0038] Figure 5 Disclosed according to the present invention Figure 3 In a digital isolator circuit, the waveform diagram of the first transmitter output signal TXO compared to the data input signal DI is shown.

[0039] Figure 6 This is a detailed circuit diagram of a transmitter circuit with additional delay disclosed in an embodiment of the present invention.

[0040] Figure 7 According to Figure 6 The waveform diagrams of the data input signal DI, the converted data signal DI_C, the carrier signal CS, and the first transmitter output signal TXO in the transmitter circuit shown are as follows.

[0041] Figure 8 The present invention discloses a waveform diagram of the second transmitter output signal TXOD compared to the first transmitter output signal TXO in an embodiment of the present invention.

[0042] Figure 9A detailed circuit diagram of a delay circuit according to an embodiment of the present invention is disclosed.

[0043] Figure 10 A detailed circuit diagram of a delay circuit according to another embodiment of the present invention, consisting of three inverting units connected in series, is disclosed.

[0044] Figure 11 This is a detailed circuit diagram of a delay logic unit according to an embodiment of the present invention.

[0045] Figure 12 According to Figure 11 The waveform diagrams of each node in the circuit shown are illustrated.

[0046] Figure 13 This is a detailed circuit diagram of the top and bottom edge converter according to a first embodiment of the present invention.

[0047] Figure 14 According to Figure 13 The waveform diagrams of each node in the circuit shown are illustrated.

[0048] Figure 15 This is a detailed circuit diagram of the top and bottom edge converter according to a second embodiment of the present invention.

[0049] Figure 16 According to Figure 15 The waveform diagrams of each node in the circuit shown are illustrated.

[0050] Figure reference numerals: 10 - Transmitter circuit; 11 - Oscillator; 12 - Mixer; 20 - Receiver circuit; 21 - Mixer; 22 - Isolation capacitor; 60, 60' - Upper and lower edge converters; 62 - Delay logic unit; 64 - AND logic gate; 66, 66' - Delay circuit; 90 - Inverting unit; 111A, 111B, 111C, 111N - Delay units; 131A, 131B, 131N - Multiplexer; 151 - OR logic gate; DI_C_D_1X - First delayed signal; DI_C_D_2X - Second delayed signal; DI_C_D_3X - Third delayed signal; DI_C_D_NX - Nth delayed signal; MUX1_C - First multiplexed signal; MUX2_C - Second multiplexed signal; MUXN_C - Nth multiplexed signal; 300 - Digital isolator; 302 - Transmitter circuit; 304 - Isolation barrier; 306 - Receiver circuit; V ss1 - First grounding voltage; V ss2- Second ground voltage; DI - Data input signal; DI_C - Conversion data signal; DI_CP1 - First partition signal; DI_CP2 - Second partition signal; t1' - First operating time; t2' - Second operating time; CS - Carrier signal; TXO - First transmitter output signal; TXOD - Second transmitter output signal; RXIN - First isolation output signal; RXIND - Second isolation output signal; RO - Data output signal; TXO_D1 - First partition signal; TXO_D2 - Second partition signal; RE - Rising edge; FE - Falling edge; t1 - First operating time; t2 - Second operating time; INV, INV1, INV2 - Inverters; TG1 - First transmission gate; TG2 - Second transmission gate; TG3 - Third transmission gate; TG4 - Fourth transmission gate; NOR - Inverting OR gate; N1 - First input terminal; N2 - Second input terminal; DI_B - Inverted data input signal; DI_D - Delayed signal of data input signal; DI_3D - Delayed signal of data input signal; DI_DB - Delayed signal of inverted data input signal; DI_3DB - Delayed signal of inverted data input signal; TX_1 - First transmitter; TX_2 - Second transmitter; RX_1 - First receiver; RX_2 - Second receiver; TXO_1 - First transmitter output signal; TXO_2 - Second transmitter output signal; RXIN_1 - First receiver input signal; RXIN_2 - Second receiver input signal; OSC - Output oscillation signal. Detailed Implementation

[0051] The foregoing description of the present invention, along with the following embodiments, serves to demonstrate and explain the spirit and principles of the invention, and provides a further explanation of the claims. Please refer in detail to the preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used in the drawings and description to refer to the same or similar elements. It should be understood that, for clarity and convenience, the invention may be enlarged in terms of shape and thickness in the drawings, and elements not specifically shown or described may take various forms known to those skilled in the art. Once disclosed by this invention, such alternatives and modifications will be apparent to those skilled in the art.

[0052] To illustrate the technical content and features of this invention and to enable those skilled in the art to understand, create, and use it, numerous embodiments are described below. However, it should be noted that these embodiments are not intended to limit the scope of this invention. Therefore, all equivalent modifications or variations made in accordance with the spirit of this invention should be included within the scope of protection of this invention.

[0053] Unless otherwise stated, certain conditional phrases or words, such as “may” or “possibly,” are generally used to express that embodiments of the invention “have,” but may also be interpreted as unnecessary features, elements, or steps. In other embodiments, these features, elements, or steps may not be required.

[0054] In the embodiments described in this specification, the reference to "one embodiment" or "in one embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, "one embodiment" or "in one embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment.

[0055] In the embodiments and claims of this invention, specific terms are used to refer to specific elements. Those skilled in the art will understand that the same element can have different names. This invention does not distinguish between elements with different names but the same function. In this specification and claims, "comprising" is used in an open-ended manner and should therefore be interpreted as "including but not limited to". "Coupled with" is intended to cover any indirect or direct connection. In other words, if this invention provides a first device coupled to a second device, it means that the first device can be connected to the second device directly or indirectly through other intermediate devices or connection methods via electrical connection, wireless communication, optical communication, or other signal connections, with or without signal connections.

[0056] The present invention is described in detail through the following embodiments, which are merely illustrative examples. Those skilled in the art can readily make appropriate modifications and variations to the apparatus and methods while retaining the teachings of the invention. Therefore, the following disclosure of the invention should be interpreted as being limited only by the scope of the appended claims. Throughout the specification and claims, except where clearly described, the meanings of “a” and “the” include “one or at least one” of an element or component. Furthermore, throughout the specification and claims, the singular includes descriptions of multiple elements or components, except where the context clearly excludes multiples. Throughout the specification and claims, unless the meaning of certain words is explicitly defined, the word “wherein” includes “among” or “above”. Generally, the meaning of each term used in the claims and specification of this invention refers to its common meaning known to those skilled in the art, unless otherwise noted. Some terms used to describe the invention and to guide those skilled in the art in understanding the invention may be discussed. Each illustrative example in this specification should not be used to limit the scope of protection of the invention.

[0057] The terms “basically,” “approximately,” “about,” and “probably” can refer to a value within 20% of a given value or range, preferably within 10%. Furthermore, the quantities or figures provided in this invention can be approximate values, and unless otherwise specified, can be described using the terms described above. When a quantity, density, or other parameter includes a specified range, preferred range, or listed ideal value, its value can be considered as any number within that given range.

[0058] As described in the background section of this invention, the existing digital isolator architecture suffers from excessively high circuit design complexity and lacks design flexibility. In particular, when using traditional transmitter circuits, the internal oscillator typically causes significant power consumption and electromagnetic interference. These shortcomings prevent the prior art from being applied to mass production of actual products. Furthermore, existing digital isolator circuits employ common On / Off Keying (OOK), Frequency Shift Keying (FSK), or Amplitude Shift Keying (ASK) modulation mechanisms for data signal transmission and coupling. These existing signal modulation methods are known to have severe power consumption and electromagnetic interference problems. Therefore, considering these shortcomings, this invention proposes a novel transmitter circuit that not only avoids the use of traditional oscillators but also provides an additional signal delay path for generating another transmitter output signal. Therefore, compared with the prior art, the present invention can improve the data robustness of the transmission system. The specific implementation methods and technical features of the present invention are described in detail below for reference.

[0059] Please refer to the accompanying drawings of this invention first. Figure 3 As shown, a schematic diagram of the architecture of a digital isolator according to an embodiment of the present invention is disclosed. According to an embodiment of the present invention, as shown, the transmitter circuit 302 provided by the present invention is adapted to a digital isolator 300, and the transmitter circuit 302 provided by the present invention has an additional signal delay path. As... Figure 3 As shown, the digital isolator 300 includes a transmitter circuit 302, an isolation barrier 304 electrically coupled to the transmitter circuit 302, and a receiver circuit 306 electrically coupled to the isolation barrier 304. The transmitter circuit 302 is electrically coupled to a first ground voltage V. ss1 The receiver circuit 306 is electrically coupled to a second ground voltage V. ss2The isolation barrier 304 is electrically coupled between the transmitter circuit 302 and the receiver circuit 306, thereby providing coupling and appropriate isolation for the transmitted signal. According to an embodiment of the present invention, the transmitter circuit 302 is used to receive a data input signal DI, and generate a first transmitter output signal TXO and a second transmitter output signal TXOD based on the data input signal DI, wherein the second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO.

[0060] An isolation barrier 304 is electrically coupled to the transmitter circuit 302 and receives the first transmitter output signal TXO and the second transmitter output signal TXOD, enabling the isolation barrier 304 to generate a first isolated output signal and a second isolated output signal based on the received first transmitter output signal TXO and second transmitter output signal TXOD. According to an embodiment of the present invention, the isolation barrier 304 may include, for example, at least one set of isolation capacitors, or be composed of equal elements thereof. One capacitor in the set of isolation capacitors is adapted to receive the first transmitter output signal TXO and generate the first isolated output signal, and another capacitor in the set of isolation capacitors is adapted to receive the second transmitter output signal TXOD and generate the second isolated output signal.

[0061] Please refer to the drawings of this invention. Figure 3 As shown, the first isolated output signal and the second isolated output signal are the input signals of the receiver circuit 306, which are the receiver input signals (first isolated output signal RXIN and second isolated output signal RXIND) indicated in the figure.

[0062] Therefore, with such a circuit configuration, the receiver circuit 306 electrically coupled to the isolation barrier 304 can receive the first isolation output signal RXIN and the second isolation output signal RXIND, so that the receiver circuit 306 responds to the first isolation output signal RXIN and the second isolation output signal RXIND, thereby generating and outputting a data output signal RO.

[0063] According to a preferred embodiment of the present invention, the transmitter circuit 302 disclosed herein generates a first transmitter output signal TXO based on the data input signal DI, and simultaneously, a second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO. To enable those skilled in the art to better understand the technical means employed in this invention, please also refer to... Figure 4 As shown, it is according to the present invention. Figure 3The digital isolator circuit includes waveform diagrams of its data input signal DI, first transmitter output signal TXO, second transmitter output signal TXOD, first isolation output signal RXIN, second isolation output signal RXIND, and data output signal RO. These waveform diagrams clearly show that the second transmitter output signal TXOD is a delayed version of the first transmitter output signal TXO. For example, in one embodiment of the invention, when the first transmitter output signal TXO has a duty time T, the second transmitter output signal TXOD can be generated, for example, by delaying the first transmitter output signal TXO by half a duty time (T*1 / 2). The invention will be further explained in subsequent paragraphs as to how the invention generates the desired second transmitter output signal TXOD by delaying the first transmitter output signal TXO; this will be detailed later.

[0064] Here, the present invention first describes the signal modulation mechanism employed in the present invention. Please refer to [link to documentation]. Figure 5 As shown, it discloses according to the present invention Figure 3 In a digital isolator circuit, the waveform diagram of its first transmitter output signal TXO compared to the data input signal DI is shown below. Figure 5 As shown, the first transmitter output signal TXO disclosed in this invention includes a first component signal TXO_D1 and a second component signal TXO_D2. Furthermore, since the data input signal DI is periodic, and the voltage level of the first transmitter output signal TXO typically follows the voltage level of the data input signal DI, the first transmitter output signal TXO is also periodic. According to embodiments of the present invention, under the same principle, as... Figure 4 As shown, the second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO. Furthermore, the voltage level of the second transmitter output signal TXOD will also follow the voltage level of the data input signal DI, so that the generated second transmitter output signal TXOD is also a periodic signal.

[0065] Please refer to the following at the same time Figure 3 , Figure 4 and Figure 5As shown, in detail, the transmitter circuit 302 starts generating the first partial signal TXO_D1 in response to a first transition of the data input signal DI from a first logic state to a second logic state, and stops generating the first partial signal TXO_D1 while the data input signal DI is still in the second logic state. In this embodiment, the first logic state refers to when the data input signal DI is at a low voltage level, which can be represented as digital logic "0". The second logic state refers to when the data input signal DI is at a high voltage level, which can be represented as digital logic "1". The "first transition" of the data input signal DI from the first logic state to the second logic state refers to the transition of the data input signal DI from digital logic "0" to digital logic "1" in response to a rising edge RE of the data input signal DI. Similarly, the "second transition" of the data input signal DI from the second logic state to the first logic state refers to the response of the data input signal DI to a falling edge FE when the data input signal DI transitions from digital logic "1" to digital logic "0".

[0066] As shown in the figure, the transmitter circuit 302 starts generating the second partial signal TXO_D2 in response to the data input signal DI transitioning from the second logic state "1" to the first logic state "0", and stops generating the second partial signal TXO_D2 while the data input signal DI is still in the first logic state "0". According to a preferred embodiment of the present invention, the first partial signal TXO_D1 includes a first group of pulse carriers, the second partial signal TXO_D2 includes a second group of pulse carriers, and the number of the first group of pulse carriers in the first partial signal TXO_D1 is different from the number of the second group of pulse carriers in the second partial signal TXO_D2. The pulse carrier modulation mechanism provided by the present invention, for example, can be as described in the present invention... Figure 5The illustrated embodiment is designed such that the first segment signal TXO_D1 has a greater number of pulse carriers than the second segment signal TXO_D2. However, the invention is not limited thereto. In other implementable embodiments of the invention, the second segment signal TXO_D2 may also be selectively designed to have a greater number of pulse carriers than the first segment signal TXO_D1. The invention is not limited to whether the first segment signal TXO_D1 or the second segment signal TXO_D2 has a greater number of pulse carriers. Generally speaking, those skilled in the art can make modifications or variations according to the specifications and requirements of their actual circuits without departing from the spirit and intent of the invention. Such modifications or variations should still fall within the scope of the invention. In other words, the invention is not limited to the above-described embodiments.

[0067] In summary, this invention improves upon existing signal modulation mechanisms and employs an innovative Pulse Carrier Modulation (PCM) mechanism. When the data input signal DI transitions from digital logic "0" to digital logic "1" and from digital logic "1" to digital logic "0", the transmitter circuit can generate different numbers of pulse carriers.

[0068] For example, according to the PCM modulation mechanism disclosed in this invention, such as Figure 5 As shown, the first portion of the first transmitter output signal TXO, TXO_D1, can have more pulse carriers than the second portion, TXO_D2. In other embodiments, those skilled in the art may optionally design the second portion, TXO_D2, to have more pulse carriers than the first portion, TXO_D1; this is not intended to limit the scope of protection of this invention. Generally speaking, it is believed that those skilled in the art, and those with a proper understanding and technical background of this invention, can make appropriate modifications or improvements according to the actual needs and specifications of different circuits without departing from the core technology of this invention; such modifications or improvements should still fall within the scope of protection claimed by this invention.

[0069] In addition, according to an embodiment of the present invention, the frequency of the first group of pulse carriers of the first segment signal TXO_D1 and the frequency of the second group of pulse carriers of the second segment signal TXO_D2 can each be a variable. Similarly, according to another embodiment of the present invention, the amplitude of the first group of pulse carriers of the first segment signal TXO_D1 and the amplitude of the second group of pulse carriers of the second segment signal TXO_D2 can also be selectively each a variable.

[0070] On the other hand, specifically speaking, such as Figure 5 As shown, the first segment signal TXO_D1 disclosed in this invention has a first operating time t1, which is a first time interval between the start of the transmitter circuit 302 generating the first group of pulse carriers of the first segment signal TXO_D1 and the termination of the transmitter circuit 302 generating the first group of pulse carriers of the first segment signal TXO_D1. Similarly, the second segment signal TXO_D2 has a second operating time t2, which is a second time interval between the start of the transmitter circuit 302 generating the second group of pulse carriers of the second segment signal TXO_D2 and the termination of the transmitter circuit 302 generating the second group of pulse carriers of the second segment signal TXO_D2. According to an embodiment of the present invention, the first operating time t1 of the first segment signal TXO_D1 and the second operating time t2 of the second segment signal TXO_D2 are different. Through the pulse carrier modulation mechanism provided above in this invention, for example, the first operating time t1 of the first segment signal TXO_D1 can be as follows: Figure 5 As shown, the second operation time t2 is designed to be slightly longer than the second segment signal TXO_D2. Alternatively, in other embodiments of the present invention, the second operation time t2 of the second segment signal TXO_D2 may also be selectively designed to be longer than the first operation time t1 of the first segment signal TXO_D1. The present invention is not limited to whether the first operation time t1 of the first segment signal TXO_D1 or the second operation time t2 of the second segment signal TXO_D2 is longer or shorter.

[0071] From these technical solutions, it is evident that the pulse carrier modulation mechanism provided by this invention can be effectively applied to a first transmitter output signal TXO generated by a transmitter circuit, enabling the first transmitter output signal TXO generated by the transmitter circuit to respond to the rising and falling edges of the data input signal DI respectively, and thus containing different numbers of pulse carriers. Through this pulse carrier modulation mechanism, this invention effectively improves upon and avoids the use of existing technologies such as on-off keying (OOK) modulation, frequency shift keying (FSK) modulation, and amplitude shift keying (ASK) modulation.

[0072] Meanwhile, according to the illustrations of the present invention Figure 5From the waveform diagram of the disclosed first transmitter output signal TXO, it can be observed that after the transmitter circuit stops generating the pulse carrier of the first sub-signal TXO_D1 or the second sub-signal TXO_D2, the first transmitter output signal TXO enters a stable state (or steady state). Under this steady state condition, the voltage level of the first transmitter output signal TXO is not necessarily limited to a certain fixed value and can be variable. In other words, according to the technical solution of the present invention, after the transmitter circuit stops generating the first sub-signal TXO_D1 or the second sub-signal TXO_D2, the first transmitter output signal TXO has an adjustable voltage level. Based on the fact that the present invention avoids the unlimited generation of continuous and uninterrupted pulse carriers in the time segment between the high voltage level (digital logic "1") and the low voltage level (digital logic "0") of the data input signal DI, as in the prior art, the present invention can successfully achieve the inventive objective of reducing power consumption and electromagnetic interference in the circuit system through this technical feature.

[0073] Please refer to the accompanying drawings of this invention below. Figure 6 As shown, it is a detailed circuit diagram of a transmitter circuit with additional delay disclosed in an embodiment of the present invention. Figure 6As shown, the transmitter circuit 302 disclosed in this invention includes a rising and falling converter 60, a delay logic unit 62, an AND logic gate 64, and a delay circuit 66. The rising and falling converter 60 is adapted to receive the data input signal DI and output a converted data signal DI_C accordingly. The delay logic unit 62 is electrically coupled to the rising and falling converter 60 to receive the converted data signal DI_C and generate a carrier signal CS accordingly. The AND logic gate 64 is electrically coupled to the rising and falling converter 60 and the delay logic unit 62 to receive the converted data signal DI_C and the carrier signal CS, and generates and outputs the first transmitter output signal TXO through an intersection logic (AND logic). As in the embodiment disclosed in this invention, the input signals of the AND logic gate 64 are the converted data signal DI_C generated by the rising and falling converter 60 and the carrier signal CS generated by the delay logic unit 62. Subsequently, the delay circuit 66 is further electrically coupled to the output of the AND logic gate 64. Through this circuit configuration, the delay circuit 66 receives the first transmitter output signal TXO, delays the first transmitter output signal TXO, and thus generates the second transmitter output signal TXOD. As mentioned above, since the second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO, when the first transmitter output signal TXO has a duty time T, the second transmitter output signal TXOD can be generated, for example, by delaying the first transmitter output signal TXO by half a duty time (T*1 / 2). The waveform diagram of the second transmitter output signal TXOD compared to the first transmitter output signal TXO in the embodiment of the present invention is disclosed as described above. Figure 4 In the waveform diagram.

[0074] like Figure 6 The circuit shown, based on a top-to-bottom edge converter 60 adapted to receive a data input signal DI and thereby generate the converted data signal DI_C, further provides the present invention. Figure 7 According to Figure 6 The waveform diagrams of the relevant signals in the transmitter circuit shown include the data input signal DI, the converted data signal DI_C generated by the upper and lower edge converters 60, the carrier signal CS generated by the delay logic unit 62, and the waveform diagrams of the first transmitter output signal TXO generated and output by the AND logic gate 64.

[0075] Depend on Figure 7As shown in the waveform diagram, the top-to-bottom edge converter 60 is adapted to receive the data input signal DI and generate the converted data signal DI_C based on and in response to the rising edge RE and falling edge FE of the data input signal DI. Specifically, the converted data signal DI_C includes a first partition signal DI_CP1 and a second partition signal DI_CP2, and the converted data signal DI_C is periodic because the data input signal DI is periodic. According to an embodiment of the present invention, the top-to-bottom edge converter 60 generates the first partition signal DI_CP1 in response to the rising edge RE of the data input signal DI, and terminates the generation of the first partition signal DI_CP1 before the data input signal DI reaches its falling edge FE. Then, the top-to-bottom edge converter 60 generates the second partition signal DI_CP2 in response to the falling edge FE of the data input signal DI, and terminates the generation of the second partition signal DI_CP2 before the data input signal DI reaches its next rising edge RE.

[0076] According to a preferred embodiment of the present invention, the first partition signal DI_CP1 has a first operating time t1', which is the time interval between the start and end of generation of the first partition signal DI_CP1 by the top-to-bottom edge converter 60. Similarly, the second partition signal DI_CP2 has a second operating time t2', which is the time interval between the start and end of generation of the second partition signal DI_CP2 by the top-to-bottom edge converter 60. According to an embodiment of the present invention, the first operating time t1' of the first partition signal DI_CP1 and the second operating time t2' of the second partition signal DI_CP2 are different.

[0077] like Figure 6 As shown, the delay logic unit 62 is electrically coupled to the top-to-bottom edge converter 60 to receive the converted data signal DI_C. Through this circuit configuration, the delay logic unit 62 generates a carrier signal CS based on the converted data signal DI_C. How the present invention uses the delay logic unit 62 to generate the carrier signal CS based on the converted data signal DI_C will be explained in more detail in subsequent relevant paragraphs.

[0078] Depend on Figure 7 The waveform shown clearly indicates that the carrier signal CS has multiple pulses between the rising edge RE and the falling edge FE of the data input signal DI, and the number of these pulses is finite. In other words, according to embodiments of the present invention, the number of multiple pulses of the carrier signal CS disclosed in the present invention is finite and has a definite quantity.

[0079] Subsequently, the AND logic gate 64 is electrically coupled to the upper and lower edge converters 60 and the delay logic unit 62, and receives the converted data signal DI_C and the carrier signal CS as input signals to the AND logic gate 64. The AND logic gate 64 can generate the first transmitter output signal TXO at its output terminal by performing intersection logic on the converted data signal DI_C and the carrier signal CS. It is worth noting that, due to the effect of the intersection logic provided by the AND logic gate 64, the first operating time t1 of the first part signal TXO_D1 of the first transmitter output signal TXO is controlled to be equal to the first operating time t1' of the first partition signal DI_CP1 of the converted data signal DI_C. At the same time, the second operating time t2 of the second part signal TXO_D2 of the first transmitter output signal TXO is controlled to be equal to the second operating time t2' of the second partition signal DI_CP2 of the converted data signal DI_C.

[0080] Therefore, after the first transmitter output signal TXO is generated by the output of the AND logic gate 64, the delay circuit 66 is further electrically coupled to the output of the AND logic gate 64. Through this circuit configuration, the delay circuit 66 receives the first transmitter output signal TXO, delays the first transmitter output signal TXO, and thereby generates the second transmitter output signal TXOD. Please refer to [reference needed]. Figure 8 The diagram shows a waveform representation of the second transmitter output signal TXOD compared to the first transmitter output signal TXO in an embodiment of the present invention. It is evident that by further incorporating the delay circuit 66 in the transmitter circuit, the present invention enables the second transmitter output signal TXOD to be a delayed signal of the first transmitter output signal TXO. For example, when the first transmitter output signal TXO has a duty time T, the second transmitter output signal TXOD can be generated, for instance, by delaying the first transmitter output signal TXO by half a duty time (T*1 / 2).

[0081] For details regarding the specific circuitry of the delay circuit 66 provided in this embodiment of the invention, please refer to [link / reference needed]. Figure 9 As shown, it discloses the present invention. Figure 6 A schematic diagram of an implementable delay circuit 66 provided in the embodiment. (e.g.) Figure 9 As shown, the delay circuit 66 disclosed in this invention includes at least one inverting unit 90, wherein the inverting unit 90 is composed of two inverters INV1 and INV2 connected in series, so that the inverting unit 90 can receive the aforementioned first transmitter output signal TXO, delay the first transmitter output signal TXO, and generate the aforementioned second transmitter output signal TXOD accordingly.

[0082] However, the delay circuit disclosed in this invention is not limited to such a circuit configuration. Please refer further to the accompanying drawings of this invention. Figure 10 As shown, its disclosure is based on the present invention. Figure 6 Another specific implementable circuit diagram of the delay circuit used in the embodiment. For example... Figure 10 As shown, the delay circuit 66' may, for example, include multiple inverting units 90, which are interconnected and receive the first transmitter output signal TXO, thereby generating a second transmitter output signal TXOD. For example, in Figure 10 In one embodiment, the delay circuit 66' can be formed by three inverting units 90 connected in series, thereby receiving and delaying the first transmitter output signal TXO to generate the second transmitter output signal TXOD. Therefore, those skilled in the art can implement other alternative embodiments based on the technical teachings of this invention. For example, the number of inverting units 90 connected in series in the delay circuit can be any positive integer greater than 1. This invention does not limit... Figure 10 The three inverting units 90 shown in series are a limitation. Regardless of the number of inverting units and / or inverters included in the delay circuit, the present invention covers modifications and equivalent embodiments based on the technical content provided by the present invention, and such embodiments are still suitable for achieving the inventive objectives of the present invention, thereby delaying a signal based on an original transmitter output signal (the first transmitter output signal TXO of the present invention) to generate a delayed transmitter output signal (the second transmitter output signal TXOD of the present invention).

[0083] In the following paragraphs, the present invention focuses on how it designs a delay logic unit that can replace the oscillator required in traditional transmitter circuit structures. The present invention further provides a detailed internal circuit diagram of this delay logic unit, which is described in detail below. As previously mentioned, in Figure 6 After receiving the conversion data signal DI_C from the top-to-bottom edge converter 60, the delay logic unit 62 can generate a carrier signal CS based on the conversion data signal DI_C. For details on the signal generation process, please refer to [link to relevant documentation]. Figure 11 As shown, where, Figure 11 A detailed circuit diagram of a delay logic unit according to an embodiment of the present invention is disclosed. As shown in the figure, the delay logic unit 62 includes a plurality of delay units 111A, 111B, 111C...111N, a plurality of multiplexers 131A, 131B...131N, and an OR logic gate 151.

[0084] The multiple delay units 111A, 111B, 111C...111N are connected in series to receive the converted data signal DI_C, sequentially delay the converted data signal DI_C, and output multiple delayed signals, including: a first delayed signal DI_C_D_1X, a second delayed signal DI_C_D_2X, a third delayed signal DI_C_D_3X, ..., an Nth delayed signal DI_C_D_NX. According to an embodiment of the present invention, the signal delay time of each delay unit 111A, 111B, 111C...111N is one period "X". Therefore, the first delay unit 111A receives the converted data signal DI_C, delays the converted data signal DI_C by one period "X", and outputs a first delayed signal DI_C_D_1X. The second delay unit 111B receives the first delayed signal DI_C_D_1X, delays the first delayed signal DI_C_D_1X by one period "X", and outputs a second delayed signal DI_C_D_2X. The third delay unit 111C receives the second delayed signal DI_C_D_2X, delays the second delayed signal DI_C_D_2X by one period "X", and outputs a third delayed signal DI_C_D_3X, and so on.

[0085] Each multiplexer 131A, 131B...131N has two inputs and one output. The two inputs are electrically coupled to two consecutive of the converted data signal and the plurality of delayed signals to generate a multiplexed signal at its output. For example, the two inputs of multiplexer 131A are electrically coupled to the converted data signal DI_C and the first delayed signal DI_C_D_1X, and generate a first multiplexed signal MUX1_C at its output.

[0086] The two input terminals of multiplexer 131B are electrically coupled to the second delayed signal DI_C_D_2X and the third delayed signal DI_C_D_3X, and generate a second multiplexed signal MUX2_C at its output terminal, and so on. Based on the same principle, multiplexer 131N receives the Nth delayed signal DI_C_D_NX and its previous delayed signal, and thus outputs the Nth multiplexed signal MUXN_C.

[0087] Specifically, please also refer to Figure 12 The waveform diagram of the multiplexed signal shown is as follows. Figure 12 According to Figure 11The diagram shows the waveforms of each node in the circuit. According to an embodiment of the present invention, when two consecutive signals are selected from the conversion data signal DI_C and the first delayed signal DI_C_D_1X, the second delayed signal DI_C_D_2X, the third delayed signal DI_C_D_3X…, where the former is a high voltage level and the latter is a low voltage level, the multiplexing signal will be converted to a high voltage level. Therefore, the present invention can generate... Figure 12 The waveform diagrams of the first multiplexed signal MUX1_C, the second multiplexed signal MUX2_C, etc. are shown.

[0088] For example, when the conversion data signal DI_C is at a high voltage level (logic "1") and the first delay signal DI_C_D_1X is at a low voltage level (logic "0"), the first multiplexing signal MUX1_C will be at a high voltage level (logic "1"). When the second delay signal DI_C_D_2X is at a high voltage level (logic "1") and the third delay signal DI_C_D_3X is at a low voltage level (logic "0"), the second multiplexing signal MUX2_C will be at a high voltage level (logic "1").

[0089] Subsequently, the OR logic gate 151 can receive the multiple multiplexed signals from the outputs of the multiple multiplexers 131A, 131B...131N, including: the first multiplexed signal MUX1_C, the second multiplexed signal MUX2_C...the Nth multiplexed signal MUXN_C, and generate the carrier signal CS accordingly. Figure 12 The disclosed waveform diagrams confirm that the carrier signal CS generated by this invention has multiple pulses, and that the number of these pulses is finite and definite. Therefore, this invention, through design as follows... Figure 11 The delay logic unit 62 shown generates a carrier signal CS with a finite and defined number of pulses, successfully replacing the existing oscillators that continuously output continuous and uninterrupted pulses in the prior art. Through these improvements and replacements, the present invention effectively reduces the enormous power consumption and severe electromagnetic interference problems of the prior art. Furthermore, the present invention can maintain accurate data output signals while avoiding signal jitter problems.

[0090] Therefore, according to the technical solution provided above by the present invention, it is evident that by setting the aforementioned delay logic unit 62, the present invention can successfully eliminate the oscillator circuit that must be used in traditional transmitter circuits. It is certain that the transmitter circuit provided by the present invention is novel and unprecedented, utilizing a rising-falling edge converter, a delay logic unit, an AND logic gate, and a delay circuit to replace the oscillator required in the prior art. Through the ingenious design of the present invention, the transmitter circuit provided by the present invention can generate its first transmitter output signal (TXO) based on the data input signal (DI) and responding to the rising and falling edges of the data input signal (DI). Under this architecture, the use of a traditional oscillator can be eliminated, allowing the present invention to effectively improve power consumption and electromagnetic interference, while also ensuring the accuracy of data transmission and maintaining the robustness of the system output voltage.

[0091] On the other hand, please refer further to the accompanying drawings of this invention. Figure 13 As shown, it is a detailed circuit diagram of the top and bottom edge converter according to a first embodiment of the present invention. Figure 14 According to Figure 13 The diagram shows the waveforms at each node in the circuit. Please also refer to the following technical specifications. Figure 13 and Figure 14 As shown, the top-to-bottom edge converter 60 includes an inverter INV, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a NOR gate NOR. The inverter INV receives a data input signal DI and outputs an inverted data input signal DI_B. One input terminal of the inverter INV receives the data input signal DI, and one output terminal of the inverter INV generates the inverted data input signal DI_B. Simultaneously, the input terminal of the inverter INV is connected to the first transmission gate TG1, and the output terminal of the inverter INV is connected to the third transmission gate TG3. In a first embodiment of the top-to-bottom edge converter provided by the present invention, the data input signal DI is delayed by a first period 3Z to form a signal as shown in the delayed signal "DI_3D" of the data input signal, and the data input signal DI is delayed by a second period 1Z to form a signal as shown in the delayed signal "DI_D" of the data input signal. In this first embodiment, the first period 3Z is longer than the second period 1Z. Furthermore, the delayed signal DI_3D of the data input signal formed by delaying the data input signal DI by the first period 3Z is used to control the first transmission gate TG1, and the delayed signal DI_D of the data input signal formed by delaying the data input signal DI by the second period 1Z is used to control the fourth transmission gate TG4.

[0092] Similarly, the inverted data input signal DI_B is delayed by a first period 3Z to form a signal as shown in the delayed signal "DI_3DB" of the inverted data input signal, and the inverted data input signal DI is delayed by a second period 1Z to form a signal as shown in the delayed signal "DI_DB" of the inverted data input signal. These delayed signals "DI_3DB" and "DI_DB" of the inverted data input signal are used to control the second transmission gate TG2 and the third transmission gate TG3, respectively. A first input terminal N1 of the NOR gate is electrically coupled to the first transmission gate TG1 and the second transmission gate TG2, and a second input terminal N2 of the NOR gate is electrically coupled to the third transmission gate TG3 and the fourth transmission gate TG4. According to an embodiment of the present invention, when the control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are at a high voltage level (digital logic "1"), the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are turned on; otherwise, when the control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are at a low voltage level (digital logic "0"), the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are turned off. Through this design, the present invention can achieve the following... Figure 14 The diagram shows the waveforms of the first input terminal N1 and the second input terminal N2. Subsequently, the inverting NOR gate can generate and output the waveforms shown in the diagram based on the input signal waveforms of its first input terminal N1 and second input terminal N2. Figure 14 The converted data signal DI_C is shown in the figure. It is worth noting that in the first embodiment of the upper and lower edge converter provided by the present invention, since the first period 3Z is longer than the second period 1Z, it can be controlled such that the first working time t1' of the first partition signal DI_CP1 of the converted data signal DI_C is longer than the second working time t2' of the second partition signal DI_CP2 of the converted data signal DI_C.

[0093] On the other hand, please see Figure 15 As shown, it is a detailed circuit diagram of the top and bottom edge converter according to a second embodiment of the present invention. Figure 16 According to Figure 15The diagram shows the waveforms of each node in the circuit. As shown, the upper and lower edge converter 60' in the second embodiment includes an inverter INV, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and an inverting OR gate NOR. The inverter INV receives the data input signal DI and outputs an inverted data input signal DI_B. A first input terminal N1 of the inverting OR gate NOR is electrically coupled to the first transmission gate TG1 and the second transmission gate TG2, and a second input terminal N2 of the inverting OR gate NOR is electrically coupled to the third transmission gate TG3 and the fourth transmission gate TG4. Therefore, the inverting OR gate NOR can generate and output a waveform based on the input signal waveforms of its first input terminal N1 and second input terminal N2. Figure 16 The conversion data signal DI_C is shown. When this second embodiment's upper and lower edge converter 60' is compared with the previous first embodiment (such as...), Figure 13 When comparing the shown upper and lower edge converters (60), it can be observed that in this second embodiment, the first period for delaying the data input signal DI and the inverted data input signal DI_B is 1Z, and the second period for delaying the data input signal DI and the inverted data input signal DI_B is 3Z. Therefore, in this second embodiment, the control signals for the first transmission gate TG1 and the fourth transmission gate TG4 are respectively the delayed signal DI_D and the delayed signal DI_3D of the data input signal, while the control signals for the second transmission gate TG2 and the third transmission gate TG3 are respectively the delayed signal DI_DB and the delayed signal DI_3DB of the inverted data input signal.

[0094] Therefore, in the second embodiment of the upper and lower edge converter provided by the present invention, since the second period 3Z is longer than the first period 1Z, it can be controlled to make the second working time t2' of the second partition signal DI_CP2 of the converted data signal DI_C longer than the first working time t1' of the first partition signal DI_CP1 of the converted data signal DI_C, as shown in the figure. Figure 16 As shown.

[0095] Therefore, in view of the above-described invention Figures 13-14 as well as Figures 15-16The disclosed embodiments effectively demonstrate how the present invention precisely and ingeniously designs the aforementioned top and bottom edge converters, ensuring that the first operating time t1' of the first partition signal DI_CP1 of the converted data signal DI_C is different from the second operating time t2' of the second partition signal DI_CP2 of the converted data signal DI_C. According to the technical solution disclosed in the present invention, the first operating time t1' of the first partition signal DI_CP1 is not limited to whether it must be longer or shorter than the second operating time t2' of the second partition signal DI_CP2. As long as the first operating time t1' of the first partition signal DI_CP1 and the second operating time t2' of the second partition signal DI_CP2 are different, and the first operating time t1 of the first branch signal TXO_D1 of the first transmitter output signal TXO is also different from the second operating time t2 of the second branch signal TXO_D2 of the first transmitter output signal TXO, it is possible to successfully control that the number of the first group of pulse carriers contained in the first branch signal TXO_D1 is different from the number of the second group of pulse carriers contained in the second branch signal TXO_D2. In other words, when responding to the rising and falling edges of the data input signal DI, the first part signal TXO_D1 and the second part signal TXO_D2 of the first transmitter output signal TXO generated by the transmitter circuit of the present invention will have different numbers of pulse carriers. This allows the present invention to successfully design an innovative pulse carrier modulation (PCM) mechanism. Furthermore, by adopting such a PCM signal modulation mechanism, the data channel used by traditional digital isolators for signal coupling and transmission can be effectively eliminated. Compared with the prior art, the transmitter output signal generated based on the present invention has fewer pulse carriers, whether for the first transmitter output signal TXO or the second transmitter output signal TXOD. This makes the present invention also beneficial in reducing power loss and electromagnetic interference in the circuit, thus better achieving the purpose of the present invention.

[0096] Therefore, based on at least one embodiment provided above, it is evident that the present invention proposes a novel pulse carrier modulation mechanism (PCM). Furthermore, by applying this PCM signal modulation mechanism to a transmitter circuit, the transmitter circuit can generate different numbers of pulse carriers in response to the rising and falling edges of the data input signal. Accordingly, when the data input signal transitions from digital logic "0" to digital logic "1", the transmitter circuit generates a first set of pulse carriers; and when the data input signal transitions from digital logic "1" to digital logic "0", the transmitter circuit generates a second set of pulse carriers, such that the number of pulse carriers in the first set and the number of pulse carriers in the second set are different. Based on these technical features, the present invention helps to reduce power loss and electromagnetic interference in the circuit. Simultaneously, leveraging the advantages of the PCM signal modulation mechanism, it can also maintain the correctness of data transmission, the robustness of the system output voltage, and avoid signal jitter interference.

[0097] In addition, the digital isolator circuit disclosed in this invention has an additional signal delay path, which can delay the original transmitter output signal (the first transmitter output signal TXO of this invention) to generate a delayed transmitter output signal (the second transmitter output signal TXOD of this invention). This invention can effectively amplify the receiver input signal by more than two times. Simultaneously, based on this gain and improvement, the robustness of data transmission of the digital isolator circuit provided by this invention can be significantly improved, while avoiding common-mode voltage signal drift. This not only ensures the correctness of the data output signal but also avoids signal jitter disturbance. Furthermore, this invention can further reduce the enormous power consumption and severe electromagnetic interference problems in the prior art, verifying the inventive efficacy achieved by this invention.

[0098] Therefore, in view of the above, compared with the prior art, it is obvious that the embodiments and circuit architecture disclosed in this invention can effectively solve many shortcomings of the prior art and present more efficient circuit performance. Furthermore, the technical solution provided by this invention can be applied not only to common electronic components, but also widely to various electronic circuit components in the semiconductor industry, integrated circuit industry, or power electronics. Clearly, the technical solution claimed herein has excellent industrial applicability and competitiveness. At the same time, this invention also verifies through various experimental and empirical data that the technical features, methods, and effects achieved by this invention are significantly different from existing solutions, and cannot be easily accomplished by those skilled in the art.

[0099] The embodiments described above are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. In other words, all equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered within the scope of protection of the present invention.

Claims

1. A transmitter circuit with additional delay, suitable for a digital isolator, characterized in that, The digital isolator includes a receiver circuit and an isolation barrier electrically coupled between the transmitter circuit and the receiver circuit; The transmitter circuit receives a data input signal and generates a first transmitter output signal and a second transmitter output signal based on the data input signal, wherein the second transmitter output signal is a delayed signal of the first transmitter output signal. The isolation barrier is electrically coupled to the transmitter circuit and receives the first transmitter output signal and the second transmitter output signal. Based on the received first transmitter output signal and second transmitter output signal, the isolation barrier generates a first isolated output signal and a second isolated output signal; and The receiver circuit is electrically coupled to the isolation barrier to receive the first isolation output signal and the second isolation output signal, so that the receiver circuit responds to the first isolation output signal and the second isolation output signal to generate a data output signal.

2. The transmitter circuit with additional delay as described in claim 1, characterized in that, Based on the fact that the data input signal is periodic, and the voltage level of the first transmitter output signal follows the voltage level of the data input signal, the first transmitter output signal is periodic.

3. The transmitter circuit with additional delay as described in claim 1, characterized in that, The first transmitter output signal includes a first part signal and a second part signal. The transmitter circuit starts generating the first part signal of the first transmitter output signal in response to a first transition state of the data input signal from a first logic state to a second logic state. When the data input signal is still in the second logic state, the transmitter circuit stops generating the first part signal of the first transmitter output signal. The transmitter circuit starts generating the second part signal of the first transmitter output signal in response to a second transition state of the data input signal from the second logic state to the first logic state. When the data input signal is still in the first logic state, the transmitter circuit stops generating the second part signal of the first transmitter output signal.

4. The transmitter circuit with additional delay as described in claim 3, characterized in that, The first part of the signal output by the first transmitter includes a first group of pulse carriers, and the second part of the signal output by the first transmitter includes a second group of pulse carriers, wherein the number of the first group of pulse carriers in the first part of the signal is different from the number of the second group of pulse carriers in the second part of the signal.

5. The transmitter circuit with additional delay as described in claim 4, characterized in that, The frequency of the first group of pulse carriers in the first segment signal and the frequency of the second group of pulse carriers in the second segment signal are each a variable.

6. The transmitter circuit with additional delay as described in claim 4, characterized in that, The amplitude of the first group of pulse carriers in the first segment signal and the amplitude of the second group of pulse carriers in the second segment signal are each a variable.

7. The transmitter circuit with additional delay as described in claim 3, characterized in that, After the transmitter circuit stops generating the first or second component signal of the first transmitter output signal, the first transmitter output signal has a moduloable voltage level.

8. The transmitter circuit with additional delay as claimed in claim 1, characterized in that, Since the data input signal is periodic, and the voltage level of the second transmitter output signal follows the voltage level of the data input signal, the second transmitter output signal is periodic.

9. The transmitter circuit with additional delay as claimed in claim 1, characterized in that, The first transmitter outputs a signal with one duty cycle, and the second transmitter outputs a signal by delaying the first transmitter output signal by half of that duty cycle.

10. The transmitter circuit with additional delay as claimed in claim 4, characterized in that, The first portion of the first transmitter output signal has a first operating time, which is a first time interval between the transmitter circuit starting to generate the first group of pulse carriers and the transmitter circuit stopping the generation of the first group of pulse carriers. The second portion of the first transmitter output signal has a second operating time, which is a second time interval between the transmitter circuit starting to generate the second group of pulse carriers and the transmitter circuit stopping the generation of the second group of pulse carriers. Furthermore, the first operating time of the first portion of the signal and the second operating time of the second portion of the signal are different.

11. The transmitter circuit with additional delay as claimed in claim 10, characterized in that, The transmitter circuitry includes: A top-to-bottom edge converter receives a data input signal and outputs a converted data signal in response to a rising edge and a falling edge of the data input signal. The converted data signal includes a first partition signal and a second partition signal. The top-to-bottom edge converter generates the first partition signal in response to the rising edge of the data input signal, and terminates the generation of the first partition signal before the data input signal reaches the falling edge. The top-to-bottom edge converter generates the second partition signal in response to the falling edge of the data input signal, and terminates the generation of the second partition signal before the data input signal reaches the next rising edge. A first operating time of the first partition signal and a second operating time of the second partition signal are different. A delay logic unit is electrically coupled to the rising and falling edge converter to receive the converted data signal and generate a carrier signal thereon, wherein the carrier signal has multiple pulses between the rising edge and the falling edge of the data input signal; An AND logic gate, electrically coupled to the upper and lower edge converter and the delay logic unit, receives the converted data signal and the carrier signal to generate the first transmitter output signal; and A delay circuit is electrically coupled to the AND logic gate. The delay circuit receives the output signal of the first transmitter, delays the output signal of the first transmitter, and thus generates the output signal of the second transmitter.

12. The transmitter circuit with additional delay as described in claim 3, characterized in that, The first transition state of the data input signal from the first logic state to the second logic state is responded to a rising edge of the data input signal.

13. The transmitter circuit with additional delay as described in claim 3, characterized in that, The second transition state of the data input signal from the second logic state to the first logic state is responded to a falling edge of the data input signal.

14. The transmitter circuit with additional delay as claimed in claim 11, characterized in that, The number of pulses in the carrier signal is finite and has a definite quantity.

15. The transmitter circuit with additional delay as claimed in claim 11, characterized in that, The first operation time of the first segment signal of the first transmitter output signal is equal to the first working time of the first partition signal of the converted data signal, and the second operation time of the second segment signal of the first transmitter output signal is equal to the second working time of the second partition signal of the converted data signal.

16. The transmitter circuit with additional delay as claimed in claim 11, characterized in that, The delay logic unit includes: Multiple delay units are connected in series to receive the converted data signal, sequentially delay the converted data signal, and output multiple delayed signals, wherein the signal delay time of each delay unit is one cycle; Multiple multiplexers, each having two inputs and one output. The two input terminals are electrically coupled to consecutive pairs of the converted data signal and the plurality of delayed signals to generate a multiplexed signal at the output terminal; and An OR logic gate receives each multiplexed signal from each of the multiplexers' outputs and generates the carrier signal accordingly.

17. The transmitter circuit with additional delay as claimed in claim 16, characterized in that, When the converted data signal and two consecutive delayed signals, where the former is a high voltage level and the latter is a low voltage level, the multiplexing signal will be converted to the high voltage level.

18. The transmitter circuit with additional delay as claimed in claim 11, characterized in that, The top-to-bottom edge converter includes an inverter, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, and an inverting OR gate. The inverter receives the data input signal and outputs an inverted data input signal. A first input terminal of the inverting OR gate is electrically coupled to the first transmission gate and the second transmission gate, and a second input terminal of the inverting OR gate is electrically coupled to the third transmission gate and the fourth transmission gate. The first and third transmission gates are each connected to an input terminal and an output terminal of the inverter. The data input signal is delayed by a first period and a second period to control the first and fourth transmission gates respectively, and the inverted data input signal is delayed by the first and second periods to control the second and third transmission gates respectively, so that the inverting OR gate outputs the converted data signal.

19. The transmitter circuit with additional delay as described in claim 18, characterized in that, When the first period is longer than the second period, the first working time of the first partition signal of the converted data signal is longer than the second working time of the second partition signal of the converted data signal.

20. The transmitter circuit with additional delay as claimed in claim 18, characterized in that, When the second period is longer than the first period, the second working time of the second partition signal of the converted data signal is longer than the first working time of the first partition signal of the converted data signal.

21. The transmitter circuit with additional delay as claimed in claim 11, characterized in that, The delay circuit includes at least one inverting unit, which is composed of two inverters connected in series, such that the at least one inverting unit receives the output signal of the first transmitter and generates the output signal of the second transmitter accordingly.

22. The transmitter circuit with additional delay as claimed in claim 21, characterized in that, The delay circuit also includes multiple inverting units, which are connected in series and receive the output signal of the first transmitter to generate the output signal of the second transmitter.

23. The transmitter circuit with additional delay as claimed in claim 1, characterized in that, The isolation barrier includes at least one set of isolation capacitors, one capacitor in the set of isolation capacitors being adapted to receive the output signal of the first transmitter and generate the first isolated output signal, and another capacitor in the set of isolation capacitors being adapted to receive the output signal of the second transmitter and generate the second isolated output signal.

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