High performance CMOS shot integrator

Abstract

This disclosure relates to high-performance CMOS shoot integrators. According to one aspect of the invention, a high-performance CMOS shoot integrator is provided. According to a second aspect of the disclosure, a method of using a high-performance CMOS shoot integrator is provided.

Description

[0001] Priority claims and cross-referencing of related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 726,820, filed December 2, 2024, entitled “HIGH PERFORMANCE CMOS SHOOTING INTEGRATOR”, the entire contents of which are incorporated herein by reference and are based. Technical Field

[0003] This invention relates to the field of data converters, and in particular to a high-performance CMOS shot integrator. Background Technology

[0004] Energy efficiency is a critical issue in data converters for sensing and instrumentation applications. In high-resolution switched-capacitor (SC) data converters, particularly delta-sigma converters, analog integrators typically consume most of the system power due to the need to drive large sampling and integrating capacitors to meet noise and speed requirements. Recent advances have focused on replacing traditional operational amplifiers (op-amps) in integrators with more efficient alternatives, such as dynamic amplifiers, ring amplifiers [1], floating inverter amplifiers [2] or other amplifier types, as well as topology techniques such as scaling [3], integrator slicing [4], pseudo-differential [5]. These devices and methods have significantly improved the efficiency of data converters. Despite these advances, fundamental trade-offs between noise, power, speed, and accuracy still exist in integrator design. Using integrators with virtual ground reference buffers can reduce their effective capacitive load, thereby reducing power consumption [6], but the noise and nonlinearity introduced by the buffers remain a problem. Zero-crossing (ZCB) based integrators can completely isolate their capacitive load from the drive circuitry [7]. However, even with overshoot correction, the large settling error caused by comparator delay limits the use of ZCBs only in medium-resolution analog-to-digital converters (ADCs). Integrators with capacitor stacks and buffers (CSB) inherit the efficiency of passive integrators [8], but their signal gain is close to unit 1. Although feasible, performing signal scaling, often required in delta-sigma modulators, or amplification, required in multiplicative digital-to-analog converters (MDACs) in pipelined analog-to-digital converters (ADCs), is quite challenging. CSB integrators are also sensitive to circuit parasitics.

[0005] Therefore, a higher performance CMOS integrator is needed. Summary of the Invention

[0006] In one aspect, this disclosure relates in part to systems and methods for implementing high-performance CMOS shooting integrators.

[0007] In one non-limiting aspect, this disclosure describes exemplary embodiments of a high-performance CMOS shoot-type integrator.

[0008] In another non-limiting aspect, this disclosure describes exemplary embodiments of a method using a high-performance CMOS shot integrator.

[0009] Additional features and advantages are described in the following detailed description and accompanying drawings, and will be apparent therefrom. The features and advantages described herein are not exhaustive; in particular, many additional features and advantages will be apparent to those skilled in the art from the accompanying drawings and description. Furthermore, no particular embodiment is required to possess all the advantages listed herein, and it is expressly intended that various advantageous embodiments be claimed individually. Moreover, it should be noted that the language used in the specification has been chosen primarily for readability and pedagogical purposes, and not to limit the scope of the subject matter of the invention. Attached Figure Description

[0010] Figures 1-4 A simplified diagram of a prior art switched capacitor integrator is shown.

[0011] Figure 5A and Figure 5B A circuit diagram of a high-performance CMOS shot integrator according to an exemplary embodiment of the present disclosure is shown.

[0012] Figure 6 An example frequency response of an amplifier used in a high-performance CMOS shot integrator according to an example embodiment of this disclosure is shown.

[0013] Figure 7 The image shows the signal waveforms at key nodes in the sampling and integration phases of a high-performance CMOS shot integrator according to an example embodiment of the present disclosure.

[0014] Figure 8 The stable behavior of a high-performance CMOS shot integrator according to an exemplary embodiment of this disclosure is shown.

[0015] Figure 9 A noise model of a high-performance CMOS shot integrator according to an exemplary embodiment of this disclosure is shown.

[0016] Figure 10 A circuit diagram is shown for a pseudo-differential implementation of a high-performance CMOS shot integrator with a passive common-mode cancellation scheme according to an embodiment of the present invention.

[0017] Figure 11An example implementation of an amplifier used in a high-performance CMOS shot integrator according to an example embodiment of this disclosure is shown. Detailed Implementation

[0018] This disclosure generally relates to high-performance CMOS shoot-type integrators. Various embodiments may include switched-capacitor (SC) shoot-type integrators that utilize uncompensated feedback loops and barrier resistors to achieve precise charge transfer. In various embodiments, the power consumption of the error amplifier in a high-performance CMOS shoot-type integrator as disclosed herein may be independent of the sampling and / or integrating capacitor size and / or integrator settling speed. In various embodiments, a high-performance CMOS shoot-type integrator as disclosed herein may be affected only by a half-normal noise distribution, thereby reducing the integrator's noise power.

[0019] Figure 1 , Figure 2 , Figure 3 and Figure 4 Various prior art embodiments of switched capacitor (SC) integrators are described.

[0020] Figure 5A and Figure 5B A high-performance CMOS shot integrator according to an example embodiment of the present disclosure is illustrated. The high-performance CMOS shot integrator may include an error amplifier A. e 501. Switch 505 can supply or limit power to error amplifier 501. The high-performance CMOS shot integrator may also include a control transistor M. c 506. Barrier resistor R b 508A, sampling capacitor C s 510. Integrating capacitor C i 512 and / or various switches 514-517 controlled by two non-overlapping clock phases. In various embodiments, for example... Figure 5A Example embodiment, blocking resistor R b 508A can be used with node v s 520 connected. In other embodiments, for example... Figure 5B Example embodiment, blocking resistor R b 508B can communicate with node V b 522 connected. The integrator performance may be invariant regardless of the placement of the blocking resistor. Integrating capacitor C i 512 Reference ground or common-mode voltage, not as Figure 1 and Figure 2 In some embodiments, it is connected around a virtual ground force or sense amplifier. Figure 5A and Figure 5BDuring the sampling phase, switches 514 and 516 are closed, while switches 505, 515, and 517 are open. During the sampling phase, the sampling capacitor C... s At the first node of 510, the input voltage V in 503 performs sampling. In some embodiments, during the integration phase, switches 514 and 516 are open, and switches 505, 515, and 517 are closed. Therefore, the sampling capacitor C... s The second node of 510 is set to the bias voltage V. b Circuit node v c and v s Accordingly, it is boosted to V in +V b In some embodiments, the control transistor M c The 506 exhibits a small gate capacitance as error amplifier A. e The load is 501. During the integration phase, the error amplifier A... e 501 is powered and drives the load to the amplifier output voltage V. g 530, turn on control transistor M c 506 and trigger from C s 510 via M c 506 to C i 512 unidirectional charge transfer. This charge transfer can be referred to herein as "shooting". In most embodiments, node v s The voltage at 520 is higher than the output voltage V. o 535, to achieve from C s 510 to C i Unidirectional charge transfer at 512. In Figure 5A In, as the current i s With an increase of 540, the voltage drop across the blocking resistor 508A is i s ·R b A reduction relative to 520. In many embodiments, if v s Less than V b， i.e. i s 540 to Large, due to amplifier A e Due to the phase shift, vg will begin to decrease after a short delay. During this rise-fall cycle of vg, a small amount of charge is transferred from the sampling capacitor C. s Transferred to integrating capacitor C i The decrease of vg then makes v s Higher than V b Repeat the charge transfer process described above. When A eWhen it is an uncompensated two- or multi-stage operational amplifier, the integrator will oscillate if designed to intentionally meet the Barkhausen stability criteria. In various embodiments, the sampling capacitor C s To the integrating capacitor C i The discharge will suppress the oscillation. In fact, v s Its behavior is like an oscillating virtual ground. From the sampling capacitor C s To the integrating capacitor C i The charge transfer repeats until v c、 v s and V b Approximately equal, V at sampling period n o Approximately equal to V o [n-1]+V in ·C s / C i In various embodiments, the control transistor M c Upon entering the weakly inverse region, the integration completes after a short period of linear stability. In some embodiments, the duration of the integration may depend on the resolution requirements.

[0021] Figure 6 An example frequency response of the error amplifier used in a high-performance CMOS shot integrator according to an exemplary embodiment of this disclosure is shown. Figure 6 In the middle, when A e The phase shift reaches -180 ° At that time, v s With frequency f s Oscillation. In Figure 6 In the diagram, p1 is A e The dominant pole, p2 is A e In-band non-dominant pole, p3 is an A pole outside unity-gain bandwidth. e The first extreme point. Once the Barkhausen standard A st ·g mc ·R b The value ≥1 no longer holds, and the oscillation may stop because more charge is transferred to C. i M c transconductance g mc Decrease, A st The error amplifier is at a phase shift of -180° ° Open-loop gain at time, g mc It is M c Mutual guidance.

[0022] Figure 7 The diagram illustrates some key signal waveforms during the sampling and integration phases of a high-performance CMOS shot-type integrator according to an example embodiment of this disclosure. During operation, v sIt contains three signal components: a DC component, a frequency of f s The high-frequency components and low-frequency signals, they are expressed in R b The time constant of Cs decays exponentially, causing v c Stable to V b For the integrator output V o Its mathematical expression is It follows v c The stable envelope, and A e It is unrelated to speed.

[0023] Figure 8 Stable behavior of a high-performance CMOS shot integrator according to an example embodiment of the present disclosure is shown. Figure 8 The embodiment illustrates the time-varying output voltage Vo 835 of a high-performance CMOS shooting integrator. The shooting steps 801 represent the transfer of charge from the sampling capacitor C. s Transferred to integrating capacitor C i In various embodiments, the error amplifier A of the high-performance CMOS shot integrator e It may consume a small amount of electrical power to drive an fF-level load in order to keep its unity-gain frequency fu above 1 / (2πRbCs). At the end of the integration process, A e It can handle residuals close to DC. At the end of the integration process, amplifier A... e The static stability error caused by the gain and amplifier A e The DC gain is inversely proportional to the DC gain. This can be achieved through R... b and M c Size to prevent A e Entering its conversion-limited region. Overall, this integrator can achieve accurate charge transfer without the need for dynamic loop compensation as required by ring amplifier-based integrators [1], or overshoot correction as required by ZCB integrators [7]. In various embodiments, amplifier A e It can be independent of the sampling capacitor C s Size, Integrating Capacitor C i The size and / or integrator stabilization speed. Apart from DC gain and pole location, analog specifications such as linearity, output swing, and output common-mode level are not important.

[0024] Figure 9 A noise model of a high-performance CMOS shoot-type integrator according to an example embodiment of the present disclosure is shown. In some embodiments, when the integrator is stable, the control transistor of the high-performance CMOS shoot-type integrator, such as control transistor M, ... c906 may be nearing cutoff. In this case, noise present at the drain of the control transistor may affect the integrator output voltage V. o The impact is minimal. In some embodiments, only the amplifier output v is affected. g 930. Positively varying circuit noise can increase current i. s 940, thus triggering a noise charge flow. Therefore, when reference amplifier A... e Undesirable noise v when the 901 is a non-inverting input n 981 may follow a semi-normal distribution. 982. n This half-normal distribution may only include about 36% (i.e., 1-2 / π) of the amplifier's inherent noise power. In various embodiments, the noise charge may be generated solely by the sampling capacitor C. s 910 is provided. Therefore, as more noise charge accumulates in the integrating capacitor C i In 912, the voltage v c v s and v g It may decrease. Therefore, the integrator will be primarily affected by the noise v experienced during integration. n The maximum amplitude of the noise is affected. Therefore, in differential or pseudo-differential implementations, both the positive and negative paths track their respective maximum noise amplitudes, which can be partially canceled (subtracted) during common-mode cancellation. Although amplifier A e The power consumption is very small, but in various embodiments, given sufficient integration time, amplifier A can be suppressed. e Approximately 75% of the noise power. Residual low-frequency noise can be further suppressed by chopping between the two paths in a differential or pseudo-differential implementation.

[0025] Figure 10 A circuit diagram of a pseudo-differential implementation of a high-performance CMOS shot-type integrator with a passive common-mode cancellation scheme according to an embodiment of the present invention is shown. In various embodiments, during the sampling phase, switches 1014A, 1014B, 1016A, 1016B, 1018A, and 1018B are closed, and switches 1005A, 1005B, 1015A, 1015B, 1017A, and 1017B are open. In some embodiments, during the integration phase, switches 1014A, 1014B, 1016A, 1016B, 1018A, and 1018B are open, and switches 1005A, 1005B, 1015A, 1015B, 1017A, and 1017B are closed. The first integrating capacitor 1012A and the second integrating capacitor 1012B reference the common-mode voltage V. cm1070. After each integration (during sampling), the first integrating capacitor 1012A and the second integrating capacitor 1012B are cross-connected by closing switches 1018A and 1018B to eliminate common-mode content of the integrating input. The upper and lower paths are choppered by choppers 1019A and 1019B to suppress low-frequency noise.

[0026] Figure 11 An example implementation of an amplifier (e.g., an error amplifier) ​​used in a high-performance CMOS shot integrator according to an exemplary embodiment of this disclosure is shown. The amplifier in the high-performance CMOS shot integrator, such as... Figure 11 The amplifier can be a two-stage operational amplifier without frequency compensation. Figure 11 In the amplifier, the first amplification stage may include NMOS differential pairs 1101 and 1102. In some embodiments, a PMOS current mirror including PMOS transistors 1105 and 1106 may load the first amplification stage. In various embodiments, the second amplification stage may include a PMOS input transistor 1111 with an NMOS load 1112. In various embodiments, a current mirror including transistors 1121 and 1122 may load a bias current I. b 1130 is mirrored to the first amplification stage. Various transistors 1141, 1142, 1143, and 1144 enable or disable the amplifier according to complementary control signals en and en'. In some embodiments, the complementary control signals en and en' can be generated externally. In other embodiments, for example, the complementary control signals en and en' can be generated internally within the inverter.

[0027] References cited: [1] B. Hershberg et al., “Ring Amplifier with Switched Capacitor Circuit”, ISSCC, pp. 460-462, 2012; [2] Y. Liu et al., “Incremental Zoom ADC Based on 4.96μW 15b Self-Timing Dynamic Amplifier”, ISSCC, pp. 170-172, February 2022; [3] L. Jie et al., “0.014mm2 10kHz BW Zoom Incremental Counting ADC with 103dB SNDR and 100dB Full-Scale CMRR”, ISSCC, pp. 1-3, February 2022; [4] P. Vogelmann et al., “1.1mW 200kS / s Incremental Δ∑ ADC with DR of 91.5dB and Dynamic Power Reduction Using Integrator Limiting”, ISSCC, pp. 236-238, February 2018; [5] CY Lee et al., “At 180nm 0.0375mm² 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring Amplifier-Based Integrator in CMOS, ISSCC, pp. 412-414, February 2022; [6] HHBoo et al., “12b 250MS / S Pipeline ADC with Virtual Ground Reference Buffer”, ISSCC, pp. 1-3, February 2015; [7] HSLee et al., “Ultra-Low Power A / D Converter Based on Zero Crossing”, Proc. IEEE, Vol. 98, No. 2, pp. 315-332, February 2010; [8] J. Liu et al., “250kHz BW 93dB SNDR Fourth Order Noise Shaping SAR Using Capacitor Stacking and Dynamic Buffering”, ISSCC, pp. 369-371, February 2021; [9] MAMokhtar et al., “Implementation of 104dB "40kS / s Uncalibrated Incremental Δ∑ADC with DR and 105.7dB SFDR", ESSCIRC, pp. 401-404, September 2023;

[10] J.-S. Huang et al., "A Multi-Stage Fifth-Order Incremental Δ∑ Analog-to-Digital Converter for Sensor Interface", JSSC, Vol. 58, No. 10, pp. 2733-2744, October 2023; and

[11] C. Chen et al., "Incremental Δ∑ADC Based on 1V 14b Self-Timing Zero Crossing", ISSCC, pp. 274-275, February 2013.

[0028] It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. These changes and modifications can be made without departing from the spirit and scope of the subject matter and without diminishing its intended advantages. Therefore, the appended claims are intended to cover such changes and modifications.

Claims

1. An integrator, comprising: An amplifier, wherein the inverting input of the amplifier is electrically connected to an electrical bias voltage; The first switch is electrically connected to the power rail and power supply of the amplifier. An NMOS transistor is provided, wherein the gate terminal of the NMOS transistor is electrically connected to the output terminal of the amplifier, and wherein the drain terminal of the NMOS transistor is electrically connected to the non-inverting input of the amplifier. An integrating capacitor, wherein the integrating capacitor is electrically connected to the source terminal and the common node of the NMOS transistor; A resistor, which is electrically connected to the non-inverting input of the amplifier and the second switch; A sampling capacitor, the sampling capacitor including a first terminal and a second terminal, wherein the first terminal is electrically connected to a second switch and a third switch, and wherein the second terminal is electrically connected to a fourth switch and a fifth switch.

2. The integrator according to claim 1, wherein, The resistor is placed between the electrical bias voltage and the second switch.

3. The integrator according to claim 1, wherein, The resistor is placed between the second switch and the sampling capacitor.

4. The integrator according to claim 1, wherein, The resistor is placed at V c Between the node and the fourth switch.

5. The integrator according to any one of claims 1, 2, 3, and 4, wherein, The resistor is implemented using a metal resistor, a polysilicon resistor, or a MOS transistor.

6. The integrator according to any one of claims 1, 2, 3, 4, and 5, wherein, The resistor is programmable.

7. The integrator according to claim 1, wherein, The sampling capacitor and the integrating capacitor are programmable.

8. The integrator according to claim 1, wherein, The electrical bias voltage is one of constant, time-varying, or programmable.

9. The integrator according to claim 1, wherein, The NMOS transistor is implemented using PMOS, and the input polarity of the amplifier is switched to enable the circuit to operate.

10. The integrator according to any one of claims 1 and 9, wherein, The NMOS or PMOS transistor is programmable.

11. The integrator according to claim 1, wherein, The amplifier is implemented using a two-stage or multi-stage topology.

12. The integrator according to claim 1, wherein the first switch, the second switch, the third switch, the fourth switch, or the fifth switch is implemented using at least one of NMOS, PMOS, and CMOS transmission gates.

13. The integrator according to claim 1, wherein, The first switch is used to enable or disable the amplifier bias current, rather than the power rail.

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