An interconnect structure and design method for AC-coupled capacitor pads

Abstract

This invention relates to an interconnect structure and design method for AC-coupled capacitor pads, belonging to the field of circuit board design technology. It includes: a PCB substrate; differential pair signal vias disposed on the PCB substrate, penetrating multiple metal layers of the PCB substrate; AC-coupled capacitor pads stacked on the surface layer of the PCB substrate, adjacent to the differential pair signal vias; differential pair return ground vias disposed on the PCB substrate, surrounding the differential pair signal vias; high-speed differential signal lines, divided into multi-segment structures to achieve one-to-many signal transmission; and an impedance matching component integrated on the PCB substrate, adapted to the differential pair signal vias and the AC-coupled capacitor pads, used to balance impedance fluctuations during signal transmission and ensure impedance continuity. This invention addresses the technical problem in existing technologies where, for one-to-many interconnect scenarios involving high-speed differential pairs, there is a lack of optimal layout and routing schemes, resulting in an inability to effectively balance impedance fluctuations and consequently poor signal integrity.

Description

Technical Field

[0001] This invention belongs to the field of circuit board design technology, and specifically relates to an interconnection structure and design method for AC coupling capacitor stacked pads. Background Technology

[0002] As the basic carrier of signal transmission in electronic devices, the PCB's high-quality layout and routing design determines the product design quality, and signal integrity design is the most critical aspect, especially for high-speed signals such as PCIe, SAS, and SATA. Designs with impedance discontinuities can lead to serious signal quality problems, specifically manifested in large impedance fluctuations, return loss exceeding specifications, and the presence of resonant points in the insertion loss curve within the operating frequency range.

[0003] The existing design scheme is a one-to-one, end-to-end interconnection of devices. The AC coupling capacitor uses an inner layer with a hollowed-out anti-pad area to balance the impedance fluctuation. Moreover, when the AC coupling capacitor is close to the differential pair via, the impedance continuity of the via must also be considered. The capacitor + via area needs to be combined for simulation optimization to obtain a better passive optimization scheme.

[0004] The existing technology has at least the following problems in its use: For one-to-many interconnect scenarios, there is no optimal layout and routing scheme to balance impedance fluctuations at the AC coupling capacitor. Summary of the Invention

[0005] This invention provides an interconnect structure and design method for AC-coupled capacitor stacked pads, which solves the technical problem in the prior art that, for one-to-many interconnect scenarios of high-speed differential pair signals, there is a lack of optimal layout and routing schemes, which cannot effectively balance impedance fluctuations and thus lead to poor signal integrity.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: An interconnect structure of AC-coupled capacitor pads includes: a PCB substrate, providing a basic mounting carrier for high-speed differential signal transmission; differential pair signal vias disposed on the PCB substrate, penetrating multiple metal layers of the PCB substrate, for realizing the transfer of high-speed differential signals on different trace layers of the PCB substrate; AC pads, stacked on the surface layer of the PCB substrate, adjacent to the differential pair signal vias, for soldering AC coupling capacitors and realizing signal coupling transmission; and return ground vias disposed on the PCB substrate, surrounding the differential pair signal vias, for providing a return path for high-speed differential signals and suppressing signal interference; and high-speed differential signals... The signal line is divided into a multi-segment structure, specifically including a high-speed differential signal line A, a surface signal line, a high-speed differential signal line B, and a high-speed differential signal line C. High-speed differential signal line A connects the transmitting device to the AC pad, the surface signal line connects the differential pair signal via to the AC pad, and high-speed differential signal lines B and C connect the AC pad to multiple receiving devices, respectively, to achieve one-to-many signal transmission. An impedance matching component, integrated on the PCB substrate, is adapted to the differential pair signal via and the AC pad to balance impedance fluctuations during signal transmission and ensure impedance continuity.

[0007] Furthermore, the differential signal vias are configured as a symmetrical structure of two in a group, with a center-to-center distance of 40 mil between the two differential signal vias and a diameter of 8 mil for the differential signal vias; the center-to-center distance between the return ground via and the differential signal via is 40 mil, and the diameter of the return ground via is 8 mil.

[0008] Furthermore, the AC pads and the differential pair signal vias are directly connected via surface signal lines. The center-to-center spacing of the AC pads is 50 mil, the pad width is 20 mil, and the edge spacing between two adjacent AC pads is 100 mil.

[0009] Furthermore, the high-speed differential signal line is divided into a transmitting segment, a via capacitor segment, and a receiving segment. The transmitting segment is a high-speed differential signal line A, which is a non-surface trace and is located on the inner or bottom layer of the PCB substrate. The via capacitor segment is a surface signal line, which is a surface trace and connects the differential pair signal via to the AC pad. The receiving segment includes high-speed differential signal lines B and C, which are connected to multiple receiving devices to realize one-to-many split transmission of high-speed differential signals.

[0010] Furthermore, the impedance matching component includes an AC coupling capacitor antipad cutout structure and a differential pair via antipad cutout structure. The cutout width of the AC coupling capacitor antipad cutout structure is adapted to the width of the AC pad, and the cutout width of the differential pair via antipad cutout structure is 26mil.

[0011] Furthermore, the AC coupling capacitor anti-pad hollowing structure only hollows out the second and third metal layers adjacent to the surface layer of the PCB substrate, with the fourth metal layer as the reference layer; if the AC pad is located on the bottom layer of the PCB substrate, the penultimate and penultimate metal layers are symmetrically hollowed out, with the penultimate metal layer as the reference layer; the differential pair via anti-pad hollowing structure hollows out all metal layers of the PCB substrate.

[0012] Furthermore, the design method based on the above interconnect structure includes the following steps: sequentially completing the PCB substrate stack-up and differential pair signal vias, the placement of return ground vias, the stacking of AC pads and the routing of high-speed differential signal lines, the fabrication of the anti-pad cutout structure, SI simulation verification and parameter optimization. During the simulation verification process, the focus is on detecting impedance fluctuation, return loss and insertion loss curve indicators, and the structural parameters are iteratively optimized based on the results.

[0013] This invention provides an interconnect structure and design method for AC-coupled capacitor stacked pads. The advantages are as follows: By combining AC-coupled capacitor pads with differential pair signal vias and return ground vias in a stacked pad design, a one-to-many interconnect layout for high-speed differential signals is achieved, filling a gap in existing technologies for this scenario; by setting up multiple high-speed differential signal lines and defining routing layers, along with standardized via and pad spacing designs, the rationality of the signal transmission path is ensured, reducing signal transmission loss; by designing a layered, hollowed-out anti-pad structure to form an impedance matching component, impedance fluctuations during signal transmission are precisely balanced, ensuring impedance continuity and improving signal integrity; through iterative optimization using SI simulation technology, the parameters of the interconnect structure are adapted to different PCB stack-ups and high-speed signal output layers, ensuring that impedance fluctuations, return loss, and other indicators meet the requirements of high-speed signal transmission; by placing return ground vias around the differential pair signal vias, a stable return path is provided for high-speed differential signals, effectively suppressing signal interference and further improving signal transmission quality in one-to-many interconnect scenarios. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the interconnection structure of an AC coupling capacitor stacked pad provided in an embodiment of the present invention; Figure 2 A top-view flow path for an interconnect structure of AC-coupled capacitor stacked pads provided in an embodiment of the present invention; Figure 3 This is another top-view flow path for an interconnect structure of AC-coupled capacitor stacked pads provided in an embodiment of the present invention; Figure 4 A schematic diagram of the parameter design distribution of an AC-coupled capacitor stacked pad interconnect structure provided in an embodiment of the present invention; Figure 5 This invention provides a schematic diagram of the dimensions of the anti-pad cutout area for AC coupling capacitor stacked pads in an embodiment of the invention. Figure 6 A schematic diagram illustrating a one-to-many interconnect scenario for PCB layout and routing impedance continuity design according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a PCB stack-up cross-section provided in an embodiment of the present invention.

[0016] In the diagram: 101-High-speed differential signal line A; 102-Differential pair signal via; 103-Surface signal line; 104-AC pad; 105-High-speed differential signal line B; 106-High-speed differential signal line C; 107-Return ground via. Detailed Implementation

[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0018] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0019] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to welding, bolting, or riveting; they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] Example: like Figures 1 to 6 As shown, this embodiment provides an interconnect structure and design method for AC coupling capacitor stacked pads, including: a PCB substrate, providing a basic layout carrier for high-speed differential signal transmission; differential pair signal vias 102, disposed on the PCB substrate, penetrating multiple metal layers of the PCB substrate, used to realize the transfer of high-speed differential signals on different trace layers of the PCB substrate; AC pads 104, stacked on the surface layer of the PCB substrate, adjacent to the differential pair signal vias 102, used to solder AC coupling capacitors and realize signal coupling transmission; return ground vias 107, disposed on the PCB substrate, surrounding the differential pair signal vias 102, used to provide a return path for high-speed differential signals and suppress signal interference; and high-speed differential signal lines, divided into multiple... The segmented structure specifically includes a high-speed differential signal line A101, a surface signal line 103, a high-speed differential signal line B105, and a high-speed differential signal line C106. High-speed differential signal line A101 connects the transmitting device to the AC pad 104; surface signal line 103 connects the differential pair signal via 102 to the AC pad 104; and high-speed differential signal lines B105 and C106 connect the AC pad 104 to multiple receiving devices, respectively, to achieve one-to-many signal transmission. An impedance matching component, integrated on the PCB substrate, is adapted to the differential pair signal via 102 and the AC pad 104 to balance impedance fluctuations during signal transmission and ensure impedance continuity.

[0022] In this embodiment, the PCB substrate uses FR-4 fiberglass epoxy board. Based on the transmission frequency requirements of high-speed differential signals (PCIE / SAS / SATA), a 4-8 layer stack-up design is selected. The metal layer uses electrolytic copper with a thickness of 1 oz. The dielectric constant of the substrate is controlled within the range of 4.2 ± 0.2, providing a stable physical and electrical foundation for the overall interconnect structure. The differential pair signal vias 102 and return ground vias 107 are both processed by mechanical drilling, with drilling accuracy controlled within ± 0.5 mil. The via walls are treated with copper plating to ensure conductivity.

[0023] Furthermore, the differential signal vias 102 are configured as a pair of symmetrical structures, with a center-to-center distance of 40 mil between the two differential signal vias 102 and a diameter of 8 mil; the center-to-center distance between the return ground via 107 and the differential signal vias 102 is 40 mil, and the diameter of the return ground via 107 is 8 mil.

[0024] In this embodiment, as Figure 4 The figure shows the detailed parameter design of the design scheme of the present invention, wherein: D1: Differential pair signal via 102 - the center-to-center distance of the differential pair signal via 102; D2: Center-to-center distance between differential pair signal via 102 and return ground via 107; D3: Center distance of AC pads 104; D4: Diameter of differential pair signal via 102; D5: 107mm diameter return hole; like Figure 5 The diagram shows the dimensions of the anti-pad cutout area, where: L1: Distance between the edge of AC pad 104 and the edge of the pad, usually taken as 100mil; L2: AC pad width 104, usually taken as 20mil; L3: Width of differential pair via anti-pad, typically 26mil; The anti-solder pads of the AC coupling capacitors require the L2 and L3 layers to be hollowed out, with reference to the L4 layer. If the device is placed on the L1 layer, and if it is placed on the bottom layer, a symmetrical design should be used, hollowing out the second-to-last and third-to-last layers, with reference to the fourth-to-last layer. The differential pair signal vias 102 are arranged symmetrically in the signal transition area of ​​the PCB substrate. Two return ground vias 107 are symmetrically arranged next to each group of differential pair signal vias 102, forming a "signal via + ground via" combination structure. The spacing deviation between the ground vias and signal vias does not exceed ±1 mil, and the machining deviation of the via diameter is controlled within ±0.3 mil to ensure the symmetry and stability of the return path.

[0025] Furthermore, the AC pad 104 and the differential pair signal via 102 are directly connected via a surface signal line 103. The center-to-center spacing of the AC pads 104 is 50 mil, the pad width is 20 mil, and the edge spacing between two adjacent AC pads 104 is 100 mil.

[0026] In this embodiment, the AC pad 104 adopts a square pad design with a tin-plated surface and a tin layer thickness of 2-3μm. The surface signal line 103 between the AC pad 104 and the differential pair signal via 102 has a trace width of 8mil and a trace length controlled within 50mil to reduce signal loss of the surface trace. The center spacing and edge spacing of the pads are processed according to standardized dimensions to accommodate AC coupling capacitors in 0402 and 0603 packages.

[0027] Furthermore, the high-speed differential signal line is divided into a transmitting segment, a via capacitor segment, and a receiving segment. The transmitting segment is a high-speed differential signal line A101, which is a non-surface trace and is located on the inner or bottom layer of the PCB substrate. The via capacitor segment is a surface signal line 103, which is a surface trace and connects the differential pair signal via 102 to the AC pad 104. The receiving segment includes high-speed differential signal lines B105 and C106, which are connected to multiple receiving devices to realize one-to-many split transmission of high-speed differential signals.

[0028] In this embodiment, the high-speed differential signal line A101 of the transmitting end segment is laid on the second layer (inner layer) or the penultimate layer (bottom layer) of the PCB substrate. The trace adopts a differential equal-length design with an equal-length deviation of no more than 2mil, a trace width of 6mil, a line spacing of 8mil, and a characteristic impedance controlled at 100Ω±10%. The surface signal line 103 of the via capacitor segment is a short surface trace to minimize trace bends and avoid impedance abrupt changes. The high-speed differential signal line B105 of the receiving end segment connects the receiving device 2 to the AC pad 104, and the high-speed differential signal line C106 connects the receiving device 1 to the AC pad 104. All traces maintain differential equal length and characteristic impedance matching to achieve one-to-many signal uniform splitting.

[0029] Furthermore, the impedance matching component includes an AC coupling capacitor antipad cutout structure and a differential pair via antipad cutout structure. The cutout width of the AC coupling capacitor antipad cutout structure is adapted to the width of the AC pad 104, and the cutout width of the differential pair via antipad cutout structure is 26mil.

[0030] In this embodiment, the cutout width of the AC coupling capacitor anti-pad cutout structure is the same as the width of the AC pad 104, which is 20 mil. The cutout area is the metal layer area below the AC pad 104, and the distance between the edge of the cutout area and the edge of the AC pad 104 is 5 mil. The differential pair via anti-pad cutout structure is a circular cutout area with a cutout width of 26 mil. With the center of the differential pair signal via 102 as the center, the distance between the edge of the cutout area and the edge of the differential pair signal via 102 is 9 mil, ensuring the effectiveness of impedance matching.

[0031] Furthermore, the AC coupling capacitor anti-pad hollowing structure only hollows out the second and third metal layers adjacent to the surface layer of the PCB substrate, with the fourth metal layer as the reference layer; if the AC pad 104 is located on the bottom layer of the PCB substrate, the penultimate second and third metal layers are symmetrically hollowed out, with the penultimate fourth metal layer as the reference layer; the differential pair via anti-pad hollowing structure hollows out all metal layers of the PCB substrate.

[0032] In this embodiment, as Figure 7 As shown, layers L1, L2, ... Ln are conductor layers, with dielectric filling between them. The pads for the AC coupling capacitors are located on the top / bottom of the PCB (i.e., layers L1 and Ln), with the reference plane being the 4th layer / 4th from the bottom (i.e., layer L4 / Ln-3). If the AC pad 104 is located on the top layer of the PCB substrate (layer L1), the corresponding metal layers of layers L2 and L3 are removed, leaving layer L4 as the reference ground layer. The removed areas are processed using a chemical etching process, with etching accuracy controlled within ±0.5mil. If the AC pad 104 is located on the bottom layer (layer Ln), layers Ln-1 and Ln-2 are symmetrically removed, leaving layer Ln-3 as the reference ground layer. The anti-pad removal structure of the differential pair signal via 102 etches the corresponding areas of all metal layers to ensure impedance consistency of the vias across all layers.

[0033] Furthermore, the design method based on the above interconnect structure includes the following steps: Step 1: Based on the transmission requirements of high-speed differential signals, determine the stack-up design scheme of the PCB substrate, and complete the hole layout of differential pair signal vias 102 and return ground vias 107 on the PCB substrate to ensure that the hole spacing and hole diameter meet the basic requirements of impedance matching. Step 2: Complete the stacking layout of AC pad 104 on the surface layer of the PCB substrate, so that the pad is adjacent to and corresponds to the differential pair signal via 102. Then, perform segmented routing of high-speed differential signal lines to complete the routing connection of high-speed differential signal line A101, surface signal line 103, high-speed differential signal line B105 and high-speed differential signal line C106. Step 3: Based on the layout positions of AC pad 104 and differential pair signal via 102, process the anti-pad cutout structure of the impedance matching component on the PCB substrate, and complete the cutout process of the corresponding metal layer as required. Step 4: Perform signal integrity simulation verification on the overall interconnect structure using SI simulation technology. Adjust parameters such as hole spacing, pad size, and anti-pad cutout range based on the simulation results until the impedance fluctuation, return loss, and other indicators meet the requirements of high-speed differential signal transmission.

[0034] In this embodiment, step one involves using AllegroPCB design software to complete the PCB stack-up and via placement. During the stack-up design, the reference ground layer and signal layer are placed adjacent to each other to reduce signal crosstalk. Step two involves completing the AC pad 104 stack-up and high-speed differential signal line routing in the software, strictly adhering to the design rules of differential equal length and impedance matching. Step three involves outputting the anti-pad cutout processing file through CAM350 software and handing it over to the PCB manufacturing plant for etching. Step four involves using SigrityPowerSI software for SI simulation, with the simulation frequency covering the operating frequency of high-speed signals. During the simulation, a three-dimensional model is established to simulate the actual signal transmission environment.

[0035] Furthermore, during the SI simulation verification process, the impedance fluctuation range, return loss value, and insertion loss curve within the operating frequency range are the main focus of detection. If a resonance point appears in the insertion loss curve, the structural parameters of the impedance matching component and the routing layout of the high-speed differential signal line are re-optimized.

[0036] In this embodiment, the criteria for SI simulation are: impedance fluctuation range controlled within ±10Ω, return loss ≤-15dB, and insertion loss curve without obvious resonance point within the operating frequency range. If the criteria are not met, first adjust the size and range of the anti-pad cutout, then optimize the routing bends and lengths of the high-speed differential signal lines, and finally fine-tune the hole positions and pad spacing until all criteria are met, and the final design scheme is output.

[0037] In summary, this invention patent, through a stacked pad layout design, organically combines the AC pad 104 with the differential pair signal via 102 and the return ground via 107, achieving an innovative layout and routing scheme for high-speed differential signal one-to-many interconnection scenarios, filling a gap in existing technology. Through a multi-segment high-speed differential signal line layered routing design and standardized via and pad parameter settings, the rationality of the signal transmission path is ensured, reducing signal loss and crosstalk during transmission. Furthermore, the layered, hollowed-out anti-pad structure forms an impedance matching component, precisely balancing impedance fluctuations and ensuring impedance continuity. This design effectively solves the signal quality problem caused by impedance discontinuity. Through iterative optimization using SI simulation technology, the parameters of the interconnect structure can be adapted to different PCB stack-ups and high-speed signal output layers, improving the versatility and adaptability of the solution. The combination design of differential pair signal vias 102 and return ground vias 107 provides a stable return path for high-speed differential signals, suppresses signal interference, and significantly improves signal integrity in one-to-many interconnect scenarios. It can be widely used in high-speed signal PCB design in fields such as power electronics, automotive electronics, communication equipment, and server technology.

[0038] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope described in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An interconnection structure for AC-coupled capacitor pads, characterized in that, include: PCB substrates provide the basic layout carrier for high-speed differential signal transmission; Differential pair signal vias are provided on the PCB substrate and penetrate multiple metal layers of the PCB substrate to realize the transfer of high-speed differential signals on different trace layers of the PCB substrate. AC pads are stacked on the surface of the PCB substrate and arranged adjacent to the differential pair signal vias. They are used to solder AC coupling capacitors and realize signal coupling transmission. A return via is provided on the PCB substrate and arranged around the differential pair signal via to provide a return path for high-speed differential signals and suppress signal interference. The high-speed differential signal line is divided into a multi-segment structure, specifically including high-speed differential signal line A, surface signal line, high-speed differential signal line B, and high-speed differential signal line C. High-speed differential signal line A is connected between the transmitting device and the AC pad, the surface signal line is connected between the differential pair signal via and the AC pad, and high-speed differential signal lines B and C are respectively connected between the AC pad and multiple receiving devices to achieve one-to-many signal transmission. An impedance matching component, integrated on the PCB substrate, is adapted to the differential pair signal vias and the AC pads to balance impedance fluctuations during signal transmission and ensure impedance continuity.

2. The interconnection structure of AC-coupled capacitor stacked pads according to claim 1, characterized in that, The differential signal vias are configured in a symmetrical structure of two pairs, with a center-to-center distance of 40 mil between the two differential signal vias and a diameter of 8 mil. The center-to-center distance between the return ground via and the differential signal via is 40 mil, and the diameter of the return ground via is 8 mil.

3. The interconnection structure of AC-coupled capacitor stacked pads according to claim 1, characterized in that, The AC pads are directly connected to the differential pair signal vias via surface signal lines. The center-to-center spacing of the AC pads is 50 mil, the pad width is 20 mil, and the edge spacing between two adjacent AC pads is 100 mil.

4. The interconnection structure of AC-coupled capacitor stacked pads according to claim 1, characterized in that, The high-speed differential signal line is divided into a transmitting segment, a via capacitor segment, and a receiving segment. The transmitting segment is a high-speed differential signal line A, which is a non-surface trace and is located on the inner or bottom layer of the PCB substrate. The via capacitor segment is a surface signal line, which is a surface trace and connects the differential pair signal via to the AC pad. The receiving segment includes high-speed differential signal lines B and C, which are connected to multiple receiving devices to realize one-to-many split transmission of high-speed differential signals.

5. The interconnection structure of AC-coupled capacitor stacked pads according to claim 1, characterized in that, The impedance matching component includes an AC coupling capacitor antipad cutout structure and a differential pair via antipad cutout structure. The cutout width of the AC coupling capacitor antipad cutout structure is adapted to the width of the AC pad, and the cutout width of the differential pair via antipad cutout structure is 26mil.

6. The interconnection structure of AC-coupled capacitor stacked pads according to claim 5, characterized in that, The AC coupling capacitor anti-pad hollowing structure only hollows out the second and third metal layers adjacent to the surface layer of the PCB substrate, with the fourth metal layer as the reference layer; if the AC pad is located on the bottom layer of the PCB substrate, the penultimate and penultimate metal layers are symmetrically hollowed out, with the penultimate metal layer as the reference layer; the differential pair via anti-pad hollowing structure hollows out all metal layers of the PCB substrate.

7. An interconnect design method for AC-coupled capacitor stacked pads, characterized in that, The interconnection structure based on the AC coupling capacitor stacked pads according to claim 6 includes the following steps: Step 1: Based on the transmission requirements of high-speed differential signals, determine the stack-up design scheme of the PCB substrate, and complete the hole layout of differential pair signal vias and return ground vias on the PCB substrate to ensure that the hole spacing and hole diameter meet the basic requirements of impedance matching. Step 2: Complete the stacking and layout of AC pads on the surface layer of the PCB substrate, so that the pads are adjacent to and correspond to the differential pair signal vias. Then, perform segmented routing of high-speed differential signal lines to complete the routing connection of high-speed differential signal line A, surface signal line, high-speed differential signal line B and high-speed differential signal line C. Step 3: Based on the layout positions of the AC pads and differential pair signal vias, process the anti-pad cutout structure of the impedance matching component on the PCB substrate, and complete the cutout process of the corresponding metal layer according to regulations. Step 4: Perform signal integrity simulation verification on the overall interconnect structure using SI simulation technology. Adjust the parameters of hole spacing, pad size, and anti-pad cutout range based on the simulation results until the impedance fluctuation and return loss indicators meet the requirements of high-speed differential signal transmission.

8. The interconnect design method for AC-coupled capacitor stacked pads according to claim 7, characterized in that, During the SI simulation verification process, the focus is on detecting the impedance fluctuation range, return loss value, and insertion loss curve within the operating frequency range. If a resonance point appears in the insertion loss curve, the structural parameters of the impedance matching component and the routing layout of the high-speed differential signal lines are re-optimized.

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