Semiconductor memory device

Abstract

The semiconductor memory device of the embodiment includes: a plurality of first conductive layers disposed spaced apart from each other in a first direction; a structure having a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer disposed at one end of the first semiconductor layer in the first direction and connected to the first semiconductor layer; a contact connected to the second semiconductor layer of the structure; an insulating portion having a portion of the plurality of first conductive layers disposed at one end of the first direction of the structure separated in a second direction intersecting the first direction, and connected to the structure and the contact from one side of the second direction; and a first insulating layer connected from the other side of the contact in the second direction. The insulating portion comprises an insulating material of a different type than the first insulating layer.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on March 11, 2021, with application number 202110265459.4 and title "Semiconductor Memory Device".

[0003] Cross-reference of related applications

[0004] This application claims priority to Japanese Patent Application No. 2020-149394 (filed on September 4, 2020). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0005] This embodiment relates to a semiconductor memory device. Background Technology

[0006] A semiconductor memory device is known, comprising: a substrate; a plurality of conductive layers; a semiconductor layer facing the plurality of conductive layers; and a gate insulating layer disposed between the semiconductor layer and the plurality of conductive layers. Summary of the Invention

[0007] The implementation provides a highly reliable semiconductor memory device.

[0008] One embodiment of a semiconductor memory device includes: a plurality of first conductive layers disposed spaced apart from each other in a first direction; a structure comprising a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer disposed at one end of the first semiconductor layer in the first direction and connected to the first semiconductor layer; a contact connected to the second semiconductor layer of the structure; an insulating portion comprising a portion of the plurality of first conductive layers disposed at one end of the first conductive layer in the first direction of the structure being separated in a second direction intersecting the first direction, and being connected to the structure and the contact from one side of the second direction; and a first insulating layer connected from the other side of the contact in the second direction. The insulating portion comprises an insulating material of a different type than the first insulating layer. Attached Figure Description

[0009] Figure 1 This is a schematic top view of the semiconductor memory device according to the first embodiment.

[0010] Figure 2 This is an equivalent circuit diagram representing the schematic configuration of the semiconductor memory device.

[0011] Figure 3 It means Figure 1 A schematic 3D view of part A.

[0012] Figure 4 yes Figure 3 An enlarged view of part B.

[0013] Figure 5 yes Figure 1 An enlarged view of part A.

[0014] Figure 6 It is Figure 5 The structure is shown in a schematic cross-sectional view taken from the direction of the arrow, with the C-C' line cutting through it.

[0015] Figure 7 This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device.

[0016] Figure 8 This is a schematic cross-sectional view illustrating the manufacturing method.

[0017] Figure 9 This is a schematic cross-sectional view illustrating the manufacturing method.

[0018] Figure 10 This is a schematic cross-sectional view illustrating the manufacturing method.

[0019] Figure 11 This is a schematic cross-sectional view illustrating the manufacturing method.

[0020] Figure 12 This is a schematic cross-sectional view illustrating the manufacturing method.

[0021] Figure 13 This is a schematic cross-sectional view illustrating the manufacturing method.

[0022] Figure 14 This is a schematic cross-sectional view illustrating the manufacturing method.

[0023] Figure 15 This is a schematic cross-sectional view illustrating the manufacturing method.

[0024] Figure 16 This is a schematic cross-sectional view illustrating the manufacturing method.

[0025] Figure 17 This is a schematic cross-sectional view illustrating the manufacturing method.

[0026] Figure 18 This is a schematic cross-sectional view illustrating the manufacturing method.

[0027] Figure 19 This is a schematic cross-sectional view illustrating the manufacturing method.

[0028] Figure 20 This is a schematic cross-sectional view illustrating the manufacturing method.

[0029] Figure 21A This is a schematic top view illustrating the manufacturing method.

[0030] Figure 21B This is a schematic cross-sectional view illustrating the manufacturing method.

[0031] Figure 22 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0032] Figure 23 This is a schematic cross-sectional view of the semiconductor memory device according to the second embodiment.

[0033] Figure 24 This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device.

[0034] Figure 25 This is a schematic cross-sectional view illustrating the manufacturing method.

[0035] Figure 26 This is a schematic cross-sectional view illustrating the manufacturing method.

[0036] Figure 27 This is a schematic cross-sectional view illustrating the manufacturing method.

[0037] Figure 28 This is a schematic cross-sectional view illustrating the manufacturing method.

[0038] Figure 29 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment.

[0039] Figure 30 This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device.

[0040] Figure 31 This is a schematic cross-sectional view illustrating the manufacturing method. Detailed Implementation

[0041] Next, with reference to the accompanying drawings, the semiconductor memory device of the embodiments will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple drawings are labeled with the same symbols, and sometimes explanations are omitted.

[0042] Furthermore, in this specification, a specific direction parallel to the substrate surface is referred to as the X direction, a direction parallel to the substrate surface and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the substrate surface is referred to as the Z direction. Additionally, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, a direction along the Z direction away from the substrate is called "upper," and a direction along the Z direction approaching the substrate is called "lower." Furthermore, when referring to a component as a lower surface or lower end, it refers to the surface or end of that component on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of that component on the opposite side from the substrate.

[0043] Furthermore, in this specification, the term "semiconductor memory device" has various meanings: memory die, memory chip, memory card, SSD (Solid State Drive) and other memory systems containing control dies, smartphones, tablet terminals, personal computers and other components including a host, etc. Also, in this specification, the phrase "electrically connected to" the second component means that the first component is directly connected to the second component, or connected to the second component via wiring, semiconductor components or transistors, etc. For example, in the case of three transistors connected in series, even if the second transistor is in an OFF state, the first transistor is still "electrically connected" to the third transistor.

[0044] [First Implementation]

[0045] [constitute]

[0046] Hereinafter, the configuration of the semiconductor memory device according to the first embodiment will be described with reference to the accompanying drawings.

[0047] [Composition of Semiconductor Memory Devices]

[0048] Figure 1 This is a schematic top view illustrating a configuration example of the semiconductor memory device according to the first embodiment, showing the planar structure of the memory die.

[0049] On the substrate 100, multiple memory cell arrays (MCAs) and PERI regions are disposed. In the illustrated example, two memory cell arrays (MCAs) are disposed side by side on the substrate 100 in the X direction, and a PERI region is disposed at one end in the Y direction.

[0050] The memory cell array (MCA) has multiple memory blocks (BLKs) arranged along the Y direction. Additionally, the MCA has a region R1 containing memory cells and a region R2 with contacts arranged in a stepped pattern. Region R1 may contain, for example, a portion of peripheral circuitry, solder pads, etc.

[0051] Figure 2This is a schematic equivalent circuit diagram of the semiconductor memory device.

[0052] The memory cell array MCA consists of multiple memory blocks BLK, each with multiple string components SU. Each string component SU has multiple memory strings MS. One end of each memory string MS is connected to the peripheral circuit PC via bit line BL. The other end of each memory string MS is connected to the peripheral circuit PC via lower wiring SC and a common source line SL.

[0053] The memory string (MS) includes a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS). Furthermore, in... Figure 2 In the diagram, one STD and one STS transistor are shown, but multiple STD and STS transistors can also be connected in series.

[0054] A memory cell (MC) is a field-effect transistor comprising a semiconductor layer that functions as a channel region, a gate insulating layer that serves as a charge accumulation layer, and a gate electrode. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge accumulation layer. A memory cell (MC) stores one bit or more bits of data. Furthermore, word lines (WL) are connected to the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS). These word lines (WL) are collectively connected to all memory strings (MS) within a memory block (BLK).

[0055] Select transistors (STD, STS) are field-effect transistors that function as channel regions, consisting of a semiconductor layer, a gate insulating layer, and a gate electrode. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS). The drain-side select gate line SGD is correspondingly provided with a string assembly SU and is commonly connected to all memory strings MS within a single string assembly SU. The source-side select gate line SGS is commonly connected to all memory strings MS within multiple string assemblies SU within a single memory block BLK.

[0056] [Memory Cell Array MCA]

[0057] Figure 3 It is by Figure 1 A schematic three-dimensional view of part A.

[0058] The memory cell array MCA has a memory layer ML and a circuit layer CL located below the memory layer ML.

[0059] [Memory Layer ML]

[0060] Between two adjacent memory blocks BLK in the Y direction, an inter-block insulating layer ST extending in both the X and Z directions is provided. Additionally, between two adjacent string components SU in the Y direction, an insulating portion SHE is provided that separates only the drain-side select gate line SGD in the Y direction and extends in both the X and Z directions.

[0061] The memory block BLK includes: multiple memory structures MH extending in the Z direction; multiple conductive layers 110 arranged in the Z direction and covering the outer peripheral surfaces of these multiple memory structures MH in the XY cross section; multiple insulating layers 101 disposed between the multiple conductive layers 110; multiple bit lines BL connected to the upper end of the memory structures MH; and a lower wiring layer 150 connected to the lower end of the memory structures MH.

[0062] The memory structure MH is arranged in a specific pattern in the X and Y directions. The memory structure MH includes: a semiconductor layer 120 extending in the Z direction; a gate insulating layer 130 disposed between the semiconductor layer 120 and the conductive layer 110; a semiconductor layer 121 connected to the upper end of the semiconductor layer 120; and a core insulating layer 125 disposed in the center portion of the memory structure MH.

[0063] Semiconductor layer 120, for example, serves as a memory string MS ( Figure 2 The multiple memory cells MC, drain-side select transistor (STD), and source-side select transistor (STS) contained in the semiconductor layer 120 function as channel regions. The semiconductor layer 120 has a generally cylindrical shape integrally formed from bottom to top. The semiconductor layer 120 may include, for example, undoped polysilicon (Si). The core insulating layer 125, buried in the central portion of the semiconductor layer 120, may include, for example, silicon oxide (SiO2).

[0064] The gate insulating layer 130 extends along the outer peripheral surface of the semiconductor layer 120 in the Z direction and has a generally cylindrical shape integrally formed from the lower end to the upper end, except for the connection portion between the semiconductor layer 120 and the lower wiring layer 150.

[0065] Semiconductor layer 121 may include, for example, polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P).

[0066] The conductive layer 110 is a generally plate-shaped conductive film in which multiple insulating layers 101 are disposed in the Z direction and extend in the X and Y directions. The conductive layer 110 in the central part in the Z direction serves as the word line WL ( Figure 3 ) and multiple memory cells MC connected to the word line WL. Figure 2 The gate electrode of the ) performs its function.

[0067] A portion of the upper conductive layer 110 among the multiple conductive layers 110 serves as the drain-side selected gate line (SGD). Figure 2 ) and a plurality of drain-side select transistors STD connected to the drain-side select gate line SGD. Figure 2 The gate electrode of the ) performs its function.

[0068] A portion of the underlying conductive layer 110 of the plurality of conductive layers 110 serves as the source-side selected gate line (SGS). Figure 2 and a plurality of source-side select transistors STS connected to the source-side select gate line SGS. Figure 2 The gate electrode of the ) performs its function.

[0069] Insulating layers 101 are respectively disposed between a plurality of conductive layers 110 arranged in the Z direction. The insulating layers 101 may contain, for example, silicon oxide (SiO2).

[0070] Multiple bit lines BL are provided in the X direction and extend in the Y direction. Bit lines BL are connected to semiconductor layer 120 via contacts Cb, Ch and semiconductor layer 121.

[0071] The lower wiring layer 150 includes a semiconductor layer 151 connected to the semiconductor layer 120 and a conductive layer 152 disposed on the lower surface of the semiconductor layer 151. The lower wiring layer 150 serves as the lower wiring SC ( Figure 2 To fulfill its function.

[0072] The conductive layer 152 and the insulating layer 160 are formed on the substrate 100, for example, a conductive film containing a metal such as tungsten (W), polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P), or a silicide. The semiconductor layer 151 contains, for example, polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P). The insulating layer 160 contains, for example, silicon oxide (SiO2).

[0073] [Circuit Layer CL]

[0074] The circuit layer CL has a substrate 100, multiple transistors Tr that constitute the peripheral circuit PC, and multiple wirings and contacts connected to these multiple transistors Tr.

[0075] The substrate 100 is, for example, a semiconductor substrate including single-crystal silicon (Si). The substrate 100 has, for example, a dual-well structure in which an N-type impurity layer such as phosphorus (P) is formed on the surface of the semiconductor substrate, and a P-type impurity layer such as boron (B) is formed in the N-type impurity layer.

[0076] [Construction of the memory cell MC]

[0077] Figure 4 yes Figure 3The schematic cross-sectional view shown in section B illustrates the details of the construction at the locations where the conductive layer 110 and the gate insulating layer 130 face each other.

[0078] like Figure 4 As shown, the gate insulating layer 130 includes a tunnel insulating layer 131, a charge storage layer 132, and a barrier insulating layer 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating layer 131, the charge storage layer 132, and the barrier insulating layer 133 are integrally and continuously disposed in the Z direction. However, the charge storage layer 132 may also be interrupted in the Z direction.

[0079] The tunnel insulating layer 131 and the barrier insulating layer 133 may include, for example, silicon oxide (SiO2). The charge storage layer 132 may be, for example, a layer capable of storing charge, such as silicon nitride (SiN). Alternatively, the charge storage layer 132 may be, for example, a floating gate comprising polysilicon (Si) doped with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0080] The conductive layer 110 may contain a metal film such as tungsten (W) or molybdenum (Mo). Alternatively, the conductive layer 110 may also cover the outer peripheral surface with a barrier metal film such as titanium nitride (TiN).

[0081] Figure 5 yes Figure 1 A schematic top view of part A shown. Additionally, Figure 6 It is Figure 5 The structure shown is cut along line C-C', and is a schematic cross-sectional view viewed from the direction of the arrow.

[0082] exist Figure 5 and Figure 6 In this configuration, an inter-block insulating layer ST extending along both the X and Z directions is provided between two adjacent memory blocks BLK in the Y direction. The inter-block insulating layer ST extends to the lower wiring layer 150 in the Z direction, separating the memory blocks BLK in the Y direction. Alternatively, an insulating film may remain on the side of the inter-block insulating layer ST, and a conductive film (not shown) may be formed inside it. This conductive film connects to the lower wiring layer 150, thereby functioning as a contact point for the lower wiring layer 150.

[0083] The memory block BLK in region R1 includes: multiple memory structures MH extending in the Z direction and arranged in a zigzag pattern in the XY direction; multiple conductive layers 110 arranged in the Z direction and covering the outer peripheral surfaces of these multiple memory structures MH in the XY cross section; multiple insulating layers 101 disposed between the multiple conductive layers 110; and multiple bit lines BL electrically connected to the upper end of the memory structures MH via contacts Ch and Cb.

[0084] The storage block BLK has a contact region Rcc in region R2. The contact region Rcc is located at the end of the conductive layer 110, which is formed in a stepped manner. Contacts CC and support structures HR are arranged in the contact region Rcc.

[0085] like Figure 5 As shown, the storage block BLK has multiple string components SU in the Y direction. Between two adjacent string components SU in the Y direction, insulating portions SHE extending in the X and Z directions are provided. Figure 6 As shown, the insulating portion SHE separates only the conductive layer 110 that corresponds to the drain-side selected gate line SGD among the multiple conductive layers 110 in the Y direction.

[0086] In this embodiment, such as Figure 5 As shown, the columns of the memory structure MH arranged in the X direction are arranged in four columns in the Y direction to form one string assembly SU. Furthermore, three or more of these string assemblies SU are arranged in the Y direction to form one memory block BLK. That is, two or more insulating portions SHE are arranged in one memory block BLK. In addition, the insulating portions SHE are formed continuously in the X direction. Therefore, as described below, when the conductive layer 110, which forms the drain-side select gate line SGD, is formed by replacing the sacrificial layer through the opening of the inter-block insulating layer ST, if the insulating portions SHE are formed first, the sacrificial layer between the insulating portions SHE cannot be replaced. Therefore, the insulating portions SHE are formed after the memory structure MH or the conductive layer 110.

[0087] In other words, after the first insulating layer 201 covers the memory structure MH and the conductive layer 110, the insulating portion SHE is formed in such a way that it extends from the first insulating layer 201 to the conductive layer 110 corresponding to the drain-side select gate line SGD. Such an insulating portion SHE is as follows: Figure 5 As shown, it is formed by cutting a portion of the memory structure MH between two columns that are adjacent in the Y direction and arranged in the X direction. In other words, as Figure 6 As shown, the insulating portion SHE is formed in a manner that connects to a portion of the memory structure MH (the portion corresponding to the drain-side select transistor STD). The portion of the memory structure MH connected to the insulating portion SHE does not form a complete cylindrical shape, but functions as a memory string MS.

[0088] In addition, the insulation part SHE such as Figure 6As shown, the memory structure MH is located above and connected to the side of the contact Ch. The upper side of the memory structure MH and the side of the contact Ch, which are not connected to the insulating portion SHE, are covered by a first insulating layer 201. The first insulating layer 201 contains, for example, silicon oxide such as dTEOS (Tetraethyl orthosilicate, tetraethoxysilane) formed by plasma CVD (Chemical Vapor Deposition). The insulating portion SHE has: a second insulating layer 202 containing a different type of insulating material than the first insulating layer 201; and a third insulating layer 203 covering the outer side of the second insulating layer 202. The second insulating layer 202 contains, for example, silicon nitride (SiN). The third insulating layer 203 contains, for example, silicon oxide (SiO2). The second insulating layer 202 is connected to the contact Ch, and the third insulating layer 203 is connected to the memory structure MH. The portion of the semiconductor layer 121 connected to the insulating portion SHE has a recess E. The recess E becomes a factor in the gap 300 in the portion of the insulating portion SHE that faces the semiconductor layer 121.

[0089] The contact Ch has a first end S1 that is in contact with the semiconductor layer 121, and a second end S2 located on the opposite side of the first end S1 in the Z direction. In addition, on the side of the contact Ch that is in contact with the insulating portion SHE, the side surface S3 on the side of the first end S1 is displaced further inward in the Y direction than the side surface S4 on the side of the second end S2.

[0090] Furthermore, the insulating layers (second insulating layer 202 and third insulating layer 203) forming the insulating portion SHE extend in the X and Y directions on the first insulating layer 201 through which the insulating portion SHE passes. Thus, an insulating layer 204 is formed on the second and third insulating layers 202 and 203 covering the first insulating layer 201. A bit line BL is formed on the insulating layer 204. The contact Ch, which is not in contact with the insulating portion SHE, is formed on the second end S2 side in a manner that penetrates the second and third insulating layers 202 and 203 covering the first insulating layer 201. A contact Cb is provided on the insulating layer 204 to connect the contact Ch to the bit line BL.

[0091] [Manufacturing Method]

[0092] Next, refer to Figures 7 to 21A , Figure 21B The manufacturing method of the semiconductor memory device according to this embodiment will be described. Furthermore, Figures 7 to 20 and Figure 21B Indicates and Figure 5 The cross section corresponding to line C-C' in the diagram. Figure 21A Is with Figure 21B The corresponding top view.

[0093] like Figure 7 As shown, an insulating layer 160, a conductive layer 152, a semiconductor layer 151A, an insulating layer 151B, a sacrificial layer 151C, an insulating layer 151D, and a semiconductor layer 151E are formed on a substrate 100. Furthermore, a plurality of insulating layers 101 and sacrificial layers 110A are alternately formed above these layers. And, above these layers, an insulating layer 201A is formed.

[0094] Substrate 100 is, for example, an image formed thereon. Figure 3 The circuit layer CL shown is on a substrate such as a transistor Tr, or a semiconductor substrate such as Si. Insulating layer 160 includes, for example, silicon oxide. Conductive layer 152 includes, for example, tungsten silicide (WSi). Semiconductor layers 151A and 151E include, for example, polycrystalline silicon (Si) doped with phosphorus (P). Insulating layers 151B, 151D, and 101 include, for example, silicon oxide. Sacrificial layers 151C and 110A include, for example, silicon nitride (SiN). Insulating layer 201A includes, for example, silicon oxide such as dTEOS. This process is performed, for example, by a method such as CVD.

[0095] Next, as Figure 8 As shown, an opening MHA is formed in the multilayer structure. The opening MHA extends in the Z direction and penetrates the insulating layer 201A, sacrificial layer 110A, insulating layer 101, semiconductor layer 151E, insulating layer 151D, sacrificial layer 151C, and insulating layer 151B, exposing the semiconductor layer 151A. This process is achieved, for example, by forming an insulating layer with an opening in the portion corresponding to the opening MHA. Figure 7 The upper surface of the stacked structure shown is used as a mask for RIE (Reactive Ion Etching) and other processes.

[0096] Next, as Figure 9 As shown, a gate insulating layer 130, a semiconductor layer 120, and a core insulating layer 125 are sequentially formed on the inner peripheral surface of the open MHA. This process is performed, for example, by a method such as CVD. This forms a memory stack structure (MHB). Furthermore, in this process, for example, a heat treatment is performed to modify the crystal structure of the semiconductor layer 120.

[0097] Next, as Figure 10 As shown, a portion of the insulating layer 125, semiconductor layer 120, and gate insulating layer 130 of the memory stacked layer structure (MHB) is removed to expose the uppermost insulating layer 201A. Furthermore, the upper end of the core insulating layer 125 of the memory stacked layer structure (MHB) is etched back. This process is performed, for example, by methods such as CMP (Chemical Mechanical Polishing) or RIE.

[0098] Next, as Figure 11 As shown, a semiconductor layer 121 is formed on the top of the memory stacked structure MHB. The semiconductor layer 121 includes, for example, amorphous silicon doped with N-type impurities such as phosphorus (P). This process is performed, for example, by a method such as CVD. As a result, a generally cylindrical memory structure MH is formed.

[0099] Next, for example, such as Figure 12 As shown, in Figure 11 An insulating layer 201B, such as dTEOS, is formed on the upper surface of the structure shown, and then a mask (not shown) is formed to create an opening STA. The opening STA extends in the X and Z directions, separating the insulating layers 201B and 201A, multiple sacrificial layers 110A, and multiple insulating layers 101 in the Y direction. Furthermore, the opening STA penetrates the semiconductor layer 151E and the insulating layer 151D, exposing the sacrificial layer 151C at the bottom. This process is performed, for example, by a method such as RIE. Furthermore, an insulating layer 161, such as silicon oxide (SiO2), is formed on the inner wall and bottom surface of the opening STA to cover the sides of the multilayer structure. Then, the bottom surface of the opening STA is excavated down to the sacrificial layer 151C. This process is performed by a method such as RIE.

[0100] Next, as Figure 13 As shown, the sacrificial layer 151C is removed via the opening STA, exposing a portion of the sidewall of the gate insulating layer 130 of the memory structure MH. This process is performed, for example, by a wet etching method. In this process, the sacrificial layer 110A, which contains the same type of material as the sacrificial layer 151C, is not etched at the same time because it is protected by the insulating layer 161.

[0101] Next, as Figure 14 As shown, a portion of the gate insulating layer 130 is removed through the opening STA and the gap where the sacrificial layer 151C is disposed, exposing the side surface of the semiconductor layer 120. During this process, insulating layers 151B and 151D, which contain the same type of material as the gate insulating layer 130, are also removed simultaneously. This process is performed, for example, by a chemical dry etching method.

[0102] Next, as Figure 15 As shown, a polycrystalline silicon (Si) semiconductor layer 151F is formed on the side surface of semiconductor layer 120, the upper surface of semiconductor layer 151A, the lower surface of semiconductor layer 151E, and the inner wall of opening STA. This process is performed, for example, by methods such as semiconductor epitaxial growth.

[0103] Next, as Figure 16As shown, the semiconductor layer 151F on the inner wall of the opening STA is removed. This process is performed, for example, by wet etching. Next, after removing the insulating layer 161 covering the sidewall of the opening STA, multiple sacrificial layers 110A are removed through the opening STA, and multiple conductive layers 110 are formed in the portions where the sacrificial layers 110A were previously present. The process of removing the insulating layer 161 and the sacrificial layers 110A is performed, for example, by wet etching. The conductive layers 110 are formed, for example, by CVD.

[0104] Next, as Figure 17 As shown, an inter-block insulating layer ST is formed in the opening STA. This process is performed, for example, by methods such as CVD.

[0105] Next, as Figure 18 As shown, an opening SHEA is formed, which is used to form an insulating portion SHE that separates the memory structure MH for each string component SU. The opening SHEA is formed by cutting away a portion (upper side) of the memory structure MH. The opening SHEA is formed by breaking the conductive layer 110, which only serves as the drain-side select gate line SGD, in the Y direction. This process is performed using methods such as RIE.

[0106] like Figure 18 As shown, when forming the opening SHEA, the semiconductor layer 120 and semiconductor layer 121 are easier to be removed than the core insulating layer 125. Therefore, during the RIE process, the etching progress in the Y direction in the semiconductor layer 121 sometimes forms a recess E.

[0107] Next, as Figure 19 As shown, an insulating layer 203A, such as silicon oxide (SiO2), is formed on the side and bottom surfaces of the open SHEA. This process is performed, for example, by a method such as CVD.

[0108] Next, as Figure 20 As shown, an insulating layer 202A, such as silicon nitride (SiN), is formed, for example, inside the insulating layer 203A of the opening SHEA. This process is performed, for example, by a method such as CVD. Thus, the insulating portion SHE is formed. Furthermore, as... Figure 20 As shown, if a recess E is formed on the side of the semiconductor layer 121, then when the insulating layer 202A is buried in the opening SHEA, there is a possibility that a gap 300 will be generated at the position corresponding to the position in the Z direction where the recess E is formed.

[0109] Next, as Figure 21B As shown, the upper part of the insulating layer 202A is planarized using methods such as CMP, and a mask (not shown) is formed on it. A cylindrical opening ChA for forming the contact Ch is formed above the memory structure MH. This process is performed using methods such as RIE.

[0110] When forming the opening ChA of the contact Ch connecting to the memory structure MH which is in contact with the insulating portion SHE, the opening ChA is also formed at the interface between the insulating portion SHE and the first insulating layer 201. The second insulating layer 202, which comprises silicon nitride and constitutes the insulating portion SHE, has a lower etching rate compared to the first insulating layer 201, which comprises silicon oxide, and the third insulating layer 203, which constitutes the insulating portion SHE. Therefore, as... Figure 21B As shown, the opening ChA that is connected to the insulating portion SHE is etched before the etching of the first insulating layer 201 and the third insulating layer 203, compared to the etching of the second insulating layer 202. As a result, on the side connected to the insulating portion SHE, a step difference D is formed where the lower side is displaced further inward than the upper side.

[0111] Then, a contact Ch is formed in the opening ChA thus formed, an insulating layer 204 is formed thereon, and a contact Cb electrically connected to the contact Ch is formed in the insulating layer 204. Furthermore, a reference is formed by providing bit lines BL on the upper portion of the contact Cb. Figure 6 The composition described.

[0112] [Effects of this implementation method]

[0113] Next, we will also refer to Figure 22 The comparative examples shown illustrate the effects of this embodiment.

[0114] like Figure 22 As shown, when the insulating portion SHE is formed from an insulating layer 205 such as silicon oxide, the same as the first insulating layer 201, etching is performed uniformly throughout the opening ChA when forming the contact Ch that connects to the insulating portion SHE. Therefore, the leading edge of the opening ChA reaching the semiconductor layer 121 may be etched along the insulating layer 205 side until it reaches the gap 300. In this case, if a conductive contact Ch is formed, there is a possibility that the contact Ch may pass through the gap 300. The gap 300 is as follows... Figure 21A As shown, it extends in the X direction, so if a conductor enters into the gap 300, there is a possibility that it will cause a short circuit in the multiple contacts Ch arranged in the X direction.

[0115] Therefore, in the semiconductor memory device of this embodiment, as Figure 21A , Figure 21B As shown, during the formation of opening ChA, due to the etching delay on the side connected to the insulating portion SHE, a step D is formed on the side of opening ChA on the insulating portion SHE side, preventing the formation of a hole reaching the gap 300. Therefore, the problem of short-circuiting between adjacent contacts Ch in the X direction can be reliably avoided.

[0116] Furthermore, in this embodiment, since a third insulating layer 203, which serves as an oxide film, is formed at the portion in contact with the memory structure MH, the same electrical characteristics as those of the insulating portion SHE filled with a conventional oxide film can be maintained. Additionally, since only the third insulating layer 203 and the second insulating layer 202 need to be formed sequentially, control is easy, and the manufacturing process is not complicated.

[0117] [Second Implementation]

[0118] Figure 23 This is a cross-sectional view of the semiconductor memory device according to the second embodiment, corresponding to the view along... Figure 5 The C-C' line cuts through the cross-sectional view viewed from the direction of the arrow.

[0119] In the second embodiment, the insulating portion SHE includes: a second insulating layer 206 located above the upper surface of the semiconductor layer 121 in the Z direction; and a third insulating layer 207 located below the upper surface of the semiconductor layer 121 in the Z direction. The second insulating layer 206 includes, for example, silicon nitride (SiN). The third insulating layer 207 includes, for example, silicon oxide (SiO2) such as LTO (Low Temperature Oxide). The second insulating layer 206 is connected to the contact Ch, and the third insulating layer 207 is connected to the memory structure MH. The etch rate of the second insulating layer 206 is lower than that of the first insulating layer 201.

[0120] Next, refer to Figures 24-28 The manufacturing method of the semiconductor memory device according to this embodiment will be described. Furthermore, Figures 24-28 Indicates and Figure 5 The cross section corresponding to the C-C' line in the diagram.

[0121] The manufacturing process of this embodiment continues until... Figure 17 The formation of the inter-block insulating layer ST shown is the same as in the first embodiment. In this state, as... Figure 24 As shown, for example, an insulating layer 206A such as silicon nitride (SiN) is used to form a mask to form an opening SHEA for forming the insulating portion SHE. This process is performed by methods such as RIE. In this case, a recess E is sometimes formed on the sidewall of the semiconductor layer 121.

[0122] Next, as Figure 25 As shown, an insulating layer 207A, such as LTO, is buried inside the open SHEA. This process is performed by methods such as CVD. At this time, gaps 300 are sometimes formed in the portion of the insulating layer 207A facing the semiconductor layer 121.

[0123] Next, as Figure 26As shown, the third insulating layer 207 is formed by drilling the insulating layer 207A down to the top of the semiconductor layer 121. This process is performed by methods such as RIE.

[0124] Next, as Figure 27 As shown, an insulating layer 206B, including silicon nitride (SiN) or the like, is formed on the third insulating layer 207 of the open SHEA. This process is performed by methods such as CVD.

[0125] Next, as Figure 28 As shown, after planarizing the upper surface of the insulating layer 206B using methods such as CMP, an opening ChA for forming the contact Ch is formed on each memory structure MH. This process is performed using methods such as RIE. In this case, the etching rate of the second insulating layer 206 is also lower than that of the first insulating layer 201, so a step difference D caused by the difference in etching rate is formed on the side of the opening ChA that is in contact with the second insulating layer 206.

[0126] Therefore, in the semiconductor memory device of this embodiment, the contact Ch will not pass through the gap 300.

[0127] Furthermore, according to this embodiment, since the portion of the insulating part SHE that is in contact with the memory structure MH is entirely formed by the third insulating layer 207, which is an oxide film, it is possible to maintain almost the same electrical characteristics as the insulating part SHE that is filled with a conventional oxide film.

[0128] [Third Implementation]

[0129] Figure 29 This is a cross-sectional view of the semiconductor memory device according to the third embodiment, corresponding to the view along... Figure 5 The C-C' line cuts through the cross-sectional view viewed from the direction of the arrow.

[0130] In the third embodiment, the insulating portion SHE is formed, for example, only by a second insulating layer 208 comprising silicon nitride (SiN) or the like. The second insulating layer 208 is in contact with the contact Ch and the memory structure MH. The etch rate of the second insulating layer 208 is lower than that of the first insulating layer 201.

[0131] Next, refer to Figure 30 and Figure 31 The manufacturing method of the semiconductor memory device according to this embodiment will be described. Furthermore, Figure 30 and Figure 31 Indicates and Figure 5 The cross section corresponding to the C-C' line in the diagram.

[0132] The manufacturing process of this embodiment continues until... Figure 18 The formation of the opening SHEA shown is the same as in the first embodiment. In this state, as... Figure 30As shown, an insulating layer 208A containing silicon nitride (SiN) or similar materials is buried inside the open SHEA. This process is performed by methods such as CVD. At this time, gaps 300 may sometimes be formed in the portion of the insulating layer 208A facing the semiconductor layer 121.

[0133] Next, as Figure 31 As shown, after the upper surface of the insulating layer 208A is planarized using methods such as CMP, an opening ChA for forming the contact Ch is formed on each memory structure MH. This process is performed using methods such as RIE. In this case, the etching rate of the second insulating layer 208 is also lower than that of the first insulating layer 201, so a step difference D caused by the difference in etching rate is formed on the side of the opening ChA that is in contact with the second insulating layer 208.

[0134] Therefore, in the semiconductor memory device of this embodiment, the contact Ch will not pass through the gap 300.

[0135] Furthermore, in this embodiment, since the insulating part SHE is formed only by a nitride film, the manufacturing process is simpler than that of the first and second embodiments.

[0136] [other]

[0137] The embodiments have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. For example, in the various embodiments described, a silicon oxide film is used as the first insulating layer and a silicon nitride film is used as the second insulating layer. However, other materials may be used as long as the first and second insulating layers are made of different materials and the latter has a lower etching rate than the former and is an insulator. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device, comprising: Multiple first conductive layers are arranged spaced apart from each other in a first direction; The structure includes a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer disposed at one end of the first semiconductor layer in the first direction and connected to the first semiconductor layer. The contact is connected to the second semiconductor layer of the structure; An insulating portion wherein a portion of the plurality of first conductive layers disposed at one end in the first direction of the structure is interrupted in a second direction intersecting the first direction, and is connected to the structure and the contact from one side of the second direction; and The first insulating layer is connected to the other side of the second direction of the contact; The insulating portion expands the position in the first direction corresponding to the second semiconductor layer in the second direction. The side of the insulating portion that is in contact with the contact on one side in the second direction has a first side that is close to the second semiconductor layer and a second side that is farther away from the second semiconductor layer than the first side, and the first side protrudes further toward the other side in the second direction than the second side.

2. The semiconductor memory device according to claim 1, wherein The insulating portion further comprises: a second insulating layer, which is at least in contact with the contact and contains an insulating material of a different type than the first insulating layer; and a third insulating layer, which is in contact with the structure and contains an insulating material of a different type than the second insulating layer.

3. The semiconductor memory device according to claim 2, wherein... The third insulating layer covers the side surface of the second insulating layer at a position in the first direction at least in contact with the structure.

4. The semiconductor memory device according to claim 2, wherein The insulating portion includes: a second insulating layer disposed in the first direction in contact with the contact; and a third insulating layer disposed in the first direction in contact with the structure.

5. The semiconductor memory device according to claim 2, wherein... The etching rate of the second insulating layer is lower than that of the first insulating layer.

6. The semiconductor memory device according to claim 1, wherein The insulating portion has a gap at a position in the first direction corresponding to the second semiconductor layer.

7. A semiconductor memory device, comprising: Multiple first conductive layers are arranged spaced apart from each other in a first direction; A plurality of structures, each comprising a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer disposed at one end of the first semiconductor layer in the first direction and connected to the first semiconductor layer; and A silicon oxide layer is formed such that a portion of the plurality of first conductive layers disposed at one end side in the first direction of the plurality of structures is cut off in a second direction intersecting the first direction, and a portion of the first end side of the plurality of structures in the second direction is removed from the first direction. The gate insulating layer and the second semiconductor layer of the remaining portion of the first structure in the second direction, which has been partially removed, are aligned with the upper surface of the silicon oxide layer to which a portion of the first structure has been removed.

8. The semiconductor memory device according to claim 7, wherein Each of the plurality of structures also has a core insulating layer disposed at its center, the silicon oxide layer being in contact with the core insulating layer in a portion of the first structure that has been removed.

9. The semiconductor memory device according to claim 7, wherein The silicon oxide layer is in contact with a portion of the first structure that has been removed in the first direction and the second direction.

10. The semiconductor memory device according to claim 7, wherein The silicon oxide layer will divide a portion of the first conductive layers disposed at one end side of the plurality of structures in the first direction into segments in the second direction.

11. The semiconductor memory device according to claim 7, wherein The plurality of constructs includes: A structure that is different from the first structure, but not partially removed by the silicon oxide layer.

12. The semiconductor memory device according to claim 11, wherein The different structures are cylindrical, and cylindrical contact holes are formed on the different structures, with contact points provided in the contact holes.

13. A semiconductor memory device, comprising: Multiple first conductive layers are arranged spaced apart from each other in a first direction; Multiple first insulating layers are alternately deposited with the first conductive layer in the first direction; A plurality of structures, each having a first semiconductor layer, a gate insulating layer, and a second semiconductor layer, wherein the first semiconductor layer extends in the first direction and faces the plurality of first conductive layers, the gate insulating layer is disposed at least between the first semiconductor layer and the plurality of first conductive layers, and the second semiconductor layer is connected to one end of the first semiconductor layer in the first direction; A contact is connected to the second semiconductor layer of one of the plurality of structures; The first insulating portion divides the first plurality of first conductive layers in a second direction perpendicular to the first direction. The first plurality of first conductive layers are disposed on an end side in the first direction corresponding to an end point of the first semiconductor layer in the first direction. A portion of the end point of the first structure in the first direction in the second direction is removed. as well as A plurality of first components are disposed in the second direction and formed in a plurality of openings, each of the plurality of openings dividing a first plurality of first conductive layers and a second plurality of first conductive layers in the second direction. The second plurality of first conductive layers are disposed at the other end of the first plurality of first conductive layers in the first direction. The side of the first semiconductor layer is partially connected to the third semiconductor layer, the third semiconductor layer is disposed at the other end of the second plurality of first conductive layers in the first direction, and the gate insulating layer is partially disposed between the surface of the first semiconductor layer at the other end of the first direction and the third semiconductor layer. The first insulating portion has a gap at the position corresponding to the second semiconductor layer in the first direction.

14. The semiconductor memory device of claim 13, wherein... The width of the first insulating portion in the second direction at the position corresponding to the second semiconductor layer in the first direction is greater than the width of the first insulating portion in the second direction at the position corresponding to one of the first plurality of first conductive layers in the first direction.

15. The semiconductor memory device according to claim 13, wherein Each of the plurality of structures also has a core insulating layer disposed at its center, and in the first structure in which a portion is cut off, the first insulating portion is in contact with the core insulating layer.

16. The semiconductor memory device of claim 13, wherein... The first insulating portion is in contact with a portion of the first structure that has been cut off in the first direction and the second direction.

17. The semiconductor memory device according to claim 13, wherein The plurality of constructs includes: A different structure from the first structure, wherein the different structure is not cut off by the first insulating portion.

18. The semiconductor memory device according to claim 17, wherein The different structures are columnar, and the contacts are provided as columnar contact holes formed on the different structures.

19. The semiconductor memory device of claim 18, wherein The second semiconductor layer in the different structures is electrically connected to the bit line via the contact.

20. The semiconductor memory device of claim 13, wherein Each of the plurality of first insulating layers and each of the first insulating portions comprises silicon oxide.

21. The semiconductor memory device according to claim 13, wherein Each of the plurality of first conductive layers contains tungsten.

22. A semiconductor memory device, comprising: Multiple first conductive layers are arranged spaced apart from each other in a first direction; Multiple first insulating layers are alternately deposited with the first conductive layer in the first direction; A plurality of structures, each having a first semiconductor layer, a gate insulating layer, and a second semiconductor layer, wherein the first semiconductor layer extends in the first direction and faces the plurality of first conductive layers, the gate insulating layer is disposed at least between the first semiconductor layer and the plurality of first conductive layers, and the second semiconductor layer is connected to one end of the first semiconductor layer in the first direction; Multiple contacts, each connected to the second semiconductor layer of one of the multiple structures; The first insulating portion divides the first plurality of first conductive layers in a second direction perpendicular to the first direction, and the first plurality of first conductive layers are disposed in an end side corresponding to an end of the first semiconductor layer in the first direction. as well as A plurality of first components are disposed in the second direction and formed in a plurality of openings, each of the plurality of openings dividing a first plurality of first conductive layers and a second plurality of first conductive layers in the second direction. The second plurality of first conductive layers are disposed at the other end of the first plurality of first conductive layers in the first direction. The side of the first semiconductor layer is partially connected to the third semiconductor layer, the third semiconductor layer is disposed on the other end side of the second plurality of first conductive layers in the first direction, and the gate insulating layer is partially disposed between the surface of the first semiconductor layer on the other end side in the first direction and the third semiconductor layer. The plurality of structures includes a first structure and a second structure. When viewed from the first direction, the first structure and the second structure are adjacent to each other in a third direction perpendicular to the first direction and oblique to the second direction. The first insulating portion is inserted between the first structure and the second structure. The first contact and the second contact of the plurality of contacts are respectively connected to the second semiconductor layer in the first structure and the second semiconductor layer in the second structure. None of the plurality of structures is disposed between the first structure and the second structure. The first insulating portion has a first insulator that is directly connected to the first plurality of first conductive layers, and a gap is provided inside the first insulator.

23. The semiconductor memory device according to claim 22, further comprising: The second insulating portion further divides the first plurality of first conductive layers in the second direction, wherein... The first insulating portion and the second insulating portion are disposed in the second direction and are located between two adjacent first components among the plurality of first components.

24. The semiconductor memory device of claim 23, wherein The plurality of structures also includes a third structure, wherein, when viewed from the first direction, the first structure and the third structure are arranged in the second direction, and the first insulating portion is inserted between the first structure and the third structure.

25. The semiconductor memory device of claim 24, wherein... The plurality of structures also includes a fourth structure, the second structure and the fourth structure are disposed in the second direction, and the third structure and the fourth structure are disposed in the third direction, and none of the plurality of structures is disposed between the second structure and the fourth structure.

26. The semiconductor memory device of claim 25, wherein... The plurality of structures also includes a fifth structure and a sixth structure, which, when viewed from the first direction, are adjacent to each other in the third direction, and the second insulating portion is inserted between the fifth structure and the sixth structure. The third structure and the fifth structure are disposed in the second direction, and the fourth structure and the sixth structure are disposed in the second direction. None of the plurality of structures is disposed between the third structure and the fifth structure.

27. The semiconductor memory device of claim 26, wherein... When viewed from the first direction, the fourth structure and the sixth structure are arranged in the second direction, and the second insulating portion is inserted between the fourth structure and the sixth structure.

28. The semiconductor memory device of claim 26, wherein None of the plurality of constructs is located between the fifth and sixth constructs.

29. The semiconductor memory device of claim 28, wherein The third and fourth contacts of the plurality of contacts are respectively connected to the second semiconductor layer in the fifth structure and the second semiconductor layer in the sixth structure.

30. The semiconductor memory device of claim 22, wherein... The second semiconductor layer in the first structure is electrically connected to the first bit line via the first contact, and the second semiconductor layer in the second structure is electrically connected to the second bit line via the second contact.

31. The semiconductor memory device according to claim 22, wherein Each of the plurality of first insulating layers comprises silicon oxide, and the first insulating portion comprises silicon oxide as the first insulator.

32. The semiconductor memory device according to claim 22, wherein Each of the plurality of first conductive layers contains molybdenum.

33. A semiconductor memory device, comprising: Multiple first conductive layers are arranged spaced apart from each other in a first direction; Multiple structures, each having a first semiconductor layer extending in the first direction and facing the multiple first conductive layers, a gate insulating layer disposed between the first semiconductor layer and the multiple first conductive layers, and a second semiconductor layer disposed at one end of the first semiconductor layer in the first direction and connected to the first semiconductor layer; Contacts are connected to the second semiconductor layer of one of the plurality of structures; and An insulating portion is provided in an opening, the opening being formed such that a portion of one end side of one of the plurality of first conductive layers disposed in the first direction of the plurality of structures is cut off in a second direction intersecting the first direction, and a portion of the first end side of the first structure in the first direction in the second direction is removed. The insulating portion has a gap at least at the position corresponding to the second semiconductor layer in the first direction. The upper surface of the insulating portion disposed within the opening formed by removing a portion of the first structure is higher than the upper surfaces of the gate insulating layer and the second semiconductor layer of the remaining portion of the first structure in the second direction.

34. The semiconductor memory device of claim 33, wherein The gap in the insulating portion terminates below the upper surface of the insulating portion.

35. The semiconductor memory device of claim 33, wherein... Each of the plurality of structures also has a core insulation layer located at its center. The upper surface of the core insulating layer is in contact with the lower surface of the second semiconductor layer.

36. The semiconductor memory device of claim 35, wherein... The insulating portion is in contact with the core insulating layer in a portion of the first structure that has been removed.

37. The semiconductor memory device of claim 33, wherein... The insulating portion is connected to a portion of the first structure that has been cut off in the first direction and the second direction.

38. The semiconductor memory device according to claim 33, wherein The width of the insulating portion in the second direction at the position corresponding to the second semiconductor layer in the first direction is greater than the width in the second direction at the position corresponding to one of the first conductive layers in the first direction.

39. The semiconductor memory device according to claim 38, wherein The insulating portion extends across all positions in the first direction corresponding to the second semiconductor layer, and the width in the second direction is greater than the width in the second direction at a position in the first direction corresponding to one of the positions in the first conductive layer of the portion.

40. The semiconductor memory device of claim 33, wherein The opening extends in a third direction that intersects the first and second directions, and cuts off a portion of the plurality of structures aligned along the third direction.

41. The semiconductor memory device according to claim 33, wherein The insulating portion has a silicon oxide layer formed along the inner surface of the opening.

42. The semiconductor memory device according to claim 33, wherein The first conductive layer, which is disposed at one end in the first direction, functions as a drain-side gate selector line.

43. A semiconductor memory device, comprising: Multiple first conductive layers are arranged spaced apart from each other in a first direction; Multiple structures, each having a first semiconductor layer extending in the first direction and facing the multiple first conductive layers, a gate insulating layer disposed between the first semiconductor layer and the multiple first conductive layers, and a second semiconductor layer disposed at one end of the first semiconductor layer in the first direction and connected to the first semiconductor layer; Contacts are connected to the second semiconductor layer of one of the plurality of structures; and An insulating portion is provided in an opening, the opening being formed such that a portion of one end side of one of the plurality of first conductive layers disposed in the first direction of the plurality of structures is cut off in a second direction intersecting the first direction, and a portion of the first end side of the first structure in the first direction in the second direction is removed. The insulating portion has a gap at least at a first position corresponding to the second semiconductor layer in the first direction, and the insulating portion closes the opening end of the opening.

44. The semiconductor memory device of claim 43, wherein The upper surface of the insulating portion disposed within the opening formed by removing a portion of the first structure is higher than the upper surfaces of the gate insulating layer and the second semiconductor layer of the remaining portion of the first structure in the second direction.

45. The semiconductor memory device according to claim 43, wherein Each of the plurality of structures also has a core insulation layer located at its center. The upper surface of the core insulating layer is in contact with the lower surface of the second semiconductor layer.

46. ​​The semiconductor memory device of claim 45, wherein The insulating portion is in contact with the core insulating layer in a portion of the first structure that has been removed.

47. The semiconductor memory device of claim 43, wherein The insulating portion is connected to a portion of the first structure that has been cut off in the first direction and the second direction.

48. The semiconductor memory device according to claim 43, wherein The width of the insulating portion in the second direction at the position corresponding to the second semiconductor layer in the first direction is greater than the width in the second direction at the position corresponding to one of the first conductive layers in the first direction.

49. The semiconductor memory device of claim 48, wherein The insulating portion extends across all positions in the first direction corresponding to the second semiconductor layer, and the width in the second direction is greater than the width in the second direction at a position in the first direction corresponding to one of the positions in the first conductive layer of the portion.

50. The semiconductor memory device of claim 43, wherein... The opening extends in a third direction that intersects the first and second directions, and cuts off a portion of the plurality of structures aligned along the third direction.

51. The semiconductor memory device according to claim 43, wherein The insulating portion has a silicon oxide layer formed along the inner surface of the opening.

52. The semiconductor memory device according to claim 43, wherein The first conductive layer, which is disposed at one end in the first direction, functions as a drain-side gate selector line.

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