Integrated circuit device and method of manufacturing the same

Abstract

Embodiments of the present application relate to integrated circuit devices and methods of manufacturing the same. An integrated circuit device includes a first transistor and a second transistor. The first transistor includes a first terminal configured to receive a first supply voltage, a second terminal, and a gate terminal. The gate terminal is configured to receive a second supply voltage different from the first supply voltage, or a first voltage corresponding to the first supply voltage, or a second voltage corresponding to the second supply voltage. The second transistor includes two terminals electrically coupled to the second terminal of the first transistor.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] Integrated circuit (“IC”) devices include one or more semiconductor devices represented in an IC layout diagram (also known as an “IC design layout diagram,” “layout diagram,” “IC layout,” or “layout”). A layout diagram is hierarchical and comprises modules that perform higher-level functions according to the design specifications of the semiconductor device. These modules are typically constructed from combinations of cells, each cell representing one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layout diagrams, sometimes referred to as standard cells, are stored in a standard cell library (hereinafter referred to as a “library” or “cell library” for simplicity) and are accessible through various tools, such as electronic design automation (EDA) tools, to generate, optimize, and verify IC designs.

[0003] An Engineering Change Order (ECO) cell is an example of a standard cell in a cell library. An ECO cell is a pre-designed cell that does not have a specific function but can be programmed to perform the intended function. For example, when designing an integrated circuit (IC) device, a pre-designed layout of one or more functional cells is read from a standard cell library and placed into the initial IC layout. The IC layout also includes one or more ECO cells that are not yet connected to or routed to functional cells. When a modification to the IC layout is needed, one or more placed ECO cells can be programmed to provide the intended function and routed to the functional cells. Programming an ECO cell involves modifying one or more layers of the IC layout and / or the mask used to fabricate the IC device. Summary of the Invention

[0004] According to one aspect of the embodiments of this application, an integrated circuit device is provided, including: a first transistor including: a first terminal configured to receive a first power supply voltage, a second terminal, and a gate terminal, the gate terminal being configured to receive: a second power supply voltage different from the first power supply voltage, or a first voltage corresponding to the first power supply voltage, or a second voltage corresponding to the second power supply voltage; and the integrated circuit device further including a second transistor, the second transistor including two terminals electrically coupled to the second terminal of the first transistor.

[0005] According to another aspect of the embodiments of this application, an integrated circuit device is provided, comprising: a first active region of a first conductivity type; a second active region having a second conductivity type different from the first conductivity type; and a plurality of gate regions extending continuously across the first active region and the second active region. The plurality of gate regions and the first active region are respectively configured with a plurality of transistors of the first type, and the plurality of gate regions and the second active region are respectively configured with a plurality of transistors of the second type different from the first type. The plurality of transistors of the first type includes: a first transistor having a first source / drain and a second source / drain, the first source / drain being electrically coupled to a first power rail configured to carry a first power supply voltage; and a second transistor having a first source / drain and a second source / drain both electrically coupled to the second source / drain of the first transistor. The plurality of transistors of the second type includes: a third transistor having a first source / drain and a second source / drain, the first source / drain of the third transistor being electrically coupled to a second power rail configured to carry a second power supply voltage different from the first power supply voltage; and a fourth transistor having a first source / drain and a second source / drain both electrically coupled to the second source / drain of the third transistor.

[0006] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit is provided, comprising: forming a first circuit region and a second circuit region over a substrate. Each of the first and second circuit regions includes an active region with a different conductivity type, and alternating gate regions and contact structures extending across the active region. The active region, gate region, and contact structure in the first circuit region are correspondingly identical to the active region, gate region, and contact structure in the second circuit region. A first set of transistors is configured in the active region and gate region of the first circuit region, and a second set of transistors is configured in the active region and gate region of the second circuit region. The method further includes depositing and patterning: a first set of via structures located above the gate region and contact structure in the first circuit region; a second set of via structures located above the gate region and contact structure in the second circuit region; a first set of conductive patterns located above the first set of via structures; and a second set of conductive patterns located above the second set of via structures in a metal layer. The first set of via structures and the first set of conductive patterns electrically couple the first set of transistors into a non-functional circuit, while leaving no floating source / drain in the first set of transistors; and the second set of via structures and the second set of conductive patterns electrically couple at least some of the transistors in the second set of transistors into a functional circuit. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A This is a block diagram of an IC device according to some embodiments.

[0009] Figure 1B This is a schematic cross-sectional view of the circuit area of ​​an IC device according to some embodiments.

[0010] Figure 1C This is a schematic diagram of the circuit layout of an IC device according to some embodiments.

[0011] Figure 1D This includes circuit diagrams of various pseudo-devices that are not desired or prohibited in one or more ECO units according to some embodiments.

[0012] Figure 2A , Figure 2B , Figure 2C , Figure 2D Circuit diagrams and voltage characteristics of various devices in one or more ECO units according to some embodiments are shown.

[0013] Figure 3A , Figure 3B , Figure 3C Circuit diagrams are shown for various example circuits in one or more ECO units according to some embodiments.

[0014] Figure 4A This is a schematic diagram of the ECO unit layout according to some embodiments.

[0015] Figure 4B This is a schematic diagram of the ECO unit layout according to some embodiments.

[0016] Figure 4C Including combinations according to some embodiments Figure 4B The circuit diagrams of the various devices in the described ECO unit.

[0017] Figure 4D This is a schematic diagram of the ECO unit layout according to some embodiments.

[0018] Figures 5A-5C These are flowcharts of various methods according to some embodiments.

[0019] Figure 6 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0020] Figure 7 This is a block diagram of an IC device manufacturing system and an associated IC manufacturing process according to some embodiments. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., may be considered. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0023] In some embodiments, the ECO unit includes a device configured to receive a supply voltage and provide a soft supply voltage. In at least one embodiment, the soft supply voltage is a constant voltage close to the supply voltage, or a voltage hovering near the supply voltage. The ECO unit also includes one or more dummy devices, each having two or more terminals electrically coupled to receive the soft supply voltage. Therefore, in at least one embodiment, the ECO unit does not include a floating source / drain. This is an improvement over other methods, where the ECO unit includes one or more undesirable floating sources / drains.

[0024] In some embodiments, the ECO cell described herein is advantageous when the cell height is reduced due to integrated circuit (IC) miniaturization and the number of tracks for conductors or conductive patterns in the metal layer above the ECO cell is limited. An example embodiment includes four tracks above the ECO cell. In other approaches, due to the limited number of tracks, it is impossible to remove unwanted floating sources / drains without increasing the size of the ECO cell, adding more ECO cells, or utilizing wiring resources in one or more higher metal layers. The ECO cell according to some embodiments can eliminate unwanted floating sources / drains without increasing the size or number of ECO cells, thereby achieving advantages including, but not limited to, improved chip area, ECO cell design flexibility, and / or enhanced usability.

[0025] In some embodiments, none of the gates in the ECO cell are directly electrically connected to the positive power rail configured to carry a positive power supply voltage. In at least one embodiment, a direct electrical connection refers to an electrical connection without a switch or controllable device. In one or more embodiments, a direct electrical connection of an element to the positive power rail allows the voltage on the positive power rail to be supplied to the element independently and / or unaffected by other elements and / or circuitry. In some embodiments, because none of the gates in the ECO cell are directly electrically connected to the positive power rail, the risk of electrostatic discharge (ESD) that could be harmful to the devices in the ECO cell can be avoided or reduced. Other features according to various embodiments and their corresponding advantages are also described herein.

[0026] Figure 1A This is a block diagram of IC device 100A according to some embodiments.

[0027] exist Figure 1A In this embodiment, integrated circuit (IC) device 100A includes macro 101 and other components. In some embodiments, macro 101 includes one or more of a memory, power grid, one or more cells, inverters, latches, buffers, and / or any other circuit arrangement that can be digitally represented in a cell library. In some embodiments, macro 101 is understood as analogous to an architectural hierarchy similar to modular programming, where a main program (or other subroutine) calls a subroutine / procedure to perform a given computational function. In this context, IC device 100A uses macro 101 to perform one or more given functions. Therefore, in this context, from an architectural hierarchy perspective, IC device 100A is analogous to a main program, and macro 101 is analogous to a subroutine / procedure. In some embodiments, macro 101 is a soft macro. In some embodiments, macro 101 is a hard macro. In some embodiments, macro 101 is a soft macro described in register-transfer-level (RTL) code numbers. In some embodiments, macro 101 has not yet been synthesized, placed, and routed so that soft macros can be synthesized, placed, and routed for various process nodes. In some embodiments, macro 101 is a hard macro digitally described in a binary file format (e.g., Graphical Database System II (GDSII) stream format), wherein the binary file format represents the planar geometry, text labels, other information, etc., of one or more layout diagrams of macro 101 in a hierarchical manner. In some embodiments, macro 101 has been synthesized, placed, and routed such that the hard macro is dedicated to a specific process node.

[0028] Macro 101 includes a circuit region 103, which contains one or more ECO cells as described herein. In some embodiments, circuit region 103 includes a substrate on which circuitry has been formed during a front-end process (FEOL) fabrication process. Furthermore, above and / or below the substrate, circuit region 103 also includes various metal layers stacked above and / or below an insulating layer during a back-end process (BEOL) fabrication process. BEOL provides wiring for the circuitry of IC device 100A, including macro 101 and circuit region 103.

[0029] Figure 1B This is a schematic cross-sectional view of the circuit area of ​​IC device 100B according to some embodiments. In some embodiments, IC device 100B corresponds to IC device 100A, and / or Figure 1B The circuit area in the document corresponds to circuit area 103 and / or includes one or more units placed and wired as described herein.

[0030] like Figure 1B As shown, integrated circuit (IC) device 100B includes a substrate 110 on which circuit elements and structures corresponding to one or more units described herein are formed. The substrate 110 has a first side 108 and a second side 109 opposite to each other along its thickness direction (i.e., along the Z-axis). In at least one embodiment, the first side 108 is referred to as the “upper side” or “front side” or “device side,” while the second side 109 is referred to as the “lower side” or “back side.” In at least one embodiment, the substrate 110 is made of silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor or dielectric materials.

[0031] The integrated circuit (IC) device 100B further includes N-type and P-type dopants added to the substrate 110 to form N-type active regions and P-type active regions, respectively. The N-type and P-type active regions are collectively referred to as active regions and are schematically represented in this disclosure by the label "OD". In some embodiments, an isolation structure is formed between adjacent active regions. For simplicity, Figure 1B The isolation structure is omitted. In at least one embodiment, Figure 1B The active region in the middle corresponds to Figure 4A , Figure 4B , Figure 4D One or more active regions as described in the text.

[0032] The integrated circuit (IC) device 100B also includes various gate structures located above the active region. In some embodiments, the gate structure includes a gate and a gate dielectric located between the gate and the underlying active region. For simplicity of description, Figure 1BThe gate dielectric is omitted. Example materials for the gate dielectric include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), etc. As shown, the gate is schematically indicated by the label "PO". For example, Figure 1B Gates 111, 113, and 115 are shown. In some embodiments, the gate of IC device 100B includes a conductive gate and a dielectric gate. Example materials for the conductive gate include conductive materials such as polysilicon, metals, etc. Example materials for the dielectric gate include dielectric materials. The conductive gate and the underlying active region together constitute a transistor or device. Examples of devices include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, P-channel metal-oxide-semiconductor (PMOS) transistors, N-channel metal-oxide-semiconductor (NMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), fin field-effect transistors (FinFETs), planar metal-oxide-semiconductor (MOS) transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc.

[0033] The integrated circuit (IC) device 100B also includes contact structures located above and electrically contacting the respective source / drain terminals of the transistors in the active region for electrically coupling the source / drain terminals of the transistors to other circuit elements. These contact structures are sometimes referred to as metal-to-device structures and are designated "MD" in this disclosure. For example, Figure 1B The diagram illustrates MD contact structures 131-134. Example conductive materials for the MD contact structures include metals. Gates 111, 113, 115 and MD contact structures 131-134 are arranged alternately along the X-axis. The pitch between directly adjacent MD contact structures (e.g., MD contact structures 133, 134), i.e., the center-to-center distance along the X-axis, is the same as the pitch CPP (contact polysilicon pitch) between directly adjacent gates (e.g., gates 111, 113). Along the X-axis, two gates (including conductive gates and / or dielectric gates) are considered directly adjacent if there are no other gates (including conductive gates or dielectric gates) between them. Similarly, two MD contact structures are considered directly adjacent if there are no other MD contact structures between them.

[0034] The integrated circuit (IC) device 100B also includes a via structure or via located above and electrically in contact with the corresponding gate or MD structure. A via located above and electrically in contact with the MD structure is sometimes referred to as a device-to-via (VD), and is denoted as "VD" in this disclosure. A via located above and electrically in contact with the gate is sometimes referred to as a gate-to-via (VG), and is denoted as "VG" in this disclosure. Figure 1BIn the example configuration, an exemplary VG via 141 is located above and electrically contacts the gate 111, and an exemplary VD via 142 is located above and electrically contacts the MD contact structure 133. Exemplary materials for the VD and VG vias include metals.

[0035] The integrated circuit (IC) device 100B also includes an interconnect or redistribution structure 150 on its front side 108, which is located above the VD and VG vias and includes multiple metal layers and multiple via layers arranged alternately in the thickness direction (i.e., along the Z-axis) of the substrate 110. The metal layer most directly above and in electrical contact with the VD and VG vias is the metal zero (M0) layer. In other words, the M0 layer is the metal layer located above or closest to the active region on the front side of the substrate. The metal layer immediately above the M0 layer is the metal one (M1) layer, and so on. The conductors or conductive patterns in the M0 layer are referred to herein as M0 conductors or M0 conductive patterns, the conductors or conductive patterns in the M1 layer are referred to herein as M1 conductors or M1 conductive patterns, and so on. A via layer Vn is arranged between the Mn layer and the Mn+1 layer, electrically coupling the Mn layer and the Mn+1 layer, where n is an integer starting from zero. For example, the via zero (V0) layer is the lowest via layer, disposed between layers M0 and M1, and electrically couples layers M0 and M1. Other via layers are V1, V2, etc. The metal layers (e.g., M0, M1, etc.) and via layers (e.g., V0, V1, etc.) on the front side of the substrate are referred to herein as front-side metal layers and front-side via layers. The redistribution structure 150 also includes various interlayer dielectric (ILD) layers (not shown or numbered), in which the metal layers and via layers are embedded. The metal layers and via layers of the redistribution structure 150 are configured to electrically couple various components or circuits of the integrated circuit (IC) device 100B to each other and / or to external circuits. For simplicity, Figure 1B The metal layer and via layer above layer M1 are omitted. Figure 1BIn the example configuration, the M0 layer includes M0 conductors 143 and 144, which are located above and electrically contacted by VG vias 141 and VD vias 142, respectively. The V0 layer includes V0 vias 145 and 146, which are located above and electrically contacted by the M0 conductors 143 and 144, respectively. The M1 layer includes M1 conductors 147 and 148, which are located above and electrically contacted by the V0 vias 145 and 146, respectively. In at least one embodiment, the M0 conductors provide internal wiring for the cell, and the V0 vias, M1 conductors, and / or one or more higher via layers and metal layers provide electrical connections from other cells of the IC device 100B to this cell. Other configurations are also within the scope of various embodiments. In some embodiments, the IC device 100B also includes another redistribution structure (not shown) on the back side 109, sometimes referred to as a back-side redistribution structure, such as a power supply network for configuring the IC device 100B. In some embodiments, this back-side redistribution structure is omitted.

[0036] Figure 1C This is a schematic layout of the circuit area of ​​an IC device 100C according to some embodiments. In some embodiments, the IC device 100C corresponds to one or more of IC devices 100A, 100B, and / or Figure 1C The circuit area in the middle corresponds to Figure 1A Circuit area 103 and / or Figure 1B The circuit area in the diagram. In some embodiments, layout 100C and other layouts described herein with respect to various embodiments are generated by an EDA system (such as an Automatic Placement and Routing (APR) system) and / or stored in a non-transitory computer-readable storage medium. The description herein with respect to layout 100C and other layouts according to various embodiments applies to IC devices that include circuit areas corresponding to said layouts.

[0037] Layout 100C includes a plurality of power rails 160-164 extending along a first axis (i.e., the X-axis) and spaced apart from each other at a center-to-center interval CH (cell height) along a second axis (Y-axis) perpendicular to the first axis. In at least one embodiment, the Y-axis is perpendicular to the X-axis. Power rails 160-164 are configured to provide a first power supply voltage and a second power supply voltage different from the first power supply voltage. For example, the first power supply voltage is one of VSS and VDD, and the second power supply voltage is the other of VSS and VDD. The power rail configured to provide VSS is sometimes referred to herein as the VSS power rail, and the power rail configured to provide VDD is sometimes referred to herein as the VDD power rail. The VDD power rail is an example of a positive power rail. The VDD power rail is an example of one of the first and second power rails, and the VSS power rail is an example of the other of the first and second power rails. The VDD and VSS power rails are arranged alternately along the Y-axis. Figure 1B In the example configuration, power rails 160, 162, and 164 are VSS power rails, which are arranged alternately with VDD power rails including power rails 161 and 163. In some embodiments, power rails 160-164 are elongated MO conductive patterns. In at least one embodiment, one or more of power rails 160-164 are elongated conductive patterns of a back-side redistribution structure.

[0038] Layout 100C also includes multiple units, such as units C1-C5, which are placed therein during a placement operation performed by EDA tools (such as an APR system) relative to power rails 160-164. Figure 1C The elements are schematically represented by their respective boundaries. In a layout operation, the boundaries of one or more elements are placed adjacent to the boundaries of one or more other elements. For example, on the X-axis, element C1 and element C2 are placed adjacent to each other along a common edge 172. On the Y-axis, element C1 and element C3 are placed adjacent to each other along a common edge 173. Elements are not always placed adjacent to each other (or may be placed side by side). For example, element C4 is placed spaced apart from element C2 along the X-axis. The described placement operations are merely examples. Other placement operations are also within the scope of various embodiments.

[0039] The cell is positioned above one or more power rails 160-164 to receive VDD and / or VSS from the power rails. In some embodiments, the cell is positioned such that its respective boundary lies above and coincides with the centerline of the two power rails. The cell's height along the Y-axis corresponds to the center-to-center distance between the two power rails. For example, in Figure 1CIn this example, cell C1 has boundaries with edges 171 and 173 that are located above and coincide with the center lines of power rails 162 and 163, respectively. Therefore, cell C1 has a cell height of 1 CH (single cell height), which is the center-to-center distance between power rails 162 and 163. Similarly, cell C2 has boundaries with edges (unnumbered) that are located above and coincide with the center lines of power rails 162 and 163, respectively. Various devices and / or circuits in cells C1 and C2 are configured to receive VSS from power rail 162 and VDD from power rail 163. As another example, cell C4 has boundaries with edges 175 and 176 that are located above and coincide with the center lines of power rails 160 and 162, respectively. Therefore, cell C4 has a cell height of 2 CH (double cell height), which is the center-to-center distance between power rails 160 and 162. Cell C4 is also located above power rail 161. Various devices and / or circuits in cell C4 are configured to receive VSS from power rails 160, 162 and VDD from power rail 161. The cells described having a single cell height or a double cell height are merely examples. Other cells with larger cell heights (e.g., 3 CH, 4 CH, etc.) are also within the scope of various embodiments.

[0040] The multiple units in layout 100C include functional units and one or more ECO units. For example, units C2, C3, and C4 are functional units, while units C1 and C5 are ECO units.

[0041] Functional units correspond to various functional circuits in an integrated circuit (IC) device. These functional circuits are configured to perform one or more functions of the IC device. In some embodiments, functional circuits include one or more active devices, logic circuits, etc. Examples of logic circuits include, but are not limited to, AND gates, OR gates, NAND gates, NOR gates, XOR gates, inverters (INV), AND-OR inverters (AOI), OR-AND inverters (OAI), multiplexers (MUX), flip-flops, buffers, latches, delay units, clocks, memories, etc. Examples of memory units include, but are not limited to, static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), read-only memory (ROM), etc. Examples of active devices or active elements include, but are not limited to, transistors, diodes, etc.

[0042] An ECO unit comprises an ECO base unit and an ECO programming unit. The ECO programming unit is a programmed ECO base unit. Similar to functional units, the ECO base unit has a pre-configured specific internal layout for various components, such as active regions, gates, MD contact structures, etc. In some embodiments, the ECO base unit is not configured to provide a specific function. In such embodiments, an unprogrammed ECO base unit is inoperable or non-operable compared to an operational or operable functional unit. During the integrated circuit (IC) device design phase, when needed, for example, to improve timing or meet one or more timing requirements, one or more placed ECO base units can be programmed to operate and provide one or more functions similar to functional units. Examples of functions provided by a programmed ECO unit include, but are not limited to, inverters, NAND gates, NOR gates, XOR gates, D latches, decoupling capacitors (DCAPs), AND-OR inverters (AOIs), OR-AND inverters (OAIs), multiplexers, flip-flops, etc.

[0043] In some embodiments, an ECO base cell is programmed into a programmed ECO cell by changing one or more connections within the ECO base cell (e.g., VD vias, VG vias, MO conductive patterns, V0 vias, etc.). In at least one embodiment, programming an ECO base cell includes replacing an ECO base cell placed in a layout with a predefined programmed ECO cell stored in and read from a cell library. The predefined programmed ECO cell has the same configuration of active regions, gates, and MD contact structures as the ECO base cell, thereby minimizing changes or modifications to the layout. The programmed ECO cell differs from the ECO base cell in one or more connections within the ECO cell (e.g., VD vias, VG vias, MO conductive patterns, V0 vias, etc.). In some embodiments, since the ECO base cell is not inoperable, it is not routed in routing operations following the placement operation. When one or more ECO base units are programmed, they are converted into one or more operable programmed ECO units. During a rerouting operation, the programmed ECO units are routed to allow operative connection to one or more functional units in the layout. In a non-limiting example, units C1 and C5, initially placed in layout 100C, are ECO base units. Subsequently, unit C1 is programmed as a programmed ECO unit, or replaced with a programmed ECO unit, while unit C5 remains an ECO base unit. During the rerouting operation, unit C1 is routed to allow operative connection to one or more functional units in layout 100C, while unit C5 remains unrouted, i.e., not operatively connected to any functional unit in layout 100C.

[0044] In some embodiments, instead of one or more ECO base units, one or more programmed ECO units are initially placed in the layout during a placement operation. In at least one embodiment, these initially placed programmed ECO units are not configured to provide logic functionality, but rather to provide functionality independent of the logic operation of the IC device. For example, the initially placed programmed ECO units are configured to provide decoupling functionality and include one or more decoupling capacitors. Such programmed ECO units are sometimes referred to as DCAP units or fill units. In other words, in one or more embodiments, the ECO base unit is a DCAP unit. In some embodiments, the initially placed DCAP unit is electrically coupled to a corresponding VSS power rail and / or VDD power rail, but is not otherwise operatively coupled or routed to a functional unit in the layout. When needed, at least one initially placed DCAP unit is programmed into another programmed ECO unit, or replaced with another programmed ECO unit configured to provide functionality other than decoupling functionality. This other programmed ECO unit is then routed during a rerouting operation to operatively connect to one or more functional units in the layout. In a non-limiting example, units C1 and C5, initially placed in layout 100C, are DCAP units. Subsequently, unit C1 is programmed to be another programmed ECO unit or replaced by another programmed ECO unit, such as an inverter unit, while unit C5 remains a DCAP unit. Unit C1 (now an inverter unit) is rerouted during a rerouting operation to be operatively connected to one or more functional units in layout 100C, while unit C5 remains unrouted, i.e., not operatively connected to any functional unit in layout 100C. In at least one embodiment, the layout initially contains one or more ECO base units and one or more DCAP units for subsequent replacement with programmed ECO units. Other arrangements are also within the scope of various embodiments.

[0045] Figure 1D Circuit diagrams of various pseudo-devices 181-188 that are not desired or prohibited in one or more ECO units according to some embodiments.

[0046] In some embodiments, a pseudo device refers to a device or transistor that is not configured to perform any function. Pseudo devices that pose a potential risk (e.g., ESD risk) are considered undesirable or prohibited, and according to some embodiments, they are not included in the ECO unit. There are three types of prohibited pseudo devices: floating source / drain pseudo devices, inverter pseudo devices, and output pseudo devices.

[0047] Pseudo-devices 181 and 182 are examples of floating source / drain pseudo-devices. Pseudo-device 181 is a P-type transistor, such as a PMOS transistor, with its gate electrically coupled to VDD and having two floating source / drain terminals. Pseudo-device 182 is an N-type transistor, such as an NMOS transistor, with its gate electrically coupled to VSS and having two floating source / drain terminals. In some cases, the gate of pseudo-device 181 being electrically coupled to VDD can pose an ESD risk. This is because VDD is supplied to the gate of pseudo-device 181 via a VDD power rail as described herein. The VDD power rail is typically a large and long metal mesh or pattern that can accumulate a significant amount of charge during the fabrication of integrated circuit (IC) devices. Specifically, in fabrication operations following the formation of transistors or devices in an IC device, various dielectric and metal layers are deposited and patterned to obtain conductive vias and / or patterns electrically coupled to the transistor gate. Deposition and / or patterning operations typically include plasma operations, such as plasma etching, plasma deposition, etc. During plasma operation, a sufficiently large amount of charge may accumulate on the conductor coupled to the gate (e.g., the VDD power rail in the case of dummy device 181), leading to breakdown and related damage to the underlying gate dielectric layer. This problem, known as "plasma-induced gate oxide damage" (PID) or "antenna effect," can cause yield and / or reliability issues during semiconductor manufacturing. In some embodiments, the ECO cell (whether an ECO base cell or a programmed ECO cell) does not contain a gate directly electrically coupled to the positive power rail, thus avoiding the aforementioned antenna effect violation risk.

[0048] Pseudo-devices 183 and 184 are examples of inverter pseudo-devices. Pseudo-device 183 is a P-type transistor, such as a PMOS transistor, with its gate electrically coupled to the input network and each of its two source / drain terminals electrically coupled to the output network. Pseudo-device 184 is an N-type transistor, such as an NMOS transistor, with its gate electrically coupled to the input network and each of its two source / drain terminals electrically coupled to the output network.

[0049] Pseudo-devices 185-188 are examples of output pseudo-devices. Pseudo-device 185 is a P-type transistor, such as a PMOS transistor, with its gate electrically coupled to the power rail, one source / drain electrically coupled to the signal network, and the other source / drain coupled to the output network. Pseudo-device 184 is an N-type transistor, such as an NMOS transistor, with its gate electrically coupled to the power rail, one source / drain electrically coupled to the signal network, and the other source / drain coupled to the output network. The power rail coupled to the gate of pseudo-device 185 or pseudo-device 186 is the VDD power rail or the VSS power rail, and is schematically marked as "PG" (power ground). Pseudo-device 187 is a P-type transistor, such as a PMOS transistor, with its gate electrically coupled to the signal network, one source / drain electrically coupled to the output network, and the other source / drain floating. Pseudo-device 188 is an N-type transistor, such as an NMOS transistor, with its gate electrically coupled to the signal network, one source / drain electrically coupled to the output network, and the other source / drain floating.

[0050] The ECO units described herein with respect to various embodiments do not include or contain dummy devices 181-188. For example, regarding Figure 1C Units C1 and C5, whether initially placed, replaced, or programmed, do not contain pseudo-devices 181-188.

[0051] Figures 2A-2D This includes circuit diagrams and voltage characteristics of various devices or transistors PMOS1, PMOS2, NMOS1, NMOS2 in one or more ECO cells according to some embodiments. In some embodiments, one or more transistors PMOS1, PMOS2, NMOS1, NMOS2 are included in the ECO cell. According to some embodiments, these transistors PMOS1, PMOS2, NMOS1, NMOS2 are sometimes referred to as drive transistors and are configured to provide various soft power supply voltages to other devices or transistors in the ECO cell.

[0052] exist Figure 2A In this transistor, PMOS1 includes source / drain terminals 211 and 212 and a gate 213. The source / drain and gate of the transistor are sometimes collectively referred to as the transistor's terminals. Source / drain 211 is configured to receive VDD. Source / drain 212 is configured to output a soft supply voltage corresponding to VDD (Soft VDD). Gate 213 is configured to receive VSS or a soft supply voltage corresponding to VSS (Soft VSS). Soft VSS will combine with... Figure 2C , Figure 2DOne or more of the following are described: VDD is an example of one of a first power supply voltage and a second power supply voltage different from the first power supply voltage. VSS is an example of the other of the first power supply voltage and the second power supply voltage. Soft VDD is an example of one of a first voltage corresponding to the first power supply voltage and a second voltage corresponding to the second power supply voltage. Soft VSS is an example of the other of the first voltage and the second voltage.

[0053] Figure 2A It also includes the voltage characteristic 215 of transistor PMOS1. In some embodiments, the gate 213 of transistor PMOS1 is configured to receive VSS, thereby turning transistor PMOS1 on. In at least one embodiment, the gate 213 of transistor PMOS1 is configured to receive soft VSS, which is as follows: Figure 2C The described constant voltage close to VSS, or as Figure 2D The described voltage hovering around VSS. In some embodiments, whether the soft VSS is a constant voltage close to VSS or a voltage hovering around VSS, the soft VSS is lower than the threshold voltage Vt_PMOS of the PMOS transistor (such as transistor PMOS1). Figure 2B (As described). Therefore, transistor PMOS1 is turned on by the VSS or soft VSS received by its gate 213. The VDD supplied to the source / drain 211 is output as soft VDD at the source / drain 212 through the turned-on transistor PMOS1. The soft VDD at the source / drain 212 is a constant voltage close to VDD. In at least one embodiment, the difference between the soft VDD at the source / drain 212 and VDD is the voltage drop Vd_PMOS across transistor PMOS1 in the on state. In at least one embodiment, the voltage drop Vd_PMOS is negligible, and the soft VDD is essentially equal to VDD.

[0054] exist Figure 2BIn this embodiment, transistor PMOS2 includes source / drain electrodes 221 and 222 and a gate 223. Source / drain electrode 221 is configured to receive VDD. Source / drain electrode 222 is configured to output soft VDD. Gate 223 is configured to receive soft VDD. In at least one embodiment, source / drain electrode 222 and gate 223 are electrically coupled to each other to provide the soft VDD output at source / drain electrode 222 to gate 223 of transistor PMOS2. In some embodiments, the soft VDD provided to gate 223 of transistor PMOS2 is output from a transistor with a similar configuration to transistor PMOS2. For simplicity, this document describes one or more operations of transistor PMOS2 with respect to embodiments where source / drain electrode 222 and gate 223 are electrically coupled to each other. Embodiments where the soft VDD provided to gate 223 of transistor PMOS2 is output from a transistor with a similar configuration to transistor PMOS2 include similar operations.

[0055] Figure 2B The voltage characteristics 225 of transistor PMOS2 are further illustrated. Initially, the voltage at the gate 223 of transistor PMOS2 is low. When the source / drain 221 receives VDD, transistor PMOS2 is in the on state, causing the soft VDD at the source / drain 222 to be pulled up to VDD or a voltage level close to VDD, such as... Figure 2A As shown. This state is... Figure 2B The time t1 is shown in the diagram. A soft VDD with a voltage level at or near VDD is supplied from the source / drain 222 to the gate 223, thereby turning off the transistor PMOS2. The conductive pattern coupled to the source / drain 222 (also known as the soft VDD network) is configured to transfer the soft VDD to the gate 223 and / or other devices, and has parasitic coupling with one or more other adjacent conductive patterns (or networks). Due to this capacitive coupling, the soft VDD on the soft VDD network decreases, for example, gradually decreasing, as... Figure 2B As shown. At time t2, the soft VDD on the soft VDD network (also at gate 223) reaches the threshold voltage Vt_PMOS, causing transistor PMOS2 to turn on. The on-state transistor PMOS2 causes VDD at source / drain 221 to pull the soft VDD at source / drain 222 up to or near VDD. This process is then repeated. For example, transistor PMOS2 turns off again, and the soft VDD on the soft VDD network decreases again until the soft VDD reaches the threshold voltage Vt_PMOS at time t3. At this point, transistor PMOS2 momentarily turns on to pull the soft VDD up to or near VDD, and this cycle repeats. Therefore, the soft VDD output by transistor PMOS2 at source / drain 222 is a voltage hovering around VDD, or a voltage varying between VDD and the threshold voltage Vt_PMOS.

[0056] exist Figure 2C In the NMOS transistor, there are source / drain terminals 231 and 232, and a gate 233. Source / drain terminal 231 is configured to receive VSS. Source / drain terminal 232 is configured to output a soft supply voltage corresponding to VSS, softVSS. Gate 233 is configured to receive soft VDD, as per [reference to...]. Figure 2A , Figure 2B One or more of the ones described in the document.

[0057] Figure 2C This also includes the voltage characteristics 235 of transistor NMOS1. The soft VDD at 233 of transistor NMOS1 is as follows... Figure 2A The constant voltage close to VDD shown, or as... Figure 2B The voltage shown hovers around VDD. In some embodiments, whether soft VDD is a constant voltage close to VDD or a voltage hovering around VDD, soft VDD is higher than the threshold voltage Vt_NMOS of the NMOS transistor (e.g., transistor NMOS1). Figure 2D (As shown). Therefore, transistor NMOS1 is turned on by soft VDD at gate 233. The VSS supplied to the source / drain 231 is output as soft VSS at source / drain 232 through the turned-on transistor NMOS1. The soft VSS at source / drain 232 is a constant voltage close to VSS. In at least one embodiment, the difference between the soft VSS at source / drain 232 and VSS is the voltage drop Vd_NMOS across transistor NMOS1 in the on state.

[0058] exist Figure 2D In this embodiment, the NMOS2 transistor includes source / drain terminals 241 and 242 and a gate 243. Source / drain terminal 241 is configured to receive a soft VSS. Source / drain terminal 242 is configured to output a soft VSS. Gate 243 is configured to receive a soft VSS. In at least one embodiment, source / drain terminals 242 and gate 243 are electrically coupled to each other to provide a soft VSS output at source / drain terminal 242 to gate 243 of the NMOS2 transistor. In some embodiments, the soft VSS provided to gate 243 of the NMOS2 transistor is output from a transistor with a similar configuration to the NMOS2 transistor. For simplicity, one or more operations of the NMOS2 transistor are described herein with respect to embodiments where source / drain terminals 242 and gate 243 are electrically coupled to each other. The operation is similar for embodiments where a soft VSS is provided to gate 243 of the NMOS2 transistor from an output of a transistor with a similar configuration to the NMOS2 transistor.

[0059] Figure 2DThe voltage characteristics 245 of transistor NMOS2 are further illustrated. Initially, the voltage at the gate 243 of transistor NMOS2 is low, and transistor NMOS2 is in the off state, causing the soft VSS at the source / drain 242 to be at or near VSS. This state... Figure 2D The time interval t4 is shown in the diagram. A conductive pattern (also called a soft VSS network) coupled to source / drain 242 and configured to transfer soft VSS to gate 243 and / or other devices has parasitic coupling with one or more other adjacent conductive patterns (or networks). Due to this capacitive coupling, the soft VSS on the soft VSS network increases, for example, gradually, as... Figure 2D As shown. At time t5, the soft VSS on the soft VSS network (also at gate 243) reaches the threshold voltage Vt_NMOS, thus turning on transistor NMOS2. The conducting transistor NMOS2 causes the VSS at source / drain 241 to pull the soft VSS at source / drain 242 down to or near the VSS voltage level, as shown in the diagram. Figure 2C The process is then repeated. For example, transistor NMOS2 turns off again, and the soft VSS on the soft VSS network increases again until, at time t6, the soft VSS reaches the threshold voltage Vt_NMOS. At this point, transistor NMOS2 instantaneously turns on to pull the soft VSS to VSS or a voltage level close to VSS, and this cycle repeats. Therefore, the soft VSS output by transistor NMOS2 at source / drain 242 is a voltage that hovers around VSS, or a voltage that varies between VSS and the threshold voltage Vt_NMOS.

[0060] In some embodiments, at least one soft supply voltage (such as soft VDD or soft VSS) output by one or more transistors PMOS1, PMOS2, NMOS1, NMOS2 in the ECO unit is provided to one or more other devices in the ECO unit. In at least one embodiment, the soft supply voltage is provided to one or more sources / drains in the ECO unit, thereby avoiding one or more problems associated with floating sources / drains, and / or eliminating them from the ECO unit. Figure 1D The prohibited dummy devices are shown. In at least one embodiment, a soft VDD is provided to the device gate in the ECO unit instead of VDD. Therefore, a direct electrical connection between the gate and the VDD power rail can be avoided, thereby avoiding or reducing the risk of ESD or antenna effect violations.

[0061] Figure 3A , Figure 3B , Figure 3CElectrical diagrams of various example circuits 301-306 in one or more ECO units according to some embodiments are shown. In some embodiments, the ECO unit includes more than one circuit of circuits 301-306 and / or multiple circuit instances of circuits 301-306. For simplicity of description, Figures 3A-3C The corresponding components are represented by the same reference numbers.

[0062] Figure 3A Circuit 301 includes PMOS transistors P31 and P32. One source / drain of transistor P31 is configured to receive VDD, for example, from the VDD power rail, and the other source / drain is coupled to a soft VDD network 311, with its gate configured to receive VSS, soft VSS, or soft VDD. When the gate of transistor P31 is configured to receive VSS (e.g., from the VSS power rail) or soft VSS (e.g., from the soft VSS network), transistor P31 corresponds to... Figure 2A The transistor PMOS1 is described in the document. When the gate of transistor P31 is configured to receive soft VDD (e.g., from a soft VDD network), transistor P31 corresponds to... Figure 2B The transistor PMOS2 is described in the text.

[0063] Transistor P32 has one source / drain configured to receive a VDD voltage from, for example, a VDD power rail, and another source / drain and gate coupled to transistor P31 via a soft VDD network 311. Therefore, transistor P32 has two terminals for receiving the soft VDD voltage. In some embodiments, transistor P32 corresponds to... Figure 2B The transistor PMOS2 described in the figure has a gate 223 electrically coupled to the source / drain 222.

[0064] In example operation according to some embodiments, when the gate of transistor P31 is configured to receive VSS or soft VSS, the soft VDD on the soft VDD network 311 is a constant voltage close to VDD (e.g., Figure 2A (as shown), and keeps transistor P32 off.

[0065] In a further example operation according to some embodiments, when the gate of transistor P31 is configured to receive soft VDD, the soft VDD on the soft VDD network 311 is a voltage hovering near VDD, causing transistor P32 to periodically turn on and off momentarily, as... Figure 2B As shown.

[0066] Other alternative configurations of circuit 301 are also within the scope of various embodiments. For example, in some embodiments, a VSS or soft VSS is provided to the gate of transistor P32 instead of a soft VDD, in which case the electrical connection between the gate of transistor P32 and the soft VDD network 311 is omitted.

[0067] Figure 3A Circuit 302 is similar to circuit 301, but uses NMOS transistors instead of PMOS transistors. Specifically, circuit 302 includes NMOS transistors N31 and N32. One source / drain of transistor N31 is configured to receive VSS, for example from the VSS power rail, the other source / drain is evenly connected to soft VSS network 312, and its gate is configured to receive soft VDD or soft VSS. When the gate of transistor N31 is configured to receive soft VDD, for example from the soft VDD network, then transistor N31 corresponds to Figure 2C The transistor NMOS1 is described in the text. When the gate of transistor N31 is configured to receive a soft VSS, for example from a soft VSS network, then transistor N31 corresponds to... Figure 2D The transistor NMOS2 is described in the text.

[0068] The gate of transistor N32 is configured to receive VSS, such as VSS from the VSS power rail, and its source / drain is coupled to transistor N31 via a soft VSS network 312. Therefore, transistor N32 has two terminals for receiving the soft VSS. In some embodiments, transistor N32 corresponds to... Figure 2D The transistor NMOS2 described in the figure has a gate 243 electrically coupled to a source / drain 242.

[0069] In example operation according to some embodiments, when the gate of transistor N31 is configured to receive soft VDD, the soft VSS on soft VSS network 312 is a near-constant voltage of VSS (as per [reference]). Figure 2C (as described above), and keep transistor N32 in the off state.

[0070] In a further example operation according to some embodiments, when the gate of transistor N31 is configured to receive a soft VSS, the soft VSS on the soft VSS network 312 is a voltage hovering near the VSS, causing transistor N32 to periodically turn on and off momentarily, as... Figure 2D As shown.

[0071] Other alternative configurations of circuit 302 are also within the scope of various embodiments. For example, in some embodiments, a soft VDD is provided to the gate of transistor N32 instead of a soft VSS, in which case the electrical connection between the gate of transistor N32 and the soft VSS network 312 is omitted. In some embodiments, circuits 301, 302 are example circuits for addressing problems related to preventing floating source / drain dummy devices.

[0072] Figure 3BCircuit 303 includes PMOS transistors P31 and P33. The source / drain of transistor P33 is coupled to transistor P31 via a soft VDD network 311, and its gate is coupled to the input network. Therefore, transistor P33 has two terminals for receiving soft VDD. The voltage on the input network does not affect the operation of circuit 303 because the source / drain of transistor P33 is electrically coupled to each other, thus configuring transistor P33 as a dummy device. In some embodiments, the voltage on the input network coupled to the gate of transistor P33 is one of VSS, soft VSS, or soft VDD.

[0073] Figure 3B Circuit 304 is similar to circuit 303, but includes NMOS transistors instead of PMOS transistors. Specifically, circuit 304 includes NMOS transistors N31 and N33. The source / drain of transistor N33 is coupled to transistor N31 via a soft VSS network 312, and its gate is coupled to the input network. Therefore, transistor N33 has two terminals for receiving soft VSS. The voltage on the input network does not affect the operation of circuit 304 because the source / drain of transistor N33 is electrically coupled to each other, thus configuring transistor N33 as a dummy device. In some embodiments, the voltage on the input network coupled to the gate of transistor N33 can be one of VSS, soft VSS, or soft VDD.

[0074] In some embodiments, circuits 303 and 304 are example circuits for solving problems related to the prohibition of inverter pseudo-devices.

[0075] Figure 3C Circuit 305 includes PMOS transistors P31 and P34. All three terminals of transistor P34 (i.e., source / drain and gate) are coupled to transistor P31 via soft VDD network 311. PMOS transistor P34 is configured as a dummy device.

[0076] Figure 3C Circuit 306 is similar to circuit 305, but includes NMOS transistors instead of PMOS transistors. Specifically, circuit 306 includes NMOS transistors N31 and N34. All three terminals (source / drain and gate) of transistor N34 are coupled to transistor N31 via a soft VSS network 312. NMOS transistor N34 is configured as a dummy device.

[0077] In some embodiments, circuits 305 and 306 are example circuits for solving problems related to suppressing output pseudo-devices.

[0078] In some embodiments, the inclusion of one or more of circuits 301-306 or alternative configurations thereof in the ECO unit can avoid one or more problems associated with floating source / drain and / or ESD risks, and / or eliminate the prohibition of dummy devices 181-188 from the ECO unit. Figure 4A , Figure 4B , Figure 4D A non-limiting example layout of an ECO cell containing one or more of the circuits 301-306 is described.

[0079] Figure 4A This is a layout diagram of an ECO unit 400A according to some embodiments. In some embodiments, the ECO unit 400A corresponds to Figure 1A The area in circuit region 103 shown, and / or Figure 1B The area in the IC device 100B shown, and / or Figure 1C The ECO unit in layout 100C is shown. In at least one embodiment, ECO unit 400A is an ECO unit initially placed in the IC device layout (hereinafter referred to as "IC layout") for later programming (or replacement) when the IC layout is modified. In some embodiments, ECO unit 400A is a programmed ECO unit used to replace another previous or initially placed ECO unit (e.g., an ECO base unit) in the IC layout to modify the IC layout. In at least one embodiment, ECO unit 400A is stored as a standard unit in a unit library on a non-transitory computer-readable medium.

[0080] ECO unit 400A includes active regions OD1 and OD2 with different conductivity types. Active region OD1 is an example of one of a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type. Active region OD2 is an example of the other of the first and second active regions. Figure 4AIn the example configuration, the first active region OD1 is a P-type active region, and the second active region OD2 is an N-type active region. In one or more embodiments, the first active region OD1 is an N-type active region, and the second active region OD2 is a P-type active region. The active regions OD1 and OD2 extend along a first axis (i.e., the X-axis). The active regions OD1 and OD2 contain P-type dopants and / or N-type dopants to form one or more circuit elements or devices. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with bulging source / drain electrodes, nanosheet FETs, nanowire FETs, etc. The active region configured to form one or more PMOS devices is sometimes referred to as a "PMOS active region". The active region configured to form one or more NMOS devices is sometimes referred to as the "NMOS active region".

[0081] ECO unit 400A also includes multiple gate regions or gates 410-418 that extend continuously across active regions OD1 and OD2 along a second axis (i.e., the Y-axis). In at least one embodiment, the Y-axis is perpendicular to the X-axis. Some of the gates 410-418 are conductive gates, which together with the active regions OD1 and OD2 form corresponding transistors. The other gates 410-418 are dielectric gates, which do not form transistors with the active regions OD1 and OD2. For example, gates 411, 413, 414, 416, and 417 are conductive gates, each of which together with the active regions OD1 and OD2 forms a PMOS transistor and an NMOS transistor, respectively, with gates electrically coupled to each other. Specifically, conductive gates 411, 413, 414, 416, and 417 form PMOS transistors P1-P5 with the active region OD1 and NMOS transistors N1-N5 with the active region OD2.

[0082] Gates 410, 412, 415, and 418 are dielectric gates, sometimes also referred to as "CPODEs". In some embodiments, the dielectric gate corresponds to an insulating structure that extends along the thickness direction (e.g., ...). Figure 1B The Z-axis (as shown) extends across the underlying active region to physically and electrically separate the two parts of the active region from each other. For example, dielectric gate 412 corresponds to an insulating structure that separates the left side of dielectric gate 412 ( Figure 4A The active region OD1 (or OD2) of the dielectric gate 412 is physically and electrically separated from the other active region OD1 (or OD2) on the right side of the dielectric gate 412. In other words, the dielectric gate 412 separates the active region OD1 (or OD2) adjacent to the left side of the dielectric gate 412 (…). Figure 4A The source / drain of transistor P1 (or N1) in the middle is physically and electrically separated from the source / drain of transistor P2 (or N2) to the right of the adjacent dielectric gate 412. Gates 410-418 include conductive gates and dielectric gates, as per [reference to...]. Figure 1B As described above, they are arranged side by side along the X-axis at a spacing or pitch of 1 CPP.

[0083] In at least one embodiment, the center lines of dielectric gates 410, 418 coincide with the corresponding vertical edges of the boundary (not shown) of ECO cell 400A. The vertical edges coinciding with the center lines of dielectric gates 410, 418 extend along the Y-axis. The boundary of ECO cell 400A corresponds to... Figure 1C The boundary of the ECO cell (e.g., cell C1) is shown. In placement operations according to some embodiments, when the ECO cell 400A is placed adjacent to another cell (e.g., similar to...), Figure 1C When cell C1 and cell C2 are adjacent, one of the dielectric gates 410 and 418 merges with the dielectric gate on the corresponding vertical edge of the boundary of the other cell. The boundary of ECO cell 400A also includes a horizontal edge extending along the X-axis. In some embodiments, the horizontal edge of the boundary of ECO cell 400A merges with the dielectric gate on the corresponding vertical edge of the boundary of the other cell. Figure 1C The center lines of the corresponding power rails shown coincide, and / or the center lines of the power rails M0_VSS and M0_VDD as described herein coincide. In some embodiments, various features of the ECO cell 400A described herein, such as the active region, gate, MD contact structure, VD via (other than the VDR via described herein), VG via, M0 conductor (other than the power rails), etc., are all confined within the boundaries of the ECO cell 400A.

[0084] The described configuration of the ECO unit 400A includes two active regions OD1 and OD2 that are adjacent to each other (or directly adjacent) along the Y-axis; this is merely an example. In various embodiments, other units include other numbers of active regions arranged along the Y-axis. When there are no other active regions between two active regions, the two active regions are adjacent along the Y-axis. The ECO unit 400A with two active regions has the following characteristics: Figure 1C The height of a single cell (1 CH) is shown. In some embodiments, the cell height is the distance between the horizontal edges of the boundary of the ECO cell 400A along the Y-axis, for example, the distance between the power rails M0_VSS and M0_VDD along the Y-axis.

[0085] The ECO unit 400A also includes MD contact structures 420-427 located above the corresponding source / drain regions of transistors P1-P5 in the active region OD1, and MD contact structures 430-437 located above the corresponding source / drain regions of transistors N1-N5 in the active region OD2. The MD contact structures and gates are arranged alternately along the X-axis. The spacing (i.e., center-to-center distance) along the X-axis between adjacent MD contact structures is the same as the pitch CPP between adjacent gates. In some embodiments, the shape and / or size of the MD contact structures are defined by one or more cut MD (CMD) mask regions of a CMD mask. Figure 4A The example configuration shows three CMD mask areas 419, 429, and 439. CMD mask area 419 defines the upper edge of MD contact structures 420-427 ( Figure 4A (Middle). CMD mask area 439 defines the lower edge of MD contact structure 430-437 ( Figure 4A (in the middle). CMD mask area 429 defines the lower edge of MD contact structure 420-427 (in the middle). Figure 4A The upper edge of the MD contact structure 430-437 (in the middle) and MD contact structure 430-437 (in the middle) Figure 4A (Middle). Along the Y-axis, MD contact structures 420-427 are aligned with MD contact structures 430-437 and separated by CMD mask area 429.

[0086] The ECO unit 400A also includes the BCMD component of the logic operation layer BCMD. Figure 4A In the example configuration, three BCMD components along the upper horizontal edge of the boundary of ECO unit 400A (e.g., along power rail M0_VDD) are collectively designated as BCMD component 428. Two BCMD components along the lower horizontal edge of the boundary of ECO unit 400A (e.g., along power rail M0_VSS) are collectively designated as BCMD component 438. In placement operations according to some embodiments, when ECO unit 400A is placed adjacent to another unit (e.g., similar to...), Figure 1C (In the case where unit C1 is adjacent to unit C3), one or more BCMD parts 428 or one or more BCMD parts 438 merge with the corresponding BCMD parts of the corresponding horizontal edge of the boundary of another unit.

[0087] The ECO unit 400A also includes VG and VD vias located above the respective gate and MD contact structures. Some VD vias are configured for electrical connection to the power rails, while others are not configured for such connection. Hereinafter, the VD vias configured for power rail connection will be referred to as VDR vias to distinguish them from the other VD vias not configured for power rail connection. Figure 4AIn the example configuration, ECO unit 400A includes VDR vias 440, 442, and 446, which are located above the source / drain terminals of MD contact structures 420, 422, and 426 and below them, respectively, and are configured for electrical connection to the VDD power rail along power rail M0_VDD. ECO unit 400A also includes VDR vias 441 and 445, which are located above the source / drain terminals of MD contact structures 430 and 436 and below them, respectively, and are configured for electrical connection to the VSS power rail along power rail M0_VSS. ECO unit 400A also includes VD vias 451, 453, 454, 455, 457, 461, 462, 463, 464, 465, 466, and 467, which are located above the source / drain electrodes below the MD contact structures 421, 423, 424, 425, 427, 431, 432, 433, 434, 435, 436, and 437, respectively. The VDR vias are larger than the other VD vias in both the X and Y axes. ECO unit 400A also includes VG vias 471, 473, 474, 476, and 477, located above the conductive gates 411, 413, 414, 416, and 417, respectively.

[0088] The ECO unit 400A also includes conductive patterns or conductors in the M0 layer. For simplicity, Figure 4A The M0 conductor is not fully shown; it is represented schematically by an arrow. Figure 4A In the example configuration, the ECO unit 400A includes M0 conductors 481, 482, 483, and 484 along the corresponding tracks M0_1, M0_2, M0_3, and M0_4 in the M0 layer. In functional circuits, functional units, or programmed ECO units, the M0 conductors along tracks M0_1, M0_2, M0_3, and M0_4 are configured to transmit signals, such as data, control, and clock signals, between various circuit elements of the IC device. Therefore, tracks M0_1, M0_2, M0_3, and M0_4 are sometimes referred to as signal tracks. The ECO unit 400A also includes a VSS power rail (not shown) and a VDD power rail (not shown) along the corresponding tracks M0_VSS and M0_VDD in the M0 layer. Therefore, the tracks M0_VSS and M0_VDD along which the power rails are arranged are sometimes referred to as power tracks. The signal tracks and power tracks in the M0 layer are sometimes collectively referred to as the M0 tracks.

[0089] The M0 track and its corresponding M0 conductor extend along the X-axis and are spaced apart from each other along the Y-axis. In some embodiments, the M0 track coincides with or indicates the centerline of the M0 conductor along which it is arranged. In at least one embodiment, the power tracks M0_VSS and M0_VDD coincide with the horizontal edge of the boundary of the ECO unit 400A, respectively. This coincidence is merely an example, and other configurations are within the scope of various embodiments. In some embodiments, such as Figure 1C As shown, power rails extend continuously along the X-axis, spanning multiple cells in the circuit area to provide VDD and VSS to these cells. The power rails are longer (along the X-axis) and wider (along the Y-axis) than the M0 conductors along the signal rails. In some embodiments, a row of cells with a cell height of 1 CH is defined between a pair of adjacent power rails. Two power rails (or power tracks) are adjacent when there are no other power rails between them along the Y-axis. Similarly, two signal tracks are adjacent when there are no other signal tracks between them along the Y-axis. Furthermore, two M0 tracks are adjacent when there are no other M0 tracks between them along the Y-axis. The number of four signal tracks M0_1, M0_2, M0_3, and M0_4 between a pair of adjacent power rails M0_VSS and M0_VDD (or above a pair of P-type and N-type active regions, or above a single cell height of 1 CH) is merely an example. Other configurations are also within the scope of various embodiments as described herein.

[0090] In some embodiments, the M0 conductors in the M0 layer belong to the same mask. In at least one embodiment, the M0 conductors in the M0 layer are divided into several masks to meet one or more design and / or manufacturing requirements. For example, the M0 conductors (including the VSS power rail) along the M0 tracks M0_VSS, M0_2, and M0_4 belong to one mask, sometimes referred to as the "M0_A mask", while the M0 conductors (including the VDD power rail) along the M0 tracks M0_1, M0_3, and M0_VDD belong to another mask, sometimes referred to as the "M0_B mask".

[0091] exist Figure 4A In the example configuration, conductor M0 481 is located above and electrically coupled to vias VG 476 and VD 461, 462, 463, 464, and 467. Conductor M0 482 is located above and electrically coupled to vias VG 471, 473, and 474 and VD 465 and 466. Conductor M0 483 is located above and electrically coupled to vias VG 477 and VD 451. Conductor M0 484 is located above and electrically coupled to vias VD 453, 454, 455, and 457. Therefore, the electrical coupling of transistors P1-P5 and N1-N5 is as follows.

[0092] Transistor P1 is electrically coupled from its source to its drain by receiving VDD from the VDD power rail through MD contact structure 420 and VDR via 440, and its gate 411 is electrically coupled by receiving VSS from the VSS power rail through M0 conductor 482, MD contact structure 436 and VDR via 445. Transistor P1 corresponds to... Figure 2A The transistor PMOS1 or Figures 3A-3CThe transistor P31 is configured to output soft VDD from another source / drain to the M0 conductor 483 via the MD contact structure 421.

[0093] Similar to transistor P1, transistor P2 has its source / drain electrically coupled to receive VDD from the VDD power rail, and its gate 413 electrically coupled to receive VSS from the M0 conductor 482. Transistor P2 corresponds to Figure 2A The described transistor PMOS1 or Figures 3A-3C The transistor P31 is described and is configured to output soft VDD from another source / drain to the M0 conductor 484 via the MD contact structure 423.

[0094] Transistor P3 is electrically coupled to its source and drain to receive soft VDD from conductor M0 484, and its gate 414 is electrically coupled to receive VSS from conductor M0 482. Transistor P3 corresponds to Figure 3B The transistor P33 is described in the text. Transistor P3 is electrically coupled as a decoupling capacitor.

[0095] Transistor P4 is electrically coupled from its source to its drain to receive VDD from the VDD power rail via the MD contact structure 426 and the VDR via 446, and electrically coupled from its gate 416 to receive soft VSS from the M0 conductor 481 (described herein with reference to transistor N5). Transistor P4 corresponds to Figure 2A The transistor PMOS1 or described in the document Figures 3A-3C The transistor P31 described herein is configured to output soft VDD from another source / drain to the M0 conductor 484 via the MD contact structure 425.

[0096] Transistor P5 has a source / drain electrical coupling to receive VDD from the VDD power rail, and a gate 417 electrical coupling to receive soft VDD from the M0 conductor 483. Transistor P5 corresponds to Figure 2B The transistor PMOS2 or described in Figures 3A-3C The transistor P31 described herein is configured to output soft VDD from another source / drain to the M0 conductor 484 via the MD contact structure 427. Figure 4A The circuit diagrams for transistors P4 and P5 were also shown.

[0097] Transistor N1 is electrically coupled at its source / drain by receiving VSS from the VSS power rail through the MD contact structure 430 and the VDR via 441, and electrically coupled at its gate 411 by receiving VSS from the M0 conductor 482. Due to the VSS at the gate 411, transistor N1 is always in the off state.

[0098] The source and drain of transistor N2 are electrically coupled to receive soft VSS from conductor 481 of M0, and the gate 413 is electrically coupled to receive VSS from conductor 482 of M0. Transistor N2 corresponds to Figure 3B The transistor N33 is described in the text.

[0099] Similar to transistor N2, transistor N3 has its source / drain electrically coupled to receive soft VSS from conductor 481 of the M0 circuit, and its gate 414 electrically coupled to receive VSS from conductor 482 of the M0 circuit. Transistor N3 corresponds to... Figure 3B The transistor N33 is described in the text.

[0100] The source and drain of transistor N4 are electrically coupled to receive VSS from conductor 482 of M0, and the gate 416 is electrically coupled to receive soft VSS from conductor 481 of M0.

[0101] Transistor N5 is electrically coupled at its source / drain to receive VSS from the VSS power rail via the MD contact structure 436 and the VDR via 445, and electrically coupled at its gate 417 to receive soft VDD from the M0 conductor 483. Transistor N5 corresponds to Figure 2C The transistor NMOS1 or described in the document Figures 3A-3C The transistor N31 described herein is configured to output a soft VSS from another source / drain to the M0 conductor 481 via the MD contact structure 437.

[0102] exist Figure 4A In the diagram, the arrow schematically representing conductor M0 481 indicates the direction of power supply (i.e., soft VSS) along conductor M0 481, specifically from the source / drain of transistor N5 below MD contact structure 437 to the source / drain of transistor N1 below MD contact structure 431. The arrow schematically representing conductor M0 482 indicates the direction of power supply (i.e., VSS) along conductor M0 482, specifically from the source / drain of transistor P1 below MD contact structure 436 to the gate 411 of transistors P1 and N1. The arrow schematically representing conductor M0 483 indicates the direction of power supply (i.e., soft VDD) along conductor M0 483, specifically from the source / drain of transistor P1 below MD contact structure 421 to the gate 417 of transistors P5 and N5. The two arrows of the bidirectional arrow schematically representing conductor M0 484 indicate that power is supplied from multiple sources along conductor M0 484, namely the source / drain of transistors P2, P4, and P5 below contact structures MD 423, 425, and 427, respectively.

[0103] ECO unit 400A does not contain any device configured to perform logic functions. In some embodiments, ECO unit 400A corresponds to an ECO base unit.

[0104] ECO cell 400A does not contain any floating source / drain. In other words, ECO cell 400A has no floating source / drain. Specifically, all source / drain terminals in ECO cell 400A are electrically coupled to one of VDD, VSS, soft VDD, or soft VSS. Therefore, in one or more embodiments, problems or concerns associated with floating source / drain terminals can be avoided.

[0105] ECO cell 400A does not contain any gate directly connected to the positive power rail (e.g., the VDD power rail). In other words, ECO cell 400A does not contain a gate directly connected to the positive power rail. According to some embodiments, a direct connection refers to a connection that is not affected or interrupted by the switching or control of any device (e.g., a transistor). For example, the connection of M0 conductor 482 to the VSS power rail through VD via 466, MD contact structure 436, and VDR via 445 is a direct connection because it is not affected or interrupted by the switching or control of any device (e.g., transistor N4 or transistor N5). In one or more embodiments, a permanent electrical connection is an example of a direct connection. Because ECO cell 400A does not contain any gate directly electrically connected to the positive power rail, in one or more embodiments, the ESD or antenna violation risks associated with such direct connections can be avoided. In some embodiments, by generating such Figures 2A-2D One or more of the ESD-safe soft VDD and soft VSS are shown, and soft VDD and soft VSS are used to turn various devices on or off (such as those related to ESD protection). Figures 3A-3C , Figure 4A This advantage can be achieved through one or more of the methods described in the text.

[0106] None of the prohibited dummy devices 181-188 are included in the ECO cell 400A. This is an improvement over other methods, which make it difficult or impossible to eliminate all prohibited dummy devices 181-188, especially when there are four signal tracks on a single cell height (1CH). Other methods require increasing the size of the ECO cell along the X-axis or requiring multiple ECO cells to eliminate all prohibited dummy devices 181-188. In either case, the chip area or cell area is disadvantageously increased. Further attempts to eliminate all prohibited dummy devices 181-188 according to other methods include using wiring resources from higher layers, such as M1 conductors, V0 vias, etc. This attempt disadvantageously occupies wiring resources that could otherwise be used for other tasks or circuits. According to some embodiments, the problems and / or disadvantages encountered in other methods can be avoided by using one or more ECO cells. For example, even with the limitation of four signal tracks on a single cell height (1 CH), all prohibited pseudo-devices 181-188 can be eliminated in the ECO cell 400A without increasing the size or number of ECO cells, and without using wiring resources above the M0 layer (e.g., without using the M1 conductor), thereby achieving advantages including but not limited to improvements in chip area, increased ECO cell design flexibility and / or usability.

[0107] In some embodiments, various layers remain unchanged when an ECO base cell or a previously placed ECO cell is programmed. For example, in one or more embodiments, the active region, gate (including conductive and dielectric gates), any diced gate mask regions used to define the gate length and / or shape, MD contact structure, CMD mask region, and BCMD components remain unchanged. In other words, the active region, gate, and MD contact structure of the ECO base cell or a previously placed ECO cell are correspondingly identical to the active region, gate, and MD contact structure of the programmed ECO cell that replaces the ECO base cell or the previously placed ECO cell. Programming an ECO cell involves changing one or more layers above the active region, gate, and MD contact structure. In some embodiments, programming an ECO cell involves changing one or more layers, including VDR vias, VD vias, VG vias, MO layers, one or more diced MO masks, and V0 layers. For example, one set of via structures and / or one set of MO conductors in the ECO base cell or a previously placed ECO cell is replaced by another set of via structures and / or another set of MO conductors in the programmed ECO cell. Non-restrictive example of a programmed ECO unit about Figure 4B , Figure 4D Describe it.

[0108] Figure 4B This is a layout diagram of an ECO unit 400B according to some embodiments. In some embodiments, the ECO unit 400B corresponds to Figure 1A The area in the described circuit region 103, and / or Figure 1B The area in the described IC device 100B, and / or Figure 1C The described layout 100C includes an ECO unit. In some embodiments, ECO unit 400B is a programmed ECO unit used to replace another ECO unit (e.g., an ECO base unit) previously or initially placed in the IC layout to modify the IC layout. For example, in one or more embodiments, ECO unit 400B is obtained by programming ECO unit 400A. In at least one embodiment, ECO unit 400B is stored as a standard unit in a unit library on a non-transitory computer-readable medium. For simplicity, Figure 4A , Figure 4B The corresponding components are represented by the same reference numbers.

[0109] Compared to ECO cell 400A, which is not configured to provide logic functionality, ECO cell 400B is programmed or configured to provide inverter functionality. In some embodiments, as described herein, the active regions OD1, OD2, gates 410-418, MD contact structures 420-427, 430-437, CMD mask regions 419, 429, 439, and BCMD components 428, 438 in ECO cell 400A are identical to the corresponding active regions, gates, MD contact structures, CMD mask regions, and BCMD components in ECO cell 400B. ECO cell 400B differs from ECO cell 400A in one or more layers above the active regions, gates, and MD contact structures, such as VD, VG, MO, etc.

[0110] ECO cell 400B includes VD vias 451B, 453, 454, 425, 427, 431, 432, 433, 434, 435, 436, 437 and their corresponding source / drain electrodes located on MD contact structures 421, 423, 424, 425, 427, 431, 432, 433, 434, 435, 436, 437 and below them. VD via 451B in ECO cell 400B is located on track M0_4, while the corresponding VD via 451 in ECO cell 400A is located on track M0_3. VD via 465B in ECO cell 400B is located on track M0_1, while the corresponding VD via 465 in ECO cell 400A is located on track M0_2.

[0111] ECO unit 400B also includes VG vias 471B, 473B, 474B, 476B, and 477B correspondingly located above conductive gates 411, 413, 414, 416, and 417. VG vias 471B, 473B, and 474B in ECO unit 400B are located above track M0_3, while the corresponding VG vias 471, 473, and 474 in ECO unit 400A are located above track M0_2. VG via 476B in ECO unit 400B is located above track M0_3, while the corresponding VG via 476 in ECO unit 400A is located above track M0_1. VG via 477B in ECO unit 400B is located above track M0_2, while the corresponding VG via 477 in ECO unit 400A is located above track M0_3.

[0112] ECO unit 400B also includes M0 conductors 481B, 482B, 483B, and 484B along the corresponding tracks M0_1, M0_2, M0_3, and M0_4 in the M0 layer. M0 conductor 481B is located above and electrically coupled to VD vias 461, 462, 463, 464, and 465B. M0 conductor 482B is located above and electrically coupled to VG via 477B. M0 conductor 483B is located above and electrically coupled to VG vias 471B, 473B, 474B, and 476B. M0 conductor 484B is located above and electrically coupled to VD vias 451B, 453, 454, and 455.

[0113] ECO unit 400B also includes cut M0 (CM0) mask regions 491, 492, 494, and 495. The CM0 mask regions are configured to physically and electrically separate the M0 conductors along the same M0 track. For example, CM0 mask region 491 will be located on track M0_1 and to the left of CM0 mask region 495. Figure 4B The M0 conductor 481B in the middle is located on the same track M0_1 and is located to the right of the CM0 mask region 491. Figure 4B The other M0 conductor (not shown) is physically and electrically isolated. In some embodiments, the CMO mask area 491 defines the right edge of the M0 conductor 481B. Figure 4B (Middle). CM0 mask area 492 will be located on track M0_2 ​​and to the right of CM0 mask area 492 ( Figure 4B The M0 conductor 482B in the middle is located on the same track M0_2 ​​and to the left of the CM0 mask region 492. Figure 4B The other M0 conductor (not shown) is physically and electrically isolated. In some embodiments, the CMO mask area 492 defines the left edge of the M0 conductor 482B. Figure 4BSimilarly, CM0 mask regions 494 and 495 physically and electrically separate the M0 conductor located on track M0_4. In some embodiments, CM0 mask regions 494 and 495 define the left and right edges of the M0 conductor 484B, respectively. Figure 4B middle).

[0114] ECO unit 400B also includes V0 vias 401, 402, 404, and 405, and M1 conductors 403 and 406. V0 via 401 is located above M0 conductor 483B, V0 via 402 is located above M0 conductor 481B, and M1 conductor 403 is located above V0 vias 401 and 402. Therefore, M0 conductor 481B is electrically coupled to M0 conductor 483B through V0 vias 401 and 402 and M1 conductor 403.

[0115] V0 via 404 is located above M0 conductor (not shown), which is located on track M0_4 and above VD via 457. V0 via 405 is located above M0 conductor (not shown), which is located on track M0_1 and above VD via 467. M1 conductor 406 is located above V0 vias 404 and 405. Therefore, the source / drain of transistor P5 below MD contact structure 427 is electrically coupled to the source / drain of transistor N5 below MD contact structure 437 through VD vias 457 and 467, the corresponding M0 conductors (not shown), V0 vias 404 and 405, and M1 conductor 406. The other sources / drains of transistors P5 and N5 below MD contact structures 426 and 436 are correspondingly electrically coupled to the VDD and VSS power rails, as described herein.

[0116] Therefore, transistors P5 and N5 are electrically coupled to form an inverter, which has an input terminal (IN) corresponding to conductor M0 482B and an output terminal (ZN) corresponding to conductor M1 406. ECO unit 400B is programmed or configured to provide the function of an inverter. The inverter configured by transistors P5 and N5 is routed to one or more additional circuits or units through one or more additional vias and / or conductors. The remaining transistors P1-P4 and N1-N4 of ECO unit 400B are electrically coupled in the following manner to avoid floating source / drain, disable dummy devices, and ensure direct electrical connection of the gate to the VDD power rail.

[0117] Transistor P1 is electrically coupled from its source to its drain to receive VDD from the VDD power rail via MD contact structure 420 and VDR via 440. Transistor P1's gate 411 is electrically coupled to receive soft VSS from conductor M0 483B, which in turn receives soft VSS from transistors N1 and N4 (described below) via conductor M0 481B, V0 vias 401 and 402, and conductor M1 403. Transistor P1 corresponds to... Figure 2A The transistor PMOS1 or described in the document Figures 3A-3C The transistor P31 described herein is configured to output soft VDD from another source / drain to the M0 conductor 484B via the MD contact structure 421.

[0118] Similar to transistor P1, transistor P2 has a source / drain electrical coupling to receive VDD from the VDD power rail, and a gate 413 electrical coupling to receive soft VSS from conductor 483B of the M0 circuit. Transistor P2 corresponds to Figure 2A The transistor PMOS1 or described in the document Figures 3A-3C The transistor P31 described herein is configured to output soft VDD from another source / drain to the M0 conductor 484B via the MD contact structure 423.

[0119] Transistor P3 is electrically coupled to its source and drain to receive soft VDD from conductor 484B of the M0 circuit, and its gate 414 is electrically coupled to receive soft VSS from conductor 483B of the M0 circuit. Transistor P3 corresponds to Figure 3B The transistor P33 is described in the text. Transistor P3 is electrically coupled as a decoupling capacitor.

[0120] Transistor P4 is electrically coupled from its source to its drain via the MD contact structure 426 and the VDR via 446 to receive VDD from the VDD power rail, and its gate 416 is electrically coupled to receive soft VSS from the M0 conductor 483B. Transistor P4 corresponds to Figure 2A The described transistor PMOS1 or Figures 3A-3C The transistor P31 is described and configured to output soft VDD from another source / drain to the M0 conductor 484B via the MD contact structure 425.

[0121] Transistor N1 is electrically coupled at its source / drain to receive VSS from the VSS power rail via the MD contact structure 430 and the VDR via 441, and electrically coupled at its gate 411 to receive soft VSS from the M0 conductor 483B. Transistor N1 corresponds to Figure 2D The transistor NMOS2 or described in the document Figure 3A The transistor N32 described herein is configured to output a soft VSS from another source / drain to the M0 conductor 481B via the MD contact structure 431.

[0122] The source and drain of transistor N2 are electrically coupled to receive soft VSS from conductor 481B of M0, and the gate 413 is electrically coupled to receive soft VSS from conductor 483B of M0. Transistor N2 corresponds to Figure 3C The transistor N34 is described in the text.

[0123] Similar to transistor N2, transistor N3 has its source / drain electrically coupled to receive soft VSS from conductor 481B of the M0 circuit, and its gate 414 electrically coupled to receive soft VSS from conductor 483B of the M0 circuit. Transistor N3 corresponds to... Figure 3C The transistor N34 is described in the text.

[0124] Transistor N4 is electrically coupled at its source / drain to receive VSS from the VSS power rail via the MD contact structure 436 and the VDR via 445, and electrically coupled at its gate 416 to receive soft VSS from the M0 conductor 483B. Transistor N4 corresponds to Figure 2D The transistor shown is NMOS2 or Figure 3A The transistor N32 shown is configured to output a soft VSS from another source / drain to the M0 conductor 481B via the MD contact structure 435. According to some embodiments, one or more of the advantages described herein can be achieved via the ECO unit 400B.

[0125] Figure 4C Circuit diagrams of various devices (i.e., transistors P3-P5, N3-N5) in the ECO unit 400B according to some embodiments are shown. For simplicity of description, Figure 4B and Figure 4C The corresponding components in the document use the same reference numerals.

[0126] Transistors P5 and N5 are electrically coupled to form an inverter, which has an input terminal IN corresponding to conductor M0 482B and an output terminal ZN corresponding to conductor M1 406.

[0127] Transistors P3, P4, N3, and N4 are not configured to provide logic functions, but are electrically coupled to avoid floating source / drain, disable dummy devices, and prevent direct electrical connection between the gate and the VDD power rail, as per [reference to...]. Figure 4B The circuit containing transistors P4 and P3 corresponds to the circuit described above. Figure 3B The described circuit 303, in which transistors P4 and P3 correspond to transistors P31 and P33, and conductor M0 484B corresponds to the soft VDD network 311. The circuit containing transistors N4 and N3 corresponds to... Figure 3C The described circuit 306, in which transistors N4 and N3 correspond to transistors N31 and N34, and conductor M0 481B corresponds to the soft VSS network 312. (As...) Figure 4C As shown, transistors P3, P4, N3, and N4 do not have floating source / drain, disable dummy devices, or direct electrical connection between the gate and the VDD power rail, thereby achieving one or more of the advantages described herein in one or more embodiments.

[0128] Figure 4DThis is a layout diagram of an ECO unit 400D according to some embodiments. In some embodiments, the ECO unit 400D corresponds to... Figure 1A The area in circuit region 103 shown, and / or Figure 1B The area in the IC device 100B shown, and / or Figure 1C The ECO unit in layout 100C is shown. In some embodiments, ECO unit 400D is a programmed ECO unit used to replace another ECO unit (e.g., an ECO base unit) previously or initially placed in the IC layout to modify the IC layout. For example, in one or more embodiments, ECO unit 400D is obtained by a programmed ECO unit 400A or ECO unit 400B. In at least one embodiment, ECO unit 400D is stored as a standard unit in a unit library on a non-transitory computer-readable medium. For simplicity, Figure 4A , Figure 4C , Figure 4D The corresponding components are represented by the same reference numbers.

[0129] Compared to ECO cell 400B, which includes an inverter configured with a pair of transistors (e.g., transistors P5 and N5), ECO cell 400D includes an inverter configured with two pairs of transistors (e.g., transistors P4 and N4, and transistors P5 and N5). The inverter in ECO cell 400B has a drive strength of 1, while the inverter in ECO cell 400D has a drive strength of 2. In some embodiments, as described herein, the active regions OD1, OD2, gates 410-418, MD contact structures 420-427, 430-437, CMD mask regions 419, 429, 439, and BCMD components 428, 438 in ECO cell 400D are identical to the corresponding active regions, gates, MD contact structures, CMD mask regions, and BCMD components in ECO cells 400A and 400B. The difference between ECO cell 400D and ECO cells 400A and 400B lies in one or more layers above the active region, gate, and MD contact structure, such as VD, VG, and M0.

[0130] ECO cell 400D includes the same VD via group as ECO cell 400B, including VD vias 451B, 453, 454, 455, 427, 431, 432, 433, 434, 435, 436, 437 and above the source / drain below, located correspondingly in MD contact structures 421, 423, 424, 425, 427, 431, 432, 433, 434, 435, 436, 437 and above the source / drain below.

[0131] ECO cell 400D also includes VG vias 471B, 473B, 474D, 476B, and 477D located above conductive gates 411, 413, 414, 416, and 417, respectively. VG via 477D in ECO cell 400D is located above track M0_3, while the corresponding VG via 477B in ECO cell 400B is located above track M0_2.

[0132] ECO unit 400D also includes M0 conductors 481D, 483D, 484D, and 489 along the corresponding tracks M0_1, M0_3, M0_4, and M0_3 in the M0 layer. M0 conductor 481D is shorter than M0 conductor 481B in ECO unit 400B and is located above and electrically coupled to VD vias 461, 462, 463, and 464. M0 conductor 483D is shorter than M0 conductor 483B in ECO unit 400B and is located above and electrically coupled to VG vias 471B, 473B, and 474B. M0 conductor 484D is shorter than M0 conductor 484B in ECO unit 400B and is located above and electrically coupled to VD vias 451B, 453, and 454. M0 conductor 489 is located above and electrically coupled to VG vias 476B and 477D.

[0133] ECO unit 400D also includes M0 (CM0) cut mask regions 494, 496, and 497. Unlike each CM0 mask region 491, 492, 494, and 495, which are configured to cut or separate the M0 conductor along one M0 track, each CM0 mask region 496 and 497 extends along the Y-axis and is configured to cut or separate the M0 conductor along two M0 tracks within the same M0 mask. For example, CM0 mask region 496 is configured to cut the M0 conductor along tracks M0_2 ​​and M0_4 belonging to the same M0_A mask. CM0 mask region 496 is not configured to cut the M0 conductor along track M0_3. CM0 mask region 497 is configured to cut the M0 conductor along tracks M0_1 and M0_3 belonging to the same M0_B mask. CM0 mask region 497 is not configured to cut the M0 conductor along track M0_2.

[0134] Specifically, CM0 mask region 496 will be physically and electrically located on orbit M0_4 and to the left of CM0 mask region 496. Figure 4D The M0 conductor 484D in the middle is located on the same M0_4 track and is located to the right of the CM0 mask region 496. Figure 4D The M0 conductor (not shown) above the VD vias 455 and 457 is separated. In some embodiments, the CMO mask areas 494 and 496 define the left and right edges of the M0 conductor 484D, respectively. Figure 4D middle).

[0135] CM0 mask region 497 will be physically and electrically located on orbit M0_3 and to the left of CM0 mask region 497. Figure 4D The M0 conductor 483D in the middle is located on the same M0_3 orbit and is located to the right of the CM0 mask region 497. Figure 4D The M0 conductor 489 is separated from the CM0 mask region 497, which is physically and electrically located on the M0_1 orbital and to the left of the CM0 mask region 497. Figure 4D The M0 conductor 481D in the middle is located on the same M0_1 track and is located to the right of the CM0 mask region 497. Figure 4D The CM0 mask area 497 separates the M0 conductor (not shown) above the VD vias 465B and 467. In some embodiments, the CM0 mask area 497 defines the right edge of the M0 conductors 481D and 438D. Figure 4D (in the middle), and also defined the left edge of conductor 489 of M0 ( Figure 4D middle).

[0136] ECO unit 400D also includes V0 vias 401, 402, 404, 405 and M1 conductors 403, 406, as described in ECO unit 400B.

[0137] Conductor M1 403 electrically couples conductors M0 481D and M0 483D. The source / drain of transistors P4 and P5 located below MD contact structures 425 and 427 are electrically coupled to the source / drain of transistors N4 and N5 located below MD contact structures 435 and 437 through vias VD 455, 457, 465B, and 467, the corresponding M0 conductors (not shown), vias V0 404 and 405, and conductor M1 406.

[0138] Therefore, transistors P4 and P5 are electrically coupled in parallel. Transistors N4 and N5 are electrically coupled in parallel. Transistors P4, P5, N4, and N5 are electrically coupled to form an inverter, which has an input terminal (IN) corresponding to conductor M0 489 and an output terminal (ZN) corresponding to conductor M1 406. The remaining transistors P1-P3 and N1-N3 of ECO cell 400D are electrically coupled as described with respect to ECO cell 400B, thereby avoiding floating source / drain, disabling dummy devices, and direct electrical connection between the gate and the VDD power rail. According to some embodiments, one or more of the advantages described herein can be achieved by ECO cell 400D.

[0139] exist Figure 4B , Figure 4DIn the non-limiting example configurations described, ECO units 400B and 400D are configured or programmed as inverter units. This is merely an example, and other functional units that can be configured or programmed from ECO units are also within the scope of various embodiments. Examples of such units include, but are not limited to, logic gate units, memory units, etc. Examples of logic gate units include, but are not limited to, AND, OR, NAND, NOR, XOR, inverters, AND-OR inverters, OR-AND inverters, multiplexers, flip-flops, buffers, latches, delay units, clock units, etc. Examples of memory units include, but are not limited to, static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), read-only memory (ROM) units, or other units capable of having multiple states representing logical values. Figure 4B , Figure 4D In the example configuration, ECO units 400B and 400D are inverters with a drive strength of 1 or 2. Other drive strengths, such as 3, 4, 6, etc., are also within the scope of various embodiments.

[0140] Figure 5A This is a flowchart of a method 500A for generating a layout and manufacturing an integrated circuit (IC) device using that layout, according to some embodiments. Method 500A may be implemented according to some embodiments, for example, using an electronic design automation (EDA) system and / or an integrated circuit (IC) manufacturing system described herein. Examples of layouts for method 500A include the layouts disclosed herein. Examples of IC devices manufactured according to method 500A include IC devices 100A, 100B, 100C and / or one or more IC devices, which contain one or more circuit regions corresponding to one or more ECO cells described herein. Method 500A includes operations 502 and 504.

[0141] In operation 502, a layout is generated that, among other things, includes at least one ECO unit as described herein. For an example of operation 502, please see [link to example]. Figure 5B .

[0142] In operation 504, based on the layout, at least one of the following is performed: (A) performing one or more photolithography exposures; or (B) fabricating one or more semiconductor masks; or (C) fabricating one or more components in an integrated circuit (IC) device layer. An example of operation 504 will be combined with... Figure 5C Describe it.

[0143] Figure 5BThis is a flowchart of a method 500B for generating an integrated circuit (IC) device layout. Method 500B is executed at least in part by a processor. In some embodiments, method 500B is performed to generate a layout including one or more ECO cells, as described herein. Method 500B includes operations 505, 510, 515, 520, 525, and 530.

[0144] In Operation 505, one or more functional units and one or more Engineering Change Order (ECO) units are placed in the layout of an integrated circuit (IC) device. For example, as... Figure 1C As shown, during the placement operation, one or more functional units C2, C3, C4 and one or more ECO units C1, C5 are placed in a layout, some of which are adjacent to one or more other units. In at least one embodiment, the placement operation is performed by the APR tool or system described herein. In some embodiments, one or more ECO units include at least one ECO base unit that is not configured to provide any logical functionality (i.e., not configured to contain any functional circuitry). In some embodiments, one or more ECO units include at least one ECO unit that has been configured to provide functionality, i.e., it already contains functional circuitry. In the example, one or more ECO units include ECO unit 400A.

[0145] In operation 510, a routing operation is performed on one or more functional units. For example, in a routing operation performed by an APR tool or system, via structures in various via layers and conductive patterns in various metal layers are generated to define the electrical connections between the circuits of the placed one or more functional units. The resulting arrangement corresponds to... Figure 1B The redistribution structure 150 is shown. In at least one embodiment, no wiring is generated for one or more ECO cells because one or more ECO cells have not yet been configured to provide functionality, and / or because any functional circuitry in one or more ECO cells does not yet need to be included in the layout.

[0146] In Operation 515, a decision to modify the layout is made based on one or more verifications. Examples of verifications include, but are not limited to, layout and schematic (LVS) checks, design rule checks (DRC), simulations, etc. For example, an LVS check is performed using electronic design automation (EDA) tools to ensure that the generated layout corresponds to the intended integrated circuit (IC) design on which the generated layout is based. For example, a DRC is performed using EDA tools to ensure that the layout meets specific manufacturing design rules, i.e., to ensure the manufacturability of the IC device. Simulations are performed using simulation tools (i.e., EDA tools) to take into account parasitic resistances and capacitances extracted from the layout, thereby determining whether the layout meets predetermined specifications, such as one or more predetermined timing requirements. A decision to modify the layout is made in response to one or more yield and / or performance issues indicated by one or more evaluation, check, and / or simulation results. The method for modifying the layout is to perform programming and routing on at least one previously placed ECO cell, as described in Operations 520 and 525.

[0147] In operation 520, at least one of one or more ECO cells is modified to configure functional circuitry, wherein the one or more ECO cells and the modified at least one ECO cell do not contain a gate directly electrically connected to the positive power rail. For example, as per [reference to...] Figure 4A , Figure 4B , Figure 4D As described, an ECO cell 400A, previously placed as an ECO cell, is programmed to include functional circuitry (e.g., an inverter) and becomes a programmed ECO cell 400B or 400D. In one or more embodiments, the functional circuitry in the programmed ECO cell is configured to improve the performance of the designed IC device. Programming the ECO cell involves changing one or more layers above the active region, gate region, and MD contact structure within the ECO cell, while keeping the active region, gate region, and MD contact structure of the ECO cell unchanged. In at least one embodiment, as per [reference to...] Figure 4A , Figure 4B , Figure 4D As described, programming an ECO cell includes generating or modifying one or more sets of VD vias, VG vias, or M0 conductors in the ECO cell being programmed.

[0148] As described in this article, for example, refer to Figure 4A , Figure 4B , Figure 4D In the placement operation of operation 505, neither the one or more ECO cells initially placed nor the modified ECO cells programmed in operation 520 contain a gate directly electrically connected to the positive power rail. Therefore, in one or more embodiments, the risk of ESD or antenna violations can be avoided or reduced during layout-based fabrication of integrated circuit (IC) devices.

[0149] In operation 525, further routing operations are performed on the functional circuitry in at least one modified ECO cell to obtain a modified layout. For example, one or more via structures and / or conductive patterns are generated to electrically couple the functional circuitry in the modified or programmed ECO cell (e.g., the inverter in ECO cells 400B, 400D) to other circuitry in other cells within the layout. In one or more embodiments, the described layout modification is achieved solely by changing or reconfiguring one or more via and / or conductive pattern sets in the ECO cell and routing the reconfigured ECO cell, without rearranging the functional cells already placed in the layout. Therefore, the performance of the IC device corresponding to the modified layout is improved while reducing the cost required to modify the layout.

[0150] In operation 530, the modified layout of the integrated circuit (IC) device is stored on a non-transitory computer-readable recording medium, for example, for subsequent retrieval and fabrication of the IC device, such as... Figure 5C As shown. According to some embodiments, the layout generated by method 500B and / or the IC device manufactured based on such layout can achieve one or more of the advantages described herein.

[0151] Figure 5C This is a flowchart of a method 500C for manufacturing an integrated circuit (IC) device according to some embodiments. In some embodiments, method 500C is performed to manufacture an IC device corresponding to one or more IC devices and / or layouts described herein. Method 500C includes operations 540, 544.

[0152] In operation 540, a first circuit region and a second circuit region are formed on a substrate. This formation process includes forming identical active regions, identical gate regions, and identical contact structures in both the first and second circuit regions. The active and gate regions in the first circuit region constitute a first set of transistors, and the active and gate regions in the second circuit region constitute a second set of transistors.

[0153] For example, such as Figure 1BAs shown, an example active region (OD) is formed along the X-axis above substrate 110. In some embodiments, the active region comprises one or more semiconductor materials, such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc., and one or more dopant materials, such as boron (B), phosphorus (P), arsenic (As), gallium (Ga), or other suitable materials. In some embodiments, the active region comprises a nanosheet structure, such as a continuous volume composed of one or more layers of semiconductor material. In various embodiments, the corresponding nanosheet layer comprises a single layer or multiple layers of a given semiconductor material. Example gates 111, 113, 115 are formed extending above the active region (OD) to configure various transistors. In some embodiments, the gate is part of a gate structure comprising one or more conductive materials, such as polycrystalline silicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials. The gate structure also includes a gate dielectric layer comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8, or high-k materials with a k value greater than 3.8, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium dioxide (TiO2). Example MD contact structures 131, 132, 133, and 134 are also formed extending over the active region (OD) to provide electrical connections to the source / drain electrodes in the active region. In some embodiments, MD contact structures 131, 132, 133, and 134 comprise metal.

[0154] In some embodiments, the first circuit region corresponds to Figure 1C Unit C1 and Figure 4A The ECO unit in the middle is 400A, while the second circuit area corresponds to Figure 1C Unit C5 and Figure 4B ECO unit 400B (or Figure 4D The first circuit region (e.g., ECO cell 400D) and the second circuit region (e.g., ECO cell 400A) have the same active regions OD1 and OD2, the same gate regions 410-418, and the same MD contact structures 420-427 and 430-437. Both the first and second circuit regions contain corresponding transistor groups, including transistors P1-P5 and N1-N5.

[0155] In operation 545, deposition and patterning processes are performed to obtain various via structures and conductive patterns. Specifically, a first set and a second set of via structures are formed on the gate region and the contact structure, respectively, located in the first and second circuit regions. In the metal layer, a first set and a second set of conductive patterns are formed on the first set and the second set of via structures, respectively. The first set of via structures and the first set of conductive patterns electrically couple a first set of transistors into a non-functional circuit while ensuring that there are no floating sources / drains in the first set of transistors. The second set of via structures and the second set of conductive patterns electrically couple at least a portion of the transistors in the second set into a functional circuit.

[0156] For example, such as Figure 4A As shown, the first circuit area (e.g., ECO unit 400A) includes a first group of VD vias 451, 453, 454, 455, 457, 461, 462, 463, 464, 465, 466, 467 and VG vias 471, 473, 474, 476, 477, as well as a first group of M0 conductors 481, 482, 483, 484. These conductors couple the first group of transistors P1-P5 and N1-N5 of the ECO unit 400A into a non-functional circuit. Similarly... Figure 4A As shown, the first group of transistors P1-P5 and N1-N5 in the ECO unit 400A does not have floating source / drain terminals. Therefore, in one or more embodiments, problems associated with floating source / drain terminals and / or the elimination of dummy devices can be avoided.

[0157] like Figure 4B As shown, the second circuit region (e.g., ECO unit 400B) includes a second set of VD vias 451B, 453, 454, 455, 457, 461, 462, 463, 464, 465B, 466, 467 and VG vias 471B, 473B, 474B, 476B, 477B, and a second set of MO conductors 481B, 482B, 483B, 484B. These conductors couple transistors P5 and N5 in the second set of transistors P1-P5 and N1-N5 of the ECO unit 400B into a functional circuit (e.g., an inverter). The remaining transistors P1-P4 and N1-N4 in the second set of transistors of the ECO unit 400B also do not have floating sources / drains to avoid problems associated with floating sources / drains and / or disable dummy devices. In at least one embodiment, one or more of the advantages described herein can be achieved by an IC device manufactured according to method 500C.

[0158] The method includes example operations, but these operations do not necessarily need to be performed in the order shown. Operations may be added, replaced, ordered, and / or deleted as appropriate, in accordance with the spirit and scope of this disclosure and the embodiments. Embodiments combining different features and / or different embodiments are all within the scope of this disclosure and will be apparent to those skilled in the art upon review of this disclosure.

[0159] In some embodiments, at least one of the methods described above may be performed, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of a design company for the integrated circuit (IC) manufacturing system described below.

[0160] Figure 6 This is a block diagram of an electronic design automation (EDA) system 600 according to some embodiments.

[0161] In some embodiments, EDA system 600 includes an APR system. According to one or more embodiments, the design layout described herein represents a method of wiring arrangement, which, for example, according to some embodiments, can be implemented using EDA system 600.

[0162] In some embodiments, the EDA system 600 is a general-purpose computing device that includes a hardware processor 602 and a non-transitory computer-readable recording medium 604. The recording medium 604, among other functions, encodes (i.e. stores) computer program code 606, a set of executable instructions. The hardware processor 602 executes the instructions 606 (at least partially) representing an EDA tool that implements some or all of the methods described herein according to one or more embodiments (hereinafter referred to as the processes and / or methods).

[0163] Processor 602 is electrically coupled to computer-readable recording medium 604 via bus 608. Processor 602 is also electrically coupled to I / O interface 610 via bus 608. Network interface 612 is also electrically connected to processor 602 via bus 608. Network interface 612 is connected to network 614, enabling processor 602 and computer-readable recording medium 604 to be connected to external components via network 614. Processor 602 is configured to execute computer program code 606 encoded in computer-readable recording medium 604 to make system 600 available for performing part or all of the process and / or method. In one or more embodiments, processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0164] In one or more embodiments, the computer-readable recording medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable recording medium 604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable recording medium 604 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0165] In one or more embodiments, recording medium 604 stores computer program code 606 configured to enable system 600 (where such execution representation (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, recording medium 604 also stores information that facilitates the execution of some or all of the said processes and / or methods. In one or more embodiments, recording medium 604 stores a standard cell library 607 comprising the standard cells disclosed herein.

[0166] EDA system 600 includes an I / O interface 610. The I / O interface 610 is coupled to external circuitry. In one or more embodiments, the I / O interface 610 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 602.

[0167] EDA system 600 also includes a network interface 612 coupled to processor 602. Network interface 612 allows system 600 to communicate with a network 614 to which one or more other computer systems are connected. Network interface 612 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 600.

[0168] System 600 is configured to receive information via I / O interface 610. The information received via I / O interface 610 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 602. The information is transferred to processor 602 via bus 608. EDA system 600 is configured to receive information related to the user interface (UI) via I / O interface 610. This information is stored as UI 642 in computer-readable recording medium 604.

[0169] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 600. In some embodiments, a layout including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0170] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0171] Figure 7 This is a block diagram of an integrated circuit (IC) manufacturing system 700 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on layout, the manufacturing system 700 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0172] exist Figure 7 In this IC manufacturing system 700, entities such as design studio 720, mask room 730, and IC manufacturing plant / manufacturer (“Fab”) 750 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 760. The entities in system 700 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 720, mask room 730, and IC manufacturing plant 750 are owned by a single, larger company. In some embodiments, two or more of the design studio 720, mask room 730, and IC manufacturing plant 750 coexist in a shared facility and use shared resources.

[0173] Design room (or design team) 720 generates IC design layout 722. IC design layout 722 includes various geometric patterns designed for IC device 760. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 760 to be manufactured. The layers combine to form various IC components. For example, a portion of IC design layout 722 includes various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design room 720 implements appropriate design procedures to form IC design layout 722. The design process includes one or more of logic design, physical design, or placement and routing operations. IC design layout 722 is presented in one or more data files containing geometric pattern information. For example, IC design layout 722 can be represented in GDSII file format or DFII file format.

[0174] Mask chamber 730 includes data preparation 732 and mask fabrication 744. Mask chamber 730 uses an IC design layout 722 to fabricate one or more masks 745 for fabricating various layers of an IC device 760 based on the IC design layout 720. Mask chamber 730 performs mask data preparation 732, where the IC design layout 722 is converted into a representative data file (“RDF”). Mask data preparation 732 provides the RDF to mask fabrication 744. Mask fabrication 744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (marker) 745 or a semiconductor wafer 753. The design layout 722 is manipulated by mask data preparation 732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 750. Figure 7 In this embodiment, mask data preparation 732 and mask manufacturing 744 are shown as separate elements. In some embodiments, mask data preparation 732 and mask manufacturing 744 may be collectively referred to as mask data preparation.

[0175] In some embodiments, mask data preparation 732 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 722. In some embodiments, mask data preparation 732 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0176] In some embodiments, mask data preparation 732 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 722 processed by OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 722 to compensate for constraints during mask fabrication 744, which can undo some modifications performed by OPC to satisfy the mask creation rules.

[0177] In some embodiments, mask data preparation 732 includes lithography process inspection (LPC), which simulates a process to be performed by IC fabrication plant 750 to manufacture IC device 760. LPC simulates this process based on IC design layout 722 to create a simulated manufactured device, such as IC device 760. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after LPC has created a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further optimize IC design layout 722.

[0178] It should be understood that, for clarity, the above description of mask data preparation 732 has been simplified. In some embodiments, data preparation 732 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 722 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 722 during data preparation 732 can be performed in various different sequences.

[0179] After mask data preparation 732 and during mask fabrication 744, a mask 745 or a set of masks 745 is fabricated based on a modified IC design layout 722. In some embodiments, mask fabrication 744 includes performing one or more photolithographic exposures based on the IC design layout 722. In some embodiments, based on the modified IC design layout 722, a pattern is formed on the mask (photomask or mask plate) 745 using a mechanism of electron beam (e-beam) or multiple electron beams. The mask 745 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 745. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of the mask 745 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, a phase-shifting technique is used to form the mask 745. In the phase-shift mask (PSM) version of mask 745, various features in the pattern formed on the phase-shift mask are configured with appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask fabrication 744 is used in a variety of processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 753, in etching processes to form various etched regions in semiconductor wafer 754, and / or in other suitable processes.

[0180] IC Manufacturing Plant 750 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Manufacturing Plant 750 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) fabrication) for interconnecting and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0181] IC manufacturing plant 750 includes manufacturing tools 752 configured to perform various manufacturing operations on semiconductor wafers 753 to manufacture IC devices 760 according to a mask (e.g., mask 745). In various embodiments, manufacturing tools 752 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0182] IC fabrication plant 750 uses a mask 745, fabricated by mask chamber 730, to fabricate IC device 760. Therefore, IC fabrication plant 750 uses IC design layout 722 at least indirectly to fabricate IC device 760. In some embodiments, semiconductor wafer 753 is fabricated by IC fabrication plant 750 using mask 745 to form IC device 760. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 722. Semiconductor wafer 753 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 753 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0183] In some embodiments, the integrated circuit (IC) device includes a first transistor and a second transistor. The first transistor includes a first terminal, a second terminal, and a gate terminal configured to receive a first power supply voltage. The gate terminal is configured to receive a second power supply voltage different from the first power supply voltage, or a first voltage corresponding to the first power supply voltage, or a second voltage corresponding to the second power supply voltage. The second transistor includes two terminals electrically coupled to the second terminal of the first transistor.

[0184] In some embodiments, the difference between the first voltage and the first power supply voltage is the voltage drop across the first transistor when it is in the on state.

[0185] In some embodiments, the first voltage varies between a first power supply voltage and a threshold voltage of the first transistor.

[0186] In some embodiments, the two terminals electrically coupled to the second terminal of the first transistor include the first terminal and the gate terminal of the second transistor, and the second transistor further includes a second terminal configured to receive a first power supply voltage.

[0187] In some embodiments, the two terminals electrically coupled to the second terminal of the first transistor include the first terminal and the second terminal of the second transistor, and the second transistor further includes a gate terminal configured to receive a second voltage.

[0188] In some embodiments, the integrated circuit device further includes a third transistor having a different conductivity type from that of the first transistor. The third transistor includes: a first terminal configured to receive a second power supply voltage, a second terminal, and a gate terminal configured to receive either a first voltage or a second voltage; and a fourth transistor including at least two terminals electrically coupled to the second terminal of the third transistor.

[0189] In some embodiments, the difference between the second voltage and the second power supply voltage is the voltage drop across the third transistor when it is in the on state.

[0190] In some embodiments, the second voltage varies between the second power supply voltage and the threshold voltage of the third transistor.

[0191] In some embodiments, at least two terminals of the fourth transistor electrically coupled to the second terminal of the third transistor include the first terminal and the second terminal of the fourth transistor, and the fourth transistor further includes a gate terminal configured to receive a second power supply voltage.

[0192] In some embodiments, the electrical coupling of the fourth transistor to at least two terminals of the second terminal of the third transistor includes the first terminal, the second terminal, and the gate terminal of the fourth transistor.

[0193] In some embodiments, an integrated circuit (IC) device includes a first active region of a first conductivity type, a second active region of a second conductivity type different from the first conductivity type, and a plurality of gate regions extending continuously through the first and second active regions. The plurality of gate regions and the first active region are respectively configured with a plurality of transistors of the first type. The plurality of gate regions and the second active region are respectively configured with a plurality of transistors of the second type different from the first type. The plurality of transistors of the first type includes: a first transistor having a first source / drain and a second source / drain, the first source / drain being electrically coupled to a first power rail configured to carry a first power supply voltage; and a second transistor having a first source / drain and a second source / drain both electrically coupled to the second source / drain of the first transistor. The plurality of transistors of the second type includes: a third transistor having a first source / drain and a second source / drain, the first source / drain of the third transistor being electrically coupled to a second power rail configured to carry a second power supply voltage different from the first power supply voltage; and a fourth transistor having a first source / drain and a second source / drain both electrically coupled to the second source / drain of the third transistor.

[0194] In some embodiments, the gates of the first transistor and the third transistor are configured with the same gate region among a plurality of gate regions, the gates of the second transistor and the fourth transistor are configured with the same gate region among a plurality of gate regions, or the gates of the first transistor and the fourth transistor are configured with the same gate region among a plurality of gate regions.

[0195] In some embodiments, the plurality of transistors of the first type further includes a fifth transistor having: a first source / drain electrically coupled to a first power rail, a second source / drain, and a gate electrically coupled to a second power rail, and the gate of the first transistor being electrically coupled to: the second power rail, the second source / drain of the third transistor, or the second source / drain of the fifth transistor.

[0196] In some embodiments, the plurality of transistors of the second type further includes a sixth transistor having: a first source / drain and a second source / drain electrically coupled to the second power rail, and a gate electrically coupled to the second source / drain of the third transistor.

[0197] In some embodiments, the integrated circuit device further includes: a first metal layer located over a plurality of gate regions, the first metal layer including: a first conductive pattern electrically coupling a second source / drain of a first transistor to a first source / drain and a second source / drain of a second transistor; a second conductive pattern electrically coupling a second source / drain of a fifth transistor to a gate of the first transistor; a third conductive pattern electrically coupling a first source / drain and a second source / drain of a sixth transistor to a gate of the fifth transistor; and a fourth conductive pattern electrically coupling a second source / drain of a third transistor to a first source / drain and a second source / drain of a fourth transistor.

[0198] In some embodiments, at least one of the gate of the first transistor and the gate of the second transistor is electrically coupled to the second source / drain of the third transistor.

[0199] In some embodiments, the gates of the first to fourth transistors are electrically coupled to the second source / drain of the third transistor.

[0200] In some embodiments, the integrated circuit device further includes: a first metal layer located over a plurality of gate regions, the first metal layer including: a first conductive pattern electrically coupling a second source / drain of a first transistor to a first source / drain and a second source / drain of a second transistor; a second conductive pattern electrically coupling a gate of the first transistor to a gate of the second transistor; and a third conductive pattern electrically coupling a second source / drain of a third transistor to a first source / drain and a second source / drain of a fourth transistor; and a second metal layer located over the first metal layer, the second metal layer including: a fourth conductive pattern electrically coupling the second conductive pattern to the third conductive pattern.

[0201] In some embodiments, a method of manufacturing an integrated circuit includes forming a first circuit region and a second circuit region over a substrate. Each of the first and second circuit regions includes an active region with a different conductivity type, and gate regions and contact structures alternately arranged and extending across the active region. The active region, gate region, and contact structure in the first circuit region are correspondingly identical to those in the second circuit region. The active region and gate region in the first circuit region configure a first set of transistors. The active region and gate region in the second circuit region configure a second set of transistors. The method further includes depositing and patterning: a first set of via structures located over the gate region and contact structure in the first circuit region; a second set of via structures located over the gate region and contact structure in the second circuit region; a first set of conductive patterns located over the first set of via structures and a second set of conductive patterns located over the second set of via structures in a metal layer. The first set of via structures and the first set of conductive patterns electrically couple the first set of transistors into a non-functional circuit while leaving no floating source / drain in the first set of transistors. The second set of via structures and the second set of conductive patterns electrically couple at least some of the transistors in the second set of transistors into a functional circuit.

[0202] In some embodiments, the second set of via structures and the second set of conductive patterns electrically couple the remaining transistors in the second set of transistors into a non-functional circuit, while leaving no floating source / drain in the remaining transistors.

[0203] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: A first transistor, the first transistor including a first terminal, a second terminal, and a gate terminal configured to receive a first power supply voltage. The gate terminal is configured to receive: a second power supply voltage different from the first power supply voltage, or a first voltage corresponding to the first power supply voltage, or a second voltage corresponding to the second power supply voltage; and The integrated circuit device further includes a second transistor, the second transistor having two terminals electrically coupled to the second terminal of the first transistor.

2. The integrated circuit device according to claim 1, wherein, The difference between the first voltage and the first power supply voltage is the voltage drop across the first transistor when it is in the on state.

3. The integrated circuit device according to claim 1, wherein, The first voltage varies between the first power supply voltage and the threshold voltage of the first transistor.

4. The integrated circuit device according to claim 1, wherein, The two terminals electrically coupled to the second terminal of the first transistor include the first terminal and the gate terminal of the second transistor. The second transistor also includes a second terminal configured to receive the first power supply voltage.

5. The integrated circuit device according to claim 1, wherein, The two terminals electrically coupled to the second terminal of the first transistor include the first terminal and the second terminal of the second transistor, and The second transistor also includes a gate terminal configured to receive the second voltage.

6. The integrated circuit device according to claim 1, further comprising: A third transistor, the conductivity type of which is different from that of the first transistor, includes a first terminal, a second terminal, and a gate terminal configured to receive the second power supply voltage, the gate terminal being configured to receive either the first voltage or the second voltage; as well as The fourth transistor includes at least two terminals electrically coupled to the second terminal of the third transistor.

7. The integrated circuit device according to claim 6, wherein, The difference between the second voltage and the second power supply voltage is the voltage drop across the third transistor when it is in the on state.

8. An integrated circuit device, comprising: The first active region of the first conductivity type; The second active region has a second conductivity type that is different from the first conductivity type; as well as Multiple gate regions extend continuously across the first active region and the second active region. in, The plurality of gate regions and the first active region are respectively configured with a plurality of transistors of the first type. The plurality of gate regions and the second active region are respectively configured with a plurality of transistors of a second type, which are different from the first type. The first type of multiple transistors includes a first transistor and a second transistor. The first transistor has a first source / drain and a second source / drain, the first source / drain being electrically coupled to a first power rail configured to carry a first power supply voltage, and The second transistor has a first source / drain and a second source / drain that are electrically coupled to the second source / drain of the first transistor, and The second type of multiple transistors includes a third transistor and a fourth transistor. The third transistor has a first source / drain and a second source / drain, the first source / drain of the third transistor being electrically coupled to a second power rail configured to carry a second power rail different from the first power supply voltage. The fourth transistor has a first source / drain and a second source / drain that are electrically coupled to the second source / drain of the third transistor.

9. The integrated circuit device according to claim 8, further comprising: A first metal layer is located above the plurality of gate regions. The first metal layer includes a first conductive pattern that electrically couples the second source / drain of the first transistor to the first source / drain and the second source / drain of the second transistor. The first metal layer includes a second conductive pattern that electrically couples the gate of the first transistor to the gate of the second transistor. The first metal layer includes a third conductive pattern that electrically couples the second source / drain of the third transistor to the first source / drain and the second source / drain of the fourth transistor. as well as The integrated circuit device further includes a second metal layer located above the first metal layer. The second metal layer includes a fourth conductive pattern that electrically couples the second conductive pattern to the third conductive pattern.

10. A method for manufacturing an integrated circuit, comprising: A first circuit region and a second circuit region are formed above a substrate, wherein each of the first circuit region and the second circuit region includes an active region with different conductivity types, and a gate region and a contact structure alternately arranged and extending across the active region. The active region, the gate region, and the contact structure in the first circuit region are correspondingly identical to the active region, the gate region, and the contact structure in the second circuit region. The active region and the gate region in the first circuit region are configured with a first set of transistors, and the active region and the gate region in the second circuit region are configured with a second set of transistors. Deposition and patterning: a first set of via structures located above the gate region and the contact structure in the first circuit region, a second set of via structures located above the gate region and the contact structure in the second circuit region, a first set of conductive patterns located in the metal layer above the first set of via structures, and a second set of conductive patterns located in the metal layer above the second set of via structures. in, The first set of via structures and the first set of conductive patterns electrically couple the first set of transistors into a non-functional circuit, while leaving no floating source / drain in the first set of transistors. The second set of via structures and the second set of conductive patterns electrically couple at least some of the transistors in the second set of transistors into a functional circuit.

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