Lateral double-diffused field-effect transistors, their fabrication methods, chips, and circuits

Abstract

This invention provides a lateral double-diffused field-effect transistor (LDFET), its fabrication method, chip, and circuit, relating to the field of semiconductor technology. The transistor includes: a base substrate; a first transistor and a second transistor having opposite carrier types, formed within the base substrate; a second source of the second transistor formed in a region of a second body region away from a second drift region, and a second drain of the second transistor formed in a region of the second drift region away from the second body region; a first gate and a first field plate of the first transistor forming the back side of the base substrate with their faces downwards, and a second gate and a second field plate of the second transistor forming the back side region of the first transistor with their faces upwards, wherein the first body region and the second body region are formed on the same side of the base substrate. This invention can reduce the vertical thickness of the device, simplify the manufacturing process, and increase the total operating current of the lateral double-diffused field-effect transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a lateral double-diffused field-effect transistor, a method for fabricating a lateral double-diffused field-effect transistor, a chip, and a circuit. Background Technology

[0002] Lateral double-diffused MOSFETs (LDMOS) are a type of lateral power device whose electrodes are all located on the device surface. They are easy to integrate with low-voltage signal circuits and other devices through internal connections. At the same time, they have advantages such as high voltage withstand capability, high gain, good linearity, high efficiency, and good broadband matching performance. They are now widely used in power integrated circuits, especially power management chips.

[0003] In the existing technology, the lateral double-diffused field-effect transistor provides a small operating current, has low output power, high on-resistance, and a large transistor thickness, making manufacturing cumbersome. Summary of the Invention

[0004] To address the technical problems of existing lateral double-diffused field-effect transistors (LDFETs) such as low operating current, low output power, high on-resistance, large transistor thickness, and cumbersome manufacturing process, this invention provides a lateral double-diffused field-effect transistor, a method for fabricating a lateral double-diffused field-effect transistor, a chip, and a circuit. Using this lateral double-diffused field-effect transistor can reduce the vertical thickness of the device, simplify the manufacturing process, reduce manufacturing costs, increase the total operating current of the lateral double-diffused field-effect transistor, reduce on-resistance, and increase the transistor's output power.

[0005] To achieve the above objectives, a first aspect of the present invention provides a lateral double-diffused field-effect transistor, comprising: a base substrate; a first transistor and a second transistor having opposite carrier types, formed within the base substrate; the first transistor comprising: a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate; the second transistor comprising: a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate; the second source is formed in a region of the second body region away from the second drift region, and the second drain is formed in a region of the second drift region away from the second body region; the first gate and the first field plate of the first transistor are formed downward on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upward on the back side region of the first body region and the first drift region of the first transistor, and the first body region and the second body region are formed on the same side of the base substrate.

[0006] Furthermore, the lateral double-diffused field-effect transistor further includes a boosting dielectric layer formed between the second transistor and the first transistor.

[0007] Furthermore, the boosting dielectric layer is an intrinsic silicon dielectric layer.

[0008] Furthermore, the pressurizing medium layer is a silicon carbide medium layer.

[0009] Furthermore, the lateral double-diffused field-effect transistor further includes: a first isolation layer formed on the side outside the second body region away from the second drift region; and a second isolation layer formed on the side outside the second drift region away from the second body region.

[0010] Furthermore, the first source electrode is formed on the side of the first body region away from the first drift region, and the first drain electrode is formed on the side of the first drift region away from the first body region.

[0011] Furthermore, the lateral double-diffused field-effect transistor further includes: a first metal electrode extending upward from the first source to the upper surface of the base substrate; a second metal electrode extending upward from the first drain to the upper surface of the base substrate; a third metal electrode extending downward from the first gate to the lower surface of the base substrate; a fourth metal electrode extending upward from the second source to the upper surface of the base substrate; a fifth metal electrode extending upward from the second drain to the upper surface of the base substrate; a sixth metal electrode extending upward from the second gate to the upper surface of the base substrate; and a dielectric layer formed between the first metal electrode and the fourth metal electrode, between the fourth metal electrode and the sixth metal electrode, between the sixth metal electrode and the fifth metal electrode, and between the fifth metal electrode and the second metal electrode.

[0012] A second aspect of the present invention provides a method for fabricating a lateral double-diffused field-effect transistor, the method comprising: forming a base substrate, and forming a first transistor and a second transistor having opposite carrier types within the base substrate; wherein the first transistor comprises: a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate; the second transistor comprises: a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate; the second source is formed in a region of the second body region away from the second drift region, and the second drain is formed in a region of the second drift region away from the second body region; the first gate and the first field plate of the first transistor are formed downward on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upward on the back side region of the first body region and the first drift region of the first transistor, and the first body region and the second body region are formed on the same side of the base substrate.

[0013] Further, the step of forming a base substrate and forming a first transistor and a second transistor having opposite carrier types within the base substrate includes: forming a first substrate and forming a first body region and a first drift region of the first transistor on the first substrate; forming a second substrate on the upper surface of the first body region and the first drift region and forming a second transistor within the second substrate; wherein the base substrate includes the first substrate and the second substrate; forming a first source, a first drain, a first gate, and a first field plate of the first transistor; wherein the first source is formed on the side of the first body region away from the first drift region, and the first drain is formed on the side of the first drift region away from the first body region.

[0014] Further, the step of forming a first substrate and forming a first body region and a first drift region of a first transistor on the first substrate includes: providing a first sub-substrate and forming a stepped etch surface on the upper surface of the first sub-substrate; wherein the stepped etch surface includes a high-order etch surface and a low-order etch surface; forming a first silicon dioxide layer on the stepped etch surface, using the first silicon dioxide layer on the high-order etch surface as a first gate oxide layer, and using the first silicon dioxide layer on the low-order etch surface as a first field plate oxide layer; forming a second sub-substrate on the upper surface of the first silicon dioxide layer, and forming the first body region and the first drift region on the second sub-substrate; wherein the first substrate includes the first sub-substrate and the second sub-substrate.

[0015] Further, forming a second substrate on the upper surface of the first body region and the first drift region includes: forming a boosting medium layer on the upper surface of the first body region and the first drift region; and forming a second substrate on the upper surface of the boosting medium layer.

[0016] Furthermore, the boosting dielectric layer is an intrinsic silicon dielectric layer.

[0017] Furthermore, the pressurizing medium layer is a silicon carbide medium layer.

[0018] Further, forming the first gate and the first field plate of the first transistor includes: thinning the first sub-substrate; heavily doping the thinned first sub-substrate to obtain a heavily doped silicon layer; using the heavily doped silicon layer and the first gate oxide layer as the first gate, and using the heavily doped silicon layer and the first field plate oxide layer as the first field plate.

[0019] Furthermore, the method further includes: forming a first isolation layer on the side of the second body region away from the second drift region; and forming a second isolation layer on the side of the second drift region away from the first body region.

[0020] Further, after forming the second transistor in the second substrate, the method further includes: forming a dielectric layer on the second substrate and the exposed first substrate; forming contact holes in the dielectric layer, the contact holes contacting the first source, the first drain, the second source, the second drain and the second gate respectively; forming a first metal electrode, a second metal electrode, a fourth metal electrode, a fifth metal electrode and a sixth metal electrode in the contact holes respectively; wherein the first metal electrode extends upward from the first source to the upper surface of the base substrate, the second metal electrode extends upward from the first drain to the upper surface of the base substrate, the fourth metal electrode extends upward from the second source to the upper surface of the base substrate, the fifth metal electrode extends upward from the second drain to the upper surface of the base substrate, and the sixth metal electrode extends upward from the second gate to the upper surface of the base substrate; and forming a third metal electrode on the lower surface of the first gate and the first field plate.

[0021] A third aspect of the present invention provides a chip comprising the lateral double-diffused field-effect transistor described above.

[0022] A fourth aspect of the present invention provides a circuit comprising the lateral double-diffused field-effect transistor described above.

[0023] The present invention has at least the following technical effects through the technical solution provided by the present invention: The lateral double-diffused field-effect transistor of the present invention includes a base substrate and a first transistor and a second transistor having opposite carrier types formed within the base substrate. The first transistor includes a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate. The second transistor includes a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second source is formed in the second body region away from the drift region, and the second drain is formed in the second drift region away from the second body region. The first gate and the first field plate of the first transistor are formed downwards on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upwards on the back side region of the first body region and the first drift region of the first transistor, and the first body region and the second body region are formed on the same side of the base substrate. The first body region and the second body region have different conductivity types, forming a PN junction with natural isolation, allowing the formation of two independent MOSFET transistors. This increases the total operating current of the lateral double-diffused field-effect transistor, reduces the on-resistance, increases the transistor's output power, and eliminates the need for additional isolation structures, thereby reducing the vertical thickness of the device, simplifying the manufacturing process, and lowering manufacturing costs. Therefore, the lateral double-diffused field-effect transistor provided by the present invention can reduce the vertical thickness of the device, simplify the manufacturing process, reduce manufacturing costs, increase the total operating current of the lateral double-diffused field-effect transistor, reduce the on-resistance, and increase the output power of the transistor.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of the first sub-substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the stepped etching surface formed after etching the first sub-substrate in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of the first field plate oxide layer formed in the lateral double-diffusion field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 4 A schematic diagram of the structure of the second sub-substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 5A schematic diagram of the structure of the first bulk region and the first drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 6 A schematic diagram of the structure of the second substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the second substrate and the boosting dielectric layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 8 A schematic diagram of the structure of the second body region and the second drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the second field plate oxide layer, the first isolation layer, and the second isolation layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 10 A schematic diagram of the structure of the second gate oxide layer and the polysilicon layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of the heavily doped silicon layer, the first source, the first drain, the second source, and the second drain formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiments of the present invention. Figure 12 A schematic diagram of the structure of the dielectric layer formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of the contact hole structure formed in the lateral double-diffusion field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of the lateral double-diffused field-effect transistor formed in the fabrication method of the lateral double-diffused field-effect transistor provided in the embodiment of the present invention.

[0026] Explanation of reference numerals in the attached figures 1-First sub-substrate; 2-First gate oxide layer; 3-First field plate oxide layer; 4-Second sub-substrate; 5-First body region; 6-First drift region; 7-Second substrate; 8-Boosting dielectric layer; 9-Second body region; 10-Second drift region; 11-Second field plate oxide layer; 12-First isolation layer; 13-Second isolation layer; 14-Second gate oxide layer; 15-Polysilicon layer; 16-Heavily doped silicon layer; 17-Second source; 18-Second drain; 19-First source; 20-First drain; 21-Dielectric layer; 22-Contact hole; 23-First metal electrode; 24-Second metal electrode; 25-Fourth metal electrode; 26-Fifth metal electrode; 27-Sixth metal electrode; 28-Third metal electrode. Detailed Implementation

[0027] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0029] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0030] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Please refer to Figure 14 A first aspect of this invention provides a lateral double-diffused field-effect transistor (LDFET), comprising: a base substrate; a first transistor and a second transistor having opposite carrier types, formed within the base substrate; the first transistor comprising: a first body region 5, a first drift region 6, a first source 19, a first drain 20, a first gate, and a first field plate; the second transistor comprising: a second body region 9, a second drift region 10, a second source 17, a second drain 18, a second gate, and a second field plate; the second source 17 is formed in a region of the second body region 9 away from the second drift region 10, and the second drain 18 is formed in a region of the second drift region 10 away from the second body region 9; the first gate and the first field plate of the first transistor are formed downward on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upward on the back side region of the first body region 5 and the first drift region 6 of the first transistor, and the first body region 5 and the second body region 9 are formed on the same side of the base substrate.

[0032] Specifically, in this embodiment of the invention, the lateral double-diffused field-effect transistor includes a base substrate on which a first transistor and a second transistor with opposite carrier types are formed. For example, the first transistor is a PLDMOS and the second transistor is an NLDMOS, or the first transistor is an NLDMOS and the second transistor is a PLDMOS. The first transistor includes a first body region 5, a first drift region 6, a first source 19, a first drain 20, a first gate, and a first field plate. The second transistor includes a second body region 9, a second drift region 10, a second source 17, a second drain 18, a second gate, and a second field plate. The second source 17 is formed in a region of the second body region 9 away from the second drift region 10, and the second drain 18 is formed in a region of the second drift region 10 away from the second body region 9.

[0033] The first transistor and the second transistor are arranged back-to-back from bottom to top within a base substrate. The first gate and first field plate of the first transistor are formed downwards on the back side of the base substrate, while the second gate and second field plate of the second transistor are formed upwards on the back side of the first body region 5 and the first drift region 6 of the first transistor. Stacking two transistors on the base substrate increases the overall operating current of the transistors, reduces on-resistance, and improves the output power. The first body region 5 and the second body region 9 are formed on the same side of the base substrate. The two body regions and the two drift regions all form a PN junction, isolating the first transistor and the second transistor. This eliminates the need for additional isolation structures between the two transistors, reducing the vertical thickness of the device, simplifying the manufacturing process, and lowering manufacturing costs.

[0034] The lateral double-diffused field-effect transistor provided by this invention can reduce the vertical thickness of the device, simplify the manufacturing process, reduce manufacturing costs, increase the total operating current of the lateral double-diffused field-effect transistor, reduce the on-resistance, and increase the output power of the transistor.

[0035] Furthermore, the lateral double-diffused field-effect transistor further includes a boosting dielectric layer 8 formed between the second transistor and the first transistor.

[0036] Furthermore, the boosting dielectric layer 8 is an intrinsic silicon dielectric layer.

[0037] Furthermore, the pressurizing medium layer 8 is a silicon carbide medium layer.

[0038] Specifically, in this embodiment of the invention, a boosting dielectric layer 8 is formed between the second transistor and the first transistor. The boosting dielectric layer 8 further enhances the isolation effect between the two transistors, enabling the lateral double-diffused field-effect transistor to withstand higher voltages and further improve the breakdown voltage. The boosting dielectric layer 8 can be an intrinsic silicon dielectric layer or a silicon carbide dielectric layer. Both intrinsic silicon and silicon carbide, when used as dielectric layers in the transistors of this application, can withstand higher electric fields, which helps in heat dissipation, improves power density, and increases reliability.

[0039] Furthermore, the lateral double-diffused field-effect transistor further includes: a first isolation layer 12 formed on the side of the second body region 9 away from the second drift region 10; and a second isolation layer 13 formed on the side of the second drift region 10 away from the first body region 5.

[0040] Specifically, in this embodiment of the invention, isolation layers are formed on both sides of the second transistor. A first isolation layer 12 is formed on the side of the second body region 9 away from the second drift region 10, and a second isolation layer 13 is formed on the side of the second drift region 10 away from the first body region 5. The first isolation layer 12 isolates the first source 19 from the second body region 9, and the second isolation layer 13 isolates the second source 20 from the second drift region 10, thereby improving the breakdown voltage of the device and enhancing its reliability.

[0041] Furthermore, the first source electrode 19 is formed on the side of the first body region 5 away from the first drift region 6, and the first drain electrode 20 is formed on the side of the first drift region 6 away from the first body region 5.

[0042] Specifically, in this embodiment of the invention, the first source 19 and the first drain 20 are formed at the two ends of the first body region 5 and the first drift region 6, respectively. This increases the area between the first source 19 and the first drain 20. When a second transistor of the same area is required, the overall area of ​​the transistor can be reduced, the effective utilization rate of the transistor area between the first source 19 and the first drain 20 can be improved, the drift region width can be increased, the breakdown voltage can be increased, and the power output per unit device area can be increased.

[0043] Furthermore, the lateral double-diffused field-effect transistor further includes: a first metal electrode 23, extending upward from the first source 19 to the upper surface of the base substrate; a second metal electrode 24, extending upward from the first drain 20 to the upper surface of the base substrate; a third metal electrode 28, extending downward from the first gate to the lower surface of the base substrate; a fourth metal electrode 25, extending upward from the first source 19 to the upper surface of the base substrate; a fifth metal electrode 26, extending upward from the second drain 18 to the second source 17 to the upper surface of the base substrate; a sixth metal electrode 27, extending upward from the second gate to the upper surface of the base substrate; and a dielectric layer 21 formed between the first metal electrode 23 and the fourth metal electrode 25, between the fourth metal electrode 25 and the sixth metal electrode 27, between the sixth metal electrode 27 and the fifth metal electrode 26, and between the fifth metal electrode 26 and the second metal electrode 24.

[0044] Specifically, in this embodiment of the invention, a first metal electrode 23, a second metal electrode 24, a third metal electrode 28, a fourth metal electrode 25, a fifth metal electrode 26, and a sixth metal electrode 27 are respectively disposed on the first source 19, the first drain 20, the first gate, the second source 17, the second drain 18, and the second gate. The first metal electrode 23, the second metal electrode 24, the fourth metal electrode 25, the fifth metal electrode 26, and the sixth metal electrode 27 are led upward to the upper surface of the base substrate, and the third metal electrode 28 is led downward from the first gate to the lower surface of the base substrate. The first metal electrode 23 and the fourth metal electrode 25, as well as the second metal electrode 24 and the fifth metal electrode 26, can be interconnected or independently connected.

[0045] A second aspect of the present invention provides a method for fabricating a lateral double-diffused field-effect transistor (LDFET). The method includes: forming a base substrate and forming a first transistor and a second transistor having opposite carrier types within the base substrate; wherein the first transistor includes a first body region 5, a first drift region 6, a first source 19, a first drain 20, a first gate, and a first field plate; the second transistor includes a second body region 9, a second drift region 10, a second source 17, a second drain 18, a second gate, and a second field plate; the second source 17 is formed in a region of the second body region 9 away from the second drift region 10, and the second drain 18 is formed in a region of the second drift region 10 away from the second body region 9; the first gate and the first field plate of the first transistor are formed downward on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upward on the back side region of the first body region 5 and the first drift region 6 of the first transistor, and the first body region 5 and the second body region 9 are formed on the same side of the base substrate.

[0046] Further, the step of forming a base substrate and forming a first transistor and a second transistor having opposite carrier types within the base substrate includes: forming a first substrate and forming a first body region 5 and a first drift region 6 of the first transistor on the first substrate; forming a second substrate 7 on the upper surface of the first body region 5 and the first drift region 6, and forming a second transistor within the second substrate 7; wherein the base substrate includes the first substrate and the second substrate 7; forming a first source 19, a first drain 20, a first gate, and a first field plate of the first transistor; wherein the first source 19 is formed on the side of the first body region 5 away from the first drift region 6, and the first drain 20 is formed on the side of the first drift region 6 away from the first body region 5.

[0047] Further, the step of forming a first substrate and forming a first body region 5 and a first drift region 6 of the first transistor on the first substrate includes: providing a first sub-substrate 1 and forming a stepped etch surface on the upper surface of the first sub-substrate 1; wherein the stepped etch surface includes a high-order etch surface and a low-order etch surface; forming a first silicon dioxide layer on the stepped etch surface, using the first silicon dioxide layer on the high-order etch surface as a first gate oxide layer 2, and using the first silicon dioxide layer on the low-order etch surface as a first field plate oxide layer 3; forming a second sub-substrate 4 on the upper surface of the first silicon dioxide layer, and forming the first body region 5 and the first drift region 6 on the second sub-substrate 4; wherein the first substrate includes the first sub-substrate 1 and the second sub-substrate 4.

[0048] Further, forming a second substrate 7 on the upper surface of the first body region 5 and the first drift region 6 includes: forming a boosting medium layer 8 on the upper surface of the first body region 5 and the first drift region 6; and forming the second substrate 7 on the upper surface of the boosting medium layer 8.

[0049] Furthermore, the boosting dielectric layer 8 is an intrinsic silicon dielectric layer.

[0050] Furthermore, the pressurizing medium layer 8 is a silicon carbide medium layer.

[0051] Furthermore, the method further includes: forming a first isolation layer 12 on the side of the second body region 9 away from the second drift region 10; and forming a second isolation layer 13 on the side of the second drift region 10 away from the first body region 5.

[0052] Specifically, in the embodiments of the present invention, the first transistor in the lateral double-diffused field-effect transistor is an NLDMOS and the second transistor is a PLDMOS, or the first transistor is a PLDMOS and the second transistor is an NLDMOS. The present invention does not limit this. In the following embodiments, only the example of the first transistor being an NLDMOS and the second transistor being a PLDMOS is used for illustration.

[0053] In this embodiment of the invention, the base substrate is composed of multiple sub-substrates, first provided Figure 1 The first sub-substrate 1 of the P-type silicon shown has a thin oxide layer thermally oxidized on its surface. Photoresist is formed on the oxide layer surface, and etching windows are formed on the photoresist. The oxide layer and the first sub-substrate 1 are etched through the etching windows to form... Figure 2 The stepped etching surface shown includes a high-order etching surface and a low-order etching surface. After removing the photoresist, the surface of the first sub-substrate 1 is thermally oxidized to form a thick oxide layer. Excess oxide layer is removed by chemical mechanical polishing to form... Figure 3 The first silicon dioxide layer shown is used as the first gate oxide layer 2 on the high-order etched surface and as the first field plate oxide layer 3 on the low-order etched surface.

[0054] A P-type silicon substrate with a thin layer of silicon dioxide on its surface is attached to the upper surface of the first silicon dioxide layer. The P-type silicon substrate is then thinned to the required thickness to form... Figure 4 The second sub-substrate 4 is shown. A thin layer of silicon dioxide is thermally oxidized on the surface of the second sub-substrate 4, and photoresist is formed on the silicon dioxide surface. Ion implantation windows are formed on the photoresist through exposure and development. N-type ion implantation is performed on the second sub-substrate 4 through the ion implantation windows to remove the photoresist. Photoresist is formed again, and ion implantation windows are formed on the photoresist through exposure and development. P-type ion implantation is performed on the second sub-substrate 4 through the ion implantation windows to remove the photoresist. High-temperature propagation is then performed to form the substrate as shown. Figure 5 The first drift region 6 and the first body region 5 are shown.

[0055] The silicon dioxide on the surface of the second sub-substrate 4 is removed by wet etching, and an N-type doped silicon substrate is epitaxially grown on the surface of the second sub-substrate 4 to obtain... Figure 6 The second substrate 7 is shown.

[0056] Before epitaxially forming the second substrate 7, a layer is epitaxially formed on the surface of the second sub-substrate 4. Figure 7The voltage boosting dielectric layer 8 is shown. The voltage boosting dielectric layer 8 further enhances the isolation effect between the two transistors, enabling the lateral double-diffused field-effect transistor to withstand higher voltages and further improve the breakdown voltage. The voltage boosting dielectric layer 8 can be an intrinsic silicon dielectric layer or a silicon carbide dielectric layer. Both intrinsic silicon and silicon carbide, when used as dielectric layers in the transistors of this application, can withstand higher electric fields, which helps in device heat dissipation, improves power density, and increases reliability.

[0057] Next, a thin layer of silicon dioxide is thermally oxidized on the surface of the second substrate 7. P-type ion implantation is then performed on a portion of the second substrate 7, followed by thermal propulsion to form a P-type doped region on the second substrate 7. The P-type doped region and the undoped second substrate 7 are then etched until a portion of the boost dielectric layer 8 is removed, resulting in... Figure 8 The P-type second body region 9 and the N-type second drift region 10 are shown.

[0058] A thick silicon dioxide layer is deposited on the surface by chemical vapor deposition, and then the silicon dioxide layer is dry etched, retaining a portion of the silicon dioxide layer on the surface of the second drift region 10, the silicon dioxide layer on the side of the second body region 9 away from the second drift region 10, and the silicon dioxide layer on the side of the second drift region 10 away from the first body region 5, thus forming... Figure 9 The second field plate oxide layer 11, the first isolation layer 12, and the second isolation layer 13 are shown.

[0059] The thin oxide layer on the surface of the second substrate 7 is removed, and a second gate oxide layer 14 is formed on the second body region 9. N-type heavily doped polysilicon is deposited on the transistor surface using low-pressure chemical vapor deposition. Part of the N-type heavily doped polysilicon is then removed using dry etching to form… Figure 10 The polysilicon layer 15 shown is formed by the second gate oxide layer 14 and the second field oxide layer 11.

[0060] Photoresist is formed, and ion implantation windows are created on the photoresist through exposure and development. N-type ion implantation is performed through the ion input windows in the regions inside the second body region 9 and the second drift region 10, removing the photoresist. Photoresist is formed again, and ion implantation windows are created on the photoresist through exposure and development. P-type ion implantation is performed on the first body region 5 and the first drift region 6 through the ion input windows, removing the photoresist. High-temperature propagation is then performed to form... Figure 11 The first source 19, the first drain 20, the second source 17, and the second drain 18 are shown.

[0061] Further, forming the first gate and the first field plate of the first transistor includes: thinning the first sub-substrate 1; heavily doping the thinned first sub-substrate 1 to obtain a heavily doped silicon layer 16; using the heavily doped silicon layer 16 and the first gate oxide layer 2 as the first gate, and using the heavily doped silicon layer 16 and the first field plate oxide layer 3 as the first field plate.

[0062] Further, after forming the second transistor within the second substrate 7, the method further includes: forming a dielectric layer on the second substrate 7 and the exposed first substrate; forming a contact hole 22 within the dielectric layer, the contact hole 22 contacting the first source 19, the first drain 20, the second source 17, the second drain 18, and the second gate, respectively; forming a first metal electrode 23, a second metal electrode 24, a fourth metal electrode 25, a fifth metal electrode 26, and a sixth metal electrode 27 within the contact hole 22, respectively; wherein the first metal electrode 23 extends upward from the first source 19 to the upper surface of the base substrate, the second metal electrode 24 extends upward from the first drain 20 to the upper surface of the base substrate, the fourth metal electrode 25 extends upward from the second source 17 to the upper surface of the base substrate, the fifth metal electrode 26 extends upward from the second drain 18 to the upper surface of the base substrate, and the sixth metal electrode 27 extends upward from the second gate to the upper surface of the base substrate; and forming a third metal electrode 28 on the lower surface of the first gate and the first field plate.

[0063] Specifically, in this embodiment of the invention, the thickness of the first sub-substrate 1 at the bottom is reduced, and then P-type heavily doped ions are implanted into the thinned first sub-substrate 1 to form... Figure 11 The heavily doped silicon layer 16 is shown. The heavily doped silicon layer 16 and the first gate oxide layer 2 constitute the first gate, and the heavily doped silicon layer 16 and the first field plate oxide layer 3 constitute the first field plate.

[0064] Forming on the surface of transistors using chemical vapor deposition Figure 12 The dielectric layer 21 shown is formed by dry etching of the dielectric layer 21 on the front side. Figure 13 The plurality of contact holes 22 shown are respectively in contact with the first source 19, the first drain 20, the second source 20, the second drain 21, and the second gate. Metallic material is physically vapor-deposited within the contact holes 22 to form... Figure 14 The first metal electrode 23, the second metal electrode 24, the fourth metal electrode 25, the fifth metal electrode 26, and the sixth metal electrode 27 are shown. Then, a metal material is physically vapor-deposited on the underside of the heavily doped silicon layer 16 on the back side to form... Figure 14 The third metal electrode 28 shown gives the final lateral double-diffused field-effect transistor.

[0065] A third aspect of the present invention provides a chip comprising the lateral double-diffused field-effect transistor described above.

[0066] A fourth aspect of the present invention provides a circuit comprising the lateral double-diffused field-effect transistor described above.

[0067] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0068] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0069] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A lateral double-diffused field-effect transistor, characterized in that, The lateral double-diffused field-effect transistor includes: Basic substrate; A first transistor and a second transistor having opposite carrier types are formed in the base substrate. The first transistor includes a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate. The second transistor includes a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second source is formed in a region of the second body region away from the second drift region, and the second drain is formed in a region of the second drift region away from the second body region. The first gate and the first field plate of the first transistor are formed downward on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upward on the back side region of the first body region and the first drift region of the first transistor, and the first body region and the second body region are formed on the same side of the base substrate.

2. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The lateral double-diffused field-effect transistor further includes a boosting dielectric layer formed between the second transistor and the first transistor.

3. The lateral double-diffused field-effect transistor according to claim 2, characterized in that, The boosting dielectric layer is an intrinsic silicon dielectric layer.

4. The lateral double-diffused field-effect transistor according to claim 2, characterized in that, The pressurization medium layer is a silicon carbide medium layer.

5. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The lateral double-diffused field-effect transistor further includes: a first isolation layer formed on the side outside the second bulk region away from the second drift region; The second isolation layer is formed on the side outside the second drift region, away from the second body region.

6. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The first source electrode is formed on the side of the first body region away from the first drift region, and the first drain electrode is formed on the side of the first drift region away from the first body region.

7. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The lateral double-diffused field-effect transistor further includes: A first metal electrode is led upward from the first source electrode to the upper surface of the base substrate; The second metal electrode is led upward from the first drain electrode to the upper surface of the base substrate; The third metal electrode is led down from the first gate to the lower surface of the base substrate; A fourth metal electrode is led upward from the second source electrode to the upper surface of the base substrate; The fifth metal electrode extends upward from the second drain electrode to the upper surface of the base substrate; The sixth metal electrode is led upward from the second gate to the upper surface of the base substrate; A dielectric layer is formed between the first metal electrode and the fourth metal electrode, between the fourth metal electrode and the sixth metal electrode, between the sixth metal electrode and the fifth metal electrode, and between the fifth metal electrode and the second metal electrode.

8. A method for fabricating a lateral double-diffused field-effect transistor, characterized in that, The method for fabricating the lateral double-diffused field-effect transistor includes: A base substrate is formed, and a first transistor and a second transistor having opposite carrier types are formed within the base substrate; The first transistor includes a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate. The second transistor includes a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second source is formed in a region of the second body region away from the second drift region, and the second drain is formed in a region of the second drift region away from the second body region. The first gate and the first field plate of the first transistor are formed downward on the back side of the base substrate, and the second gate and the second field plate of the second transistor are formed upward on the back side region of the first body region and the first drift region of the first transistor, and the first body region and the second body region are formed on the same side of the base substrate.

9. The method for fabricating a lateral double-diffused field-effect transistor according to claim 8, characterized in that, The process of forming a base substrate and forming a first transistor and a second transistor having opposite carrier types within the base substrate includes: A first substrate is formed, and a first body region and a first drift region of a first transistor are formed on the first substrate; A second substrate is formed on the upper surface of the first body region and the first drift region, and a second transistor is formed within the second substrate; wherein the base substrate includes the first substrate and the second substrate; The first source, first drain, first gate, and first field plate of the first transistor are formed; wherein the first source is formed on the side of the first body region away from the first drift region, and the first drain is formed on the side of the first drift region away from the first body region.

10. The method for fabricating a lateral double-diffused field-effect transistor according to claim 9, characterized in that, The process of forming a first substrate and forming a first body region and a first drift region of a first transistor on the first substrate includes: A first sub-substrate is provided, and a stepped etched surface is formed on the upper surface of the first sub-substrate; wherein the stepped etched surface includes a high-order etched surface and a low-order etched surface; A first silicon dioxide layer is formed on the stepped etching surface, and the first silicon dioxide layer on the higher-order etching surface is used as the first gate oxide layer, and the first silicon dioxide layer on the lower-order etching surface is used as the first field plate oxide layer. A second sub-substrate is formed on the upper surface of the first silicon dioxide layer, and the first body region and the first drift region are formed on the second sub-substrate; wherein, the first substrate includes the first sub-substrate and the second sub-substrate.

11. The method for fabricating a lateral double-diffused field-effect transistor according to claim 9, characterized in that, A second substrate is formed on the upper surface of the first body region and the first drift region, including: A pressurizing medium layer is formed on the upper surface of the first body region and the first drift region; A second substrate is formed on the upper surface of the pressurization medium layer.

12. The method for fabricating a lateral double-diffused field-effect transistor according to claim 11, characterized in that, The boosting dielectric layer is an intrinsic silicon dielectric layer.

13. The method for fabricating a lateral double-diffused field-effect transistor according to claim 11, characterized in that, The pressurization medium layer is a silicon carbide medium layer.

14. The method for fabricating a lateral double-diffused field-effect transistor according to claim 10, characterized in that, The first gate and the first field plate forming the first transistor include: Thinning of the first sub-substrate; The thinned first sub-substrate was heavily doped to obtain a heavily doped silicon layer. The heavily doped silicon layer and the first gate oxide layer are used as the first gate, and the heavily doped silicon layer and the first field plate oxide layer are used as the first field plate.

15. The method for fabricating a lateral double-diffused field-effect transistor according to claim 8, characterized in that, The method further includes: A first isolation layer is formed on the side of the second body region away from the second drift region; A second isolation layer is formed on the side of the second drift zone away from the second body zone.

16. The method for fabricating a lateral double-diffused field-effect transistor according to claim 9, characterized in that, After forming the second transistor within the second substrate, the method further includes: A dielectric layer is formed on the second substrate and the exposed first substrate; Contact holes are formed within the dielectric layer, and the contact holes are respectively in contact with the first source, the first drain, the second source, the second drain, and the second gate; A first metal electrode, a second metal electrode, a fourth metal electrode, a fifth metal electrode, and a sixth metal electrode are formed in the contact hole, respectively; wherein, the first metal electrode is led upward from the first source electrode to the upper surface of the base substrate, the second metal electrode is led upward from the first drain electrode to the upper surface of the base substrate, the fourth metal electrode is led upward from the second source electrode to the upper surface of the base substrate, the fifth metal electrode is led upward from the second drain electrode to the upper surface of the base substrate, and the sixth metal electrode is led upward from the second gate electrode to the upper surface of the base substrate. A third metal electrode is formed on the lower surface of the first gate and the first field plate.

17. A chip, characterized in that, The chip includes a lateral double-diffused field-effect transistor as described in any one of claims 1-7.

18. A circuit, characterized in that, The circuit includes a lateral double-diffused field-effect transistor as described in any one of claims 1-7.

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