A semiconductor packaging structure and its application
By embedding piezoelectric materials in the semiconductor packaging structure and constructing a circuit loop to measure current values, the accuracy problem of internal stress testing of flip-chips is solved, achieving highly reliable stress monitoring, which is applicable to FCCSP, FCBGA and HS-FCBGA type chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PIONEER ORIGINAL (SHANGHAI) NEW TECHNOLOGY RESEARCH CO LTD
- Filing Date
- 2024-11-29
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies struggle to accurately measure the internal stress of flip-chips, especially in thermal stress testing where structural distortion and individual chip testing challenges lead to discrepancies between test results and actual stress conditions.
The method involves embedding piezoelectric materials in a semiconductor packaging structure, forming a circuit loop through conductive welding units, and measuring the current value to obtain the thermal or mechanical stress of the chip.
It enables effective monitoring of internal stress in flip-chip chips, improves the reliability of stress test results, does not damage chip structure and materials, has low cost, and is compatible with semiconductor processes.
Smart Images
Figure CN122138668A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and its application. Background Technology
[0002] The technical challenges of testing the internal stress of chips, especially for flip-chip chips, present significant difficulties. Direct measurement of internal stress in these chips is extremely challenging because their design often prioritizes high integration and miniaturization, making traditional stress testing methods inapplicable. While stress simulation technology provides a qualitative analytical tool, its accuracy limitations make it insufficient for accurately assessing the stress state of chips under actual operating conditions.
[0003] Existing technologies attempt to measure chip deformation under stress by constructing a Wheatstone bridge resistor on the chip surface, thereby inferring the internal stress state. This method overcomes the difficulties of direct measurement to some extent, but still has several key limitations, especially when applied to flip-chip devices: 1) Structural distortion: The Wheatstone bridge layer added above the strain gauge not only increases packaging complexity but may also cause distortion of the chip's surface structure due to material mismatch or thermal stress during the manufacturing process. This distortion masks the chip's true intrinsic stress value, making it difficult for the test results to accurately reflect the actual internal stress state; 2) Individual chip testing challenges: Because testing requires the chip to be mounted on a PCB board, this limits the ability to perform individual-level thermal stress testing. Flip-chip devices often need to withstand thermal stress caused by temperature changes in practical applications, and the test conditions may differ from the actual working environment, leading to deviations between the test results and the actual stress state. Summary of the Invention
[0004] This invention provides a semiconductor packaging structure and its application.
[0005] In a first aspect, the present invention provides a semiconductor packaging structure, comprising:
[0006] Semiconductor wafers;
[0007] A dielectric layer formed on the semiconductor wafer;
[0008] Multiple pads formed in the dielectric layer;
[0009] A substrate having a first surface facing the semiconductor wafer and a second surface facing away from the semiconductor wafer;
[0010] The semiconductor wafer is connected to a first metal wiring layer on a first surface of the substrate via the pads and a plurality of first conductive welding units, and is connected to a second metal wiring layer on a second surface of the substrate via first through-hole metal, wherein the second metal wiring layer has a plurality of second conductive welding units.
[0011] The semiconductor packaging structure further includes a first pad and a second pad, wherein the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer.
[0012] The first pad is connected to the first metal wiring layer on the first surface of the substrate through the first conductive soldering unit. The second metal wiring layer also has a third conductive soldering unit. The first conductive soldering unit is connected to the third conductive soldering unit through a second through-hole metal.
[0013] The second pad is connected to the first metal wiring layer on the first surface of the substrate through a piezoelectric material welding unit. The second metal wiring layer also has a fourth conductive welding unit, and the piezoelectric material welding unit is connected to the fourth conductive welding unit through a third through-hole metal.
[0014] An encapsulation layer that encapsulates the semiconductor wafer on a first surface of the substrate.
[0015] Secondly, the present invention provides a method for stress testing of semiconductor packaging structures, comprising:
[0016] Provides the semiconductor packaging structure as described above;
[0017] Under the condition that the semiconductor packaging structure is subjected to thermal stress or mechanical stress, the third conductive welding unit and the fourth conductive welding unit are connected by wires, and the first pad, the first conductive welding unit, the third conductive welding unit, the fourth conductive welding unit, the piezoelectric material welding unit and the second pad constitute a circuit loop.
[0018] The thermal or mechanical stress on the semiconductor package structure is obtained by measuring the current value of the circuit loop.
[0019] Thirdly, the present invention provides a method for fabricating a semiconductor packaging structure, comprising:
[0020] Provide semiconductor wafers;
[0021] A dielectric layer is formed on the semiconductor wafer;
[0022] Multiple pads are formed in the dielectric layer;
[0023] A substrate is provided having a first surface facing the semiconductor wafer and a second surface facing away from the semiconductor wafer;
[0024] The semiconductor wafer is connected to a first metal wiring layer on a first surface of the substrate via the pads and a plurality of first conductive welding units, and is connected to a second metal wiring layer on a second surface of the substrate via first through-hole metal, wherein the second metal wiring layer has a plurality of second conductive welding units.
[0025] A first pad and a second pad are provided, wherein the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer;
[0026] The first pad is connected to the first metal wiring layer on the first surface of the substrate through the first conductive soldering unit. The second metal wiring layer also has a third conductive soldering unit. The first conductive soldering unit is connected to the third conductive soldering unit through a second through-hole metal.
[0027] The second pad is connected to the first metal wiring layer on the first surface of the substrate through a piezoelectric material welding unit. The second metal wiring layer also has a fourth conductive welding unit, and the piezoelectric material welding unit is connected to the fourth conductive welding unit through a third through-hole metal.
[0028] An encapsulation layer is provided that encapsulates the semiconductor wafer on a first surface of the substrate. Attached Figure Description
[0029] Figure 1 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to the present invention;
[0030] Figure 2 This is a cross-sectional schematic diagram of the dielectric layer in a semiconductor packaging structure according to the present invention;
[0031] Figure 3 This is another cross-sectional schematic diagram of the dielectric layer in a semiconductor packaging structure according to the present invention;
[0032] Figure 4 This is another cross-sectional schematic diagram of a semiconductor packaging structure according to the present invention;
[0033] Figure 5 This is another cross-sectional schematic diagram of a semiconductor packaging structure according to the present invention;
[0034] Figure 6 This is a top view of a semiconductor wafer representing a semiconductor packaging structure according to the present invention;
[0035] Figure 7 This is a top view of a substrate of a semiconductor packaging structure according to the present invention;
[0036] Figure 8 This is a flowchart illustrating a method for stress testing of a semiconductor packaging structure according to the present invention;
[0037] Figure 9 This is a schematic flowchart of a semiconductor packaging structure fabrication method according to the present invention;
[0038] Figure label:
[0039] 1. Semiconductor wafer; 2. Dielectric layer; 20. Pad; 21. First pad; 22. Second pad; 23. Metal interconnect layer; 24. Fourth via metal; 25. First groove; 26. Second groove; 27. Passivation layer; 3. Substrate; 31. First metal wiring layer; 32. First via metal; 33. Second metal wiring layer; 34. Second via metal; 35. Third via metal; 41. First conductive welding unit; 42. Second conductive welding unit; 43. Third conductive welding unit; 44. Fourth conductive welding unit; 411. Conductor; 412. Seed layer; 413. Welding material layer; 5. Piezoelectric material welding unit layer; 51. Piezoelectric material; 52. Seed layer; 53. Welding material layer; 6. Package. Detailed Implementation
[0040] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. The following content is for illustrative purposes only and is not intended to limit the scope of the invention.
[0041] In the description of this invention, it should be understood that the terms "first" and "second," etc., are used to distinguish different objects, rather than to describe a specific order.
[0042] In the description of this invention, it should be noted that, unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for descriptive purposes only and is not intended to limit the invention. Those skilled in the art can understand the specific meaning of the terms in this invention based on the specific circumstances.
[0043] like Figure 1 As shown, the present invention provides a semiconductor packaging structure, comprising:
[0044] Semiconductor wafer 1;
[0045] A dielectric layer formed on a semiconductor wafer;
[0046] Multiple pads 20 formed in the dielectric layer;
[0047] Substrate 3, the substrate has a first surface facing the semiconductor wafer and a second surface facing away from the semiconductor wafer;
[0048] The semiconductor wafer is connected to the first metal wiring layer 31 on the first surface of the substrate via pads and multiple first conductive welding units 41, and is connected to the second metal wiring layer 33 on the second surface of the substrate via first through-hole metal 32. The second metal wiring layer has multiple second conductive welding units 42.
[0049] The semiconductor package structure also includes a first pad 21 and a second pad 22, which are connected in the dielectric layer by a metal interconnect layer 23.
[0050] The first pad is connected to the first metal wiring layer on the first surface of the substrate through the first conductive welding unit. The second metal wiring layer also has a third conductive welding unit 43. The first conductive welding unit is connected to the third conductive welding unit through the second through-hole metal 34.
[0051] The second pad is connected to the first metal wiring layer on the first surface of the substrate through the piezoelectric material welding unit 5. The second metal wiring layer also has a fourth conductive welding unit 44. The piezoelectric material welding unit is connected to the fourth conductive welding unit through the third through-hole metal 35.
[0052] Encapsulation layer 6 encapsulates the semiconductor wafer on the first surface of the substrate.
[0053] Figure 2 It shows Figure 1 In some embodiments, in the dielectric layer 2, the metal connection layer is far from the substrate relative to the first and second pads, while the first and second pads are close to the substrate relative to the metal connection layer. The metal connection layer is connected to the first and second pads respectively through the fourth through-hole metal 24. It should be noted that both the first and second pads are passive structures and do not need to be connected to the electrodes on the semiconductor wafer. The dielectric layer includes a first groove 25 and a second groove 26. The first pad is disposed in the first groove, and the second pad is disposed in the second groove. The first conductive welding unit is disposed beyond the depth of the first groove, and the piezoelectric material welding unit is disposed beyond the depth of the second groove. A passivation layer 27 is disposed on the surface of the dielectric layer, which separates the first conductive welding unit and the piezoelectric material welding unit. The first conductive welding unit includes a conductor 411 disposed on the first pad, a seed layer 412 disposed on the conductor, and a welding material layer 413 disposed on the seed layer. The piezoelectric material welding unit includes a piezoelectric material 51 disposed on the second pad, a seed layer 52 disposed on the piezoelectric material, and a welding material layer 53 disposed on the seed layer.
[0054] In some embodiments, the encapsulation layer is made of resin, encapsulating the semiconductor wafer on the first surface of the substrate to seal the semiconductor wafer. The dielectric material in the dielectric layer includes, but is not limited to, silicon oxide, and its purpose is to insulate the conductive structure. The first and second pads are parallel to each other and fabricated simultaneously. The first metal wiring layer, second metal wiring layer, metal connection layer, first through-hole metal, second through-hole metal, third through-hole metal, fourth through-hole metal, first pad, and second pad are made of copper or aluminum, and the metal connection layer is a conductive wire. The second, third, and fourth conductive soldering units are conductive pillars or conductive balls, respectively. An opening is formed by removing the passivation layer in the central region of the first and second pads. The passivation layer is a multilayer structure including silicon nitride and silicon oxide. A conductor is deposited on the first pad by electroplating; the conductor material includes, but is not limited to, copper, silver, and copper-silver alloys. A piezoelectric material is deposited on the second pad by sputtering; the piezoelectric material is one of ZnO, PZT, or AlN. Seed layers are deposited on both conductive materials and piezoelectric materials via sputtering. The seed layer materials include, but are not limited to, nickel, titanium, and tantalum. For conductive materials, the seed layer increases reliability and prevents metal diffusion. For piezoelectric materials, the seed layer facilitates the subsequent application of a soldering material layer. Since piezoelectric materials are non-conductive and cannot undergo subsequent electroplating processes, a seed layer is sputtered first. A soldering material layer is then applied to the seed layer via electroplating. Detailed descriptions of the characteristics of the piezoelectric materials are provided in Table 1.
[0055] Table 1 Properties of different piezoelectric materials
[0056]
[0057]
[0058] Figure 3 It shows Figure 2 In some embodiments, the conductor and piezoelectric material are soldered to a first surface of the substrate. Before soldering, the solder is semi-circular; after soldering, the solder is trapezoidal.
[0059] In some implementations, the conductor is first aligned with the second through-hole metal of the substrate, and the piezoelectric material is aligned with the third through-hole metal of the substrate. Then, the semiconductor wafer and the substrate as a whole are heated. Finally, when the temperature exceeds 243 degrees Celsius, the solder melts, thereby interconnecting with the first metal wiring layer on the first surface of the substrate. No additional soldering material is required.
[0060] Figure 4A cross-sectional schematic diagram of some other embodiments of a semiconductor packaging structure according to the present invention is shown. The semiconductor packaging structure is configured to connect a third conductive bonding unit and a fourth conductive bonding unit via wires. A first pad, a first conductive bonding unit, a third conductive bonding unit, a fourth conductive bonding unit, a piezoelectric material bonding unit, and a second pad constitute a circuit loop. The thermal or mechanical stress on the semiconductor packaging structure is obtained by measuring the current value of the circuit loop.
[0061] Figure 5 It shows Figure 4 In some implementations, the negative electrode of the piezoelectric material is connected to the second pad, and the positive electrode is connected to the seed layer. When the semiconductor package structure is subjected to external thermal or mechanical stress, stress is generated on the surface of the piezoelectric material, creating a voltage difference between the positive and negative electrodes. At this time, a current is generated in the circuit due to the voltage difference, where the piezoelectric material welding unit and the fourth conductive welding unit constitute the positive electrode path. See [link to relevant documentation]. Figure 5 The red portion in the middle, consisting of the first pad, the first conductive welding unit, the third conductive welding unit, the piezoelectric material welding unit, and the second pad, forms the negative electrode path. (See [link]). Figure 5 The green part.
[0062] In some embodiments, the piezoelectric material is cylindrical with a height of 50–120 μm and a diameter of 40–120 μm. In other embodiments, PZT is selected as the piezoelectric material, with a piezoelectric coefficient of 1000 pC / N and dimensions of 50 × 50 μm. The metal circuit cross-section is 10 μm × 10 μm, and the circuit loop length is 40 mm. Under the above conditions, the semiconductor package structure is heated, and the thermal stress inside the semiconductor package structure gradually increases with temperature. When the temperature reaches 260 degrees Celsius, the circuit loop generates a current of 112 pA. If the ammeter reads a current of 112 pA, it is determined that the semiconductor wafer surface is subjected to a pressure of 300 MPa.
[0063] The remaining embodiments of the semiconductor packaging structure of the present invention will be described in detail below:
[0064] In some embodiments, the semiconductor packaging structure of the present invention is applied to stress testing of FCCSP-type chips. Piezoelectric material is placed in the area to be tested, and the internal stress of the FCCSP chip is monitored or measured in real time. Figure 6 A top view of a semiconductor wafer is shown of the semiconductor packaging structure of the present invention applied to stress testing of FCCSP type chips. Figure 7 The diagram shows a top view of a semiconductor packaging structure for stress testing of FCCSP-type chips according to the present invention.
[0065] In some embodiments, the semiconductor packaging structure of the present invention is applied to stress testing of FCBGA type chips and HS-FCBGA type chips.
[0066] This invention discloses a semiconductor packaging structure that, by embedding piezoelectric material inside a semiconductor wafer and using a conductive welding unit to extract and measure the electrical signal of the piezoelectric material, obtains the internal pressure value of the semiconductor wafer. This enables effective monitoring of micro-region stress inside flip-chips; it does not damage the chip's structure and material, improving the reliability of stress test results; it is fully compatible with semiconductor processes and has low implementation costs.
[0067] like Figure 8 As shown, the present invention provides a method for stress testing of semiconductor package structures, including the following steps:
[0068] S1. Provide a semiconductor packaging structure;
[0069] Provide such as Figure 1 The semiconductor packaging structure shown.
[0070] S2. Under the condition that the semiconductor packaging structure is subjected to thermal stress or mechanical stress, the third conductive welding unit and the fourth conductive welding unit are connected by wires, and the first pad, the first conductive welding unit, the third conductive welding unit, the fourth conductive welding unit, the piezoelectric material welding unit and the second pad constitute a circuit loop.
[0071] S3. Based on the current value of the measurement circuit loop, obtain the thermal or mechanical stress on the semiconductor package structure.
[0072] Based on the current value of the measurement circuit loop and the piezoelectric coefficient of the piezoelectric material in the piezoelectric material welding unit, the thermal or mechanical stress on the semiconductor packaging structure is obtained.
[0073] It should be noted that the specific limitations of a stress testing method for a semiconductor packaging structure are as described above regarding the limitations of a semiconductor packaging structure. The two methods have the same function and role, and will not be repeated here.
[0074] like Figure 9 As shown, the present invention provides a method for fabricating a semiconductor packaging structure, comprising the following steps:
[0075] S11, providing semiconductor wafers;
[0076] S12. Forming a dielectric layer on a semiconductor wafer;
[0077] S13. Multiple pads are formed in the dielectric layer;
[0078] S14, Provide a substrate;
[0079] The substrate has a first surface facing the semiconductor wafer and a second surface facing away from the semiconductor wafer.
[0080] S15. The semiconductor wafer is connected to the first metal wiring layer on the first surface of the substrate through pads and multiple first conductive welding units, and is connected to the second metal wiring layer on the second surface of the substrate through first through-hole metal.
[0081] The second metal wiring layer has multiple second conductive soldering units.
[0082] S16. A first pad and a second pad are provided, wherein the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer.
[0083] S17. The first pad is connected to the first metal wiring layer on the first surface of the substrate through the first conductive welding unit. The second metal wiring layer also has a third conductive welding unit. The first conductive welding unit is connected to the third conductive welding unit through the second through-hole metal.
[0084] S18. The second pad is connected to the first metal wiring layer on the first surface of the substrate through a piezoelectric material welding unit. The second metal wiring layer also has a fourth conductive welding unit. The piezoelectric material welding unit is connected to the fourth conductive welding unit through a third through-hole metal.
[0085] S19. Provide a packaging layer that encapsulates a semiconductor wafer on a first surface of a substrate.
[0086] In the dielectric layer, the metal interconnect layer is disposed away from the substrate relative to the first and second pads, while the first and second pads are disposed close to the substrate relative to the metal interconnect layer. The metal interconnect layer is connected to the first and second pads respectively through a fourth through-hole. The dielectric layer includes a first groove and a second groove. A first pad is disposed in the first groove, and a second pad is disposed in the second groove. A first conductive welding unit is disposed beyond the depth of the first groove, and a piezoelectric material welding unit is disposed beyond the depth of the second groove. A passivation layer is disposed on the surface of the dielectric layer, separating the first conductive welding unit and the piezoelectric material welding unit. The first conductive welding unit includes a conductor, a seed layer, and a welding material layer. A conductor is disposed on the first pad, a seed layer is disposed on the conductor, and a welding material layer is disposed on the seed layer. The piezoelectric material welding unit includes a piezoelectric material, a seed layer, and a welding material layer. A piezoelectric material is disposed on the second pad, a seed layer is disposed on the piezoelectric material, and a welding material layer is disposed on the seed layer.
[0087] It should be noted that the specific limitations of a semiconductor packaging structure fabrication method are as described above regarding the limitations of a semiconductor packaging structure. The two have the same function and role, and will not be repeated here.
[0088] In summary, the present invention provides a semiconductor packaging structure and its application. By embedding piezoelectric materials inside a semiconductor wafer and using a conductive welding unit to extract and measure the electrical signals of the piezoelectric materials, the internal pressure value of the semiconductor wafer can be obtained. This enables effective monitoring of the micro-region stress inside flip-chips; it does not damage the chip's structure and material, improving the reliability of stress test results; it is fully compatible with semiconductor processes and has low implementation costs.
[0089] The various embodiments in this specification are described in a progressive manner. For directly identical or similar parts of each embodiment, refer to the other embodiments. Each embodiment focuses on its differences from other embodiments. It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as these combinations of technical features do not contradict each other, they should be considered within the scope of this specification.
[0090] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.
Claims
1. A semiconductor packaging structure, characterized in that, include: Semiconductor wafers; A dielectric layer formed on the semiconductor wafer; Multiple pads formed in the dielectric layer; A substrate having a first surface facing the semiconductor wafer and a second surface facing away from the semiconductor wafer; The semiconductor wafer is connected to a first metal wiring layer on a first surface of the substrate via the pads and a plurality of first conductive welding units, and is connected to a second metal wiring layer on a second surface of the substrate via first through-hole metal, wherein the second metal wiring layer has a plurality of second conductive welding units. The semiconductor packaging structure further includes a first pad and a second pad, wherein the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer. The first pad is connected to the first metal wiring layer on the first surface of the substrate through the first conductive soldering unit. The second metal wiring layer also has a third conductive soldering unit. The first conductive soldering unit is connected to the third conductive soldering unit through a second through-hole metal. The second pad is connected to the first metal wiring layer on the first surface of the substrate through a piezoelectric material welding unit. The second metal wiring layer also has a fourth conductive welding unit, and the piezoelectric material welding unit is connected to the fourth conductive welding unit through a third through-hole metal. An encapsulation layer that encapsulates the semiconductor wafer on a first surface of the substrate.
2. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure is configured to connect the third conductive welding unit and the fourth conductive welding unit via wires. The first pad, the first conductive welding unit, the third conductive welding unit, the fourth conductive welding unit, the piezoelectric material welding unit, and the second pad constitute a circuit loop. The thermal stress or mechanical stress on the semiconductor packaging structure is obtained by measuring the current value of the circuit loop.
3. The semiconductor packaging structure according to claim 1, characterized in that, In the dielectric layer, the metal interconnect layer is away from the substrate relative to the first pad and the second pad, and the first pad and the second pad are close to the substrate relative to the metal interconnect layer. The metal interconnect layer is connected to the first pad and the second pad respectively through a fourth through-hole metal.
4. The semiconductor packaging structure according to claim 3, characterized in that, The dielectric layer includes a first groove and a second groove. The first pad is disposed in the first groove, and the second pad is disposed in the second groove. The first conductive welding unit extends beyond the depth of the first groove, and the piezoelectric material welding unit extends beyond the depth of the second groove. A passivation layer is disposed on the surface of the dielectric layer, and the passivation layer separates the first conductive welding unit and the piezoelectric material welding unit.
5. The semiconductor packaging structure according to claim 1 or 4, characterized in that, The first conductive welding unit includes a conductor disposed on the first pad, a seed layer disposed on the conductor, and a welding material layer disposed on the seed layer.
6. The semiconductor packaging structure according to claim 1 or 4, characterized in that, The piezoelectric material welding unit includes a piezoelectric material disposed on the second welding pad, a seed layer disposed on the piezoelectric material, and a welding material layer disposed on the seed layer.
7. The semiconductor packaging structure according to claim 6, characterized in that, The piezoelectric material is one of ZnO, PZT or AlN.
8. The semiconductor packaging structure according to claim 1, characterized in that, The second, third, and fourth conductive welding units are conductive welding columns or conductive welding balls, respectively.
9. A method for stress testing of semiconductor package structures, characterized in that, include: Provide a semiconductor packaging structure as described in any one of claims 1-8; Under the condition that the semiconductor packaging structure is subjected to thermal stress or mechanical stress, the third conductive welding unit and the fourth conductive welding unit are connected by wires, and the first pad, the first conductive welding unit, the third conductive welding unit, the fourth conductive welding unit, the piezoelectric material welding unit and the second pad constitute a circuit loop. The thermal or mechanical stress on the semiconductor package structure is obtained by measuring the current value of the circuit loop.
10. The semiconductor package structure stress testing method according to claim 9, characterized in that, The method of obtaining the thermal or mechanical stress on the semiconductor package structure based on measuring the current value of the circuit loop includes: The thermal or mechanical stress on the semiconductor packaging structure is obtained by measuring the current value of the circuit loop and the piezoelectric coefficient of the piezoelectric material in the piezoelectric material welding unit.
11. A method for fabricating a semiconductor packaging structure, characterized in that, include: Provide semiconductor wafers; A dielectric layer is formed on the semiconductor wafer; Multiple pads are formed in the dielectric layer; A substrate is provided having a first surface facing the semiconductor wafer and a second surface facing away from the semiconductor wafer; The semiconductor wafer is connected to a first metal wiring layer on a first surface of the substrate via the pads and a plurality of first conductive welding units, and is connected to a second metal wiring layer on a second surface of the substrate via first through-hole metal, wherein the second metal wiring layer has a plurality of second conductive welding units. A first pad and a second pad are provided, wherein the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer; The first pad is connected to the first metal wiring layer on the first surface of the substrate through the first conductive soldering unit. The second metal wiring layer also has a third conductive soldering unit. The first conductive soldering unit is connected to the third conductive soldering unit through a second through-hole metal. The second pad is connected to the first metal wiring layer on the first surface of the substrate through a piezoelectric material welding unit. The second metal wiring layer also has a fourth conductive welding unit, and the piezoelectric material welding unit is connected to the fourth conductive welding unit through a third through-hole metal. An encapsulation layer is provided that encapsulates the semiconductor wafer on a first surface of the substrate.
12. The method for fabricating a semiconductor packaging structure according to claim 11, characterized in that, In the dielectric layer, the metal connection layer is disposed away from the substrate relative to the first pad and the second pad, and the first pad and the second pad are disposed close to the substrate relative to the metal connection layer. The metal connection layer is connected to the first pad and the second pad respectively through a fourth through-hole metal.
13. The method for fabricating a semiconductor packaging structure according to claim 12, characterized in that, The dielectric layer includes a first groove and a second groove. The first pad is disposed in the first groove, and the second pad is disposed in the second groove. The first conductive welding unit is disposed beyond the depth of the first groove, and the piezoelectric material welding unit is disposed beyond the depth of the second groove. A passivation layer is disposed on the surface of the dielectric layer, and the passivation layer separates the first conductive welding unit and the piezoelectric material welding unit.
14. The method for fabricating a semiconductor packaging structure according to claim 11 or 13, characterized in that, The first conductive welding unit includes a conductor, a seed layer, and a welding material layer. The conductor is disposed on the first pad, the seed layer is disposed on the conductor, and the welding material layer is disposed on the seed layer.
15. The method for fabricating a semiconductor packaging structure according to claim 11 or 13, characterized in that, The piezoelectric material welding unit includes a piezoelectric material, a seed layer, and a welding material layer. The piezoelectric material is disposed on the second pad, the seed layer is disposed on the piezoelectric material, and the welding material layer is disposed on the seed layer.