Heat dissipation module and semiconductor package structure comprising the same

Abstract

A heat dissipation module includes a heat dissipation element and an ultrathin thermally conductive insulating layer formed and coated on a predetermined surface of the heat dissipation element. The ultrathin thermally conductive insulating layer is formed using an atomic layer deposition process and has a thickness equal to or less than 50 nanometers and an extremely low leakage current density. The ultrathin thermally conductive insulating layer effectively reduces thermal resistance and allows contact with highly thermally conductive but electrically conductive thermal interface materials without short-circuiting.

Description

Technical Field

[0001] This invention relates to a heat dissipation module and a semiconductor packaging structure including the heat dissipation module, and more particularly to a heat dissipation module utilizing an ultrathin thermally conductive insulating layer having high thermal conductivity per unit area (MW / m²·K) and extremely low leakage current density, and a semiconductor packaging structure including the heat dissipation module. Background Technology

[0002] As semiconductor manufacturing technology continues to shrink according to Moore's Law, the integration level of integrated circuit (IC) components is increasing daily. Driven by high-performance computing (HPC), artificial intelligence (AI) chips, and high-frequency communication components, the power density within a single chip or package module is rising dramatically. When excessive heat accumulates within a limited volume and cannot be effectively removed, it leads to overheating of the chip, resulting in serious problems such as decreased chip performance, reduced reliability, and even component burnout. Therefore, "thermal management" has become a key bottleneck restricting the performance of next-generation electronic products.

[0003] In traditional electronic packaging architectures, heat dissipation occurs through the active regions of the chip, passing through the passivation layer on the chip surface, then through the thermal interface material (TIM) and heat spreader to the heat sink, and finally dissipating into the environment. Each contact interface generates contact thermal resistance, and each material layer itself also has thermal conductivity resistance.

[0004] The main challenge facing existing technologies is that it is often difficult to achieve both thermal conductivity and insulation properties simultaneously, which manifests in the following aspects.

[0005] First, regarding the limitations of thermal interface materials (TIMs): TIMs are primarily used to fill gaps between rough contact surfaces. To improve thermal conductivity (k), the industry often adds high thermal conductivity fillers, such as silver, copper, graphene, or carbon nanotubes, to polymer substrates. However, these high-performance fillers are typically conductive. When the filler concentration exceeds the percolation threshold in pursuit of high thermal conductivity, the TIM will transform into an electrically conductive material due to the continuous conductive network formed by the filler. If such conductive TIMs are directly applied to the surface of wafers or components without proper insulation treatment, short circuits can easily occur. Therefore, to ensure electrical safety, existing technologies are often forced to use ceramic fillers with lower thermal conductivity (such as alumina) or limit the proportion of metal fillers, thus sacrificing heat dissipation performance.

[0006] Second, regarding the thermal resistance of the passivation layer and the insulating layer: An insulating liner is typically required on the inner wall of the through-silicon via (TSV) on the wafer surface or within the silicon interposer to prevent leakage. Traditionally, these insulating liners are made of silicon dioxide (SiO2) or silicon nitride (SiN) formed by thermal oxidation, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD) processes. x Its thickness is typically between hundreds of nanometers and several micrometers. However, SiO2 and SiN... x The inherent thermal conductivity of SiO2 is extremely low (approximately 1.4 W / m·K), and the thick insulating layer creates a significant thermal resistance barrier. Especially in 2.5D / 3D advanced semiconductor packaging structures, the TSV (Transient Voltage Shield) is a crucial path for vertical heat conduction. If the insulating pads on the inner wall of the TSV have excessively high thermal resistance, it will severely hinder the ability of heat to conduct radially from the inside of the stacked wafer to the silicon substrate, thus limiting the overall heat dissipation efficiency.

[0007] Third, the heat transfer mechanism at the nanoscale: According to the thermal resistance formula (described in detail below), when the thickness of the insulating film is reduced to the nanometer scale (e.g., less than 10 nanometers), the contribution of the bulk thermal resistance of the film material will decrease significantly, and the total thermal resistance will be mainly dominated by the "interfacial thermal resistance". However, simply thinning the insulating layer manufactured by traditional CVD processes often leads to a sharp increase in leakage current density due to excessively high pinhole or defect density, resulting in a loss of insulation function. Therefore, reducing the thickness of the insulating layer as much as possible without sacrificing electrical insulation is an effective way to improve overall heat dissipation efficiency.

[0008] Furthermore, for materials with high thermal conductivity potential, such as aluminum nitride (AlN), thin films deposited at low temperatures (e.g., below 300°C) using conventional atomic layer deposition (ALD) processes typically exhibit amorphous or polycrystalline structures. Grain boundary scattering severely restricts phonon transport, resulting in thermal conductivity far lower than the theoretical value for bulk materials. In addition, for two-dimensional materials such as boron nitride (BN), if their lattice orientation cannot be controlled, their excellent in-plane thermal conductivity cannot effectively contribute to the vertical heat dissipation path, thus limiting overall heat dissipation efficiency.

[0009] Therefore, in the field of heat dissipation technology, there is an urgent need for an innovative solution that can achieve both "extremely low leakage current" (excellent insulation) and "extremely low thermal resistance" (efficient heat dissipation) with an extremely thin insulating layer thickness (e.g., less than 50 nanometers), and can control the microstructure of the material for different application scenarios (e.g., heat dissipation components, TSVs, wafer surfaces) to break through the performance bottlenecks of existing heat dissipation modules and advanced semiconductor packaging architectures. Summary of the Invention

[0010] The purpose of this invention is to provide a heat dissipation module and a semiconductor package structure including the heat dissipation module. According to the heat dissipation module and semiconductor package structure of this invention, an "ultra-thin thermally conductive insulating layer" with ultra-thin thickness, extremely low leakage current density, and excellent thermal conductivity is formed using an atomic layer deposition-based (ALD) process, thus solving the problem of the difficulty in simultaneously achieving thermal conductivity and electrical insulation performance in the prior art.

[0011] A heat dissipation module according to a first preferred embodiment of the present invention includes a heat dissipation element and an ultrathin thermally conductive insulating layer. The heat dissipation element has a predetermined surface, and the ultrathin thermally conductive insulating layer is formed and coated on the predetermined surface of the heat dissipation element. The ultrathin thermally conductive insulating layer is formed by an atomic layer deposition (ALD-based) process. The thickness of the ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers, and the leakage current density of the ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers. 10 -6 A / cm 2 .

[0012] In one specific embodiment, the atomic layer deposition process can be a conventional atomic layer deposition process, an atomic layer annealing-enhanced atomic layer deposition (ALD) process, a hydrogen manipulated atomic layer deposition (HM-ALD) process, a plasma-activated precursor ALD (PAP-ALD) process, a UV-enhanced atomic layer deposition (UV-enhanced ALD) process, a plasma-enhanced atomic layer deposition (PEALD) process, a multiple-pulses atomic layer deposition (ALD) process, an exposure-mode atomic layer deposition (ALD) process, or other atomic layer deposition-based processes.

[0013] In one specific embodiment, a heat dissipation element is a heat sink or vapor chamber. A predetermined contact surface contacts the thermal interface material. An ultra-thin thermally conductive insulating layer provides electrical insulation between the heat sink or vapor chamber and the thermal interface material while maintaining good thermal conductivity.

[0014] In another specific embodiment, a heat dissipation element is a silicon interposer. The predetermined surface is the inner wall of a silicon through-hole formed by the silicon interposer. An ultrathin thermally conductive insulating layer serves as an insulating pad to isolate the conductive material within the silicon through-hole from the silicon interposer and to provide a path for radial heat conduction.

[0015] In one specific embodiment, the ultrathin thermally conductive insulating layer according to the present invention can be formed of a metal oxide. The metal oxide can be HfO2, ZrO2, or Hf... x Zr 1-x O2 (0≦x≦1), Ta2O3, Al2O3, Gd2O3, La2O3, SiO2, TiO2, Y2O3 or other metal oxides.

[0016] In another specific embodiment, the ultrathin thermally conductive insulating layer according to the present invention can be formed of a metal nitride. The metal nitride can be AlN. x SiN x GeN x BN x Or other metal nitrides, wherein 0.5 ≤ x ≤ 1.5.

[0017] In one specific embodiment, the thickness of the ultrathin thermally conductive insulating layer ranges from 3 nanometers to 50 nanometers. The thermal conductivity per unit area of ​​the ultrathin thermally conductive insulating layer is equal to or greater than 50 MW / m.2 ·K.

[0018] The semiconductor package structure according to a second preferred embodiment of the present invention includes a substrate, an interposer, a plurality of metal plugs, a plurality of first bumps, at least one chiplet, and a first ultrathin thermally conductive insulating layer. The interposer has a plurality of interposer vias. The interposer is disposed on the substrate. The interposer is a silicon interposer or a glass interposer. When the interposer is silicon, the plurality of interposer vias are multiple through-silicon vias (TSVs). When the interposer is glass, the plurality of interposer vias are multiple through-glass vias (TGVs). Each metal plug corresponds to one interposer via and fills its corresponding interposer via. Each first bump corresponds to one metal plug and is electrically bonded to its corresponding metal plug and the substrate. At least one chiplet is disposed on the interposer. Each chiplet has a plurality of second bumps. Each second bump corresponds to one metal plug and is electrically bonded to its corresponding metal plug. A first ultrathin thermally conductive insulating layer is formed and coated on at least one small wafer, an interposer, a plurality of first bumps, and a plurality of second bumps. The first ultrathin thermally conductive insulating layer is formed by a first atomic layer deposition process. The first thickness of the first ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers, and the first leakage current density of the first ultrathin thermally conductive insulating layer is equal to or less than... 10 -6 A / cm 2 .

[0019] When the interposer is a silicon interposer and multiple interposer vias are present, the semiconductor package structure according to the second preferred embodiment of the present invention further includes multiple second ultrathin thermally conductive insulating layers. Each second ultrathin thermally conductive insulating layer corresponds to one silicon via and is formed and coated on the respective inner wall of its corresponding silicon via. The multiple second ultrathin thermally conductive insulating layers are formed by a second atomic layer deposition (ALD-based) process. The second thickness of each second ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers, and the second leakage current density of each second ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers. 10 -6 A / cm 2 .

[0020] In one specific embodiment, the first atomic layer deposition (ALD) based process and the second atomic layer deposition (ALD) based process can be a conventional atomic layer deposition process, an atomic layer annealing enhanced atomic layer deposition (ALA-ALD) process, a hydrogen-manipulated atomic layer deposition (HM-ALD) process, a plasma activated precursor enhanced atomic layer deposition (PAP-ALD) process, a UV-enhanced atomic layer deposition (UV-enhanced ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a multiple-pulses atomic layer deposition (multiple-pulses ALD) process, an exposure-mode atomic layer deposition (exposure-mode ALD) process, or other atomic layer deposition based processes.

[0021] In one specific embodiment, the plurality of first ultrathin thermally conductive insulating layers and the second ultrathin thermally conductive insulating layer can be formed of metal oxides or metal nitrides, respectively. The metal oxides can be HfO2, ZrO2, or Hf... x Zr 1-x O2 (0≦x≦1), Ta2O3, Al2O3, Gd2O3, La2O3, SiO2, TiO2, Y2O3, or other metal oxides. Metal nitrides can be AlN. x SiN x GeN x BN x Or other metal nitrides, wherein 0.5 ≤ x ≤ 1.5.

[0022] Furthermore, the semiconductor package structure according to a second preferred embodiment of the present invention further includes a small wafer stack. The small wafer stack is disposed on an interposer. The small wafer stack has a plurality of third bumps. Each third bump corresponds to a metal plug and is electrically bonded to its corresponding metal plug. A first ultrathin thermally conductive insulating layer is applied to the entire outer surface of the small wafer stack.

[0023] Unlike existing technologies, this invention utilizes the phonon ballistic transport properties of ultrathin films or specific crystal orientations (such as hexagonal boron nitride grown close to the wafer surface) to minimize the thermal resistance of the ultrathin insulating layer. Simultaneously, this invention forms a high-quality, ultrathin thermally conductive insulating layer using an atomic layer deposition process, enabling it to maintain extremely low thermal resistance while possessing excellent electrical insulation properties. This ultrathin thermally conductive insulating layer allows for greater integration space in the heat dissipation module to accommodate TIMs with high thermal conductivity, and improves the heat dissipation performance and reliability of advanced semiconductor packaging structures such as 2.5D / 3D.

[0024] The advantages and spirit of this invention can be further understood through the following detailed description of the invention and the accompanying drawings. Attached Figure Description

[0025] Figure 1 This invention studies two AlN thin films fabricated using atomic layer deposition processes, and the relationship between the thermal conductivity per unit area and the thickness of the AlN thin film is shown in the figure.

[0026] Figure 2 This invention employs a plasma-activated precursor-enhanced atomic layer deposition (PAP-ALD) process to deposit high-resolution transmission electron microscopy (HRTEM) cross-sectional images and fast Fourier transform (FFT) patterns of boron nitride thin films on silicon substrates.

[0027] Figure 3 This is a cross-sectional schematic diagram of a heat dissipation module and its application environment and cooperating components according to a first specific embodiment of the present invention;

[0028] Figure 4 This is a cross-sectional schematic diagram of another application example of the heat dissipation module according to the first preferred embodiment of the present invention;

[0029] Figure 5 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to a second preferred embodiment of the present invention;

[0030] Figure 6 This is a modified cross-sectional schematic diagram of a semiconductor packaging structure according to a second preferred embodiment of the present invention;

[0031] Figure 7 This is a graph showing the relationship between the thermal conductivity per unit area and leakage current density of the alumina (Al2O3) thin film of the present invention and the film thickness; wherein the Al2O3 thin film is prepared using a plasma-enhanced atomic layer deposition (PEALD) process, and is further fabricated into MIS and MIM capacitor elements to measure their leakage current density.

[0032] Figure 8 This is a graph showing the relationship between the thermal conductivity per unit area and leakage current density of the aluminum nitride (AlN) thin film of the present invention and the film thickness; wherein the AlN thin film is prepared using a hydrogen-manipulated atomic layer deposition (HM-ALD) process, and further fabricated into MIS and MIM capacitor elements to measure their leakage current density.

[0033] Explanation of icon numbers:

[0034] 1: Heat dissipation module

[0035] 10: Heat dissipation elements

[0036] 10a: Radiator

[0037] 10b: Heat sink

[0038] 102: Pre-determined surface

[0039] 104: Bottom surface

[0040] 106: Outer surface

[0041] 12: Ultra-thin thermally conductive insulating layer

[0042] 20: Thermal interface materials

[0043] 22: Thermal interface materials

[0044] 24: Chip

[0045] 26: Bumps

[0046] 28: Circuit Board

[0047] 3: Silicon interposer

[0048] 30: Silicon Through-Hole

[0049] 302: Inner wall of the hole

[0050] 32: Conductive materials

[0051] 4: Semiconductor Packaging Structure

[0052] 40:Substrate

[0053] 402: Bump

[0054] 41: Intermediary layer

[0055] 410: Intermediate layer perforation

[0056] 4102: Inner wall of the hole

[0057] 42: Second ultra-thin thermally conductive insulating layer

[0058] 43: Metal plug

[0059] 44: First bump

[0060] 45: Small chip

[0061] 450: Second bump

[0062] 46: First ultra-thin thermally conductive insulating layer

[0063] 47: Small chip stacking

[0064] 470: Third bump Detailed Implementation

[0065] Please refer to the following detailed description and accompanying drawings of the invention. However, the drawings are for reference and illustration only and are not intended to limit the scope of the invention.

[0066] The core technical feature of the "heat dissipation module" and "2.5D / 3D advanced semiconductor packaging structure" proposed in this invention lies in the introduction of an "ultra-thin thermally conductive insulating layer." This functional layer is not a simple material replacement, but rather, through a specific advanced process—atomic layer deposition (ALD-based process)—it simultaneously possesses extremely low leakage current density and excellent thermal conductivity at the nanoscale. The physical principles and fabrication methods of this ultra-thin thermally conductive insulating layer will be explained first, followed by a detailed description of its specific implementation in heat dissipation modules and semiconductor packaging structures.

[0067] I. Physical principles and heat transfer mechanisms of ultrathin thermally conductive insulating layers:

[0068] 1. Regarding the relationship between heat conduction and interfacial thermal resistance:

[0069] When heat flows through the interface of different materials, the interfacial thermal resistance (R) int This will hinder heat transfer. int The larger the R value, the more difficult the heat transfer across the interface, which leads to a decrease in overall thermal conductivity. For nanoscale insulating films, its R... int It is one of the key factors governing heat transfer properties. The overall thermal conductivity (Gb) of a thin film is... total ) and overall thermal resistance (R) total The thermal conductivity (k) and interfacial thermal resistance (R) of a material are determined by its intrinsic thermal conductivity (k) and interfacial thermal resistance (R). int The two factors work together, and their combination determines the final heat transfer behavior:

[0070] Equation (1)

[0071] Where A is the cross-sectional area, R int1 With R int2 The interfacial thermal resistances R of interface 1 and interface 2 are respectively. film This represents the thermal resistance of the thin film itself. Based on the above analysis, it can be seen that as the film thickness d decreases, the thermal resistance (R) at the interface increases. int1 R int2 ) on the overall thermal resistance (R) of the thin film total The greater the contribution of R, the higher the value of R. total It is mainly controlled by the interfacial thermal resistance.

[0072] Please see Figure 1 , Figure 1This invention describes the fabrication of AlN thin films on sapphire substrates using two atomic layer deposition (ALD) processes. The relationship between the thermal conductivity per unit area and the AlN film thickness is shown in the graph. The thermal conductivity per unit area is obtained using time-domain thermal reflectance (TDTR). The inventors compared the thermal conductivity per unit area (G) of AlN films fabricated using a conventional ALD process (ALD AlN film) and an AlN film fabricated using an atomic layer annealing-enhanced atomic layer deposition (ALA AlN film). The ALA process involves in-situ He / Ar plasma treatment after each ALD cycle to anneal the atomic-level AlN. The results show that the crystallinity of the ALA AlN film is superior to that of the ALD AlN film. Figure 1 The results show that for conventional ALD AlN films, G decreases as the ALD AlN thickness (d) increases. However, when the film thickness is reduced to the nanometer scale (e.g., less than 10 nm), the thermal resistance of the film bulk (G) increases. The contribution of ) decreases significantly, and G increases rapidly as d decreases. At this point, the overall thermal resistance (R) of the thin film decreases. total It mainly consists of two interface thermal resistances (R) int1 R int2 This means that if interface quality can be effectively controlled and thickness minimized, extremely low total thermal resistance can be achieved. However, thin films formed using traditional chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes, when their thickness is reduced to the aforementioned nanoscale, often suffer from excessive porosity, grain boundaries, defects, and insufficient density, leading to a significant increase in leakage current and thus loss of insulation function. The key to this invention lies in employing an atomic layer deposition process to maintain extremely low leakage current (high insulation) at extremely thin thicknesses (e.g., 3 nm to 50 nm). Furthermore, high-efficiency thermal conductivity can also be achieved by improving crystal quality or orientation to reduce phonon scattering. It is worth noting that... Figure 1 The thermal conductivity per unit area of ​​both ALD AlN thin films and ALA AlN thin films is tens to hundreds of MW / m. 2 K level.

[0073] 2. Phonon ballistic transport:

[0074] For materials with a complete crystal structure, when the film thickness is less than the phonon mean free path, phonons can pass directly from one end of the film to the other end without scattering. This phenomenon is called ballistic transport.

[0075] Similarly, Figure 1 As shown, the aluminum nitride (ALA AlN) thin film prepared by atomic layer annealing-enhanced atomic layer deposition (ALA-ALD) technology in this invention exhibits excellent crystallinity. Its thermal conductivity per unit area tends to a constant value (Region III) after the thickness exceeds 10 nanometers, and does not decrease with increasing thickness, indicating the presence of acoustic ballistic transport behavior in the film. This phenomenon means that the film itself contributes very little to the total thermal resistance, thus possessing extremely high heat transfer efficiency. In contrast, ALD AlN films prepared using conventional ALD processes have poor crystallinity, resulting in a continuous decrease in thermal conductivity per unit area with increasing thickness. Therefore, controlling the insulating layer thickness to below 50 nanometers, particularly between 3 and 26 nanometers, and utilizing ALA technology to improve the crystallinity of the film, can effectively reduce its overall thermal resistance. It should be emphasized that for insulating films that simultaneously meet the requirements of product and packaging structures for overall thermal resistance and leakage current density, the thinner the film, the shorter the process time and the less raw materials consumed, which further contributes to product manufacturing efficiency and cost optimization.

[0076] 3. Vertical orientation of anisotropic thermally conductive materials:

[0077] Regarding boron nitride (BN) films, hexagonal boron nitride (h-BN) exhibits a graphene-like layered structure, and its thermal conductivity along the basal plane is significantly higher than that in the vertical direction. Please refer to [link / reference]. Figure 2 , Figure 2 This invention presents HRTEM cross-sectional images of boron nitride thin films deposited on silicon substrates using a plasma-activated precursor atomic layer deposition (PAP-ALD) process. Based on these images, patterns in the reciprocal lattice space obtained through Fast Fourier Transform (FFT) are also shown. Figure 2 .Depend on Figure 2 As can be seen, the present invention promotes the growth of the h-BN basal surface in a direction close to perpendicular to the substrate surface (i.e., the basal surface is nearly vertical) through the PAP-ALD process. This structure provides a vertical "highway" for heat transfer, solving the inherent disadvantage of two-dimensional materials in vertical heat dissipation.

[0078] II. Detailed Explanation of Atomic Layer Deposition (ALD-based) Process Technology:

[0079] It should be noted that, in some applications, insulating films manufactured using traditional ALD processes can indeed meet the requirements of product and packaging structures for thermal conductivity and leakage current density per unit area. However, in order to maintain high insulation performance and control the microstructure at extremely thin insulating layer thicknesses, this invention also employs a modified ALD process. These processes share the common feature of introducing additional energy sources (such as plasma or ultraviolet light irradiation) or special chemical steps to optimize film quality.

[0080] 1. Atomic layer annealing-assisted atomic layer deposition (ALA-ALD) process:

[0081] In the ALA-ALD process, after each or several cycles of ALD, an additional inert gas (such as argon or helium) plasma treatment step is introduced. High-energy particles in the plasma transfer energy to the newly deposited atomic layer, promoting the migration and rearrangement of surface atoms, thereby achieving high-quality crystal growth, and even epitaxial growth, at low temperatures (e.g., 300°C). A specific embodiment (using AlN thin films as an example): Step 1: Introduce a trimethylaluminum (TMA) precursor pulse; Step 2: Introduce argon purge; Step 3: Introduce a nitrogen / hydrogen mixed gas plasma (reactant plasma) as the reactant; Step 4: Introduce argon purge; Step 5: Introduce helium / argon plasma for in-situ atomic layer annealing (ALA). Experimental data confirm that the zirconia (ZrO2) thin films manufactured using the ALA-ALD process have a high leakage current density (J / L). g The ALA-ALD process significantly outperforms films manufactured using the traditional ALD process, reducing the electrical insulation properties by approximately two to three orders of magnitude, demonstrating that the ALA-ALD process can significantly improve the electrical insulation properties of films.

[0082] 2. Hydrogen-manipulated atomic layer deposition (HM-ALD) process:

[0083] The HM-ALD process introduces hydrogen plasma treatment at specific stages of the ALD cycle to modulate the chemical reaction pathway and improve the electrical properties of the thin film. It comprises two main modes:

[0084] (1) HAR mode (hydrogen after reactant): After the introduction of reactant (e.g., oxidant H2O) pulse and rinsing steps, hydrogen plasma treatment is introduced. This plasma treatment step provides additional energy to promote the increase of film density, similar to the effect of ALA.

[0085] (2) HAP mode (hydrogen after precursor): After introducing the precursor (such as tetrakis(dimethylamino)hafnium, TDMAHf) and rinsing, hydrogen plasma is introduced for treatment. The key to this step is to effectively remove the organic ligands of the precursor adsorbed on the surface and reduce the steric hindrance, thereby making the subsequent chemical reaction with the reactants more complete. Experimental data show that the leakage current density of hafnium oxide (HfO2) films prepared using the HAP mode can be as low as 1.17 × 10⁻⁶. -9 A / cm 2 Compared to films manufactured using traditional ALD processes, this reduces defects by approximately six orders of magnitude, and its interface defect density (D0) is significantly lower. it It also decreased significantly.

[0086] 3. Plasma-activated precursor atomic layer deposition (PAP-ALD) process:

[0087] The PAP-ALD process utilizes plasma to directly activate precursors, increasing their reactivity. The process flow is as follows (taking BN thin films as an example): Step 1: Precursor activation, simultaneously introducing a precursor pulse (such as Tris(dimethylamino)borane, TDMAB) and argon plasma, utilizing plasma energy to directly activate precursor molecules; Step 2: Argon rinsing; Step 3: Nitrogen plasma reacting with the surface; Step 4: Argon rinsing. The PAP-ALD process not only improves the deposition rate but also allows for control over the growth orientation of BN (such as the h-BN grown nearly perpendicular to the substrate surface mentioned above). Furthermore, the PAP-ALD process reduces dependence on specific highly reactive precursors.

[0088] Other applicable ALD improvement processes:

[0089] This invention also covers UV-enhanced ALD processes, which utilize UV ​​light to decompose precursors or promote reactions; plasma-enhanced atomic layer deposition (PEALD) processes, which utilize plasma to activate reactants to reduce deposition temperature; multiple-pulse ALD processes, which improve film deposition rate and quality and enhance coverage of high aspect ratio structures by applying precursor or reactant pulses multiple times in a single cycle; and exposure-mode ALD processes, which improve film deposition rate, uniformity, and quality, and further enhance coverage of high aspect ratio structures by extending the residence time of precursors or reactants in the reaction chamber.

[0090] Please see Figure 3 , Figure 3 A heat dissipation module 1 according to a first preferred embodiment of the present invention, its application environment, and cooperating elements are depicted in a cross-sectional schematic diagram.

[0091] like Figure 3 As shown, the heat dissipation module 1 according to a first preferred embodiment of the present invention includes a heat dissipation element 10 and an ultrathin thermally conductive insulating layer 12. The heat dissipation element 10 has a predetermined surface 102. The ultrathin thermally conductive insulating layer 12 is formed and covers the predetermined surface 102 of the heat dissipation element 10.

[0092] Specifically, the ultrathin thermally conductive insulating layer 12 is formed using an atomic layer deposition (ALD-based) process. The thickness of the ultrathin thermally conductive insulating layer 12 is equal to or less than 50 nanometers, and the leakage current density of the ultrathin thermally conductive insulating layer is equal to or less than... 10 -6 A / cm 2 .

[0093] In one specific embodiment, in Figure 3 In the example shown, the heat dissipation element 10 is a heat sink 10a or a heat spreader 10b. The predetermined surface 102 contacts the thermal interface material (20, 22), that is, the bottom surface 104 of the heat sink 10a and the outer surface 106 of the heat spreader 10b. Figure 3In this embodiment, the chip 24 has a plurality of bumps 26 and is electrically bonded to the circuit board 28 by the plurality of bumps 26. A heat sink 10b is disposed on the chip 24, and a thermal interface material 22 is filled between the heat sink 10b and the chip 24. A heat sink 10a is disposed on the heat sink 10b, and a thermal interface material 20 is filled between the heat sink 10a and the heat sink 10b. The ultrathin thermally conductive insulating layer 12 of the present invention provides electrical insulation between the heat sink 10a and the thermal interface material 20 and between the heat sink 10b and the thermal interface material 22, while maintaining good thermal conductivity. It should be emphasized that, through the ultrathin thermally conductive insulating layer 12 covering the bottom surface 104 of the heat sink 10a and the outer surface 106 of the heat sink 10b, the thermal interface material 20 and the thermal interface material 22 can be made of TIM with high thermal conductivity to improve the heat dissipation performance and reliability of the chip 24. In addition, the ultrathin thermally conductive insulating layer 12 of the present invention can also serve as a surface passivation layer for the wafer 24.

[0094] Please see Figure 4 , Figure 4 A cross-sectional schematic diagram of another application example of the heat dissipation module 1 according to the first preferred embodiment of the present invention.

[0095] like Figure 4 As shown, in another specific embodiment, the heat dissipation element 10 is a silicon interposer 3. The inner wall 302 of the silicon through-hole 30 in the silicon interposer 3 is predetermined on the surface 102. Generally, the silicon interposer 3 has a plurality of silicon through-holes 30. Figure 4 In the diagram, only one silicon through-hole 30 is shown as an example. The ultrathin thermally conductive insulating layer 12 serves as an insulating pad to isolate the conductive material 32 within the silicon through-hole 30 from the silicon interposer 3 and to provide a path for radial heat conduction.

[0096] In one specific embodiment, the atomic layer deposition process can be a conventional atomic layer deposition process, an atomic layer annealing enhanced atomic layer deposition (ALA-ALD) process, a hydrogen-manipulated atomic layer deposition (HM-ALD) process, a plasma activated precursor enhanced atomic layer deposition (PAP-ALD) process, a UV-enhanced atomic layer deposition (UV-enhanced ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a multiple-pulses atomic layer deposition (multiple-pulsesALD) process, an exposure-mode atomic layer deposition (exposure-mode ALD) process, or other atomic layer deposition processes.

[0097] In one specific embodiment, the ultrathin thermally conductive insulating layer 12 according to the present invention can be formed of a metal oxide. The metal oxide can be HfO2, ZrO2, or Hf... x Zr 1-xO2 (0≦x≦1), Ta2O3, Al2O3, Gd2O3, La2O3, SiO2, TiO2, Y2O3 or other metal oxides.

[0098] In another specific embodiment, the ultrathin thermally conductive insulating layer 12 according to the present invention can be formed of a metal nitride. The metal nitride can be AlN. x SiN x GeN x BN x Or other metal nitrides, wherein 0.5 ≤ x ≤ 1.5.

[0099] In one specific embodiment, the thickness of the ultrathin thermally conductive insulating layer 12 ranges from 3 nanometers to 50 nanometers. The thermal conductivity per unit area of ​​the ultrathin thermally conductive insulating layer 12 is equal to or greater than 50 MW / m. 2 ·K.

[0100] Please see Figure 5 , Figure 5 A cross-sectional schematic diagram of the semiconductor package structure 4 according to a second preferred embodiment of the present invention is shown. For example... Figure 5 As shown, the semiconductor package structure 4 according to a second preferred embodiment of the present invention includes a substrate 40, an interposer 41, a plurality of metal plugs 43, a plurality of first bumps 44, at least one small wafer 45, and a second ultrathin thermally conductive insulating layer 46. Figure 5 In the image, only a small chip 45 is shown as a representative.

[0101] Interposer 41 has a plurality of through-hole vias 410. Interposer 41 can be a silicon interposer or a glass interposer. When interposer 41 is a silicon interposer, the plurality of through-hole vias 410 are multiple silicon through-holes (TSVs). When interposer 41 is a glass interposer, the plurality of through-hole vias 410 are multiple glass through-holes (TGVs). Interposer 41 is disposed on substrate 40.

[0102] Each metal plug 43 corresponds to an interposer via 410 and is filled with its corresponding interposer via 410. Each first bump 44 corresponds to a metal plug 43 and is electrically bonded to its corresponding metal plug 43 and the substrate 40. At least one wafer 45 is disposed on the interposer 41. Each wafer 45 has a plurality of second bumps 450. Each second bump 450 corresponds to a metal plug 43 and is electrically bonded to its corresponding metal plug 43. A first ultrathin thermally conductive insulating layer 46 is formed covering the at least one wafer 45, the interposer 41, the plurality of first bumps 44, and the plurality of second bumps 450. The substrate 40 also has a plurality of bumps 402. The first ultrathin thermally conductive insulating layer 46 is formed by a second atomic layer deposition process. The first thickness of the first ultrathin thermally conductive insulating layer 46 is equal to or less than 50 nanometers, and the first leakage current density of the first ultrathin thermally conductive insulating layer 46 is equal to or less than 10 -6 A / cm 2 It must be emphasized that each small chip 45 was originally not covered with a surface passivation layer. The first ultrathin thermally conductive insulating layer 46 serves as the surface passivation layer for each small chip 45 and has excellent thermal conductivity. Furthermore, by using the first ultrathin thermally conductive insulating layer 46, which is applied to the surface of the small chip 45 and the outer surface of the interposer 41, a TIM with high thermal conductivity can be used to fill the gap between the small chip 45 and the interposer 41, thereby improving the heat dissipation performance and reliability of the small chip 45. Figure 5 The semiconductor package structure 4 shown can be regarded as a 2.5D semiconductor package structure.

[0103] When the interposer 41 is a silicon interposer and the plurality of interposer vias 410 are silicon vias, the semiconductor package structure 4 according to the second preferred embodiment of the present invention further includes a plurality of second ultrathin thermally conductive insulating layers 42. Each second ultrathin thermally conductive insulating layer 42 corresponds to one silicon via and is formed and coated on the respective inner wall 4102 of its corresponding silicon via. The plurality of second ultrathin thermally conductive insulating layers 42 are formed by a second atomic layer deposition (ALD-based) process. The second thickness of each second ultrathin thermally conductive insulating layer 42 is equal to or less than 50 nanometers, and the second leakage current density of each second ultrathin thermally conductive insulating layer 42 is equal to or less than 50 nanometers. 10 -6 A / cm 2 .

[0104] In one specific embodiment, the first atomic layer deposition (ALD) based process and the second atomic layer deposition (ALD) based process can be a conventional atomic layer deposition process, an atomic layer annealing enhanced atomic layer deposition (ALA-ALD) process, a hydrogen-manipulated atomic layer deposition (HM-ALD) process, a plasma activated precursor enhanced atomic layer deposition (PAP-ALD) process, a UV-enhanced atomic layer deposition (UV-enhanced ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a multiple-pulses atomic layer deposition (multiple-pulses ALD) process, an exposure-mode atomic layer deposition (exposure-mode ALD) process, or other atomic layer deposition based processes.

[0105] In one specific embodiment, the plurality of first ultrathin thermally conductive insulating layers 46 and second ultrathin thermally conductive insulating layers 42 can be formed of metal oxides or metal nitrides, respectively. The metal oxides can be HfO2, ZrO2, or Hf... 0.5 Zr 0.5 O2 (0≦x≦1), Ta2O3, Al2O3, Gd2O3, La2O3, SiO2, TiO2, Y2O3, or other metal oxides. Metal nitrides can be AlN. x SiN x GeN x BN x Or other metal nitrides, wherein 0.5 ≤ x ≤ 1.5.

[0106] Please see Figure 6 , Figure 6 A variation of the semiconductor package structure 4 according to a second preferred embodiment of the present invention is schematically depicted. For example... Figure 6 As shown, the semiconductor package structure 4 according to a second preferred embodiment of the present invention further includes a small die stack 47. The small die stack 47 is disposed on the interposer layer 41. The small die stack 47 has a plurality of third bumps 470. Each third bump 470 corresponds to a metal plug 43 and is electrically bonded to its corresponding metal plug 43. A first ultrathin thermally conductive insulating layer 46 is applied to the entire outer surface of the small die stack 47. It should be emphasized that the small die stack 47 was not originally covered with a surface passivation layer, and the first ultrathin thermally conductive insulating layer 46 serves as the surface passivation layer of the small die stack 47 and has excellent thermal conductivity. In addition, by applying the first ultrathin thermally conductive insulating layer 46 to the surface of the small die stack 47 and to the outer surface of the interposer layer 41, a TIM with high thermal conductivity can be further used to fill the gaps inside the small die stack 47 and the gaps between the small die stack 47 and the interposer layer 41, thereby improving the heat dissipation performance and reliability of the small die stack 47. Figure 6The semiconductor package structure 4 shown can be considered a 3D semiconductor package structure. The wafers in the wafer stack 47 can also be electrically bonded to the wafers of the upper and lower layers using silicon vias (not shown in the figure), metal plugs (not shown in the figure), and bumps.

[0107] The first, second, and third examples of this invention all fabricate an ultrathin thermally conductive insulating layer of hafnium oxide (HfO2) and further complete a metal-oxide-semiconductor (MOS) capacitor element. In these three examples, the total physical thickness of the HfO2 ultrathin insulating layer and its interfacial layer is approximately 5.3 nm. The MOS capacitor element is fabricated on a p-type (100) oriented silicon substrate with a resistivity of 1-10 Ω·cm. Its structure, from bottom to top, consists of an aluminum (Al) back electrode, a p-Si substrate, a hafnium oxide (HfO2) high-k dielectric layer, and a tungsten (W) top electrode. The precursor used in the first, second and third examples of the present invention is tetrakis(dimethylamino)hafnium (TDMAHf), and the reactant is water vapor (H2O). The deposition temperature of the HfO2 ultrathin thermally conductive insulating layer is set to 300°C.

[0108] The first example of this invention employs the HAR process of this invention, wherein the energy provided by hydrogen plasma can be transferred to the newly formed single-atom-layer HfO2 thin film, promoting the migration and rearrangement of surface atoms, achieving the effect of atomic-level annealing, and thereby improving the density and structure of the HfO2 thin film. In the first example of this invention, the plasma power of the hydrogen plasma treatment is equal to 50W, and the plasma application time is equal to 7.5 seconds.

[0109] The second example of this invention employs the HAP process of this invention. The key mechanism of this process is that, before introducing the H2O reactants, hydrogen plasma is used to effectively remove the organic ligands adsorbed on the surface of the TDMAHf molecules. Removing these ligands significantly reduces steric hindrance, allowing the subsequent H2O molecules to undergo a more complete chemical reaction with the Hf atoms, thereby forming a less defective and higher-quality HfO2 film. The third example employs the conventional ALD process.

[0110] The MOS capacitors containing an ultrathin HfO2 thermally conductive insulating layer manufactured in the first, second, and third examples of the present invention are all subjected to rapid thermal annealing at 450°C for 5 minutes in a forming gas environment containing 5% H2 / 95% N2, in order to complete post-metallization annealing (PMA).

[0111] The leakage current density-voltage measurement results of the MOS capacitor elements in the first, second, and third examples show that the leakage current density of the three types of elements can be obtained. Leakage current density (J / V) g It is then defined as the flatband voltage (V). FB -1 volt (V) FB The current density value measured at -1V. The leakage current density (J) of the device in the third example (using the conventional ALD process). g The value is 1.62 × 10 -3 A / cm 2 In comparison, the first-generation (HAR) and second-generation (HAP) elements treated with hydrogen plasma exhibit J... g They plummeted to 1.25 × 10⁻⁶. -9 A / cm 2 With 1.17×10 -9 A / cm 2 The reduction in leakage current exceeds six orders of magnitude, fully demonstrating the superior effectiveness of the method of the present invention in suppressing leakage current density. The results fully support the claim that the leakage current density of the ultrathin thermally conductive insulating layer manufactured according to the method of the present invention is equal to or less than 1. 10 -6 A / cm 2 It can even be lower than 2×10 -9 A / cm 2 The electrical parameters related to the three components are summarized in Table 1 below. Table 1 also lists the interfacial state density (D) of the three components. it Although the third paradigm uses a 5.33nm thick HfO2 ultrathin thermally conductive insulating layer manufactured using conventional ALD processes, its J g Up to 1.62×10 -3 A / cm 2 The required insulation properties were not met. However, by moderately increasing the thickness of the ultrathin thermally conductive insulating layer manufactured using the conventional ALD process and controlling this thickness to below 50 nm, its Jg can still meet the requirement of being equal to or less than that required by this invention. 10 -6 A / cm 2 The standards.

[0112] Table 1

[0113]

[0114] Table 1 lists the interface defect density (D). it The results show that, compared with the traditional ALD process, the interface defect density (DA) of the ultrathin thermally conductive insulating layer manufactured by the HAR and HAP processes according to the present invention is significantly higher. it (It is relatively small.)

[0115] To investigate the physical reasons for the significant reduction in leakage current, this invention utilizes X-ray reflectivity (XRR) measurement technology to analyze the density of the ultrathin thermally conductive insulating layer. By fitting the XRR spectrum, the film density can be accurately obtained. The density of the HfO2 ultrathin thermally conductive insulating layer manufactured using the conventional ALD process is 8.71 g / cm³. The density of the HfO2 ultrathin thermally conductive insulating layer manufactured using the HAR process increases to 9.16 g / cm³. The density of the HfO2 ultrathin thermally conductive insulating layer manufactured using the HAP process reaches the highest level of 9.44 g / cm³. 3 The significantly increased density of the ultrathin thermally conductive insulating layer means a denser atomic arrangement and fewer defects and voids, effectively blocking the path of leakage current. This result is highly correlated with leakage current measurements; that is, the HAP sample with the highest density corresponds to the lowest leakage current.

[0116] Both the fourth and fifth examples of this invention fabricate an ultrathin thermally conductive insulating layer of alumina (Al2O3) and further complete the fabrication of metal-insulator-semiconductor (MIS) and metal-oxide-metal (MIM) capacitor elements. The MIS capacitor element (fourth example) is fabricated on a p-type silicon substrate, and its structure, from bottom to top, consists of an aluminum (Al) back electrode, a p-Si substrate, an Al2O3 insulating layer, and a tungsten (W) top electrode. The MIM capacitor element (fifth example) has a structure, from bottom to top, consisting of a Si substrate, a titanium nitride (TiN) adhesive layer, a tungsten (W) bottom electrode, an Al2O3 insulating layer, and a tungsten (W) top electrode. The precursor used in both the fourth and fifth examples of this invention is trimethylaluminum (TMA), the reactant is oxygen plasma, and an Al2O3 thin film is prepared using a plasma-enhanced atomic layer deposition (PEALD) process, with the deposition temperature set at 300°C. Both MIS and MIM capacitors were subjected to rapid thermal annealing at 400°C for 5 minutes in a forming gas environment containing 5% H2 / 95% N2, followed by post-metallization annealing (PMA).

[0117] Please see Figure 7 , Figure 7 The graph shows the relationship between the unit area thermal conductivity and leakage current density of an ultrathin thermally conductive insulating layer of alumina (Al2O3) and the film thickness. The unit area thermal conductivity was obtained by time-resolved thermal reflectance (TDTR) measurement, which is derived from transient thermal transfer response analysis of Al2O3 films deposited on Si substrates. The leakage current density (J / m²) of MIS and MIM capacitor elements is also shown. g This represents the current density value measured when an applied voltage of -1V is applied. Figure 7 It can be seen that the thermal conductivity per unit area and leakage current density of Al2O3 thin films gradually decrease with increasing film thickness; when the thickness reaches about 10 nanometers, the thermal conductivity per unit area of ​​the ultrathin thermally conductive insulating layer of Al2O3 is greater than 50 MW / m. 2 ·K,J g Then around 10 -9 A / cm 2 This result is consistent with the leakage current density of the ultrathin insulating layer manufactured according to the method of the present invention being equal to or less than 1. 10 -6 A / cm 2 and thermal conductivity per unit area equal to or greater than 50 MW / m2 • The specification of K.

[0118] Both the sixth and seventh examples of this invention fabricate an ultrathin aluminum nitride (AlN) thermally conductive insulating layer and further complete the fabrication of MIS and MIM capacitor elements. The MIS capacitor element (sixth example) is fabricated on a p-type silicon substrate, and its structure, from bottom to top, consists of an aluminum (Al) back electrode, a p-Si substrate, an AlN insulating layer, and a tungsten (W) top electrode. The MIM capacitor element (seventh example) has a structure, from bottom to top, consisting of a Si substrate, a titanium nitride (TiN) adhesive layer, a tungsten (W) bottom electrode, an AlN insulating layer, and a tungsten (W) top electrode. The precursor used in the sixth and seventh examples of this invention is trimethylaluminum (TMA), the reactant is nitrogen plasma, and the AlN thin film is prepared using the HAR mode in a hydrogen-manipulated atomic layer deposition (HM-ALD) process. The deposition temperature of the thin film is set to 300°C. In both the sixth and seventh examples, neither the MIS nor the MIM capacitor element undergoes post-annealing treatment.

[0119] Please see Figure 8 , Figure 8 The graph shows the relationship between the thermal conductivity per unit area and leakage current density of an ultrathin aluminum nitride (AlN) thermally conductive insulating layer and the film thickness. The thermal conductivity per unit area was obtained by time-resolved thermal reflectance (TDTR) measurement, which is derived from transient thermal transfer response analysis of AlN films deposited on Si substrates. The leakage current density (J / m²) of MIS and MIM capacitor elements is also shown. g This represents the current density value measured when an applied voltage of -1V is applied. Figure 8 It is evident that the leakage current density of the AlN thin film decreases significantly with increasing film thickness. Furthermore, due to AlN's inherent excellent thermal conductivity, it maintains a high and stable thermal conductivity per unit area, approximately 80 MW / m²·K, across a thickness range of 4–12 nanometers, demonstrating excellent heat transfer capabilities even at the nanoscale. When the thickness reaches approximately 10 nanometers, the thermal conductivity per unit area of ​​the ultrathin AlN thermally conductive insulating layer exceeds 75 MW / m²·K. 2 ·K,J g Then around 10 -9 A / cm 2 This result is consistent with the leakage current density of the ultrathin insulating layer manufactured according to the method of the present invention being equal to or less than 1. 10 -6 A / cm 2 and thermal conductivity per unit area equal to or greater than 50 MW / m 2 • The specification of K.

[0120] Through the detailed description of the present invention above, it is clear that the present invention minimizes its thermal resistance by reducing the thickness of the insulating layer, thereby achieving excellent thermal conductivity. Simultaneously, a high-quality thin film is formed using an atomic layer deposition process to meet stringent electrical insulation requirements. This characteristic not only significantly increases the configuration space for using interface materials (TIMs) with high thermal conductivity in heat dissipation modules, but also further improves the heat dissipation performance and long-term reliability of advanced semiconductor packaging structures such as 2.5D / 3D.

[0121] The detailed description of the preferred embodiments above is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the invention to the preferred embodiments disclosed above. Rather, the aim is to cover various modifications and equivalent arrangements within the scope of the claims to be made. Therefore, the scope of the claims to be made should be interpreted in the broadest possible sense based on the foregoing description, so as to cover all possible modifications and equivalent arrangements.

Claims

1. A heat dissipation module, comprising: Heat dissipation element having a predetermined surface; and An ultrathin thermally conductive insulating layer is formed and coated on the predetermined surface of the heat dissipation element. The ultrathin thermally conductive insulating layer is formed using an atomic layer deposition process, and its thickness is equal to or less than 50 nanometers. Furthermore, the leakage current density of the ultrathin thermally conductive insulating layer is equal to or less than [missing information]. 10 -6 A / cm 2 .

2. The heat dissipation module according to claim 1, wherein the atomic layer deposition process is selected from the group consisting of conventional atomic layer deposition processes, atomic layer annealing enhanced atomic layer deposition processes, hydrogen-manipulated atomic layer deposition processes, plasma-activated precursor enhanced atomic layer deposition processes, ultraviolet light enhanced atomic layer deposition processes, plasma-enhanced atomic layer deposition processes, multi-pulse atomic layer deposition processes, and aeration mode atomic layer deposition processes.

3. The heat dissipation module according to claim 1, wherein the heat dissipation element heat sink or heat spreader, the predetermined surface of the contact surface that contacts the thermal interface material, and the ultra-thin thermally conductive insulating layer provides electrical insulation between the heat sink or heat spreader and the thermal interface material while maintaining the heat conduction path.

4. The heat dissipation module according to claim 1, wherein the heat dissipation element is a silicon interlayer, the predetermined surface is the inner wall of the silicon through-hole of the silicon interlayer, and the ultrathin thermally conductive insulating layer serves as an insulating pad to electrically isolate the conductive material within the silicon through-hole from the silicon interlayer and to provide a path for radial heat conduction.

5. The heat dissipation module according to claim 1, wherein the ultrathin thermally conductive insulating layer is formed of a metal oxide or a metal nitride, wherein the metal oxide is selected from HfO2, ZrO2, and Hf x Zr 1-x One of the group consisting of O2 (0≦x≦1), Ta2O3, Al2O3, Gd2O3, La2O3, SiO2, TiO2, and Y2O3, wherein the metal nitride is selected from AlN x SiN x GeN x and BN x One of the groups formed is 0.5≦x≦1.

5.

6. The heat dissipation module according to claim 1, wherein the thickness of the ultrathin thermally conductive insulating layer ranges from 3 nanometers to 50 nanometers, and the thermal conductivity per unit area of ​​the ultrathin thermally conductive insulating layer is equal to or greater than 50 MW / m². 2 ·K.

7. A semiconductor package structure comprising: substrate; An interposer has a plurality of interposer vias disposed on the substrate, wherein the interposer is a silicon interposer or a glass interposer, wherein when the interposer is a silicon interposer, the plurality of interposer vias are silicon vias, and when the interposer is a glass interposer, the plurality of interposer vias are glass vias. Multiple metal plugs, each metal plug corresponding to an interlayer perforation, and filling the corresponding interlayer perforation; Multiple first bumps, each first bump corresponding to a metal plug and electrically connected to its corresponding metal plug and the substrate; At least one small chip is disposed on the interposer layer, each small chip having a plurality of second bumps, each second bump corresponding to a metal plug and electrically engaging its corresponding metal plug; as well as A first ultrathin thermally conductive insulating layer is formed and coated on the at least one small wafer, the interposer, the plurality of first bumps, and the plurality of second bumps, wherein the first ultrathin thermally conductive insulating layer is formed by a first atomic layer deposition process, the first thickness of the first ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers, and the first leakage current density of the first ultrathin thermally conductive insulating layer is equal to or less than 10 -6 A / cm 2 .

8. The semiconductor package structure of claim 7, wherein when the interposer is the silicon interposer and the plurality of interposers are through the plurality of silicon vias, the semiconductor package structure further comprises: Multiple second ultrathin thermally conductive insulating layers, each corresponding to a silicon through-hole and formed to cover the respective inner wall of its corresponding silicon through-hole, wherein the multiple second ultrathin thermally conductive insulating layers are formed by a second atomic layer deposition process, the second thickness of each second ultrathin thermally conductive insulating layer is equal to or less than 50 nanometers, and the second leakage current density of each second ultrathin thermally conductive insulating layer is equal to or less than 10 -6 A / cm 2 .

9. The semiconductor packaging structure according to claim 8, wherein the first atomic layer deposition (ALD) process and the second ALD process are respectively selected from the group consisting of conventional ALD processes, ALD processes enhanced by atomic layer annealing, hydrogen-manipulated ALD processes, plasma-activated precursor-enhanced ALD processes, ultraviolet-enhanced ALD processes, plasma-enhanced ALD processes, multi-pulse ALD processes, and aeration-mode ALD processes, wherein the plurality of first ultrathin thermally conductive insulating layers and the second ultrathin thermally conductive insulating layers are respectively formed of metal oxides or metal nitrides, wherein the metal oxides are selected from HfO2, ZrO2, and Hf x Zr 1-x One of the group consisting of O2 (0≦x≦1), Ta2O3, Al2O3, Gd2O3, La2O3, SiO2, TiO2, and Y2O3, wherein the metal nitride is selected from AlN x SiN x GeN x And one of the groups consisting of BN, 0.5≦x≦1.

5.

10. The semiconductor packaging structure according to claim 7, further comprising: A small wafer stack is disposed on the interposer layer, the small wafer stack having a plurality of third bumps, each third bump corresponding to a metal plug and electrically engaging its corresponding metal plug, wherein the first ultrathin thermally conductive insulating layer covers the entire outer surface of the small wafer stack.

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