Packaging substrate and its manufacturing method

By setting a conductive reinforcement layer with a thickness greater than 30 micrometers in the packaging substrate, the warping problem of coreless packaging substrates during manufacturing and curing is solved, enhancing structural strength and electromagnetic compatibility, and improving process yield and signal transmission stability.

CN122138729APending Publication Date: 2026-06-02LEADING INTERCONNECT SEMICON TECH SHENZHEN CO LTD +1

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
LEADING INTERCONNECT SEMICON TECH SHENZHEN CO LTD
Filing Date
2024-11-29
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Coreless packaging substrates are prone to warping during manufacturing and curing, and the lack of rigid support from the core board leads to structural instability.

Method used

During the manufacturing process of the packaging substrate, a conductive reinforcement layer with a thickness greater than 30 micrometers is provided as a connection layer between the first substrate and the second substrate to disperse stress and prevent deformation caused by inconsistent material shrinkage.

Benefits of technology

It improves the structural strength and reliability of the packaging substrate, reduces warpage, increases process yield, and enhances electromagnetic compatibility and signal transmission stability.

✦ Generated by Eureka AI based on patent content.

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Abstract

This invention provides a method for manufacturing a packaging substrate, comprising the steps of: providing a separable carrier plate; disposing a first substrate on the separable carrier plate; disposing a conductive reinforcement layer on the first substrate, the thickness of the conductive reinforcement being greater than 30 micrometers to enhance the overall structural strength; disposing a second substrate on the conductive reinforcement; and removing the separable carrier plate to obtain the packaging substrate. The packaging substrate includes a first substrate, a second substrate, and a conductive reinforcement layer connecting the first substrate and the second substrate. Furthermore, this invention also provides a packaging substrate.
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Description

Technical Field

[0001] This invention relates to the field of packaging substrate manufacturing, and more particularly to a packaging substrate and its manufacturing method. Background Technology

[0002] The coreless packaging substrate removes the core board that serves as the core support layer and consists only of a multilayer board, in order to achieve higher wiring density, thinner package thickness and better high-frequency electrical performance.

[0003] However, coreless packaging substrates are prone to warping during manufacturing and curing due to the lack of a core plate for support. For example, during manufacturing and curing, when affected by process factors such as temperature changes and uneven pressure, the lack of rigid support from the core plate makes it impossible to maintain structural stability. Summary of the Invention

[0004] In view of this, it is necessary to provide a packaging substrate that can solve the above-mentioned technical problems.

[0005] In addition, it is necessary to provide a method for manufacturing a packaging substrate.

[0006] A method for manufacturing a packaging substrate includes the steps of: providing a separable carrier plate; disposing a first substrate on the separable carrier plate; disposing a conductive reinforcement layer on the first substrate, the thickness of the conductive reinforcement layer being greater than 30 micrometers to enhance the overall structural strength; disposing a second substrate on the conductive reinforcement layer; and removing the separable carrier plate to obtain the packaging substrate, wherein the packaging substrate includes the first substrate, the second substrate, and the conductive reinforcement layer connecting the first substrate and the second substrate.

[0007] In some possible implementations, the first substrate includes a first circuit layer, a second circuit layer, and a first insulating layer. The step of "depositing the first substrate on the separable carrier" includes: depositing a first photosensitive pattern on the separable carrier, the first photosensitive pattern having a plurality of first openings through it; electroplating to form the first circuit layer within the first openings; removing the first photosensitive pattern; depositing the first insulating layer on the first circuit layer; depositing a second photosensitive pattern on the first insulating layer, the second photosensitive pattern having a plurality of second openings; electroplating to form a second circuit layer within the second openings; and removing the second photosensitive pattern to obtain the first substrate.

[0008] In some possible implementations, the first substrate further includes a plurality of first interlayer conductors, and before the step of "setting a second photosensitive pattern on the first insulating layer", the substrate further includes: setting a first slot in the first insulating layer, a portion of the first circuit layer being exposed in the first slot, and the first slot communicating with the second opening.

[0009] The step "electroplated to form a second circuit layer in the second opening" further includes: electroplating to form a first interlayer conductor in the first slot, wherein the first interlayer conductor connects the first circuit layer and the second circuit layer.

[0010] In some possible implementations, the first substrate further includes a second insulating layer, and the step of "depositing the first substrate on the separable carrier" further includes: depositing the second insulating layer on the second circuit layer.

[0011] In some possible implementations, the step "depositing a conductive reinforcement layer on the first substrate" includes: depositing the conductive reinforcement layer on the second insulating layer, wherein the conductive reinforcement layer is provided with a plurality of voids through it.

[0012] In some possible implementations, the second substrate includes a third insulating layer and a third circuit layer. The step of "depositing the second substrate on the conductivity enhancement layer" includes: depositing the third insulating layer on the conductivity enhancement layer; filling a portion of the third insulating layer into the voids to form an insulating filler; the insulating filler connecting the third insulating layer and the second insulating layer; depositing a third photosensitive pattern on the second insulating layer; the third photosensitive pattern having a plurality of third openings; and exposing a portion of the second insulating layer at the bottom of the third openings; and electroplating the third openings to form the second circuit layer.

[0013] In some possible implementations, the second circuit further includes a second interlayer conductor. Prior to the step "forming a third photosensitive pattern on the third insulating layer," the step includes: forming a second slot in the insulating filler, the second slot penetrating a portion of the second insulating layer, with a portion of the second circuit layer exposed at the bottom of the second slot. The step "electroplated to form the third circuit layer in the third opening" further includes: electroplating the second interlayer conductor in the second slot.

[0014] In some possible implementations, the step of providing a solder resist layer on the side of the second substrate opposite to the first substrate is also included.

[0015] An encapsulation substrate includes a first substrate, a second substrate, and a conductive reinforcement layer. The second substrate is disposed at a distance from the first substrate. The conductive reinforcement layer is connected between the first substrate and the second substrate, and the thickness of the conductive reinforcement layer is greater than 30 micrometers.

[0016] In some possible implementations, the conductive reinforcement layer is provided with a void groove, and the second substrate includes an interlayer conductor that passes through the void groove to connect the first substrate.

[0017] The manufacturing method of the packaging substrate provided in this application involves setting a conductive reinforcement layer with a thickness greater than 30 micrometers between a first substrate and a second substrate. This conductive reinforcement layer plays a stress-balancing role similar to that of a core board in the packaging substrate, thereby strengthening the overall structural strength. Under complex process conditions such as temperature variations and uneven pressure, the conductive reinforcement layer can effectively disperse stress. For example, when localized excessively high temperatures or sudden pressure changes occur during manufacturing, the conductive reinforcement layer, due to its excellent material properties, can prevent excessive stress concentration within the laminate, prevent deformation caused by inconsistent material shrinkage, and reduce warpage. This not only improves process yield but also enhances the reliability of the packaging structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments / methods of the present invention, the drawings used in the description of the embodiments / methods will be briefly introduced below. Obviously, the drawings described below are some embodiments / methods of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a cross-sectional schematic diagram of the separable carrier plate provided in the first embodiment of this application.

[0020] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the detachable carrier plate after the dry film has been applied.

[0021] Figure 3 For exposure and development Figure 2 The diagram shows a cross-section of the dried film.

[0022] Figure 4 In order to be in Figure 3 The diagram shows a cross-sectional view of the first circuit layer on the separable carrier.

[0023] Figure 5 In order to be in Figure 4 The diagram shows a cross-sectional view of a second circuit layer installed on top of a first circuit layer.

[0024] Figure 6 In order to be in Figure 5 The diagram shows a cross-sectional view of a second insulating layer disposed on the second circuit layer.

[0025] Figure 7 In order to be in Figure 6 The diagram shows a cross-sectional view of the second insulating layer on which the first conductive reinforcement layer is disposed.

[0026] Figure 8 In order to be in Figure 7 The diagram shows a cross-sectional view of a third insulating layer disposed on a conductive reinforcement layer.

[0027] Figure 9 In order to be in Figure 8 The diagram shows a cross-sectional view of a third circuit layer disposed on a third insulating layer.

[0028] Figure 10 In order to be in Figure 9 The diagram shows a cross-sectional view of the third circuit layer with a solder mask layer.

[0029] Figure 11 This is a cross-sectional schematic diagram of the packaging substrate provided in the first embodiment of this application.

[0030] Figure 12 A cross-sectional schematic diagram of a second conductive reinforcement layer disposed on a second insulating layer, as provided in the second embodiment of this application.

[0031] Figure 13 In order to be in Figure 12 The diagram shows a cross-sectional view of a fourth insulating layer disposed on the second conductive reinforcement layer.

[0032] Figure 14 In order to be in Figure 13 The diagram shows a cross-sectional view of a fourth circuit layer disposed on the fourth insulating layer.

[0033] Figure 15 This is a cross-sectional schematic diagram of the packaging substrate provided in the second embodiment of this application.

[0034] Explanation of main component symbols

[0035] Separable carrier plate 10

[0036] Support layer 11

[0037] First copper layer 12

[0038] Second copper layer 13

[0039] Dry film 14

[0040] First photosensitive pattern 15

[0041] First opening 151

[0042] First Line Level 20

[0043] First cable tray 201

[0044] First insulating layer 21

[0045] First slot 211

[0046] Second line layer 22

[0047] Second cable tray 221

[0048] Interlayer conductor 23

[0049] Second insulating layer 24

[0050] First substrate 25

[0051] First conductive reinforcement layer 30

[0052] 31 Safeway

[0053] Third insulating layer 40

[0054] Insulating filler 41

[0055] Second slot 411

[0056] Third line layer 42

[0057] Second interlayer conductor 43

[0058] Second substrate 44

[0059] 50mm solder resist

[0060] Packaging substrates 100, 100'

[0061] Gap S

[0062] Second conductive reinforcement layer 33

[0063] Fourth insulating layer 45

[0064] Third interlayer conductor 242

[0065] Fourth interlayer conductor 46

[0066] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0067] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0068] Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. The described embodiments are only a part of, and not all, of the embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0070] Please see Figures 1 to 11 The first embodiment of this application provides a method for manufacturing a packaging substrate 100, including the following steps:

[0071] S1: Please see Figure 1 A separable carrier plate 10 is provided, the separable carrier plate 10 including a carrier layer 11, a first copper layer 12, and a second copper layer 13. The first copper layer 12 is disposed on one side of the carrier layer 11, and the second copper layer 13 is disposed on the side of the first copper layer 12 opposite to the carrier layer 11. The first copper layer 12 is detachably connected to the second copper layer 13.

[0072] In this embodiment, the material of the support layer 11 includes a glass fiber reinforced epoxy resin composite material. The thickness of the first copper layer 12 is 15-30 micrometers. The thickness of the second copper layer 13 is 5-10 micrometers. A pyrolytic adhesive is present between the first copper layer 12 and the second copper layer 13. At room temperature, the adhesive can firmly bond the first copper layer 12 and the second copper layer 13 together, ensuring the integrity and stability of the entire separable carrier plate 10. At high temperature, the adhesive undergoes a pyrolytic reaction, and its adhesive strength decreases rapidly, thereby allowing the first copper layer 12 and the second copper layer 13 to be easily separated.

[0073] In this embodiment, the separable carrier plate 10 has two oppositely arranged side surfaces, each of which is provided with a first copper layer 12 and a second copper layer 13.

[0074] S2: Please see Figure 2 A dry film 14 is disposed on the second copper layer 13. The dry film 14 is made of polyvinyl alcohol, polyester, and photoresist. Under ultraviolet light irradiation, the photosensitive component in the photoresist undergoes a chemical reaction. In the ultraviolet-irradiated areas, the chemical bonds between photoresist molecules break or cross-link, causing changes in the properties of the dry film 14 in these areas.

[0075] For positive photoresists, the resistance to photoresist in the illuminated area decreases, and it can be removed during the subsequent development process; while for negative photoresists, the illuminated area becomes more difficult to dissolve, forming a corresponding pattern protection area, providing an accurate photosensitive pattern for subsequent processing steps such as electroplating.

[0076] S3: Please see Figure 3The dry film 14 is exposed and developed to form the first photosensitive pattern 15. The first photosensitive pattern 15 is provided with a plurality of first openings 151, and a portion of the second copper layer 13 is exposed at the bottom of the first openings 151.

[0077] S4: Please see Figure 4 A first circuit layer 20 is formed by electroplating in the first opening 151, and the first photosensitive pattern 15 is removed, exposing the second copper layer 13. The first circuit layer 20 has a plurality of first grooves 201, with a portion of the second copper layer 13 exposed at the bottom of the first grooves 201.

[0078] S5: Please see Figure 5 A first insulating layer 21 is provided on the first circuit layer 20, and a portion of the first insulating layer 21 is filled into a plurality of the first wire grooves 201. The first insulating layer 21 is made of Ajinomoto Build-up Film (ABF).

[0079] In this embodiment, step S5 further includes:

[0080] S50: A first slot 211 is provided in the first insulating layer 21, and a portion of the first circuit layer 20 is exposed in the first slot 211.

[0081] S51: A second photosensitive pattern (not shown) is provided on the first insulating layer 21, and the second photosensitive pattern has a plurality of second openings (not shown). The first slot 211 connects to a portion of the second openings.

[0082] S52: A second circuit layer 22 is formed by electroplating in the second opening, and a first interlayer conductor 23 is formed by electroplating in the first groove 211.

[0083] S53: Remove the second photosensitive pattern, exposing the second circuit layer 22. The second circuit layer 22 has a plurality of second grooves 221. A portion of the first insulating layer 21 is exposed in the second grooves 221.

[0084] S54: Please see Figure 6 A second insulating layer 24 is disposed on the second circuit layer 22, and a portion of the second insulating layer 24 is filled into the second wire groove 221 to obtain the first substrate 25. The material of the second insulating layer 24 is the same as that of the first insulating layer 21.

[0085] The first substrate 25 includes a first circuit layer 20, a second circuit layer 22, a first insulating layer 21, a first interlayer conductor 23, and a second insulating layer 24. The first insulating layer 21 is disposed between the first circuit layer 20 and the second circuit layer 22. The second insulating layer 24 covers the second circuit layer 22. The first interlayer conductor 23 passes through the first insulating layer 21 and connects the first circuit layer 20 and the second circuit layer 22.

[0086] S6: Please see Figure 7 A first conductive reinforcement layer 30 is disposed on the second insulating layer 24, and a plurality of clearance grooves 31 are provided through the first conductive reinforcement layer 30, with a portion of the second insulating layer 24 exposed in the clearance grooves 31. The thickness of the first conductive reinforcement layer 30 is greater than 30 micrometers.

[0087] In this embodiment, the first conductive reinforcement layer 30 is made of copper. In other embodiments of this application, the first conductive reinforcement layer 30 is made of conductive metals such as aluminum and silver. These conductive metals can provide a certain degree of rigidity, which is beneficial to improving the structural stability of the packaging substrate 100.

[0088] S7: Please see Figure 8 A third insulating layer 40 is disposed on the first conductive reinforcement layer 30. A portion of the third insulating layer 40 is filled into the void groove 31 to form an insulating filler 41, which connects the third insulating layer 40 and the second insulating layer 24. The material of the third insulating layer 40 is the same as that of the second insulating layer 24.

[0089] S8: Please see Figure 9 A third photosensitive pattern (not shown) is provided on the third insulating layer 40. The third photosensitive pattern has multiple third openings (not shown), and a portion of the third insulating layer 40 is exposed at the bottom of the third openings.

[0090] In this embodiment, step S8 includes:

[0091] S80: A second slot 411 is provided in the insulating filler 41, such that a portion of the second circuit layer 22 is exposed at the bottom of the second slot 411.

[0092] S81: The third circuit layer 42 is formed by electroplating the third opening, and the second interlayer conductor 43 is formed by electroplating the second slot 411. The third photosensitive pattern is removed to obtain the second substrate 44.

[0093] In this embodiment, the second substrate 44 includes a third insulating layer 40, a third circuit layer 42, and a plurality of second interlayer conductors 43. The third circuit layer 42 is located on one side of the third insulating layer 40. One end of each second interlayer conductor 43 is connected to the third circuit layer 42, and the other end is connected to the second circuit layer 22. The second interlayer conductor 43 passes through the insulating filler 41 and the third insulating layer 40. That is, the second interlayer conductor 43 passes through the clearance groove 31.

[0094] In this embodiment, the cross-sectional width of the second interlayer conductor 43 is smaller than the cross-sectional width of the clearance groove 31, so that a gap S is formed between the second interlayer conductor 43 and the inner wall of the clearance groove 31, and part of the insulating filler 41 is located in the gap S.

[0095] S9: Please see Figure 10 A solder resist layer 50 is provided on the third circuit layer 42. The solder resist layer 50 is used to protect the third circuit layer 42.

[0096] In this embodiment, the material of the solder resist layer 50 includes one of epoxy resin, acrylic resin or polyimide.

[0097] S10: Please refer to Figure 11 Remove the separable carrier plate 10 to obtain the encapsulation substrate 100, wherein the encapsulation substrate 100 includes a first substrate 25, a second substrate 44, and a first conductive reinforcement layer 30 connecting the first substrate 25 and the second substrate 44.

[0098] In this embodiment, step S10 specifically includes:

[0099] S11: Cut the perimeter of the separable carrier board 10 and use a partition to embed it between the first copper layer 12 and the second copper layer 13, so that it can be separated smoothly.

[0100] S12: Using an etching process with copper sulfate as the etching solution, the second copper layer 13 is quickly etched to expose the first circuit layer 20.

[0101] Compared with the prior art, the manufacturing method of the packaging substrate 100 provided in this application has the following advantages:

[0102] (i) A first conductive reinforcement layer 30 with a thickness greater than 30 micrometers is disposed between the first substrate 25 and the second substrate 44. The first conductive reinforcement layer 30 plays a stress balancing role similar to that of a core board in the encapsulation substrate 100. Under complex process conditions such as temperature changes and uneven pressure, the first conductive reinforcement layer 30 can effectively disperse stress. For example, when local overheating or sudden pressure changes occur during the manufacturing process, the first conductive reinforcement layer 30, with its good material properties, can prevent excessive stress concentration in the laminate, prevent deformation caused by inconsistent material shrinkage, and reduce warping.

[0103] (ii) The first conductive reinforcement layer 30 can serve as part of electromagnetic shielding. The first conductive reinforcement layer 30 can reduce the impact of external electromagnetic interference on internal circuits or components by reflecting and absorbing electromagnetic radiation, while also preventing internal electromagnetic signals from leaking outward and ensuring electromagnetic compatibility. For example, in electronic equipment, it can protect sensitive components from interference from the external electromagnetic environment and ensure stable operation of the equipment.

[0104] (iii) By performing a series of fine and symmetrical process operations on both sides of the separable carrier plate 10, the amount and rate of excess copper material removed on both sides are kept consistent, which helps to control the residual copper rate of the first conductive reinforcement layer 30 on both sides of the separable carrier plate 10 to be the same, and reduces the problem of inconsistent physical properties of copper layers on both sides due to the difference in residual copper rate.

[0105] The first embodiment of this application also provides a packaging substrate 100, including a first substrate 25, a second substrate 44, and a first conductive reinforcement layer 30. The first substrate 25 and the second substrate 44 are disposed at a distance. The first conductive reinforcement layer 30 is connected between the first substrate 25 and the second substrate 44, and the thickness of the first conductive reinforcement layer 30 is greater than 30 micrometers.

[0106] During the chip packaging and curing process using the packaging substrate 100, the first conductive reinforcement layer 30 is made of copper. Copper can adapt to the differences in material shrinkage within the packaging substrate 100. The packaging substrate 100 can provide reverse support force when the laminate material shrinks, making the stress distribution of the entire packaging substrate 100 more uniform and reducing warping caused by the lack of core board support. This helps improve the flatness of the packaging substrate 100, ensures a good connection between the chip and the packaging substrate 100, reduces signal transmission errors, and improves packaging reliability and product lifespan.

[0107] In this embodiment, the first conductive enhancement layer 30 is provided with a void groove 31, and the second substrate 44 includes a second interlayer conductor 43, which passes through the void groove 31 to connect to the first substrate 25.

[0108] Please see Figures 12 to 15 The second embodiment of this application provides a method for manufacturing a packaging substrate 100', which differs from the first embodiment in that:

[0109] Step S6 includes:

[0110] S61: Please see Figure 12 A third slot 241 is provided through the second insulating layer 24, and a portion of the second circuit layer 22 is exposed at the bottom of the third slot 241.

[0111] S62: A fourth photosensitive pattern (not shown) is provided on the second insulating layer 24. The fourth photosensitive pattern has a plurality of fourth openings, some of which are connected to the third slot 241.

[0112] S63: A second conductive reinforcement layer 33 is electroplated within the plurality of fourth openings. Simultaneously, a third interlayer conductor 242 is electroplated within the third groove 241, the third interlayer conductor 242 connecting the second conductive reinforcement layer 33 and the second circuit layer 22. The fourth photosensitive pattern is then removed. The second conductive reinforcement layer 33 has a plurality of third grooves 321, with a portion of the second insulating layer 24 exposed at the bottom of the third grooves 321.

[0113] Step S7 includes:

[0114] S71: Please see Figure 13 A fourth insulating layer 45 is disposed on the second conductive reinforcement layer 33. A portion of the fourth insulating layer 45 is filled with a plurality of third grooves 321 and connected to the second insulating layer 24.

[0115] Step S8 also includes:

[0116] S82: Please see Figure 14 A plurality of fourth interlayer conductors 46 are provided on the fourth insulating layer 45, one end of the fourth interlayer conductor 46 is connected to the third circuit layer 42, and the other end is connected to the second conductive enhancement layer 33.

[0117] Compared to the first embodiment, the manufacturing method of the packaging substrate 100' provided in the second embodiment adds a third interlayer conductor 242 and a fourth interlayer conductor 46, making the connection between each layer more precise and stable, which helps to improve the stability of signal transmission.

[0118] Please see Figure 15The second embodiment of this application also provides a packaging substrate 100', which differs from the first embodiment in that the packaging substrate 100' includes a second conductive enhancement layer 33 and a third interlayer conductor 242. The second circuit layer 22 is electrically connected to the third circuit layer 42 through the third interlayer conductor 242, the second conductive enhancement layer 33, and the fourth interlayer conductor 46.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a packaging substrate, characterized in that, Including the following steps: Provide a separable carrier plate, A first substrate is disposed on the detachable carrier plate; A conductive enhancement layer is provided on the first substrate, and the thickness of the conductive enhancement layer is greater than 30 micrometers; The second substrate is disposed on the conductive enhancement, and Remove the separable carrier to obtain the packaging substrate, wherein the packaging substrate includes a first substrate and a second substrate with conductive enhancement connecting the first substrate and the second substrate.

2. The manufacturing method as described in claim 1, characterized in that, The first substrate includes a first circuit layer, a second circuit layer, and a first insulating layer. The step of "depositing the first substrate on the separable carrier" includes: A first photosensitive pattern is provided on the separable carrier plate, and the first photosensitive pattern is provided with a plurality of first openings through it; The first circuit layer is formed by electroplating inside the first opening; Remove the first photosensitive pattern; The first insulating layer is disposed on the first circuit layer; A second photosensitive pattern is provided on the first insulating layer, and the second photosensitive pattern has a plurality of second openings; A second circuit layer is formed by electroplating within the second opening; and Remove the second photosensitive pattern to obtain the first substrate.

3. The manufacturing method as described in claim 2, characterized in that, The first substrate further includes a plurality of first interlayer conductors, and the step of "setting a second photosensitive pattern on the first insulating layer" includes the following steps: A first slot is provided in the first insulating layer, and a portion of the first circuit layer is exposed in the first slot. The first slot is connected to the second opening. The step "electroplated to form a second circuit layer in the second opening" further includes: The first interlayer conductor is formed by electroplating in the first slot, and the first interlayer conductor connects the first circuit layer and the second circuit layer.

4. The manufacturing method as described in claim 2, characterized in that, The first substrate further includes a second insulating layer, and the step of "depositing the first substrate on the separable carrier plate" further includes: The second insulation layer is provided on the second circuit layer.

5. The manufacturing method as described in claim 4, characterized in that, The step "depositing a conductive enhancement layer on the first substrate" includes: The conductive reinforcement layer is disposed on the second insulating layer, and the conductive reinforcement layer is provided with a plurality of void-avoiding grooves.

6. The manufacturing method as described in claim 5, characterized in that, The second substrate includes a third insulating layer and a third circuit layer, and the step of "conforming the second substrate to the conductivity enhancement layer" includes: The third insulating layer is disposed on the conductive reinforcement layer, and a portion of the third insulating layer is filled into the void groove to form an insulating filler, the insulating filler connecting the third insulating layer and the second insulating layer; A third photosensitive pattern is formed on the third insulating layer, the third photosensitive pattern having a plurality of third openings, and a portion of the second insulating layer is exposed at the bottom of the third openings; The third circuit layer is formed by electroplating the third opening.

7. The manufacturing method as described in claim 6, characterized in that, The third circuit also includes a second interlayer conductor, and the step "setting a third photosensitive pattern on the third insulating layer" includes the following: A second slot is provided in the insulating filler, the second slot penetrates a portion of the second insulating layer, and a portion of the second circuit layer is exposed at the bottom of the second slot; The step "electroplated the third aperture to form the third circuit layer" further includes: The second interlayer conductor is formed by electroplating in the second slot.

8. The manufacturing method as described in claim 1, characterized in that, It also includes the following steps: A solder resist layer is provided on the side of the second substrate opposite to the first substrate.

9. A packaging substrate, characterized in that, include: First substrate; The second substrate is disposed at a distance from the first substrate; A conductive reinforcement layer is connected between the first substrate and the second substrate, and the thickness of the conductive reinforcement layer is greater than 30 micrometers.

10. The packaging substrate as described in claim 9, characterized in that, The conductive reinforcement layer is provided with a void groove, and the second substrate includes an interlayer conductor, which passes through the void groove to connect to the first substrate.