Power semiconductor package structure

Abstract

This invention provides a power semiconductor packaging structure, including: a substrate, multiple chips, a first terminal, and a connector clip. The multiple chips are respectively disposed on the substrate. The connector clip includes a main body, a aggregation portion, multiple connecting portions, and multiple radiating portions. The first terminal is connected to a first end of the main body, the aggregation portion is connected to a second end of the main body, the multiple radiating portions are electrically connected to the multiple chips one-to-one, and the multiple connecting portions correspond one-to-one with the multiple radiating portions. The multiple connecting portions extend from different positions on the circumferential sidewall of the aggregation portion in a direction away from the aggregation portion, and the end of each connecting portion away from the aggregation portion is connected to the corresponding radiating portion. By designing the connector clip to include an aggregation portion, multiple connecting portions, and multiple radiating portions, the path difference between each chip via the connector clip to the first terminal is very small, essentially the same, or even highly consistent, effectively balancing the current among the multiple chips and improving current sharing capability.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and more particularly to a power semiconductor packaging structure. Background Technology

[0002] In power semiconductor packaging structures, the package is typically used to house and protect chips with different functions made of different semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). These chips can be configured into various device types, such as microprocessors, discrete devices, amplifiers, controllers, and sensors. In power semiconductor packaging structures, the chip is mounted on a substrate, and the package typically uses electrically insulating encapsulating materials such as plastic, resin, or ceramic to seal and protect the chip from moisture and dust particles, and to connect the conductive terminals to the chip's pads and partially extend out of the package for external access.

[0003] Currently, commonly used power semiconductor packaging structures have increasingly higher power density requirements, and the current requirements that a single power semiconductor package structure can handle are also increasing. Since the current of a single chip is directly proportional to the chip area, taking SiC chips as an example, large-area chips have low yields. Therefore, it is necessary to increase the current capacity by increasing the number of chips within the power semiconductor package structure. Thus, current balance among multiple chips has become a problem that needs to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a power semiconductor packaging structure that can better balance the current among multiple chips and improve current sharing capability.

[0005] Specifically, an embodiment of the present invention provides a power semiconductor packaging structure, including, for example, a substrate, multiple chips, a first terminal, and a connector clip. The multiple chips are respectively disposed on the substrate. The connector clip includes a main body, a aggregation portion, multiple connecting portions, and multiple radiating portions. The first terminal is connected to a first end of the main body, the aggregation portion is connected to a second end of the main body opposite to the first end, the multiple radiating portions are electrically connected to the multiple chips in a one-to-one correspondence, and the multiple connecting portions correspond to the multiple radiating portions in a one-to-one correspondence. The multiple connecting portions extend from different positions on the circumferential sidewall of the aggregation portion in a direction away from the aggregation portion, and the end of each connecting portion away from the aggregation portion is connected to a corresponding radiating portion.

[0006] Furthermore, another power semiconductor packaging structure provided in this embodiment of the invention includes, for example, a substrate, a plurality of chips, a first terminal, a connecting clip, a second terminal, and a package body. The plurality of chips are respectively disposed on the substrate and electrically connected to the substrate. The connecting clip includes a main body, a polymerization portion, and a plurality of radial connectors. The first terminal is connected to a first end of the main body, the polymerization portion is connected to a second end of the main body opposite to the first end, and the plurality of radial connectors are spaced apart from each other circumferentially along the polymerization portion. Each radial connector corresponds one-to-one with one of the plurality of chips. One end of each radial connector is connected to a circumferential sidewall of the polymerization portion, and the other end of each radial connector extends toward and is electrically connected to the corresponding chip. The second terminal is electrically connected to the substrate. The package body encapsulates at least a portion of the substrate, the plurality of chips, a portion of the first terminal, the connecting clip, and a portion of the second terminal.

[0007] The above embodiments of the present invention can have the following beneficial effects: The power semiconductor packaging structure of the present invention designs the connector clip to include a polymerization part, multiple connecting parts and multiple radial parts, or designs it to include a polymerization part and multiple radial connectors, so that the path difference between each chip to the first terminal via the connector clip is very small or basically consistent or even highly consistent, thereby better balancing the current between multiple chips and improving the current sharing capability. Attached Figure Description

[0008] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0009] Figure 1 This is a three-dimensional structural diagram of a power semiconductor packaging structure provided in an embodiment of the present invention.

[0010] Figure 2 for Figure 1 The diagram shows a three-dimensional view of the power semiconductor packaging structure.

[0011] Figure 3 for Figure 1 The front view of the power semiconductor package structure shown.

[0012] Figure 4 for Figure 1 The left view of the power semiconductor package structure shown.

[0013] Figure 5 for Figure 1 The diagram shows a three-dimensional structure of the power semiconductor package after the package body has been removed.

[0014] Figure 6 for Figure 5 The top view of the structure shown.

[0015] Figure 7 for Figure 5 A partially enlarged schematic diagram of the connecting clip.

[0016] Figure 8 for Figure 1 The diagram shows another three-dimensional structure of the power semiconductor package after the package body is removed.

[0017] Figure 9 for Figure 8 The top view of the structure shown.

[0018] Figure 10 for Figure 8 A partial structural side view of the structure shown.

[0019] [Explanation of Key Figure Markings]

[0020] 11. Substrate; 110. Insulating layer; 112. Conductive layer; 112a. Power region; 112b. First driving region; 112c. Second driving region; 114. Heat dissipation layer; 114B. Surface of heat dissipation layer; 12. Package; 12B. Bottom surface of package; 121. Annular boss; 13a, 13b, 13c, 13d. Chip; 13T. Upper surface of chip; 13B. Lower surface of chip; 14. Resistor; 15. First terminal; 16. Connecting clip; 161. Main body; 163. Aggregation part; 165. Radial connector; 1651. Connecting part; 1653. Radial part; 167. Second bending part; 17. Second terminal; 18. Third terminal; 19. Fourth terminal; G. Third electrode pad; S. First electrode pad; K. Fourth electrode pad; BW. Metal bonding wire. Detailed Implementation

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0025] See Figures 1 to 7 This invention provides a power semiconductor packaging structure, which includes, for example, a substrate 11, a plurality of chips 13a-13d, a first terminal 15, and a connector 16. The plurality of chips 13a-13d are respectively disposed on the substrate 11. The connector 16 includes a main branch 161, a aggregation portion 163, and a plurality of radial connectors 165. The first terminal 15 is connected to a first end of the main branch 161, the aggregation portion 163 is connected to a second end of the main branch 161 opposite to the first end, and the plurality of radial connectors 165 are spaced apart from each other along the circumference of the aggregation portion 163. Each radial connector 165 corresponds one-to-one with one of the plurality of chips 13a-13d. One end of each radial connector 165 is connected to the circumferential sidewall of the aggregation portion 163, and the other end of each radial connector 165 extends toward and is electrically connected to the corresponding chip 13a (or 13b, 13c, or 13d). In this embodiment, the connector 16, by providing the aggregation part 163 and the plurality of radial connectors 165, ensures that the path difference between each chip 13a-13d via the connector 16 to the first terminal 15 is very small (e.g., path difference less than 5% or less than 4%), essentially the same (e.g., path difference less than 1%), or even highly consistent (e.g., path difference less than 0.1% or path difference of 0). This allows for better current balance among the multiple chips 13a-13d, improving current sharing capability. The aforementioned path can also be understood as a conductive path.

[0026] In some embodiments, the plurality of radial connectors 165 are circumferentially distributed; the difference between the distance from the portion of any radial connector 165 electrically connected to the corresponding chip 13a (or 13b or 13c or 13d) to the geometric center GC of the aggregation portion 163 and the distance from the portion of any other radial connector 165 electrically connected to the corresponding chip 13a (or 13b or 13c or 13d) to the geometric center GC of the aggregation portion 163 is less than 5%. This ensures that the paths of each chip 13a-13d to the first terminal 15 via the connector 16 differ by less than 5%, thereby further reducing current inconsistency between chips, better balancing the current among multiple chips 13a-13d, and further improving current sharing capability.

[0027] In some embodiments, see Figures 5 to 7 The plurality of radial connectors 165 are arranged in a circumferential pattern (e.g., Figure 6 (Indicated by the dashed circle); each of the radial connectors 165 is a straight line drawn along a direction away from the polymer 163 from the geometric center GC of the polymer portion 163 to the boundary point of the polymer portion 163 (e.g., Figure 6 Extending from the geometric center GC outwards along any one of the four dashed lines, the extension trajectory and extension length of each of the radial connectors 165 are, for example, identical. This ensures that the paths of each chip 13a-13d to the first terminal 15 via the connector 16 are highly consistent, thereby achieving better current sharing capability.

[0028] In some embodiments, see Figures 5 to 7 Each of the radial connectors 165 includes a connecting portion 1651 and a radial portion 1653, thereby the connector clip 16 has a plurality of connecting portions 1651 and a plurality of radial portions 1653. The plurality of radial portions 1653 are electrically connected to the plurality of chips 13a-13d in a one-to-one correspondence. The plurality of connecting portions 1651 correspond to the plurality of radial portions 1653 in a one-to-one correspondence. The plurality of connecting portions 1651 extend from different positions on the circumferential sidewall of the aggregation portion 163 in a direction away from the aggregation portion 163, and the end of each connecting portion 1651 away from the aggregation portion 163 is connected to a corresponding radial portion 1653. In this embodiment, the connector 16, by providing the aggregation part 163, the plurality of connecting parts 1651 and the plurality of radiating parts 1653, makes the path difference between each chip 13a-13d to the first terminal 15 via the connector 16 very small or basically the same or even highly consistent, thereby enabling better balance of current among multiple chips 13a-13d and improving current sharing capability.

[0029] In some embodiments, see Figures 5 to 7The aggregation portion 163 is spaced apart from each of the chips 13a-13d along a first direction A1, where the first direction A1 is from the substrate 11 to the chips 13a-13d. This effectively prevents the aggregation portion 163 from contacting the chips 13a-13d. For example, the connecting portion 1651 can be designed as a bent portion (e.g., ...). Figure 5 As shown, the aggregation portion 163 is spaced apart from each of the radiating portions 1653 in the first direction A1, thereby achieving the spaced-apart arrangement of the aggregation portion 163 with each of the chips 13a-13d in the first direction A1. It is understood that in some embodiments, the connecting portion 1651 is not a bent portion, but can be designed as a straight strip. In this case, the spaced-apart arrangement of the aggregation portion 163 with each of the chips 13a-13d in the first direction A1 can be achieved by using a connecting material between each radiating portion 1653 and the corresponding chip 13a-13d, or by increasing the thickness of each radiating portion 1653 in the first direction A1.

[0030] In some embodiments, see Figures 5 to 7 The difference between the distance d from each of the radial portions 1653 to the geometric center GC of the aggregation portion 163 and the distance d from any other radial portion 1653 to the geometric center GC of the aggregation portion 163 is less than 5%. In this way, the paths of each chip 13a-13d to the first terminal 15 via the connecting clip 16 can be within 5%, thereby further reducing the current inconsistency between chips, better balancing the current between each chip 13a-13d, and further improving the current sharing capability.

[0031] In some embodiments, the distance d from each of the radiating portions 1653 to the geometric center GC of the aggregation portion 163 is equal, thereby making the paths of each chip 13a-13d to the first terminal 15 via the connecting clip 16 highly consistent, thus achieving better current sharing capability.

[0032] In some embodiments, see Figure 6 The plurality of radiating portions 1653 are arranged in a circumferential pattern (e.g., Figure 6 (As shown by the dashed circle in the middle), each of the connecting portions 1651 is in a straight line direction drawn from the geometric center GC of the aggregation portion 163 to the boundary point of the aggregation portion (e.g., away from the aggregation portion 163). Figure 6 It extends along any one of the four dashed lines extending outward from the geometric center GC. In this way, the paths of each chip 13a-13d to the first terminal 15 via the connecting clip 16 are made highly consistent, thereby achieving better current sharing capability.

[0033] In some embodiments, see Figure 6 The aggregation portion 163 is a polygon, such as a square, and each of the connecting portions 1651 is along the direction away from the aggregation portion 163, which is the direction of the line connecting the geometric center GC of the aggregation portion 163 to the vertex of the polygon (e.g., Figure 6 It extends along any one of the four dashed lines extending outward from the geometric center GC. Alternatively, in some embodiments, the aggregation portion 163 is circular, and each of the connecting portions 1651 extends along the diameter direction of the aggregation portion 163 in a direction away from the aggregation portion 163. It is worth mentioning here that when the aggregation portion 163 is a polygon, it is not limited to a square, but can also be other regular polygons, such as a regular pentagon, a regular hexagon, etc. In this way, the path height of each chip 13a-13d to the first terminal 15 via the connecting clip 16 can be consistent, thereby obtaining better current sharing capability.

[0034] In some embodiments, see Figure 5 and Figure 6 The plurality of radiating parts 1653 are distributed on opposite sides of the main body 161.

[0035] In some embodiments, see Figure 5 and Figure 6 The number of chips 13a-13d, the connecting portion 1651, and the radiating portion 1653 are all even. The plurality of radiating portions 1653 are symmetrically distributed on opposite sides of the main stem 161, and the plurality of connecting portions 1651 are symmetrically distributed on opposite sides of the main stem 161. Each radiating portion 1653 is located on the side of the corresponding chip 13a (or 13b or 13c or 13d) away from the substrate 11 in the first direction A1, and the orthographic projection of each radiating portion 1653 on the substrate 11 is located within the orthographic projection of the corresponding chip 13a (or 13b or 13c or 13d) on the substrate 11. In this way, the path height of each chip 13a-13d to the first terminal 15 via the connecting clip 16 is consistent, thereby obtaining better current sharing capability.

[0036] In some embodiments, see Figure 5 and Figure 6The number of chips 13a-13d, connecting portions 1651, and radiating portions 1653 are all four. The four radiating portions 1653 are symmetrically distributed on opposite first and second sides of the main stem 161, and the four connecting portions 1651 are symmetrically distributed on the first and second sides of the main stem 161. One chip 13a located on the first side of the main stem 161 and one chip 13d located on the second side of the main stem 161 are symmetrical about the geometric center GC of the aggregation portion 163, and another chip 13b located on the first side of the main stem 161 and another chip 13c located on the second side of the main stem 161 are symmetrical about the geometric center GC of the aggregation portion 163. In this way, the paths of each chip 13a-13d to the first terminal 15 via the connecting clip 16 are highly consistent, thereby obtaining better current sharing capability.

[0037] In some embodiments, see Figure 5 and Figure 6 The first terminal 15 and the main body 161 are spaced apart in the first direction A1; the connecting clip 16 further includes a second bending portion 167, through which the first terminal 15 is connected to the first end of the main body 161; the main body 161 and the aggregation portion 163 are spaced apart in the first direction A1, that is, they are coplanar. For example, the first terminal 15 and the second bending portion 167 are connected together by welding or sintering using a connecting material. The connecting material can be a welding material, such as high-performance welding materials like SnSb5 or SAC305, which can be welded in the form of solder sheets or solder paste, with a thickness of, for example, 50-300 micrometers (μm); or, the connecting material can be a sintering material, such as Ag or Cu, which forms a high-performance connecting layer after sintering, with a thickness of, for example, 20-50 μm. In this embodiment, the first terminal 15 and the connecting clip 16 are designed as separate parts. The first terminal 15 and the connecting clip 16 can be manufactured separately first, and then the two can be combined together, which helps to improve the manufacturing flexibility of the first terminal 15 and the connecting clip 16.

[0038] In some embodiments, see Figure 8 and Figure 9 The connecting clip 16 is integrally formed with the first terminal 15. Designing the connecting clip 16 and the first terminal 15 as a single unit reduces material costs and process steps, thereby increasing product reliability.

[0039] In some embodiments, see Figures 1 to 10The power semiconductor package structure further includes a second terminal 17, a third terminal 18, and at least one resistor 14; the substrate 11 includes an insulating layer 110 and conductive layers 112 and heat dissipation layers 114 disposed on opposite sides of the insulating layer 110; the conductive layer 112 includes a power region 112a and a first driving region 112b spaced apart; the plurality of chips 13a-13d are respectively disposed on the side of the power region 112a away from the insulating layer 110; each chip 13a-13d has an upper surface 13T away from the conductive layer 112 and a lower surface 13B facing the conductive layer 112 (e.g., ...). Figure 10 As shown in the figure, each of the chips 13a-13d has a first electrode pad S and a third electrode pad G on its upper surface 13T, and a second electrode pad (not shown) on its lower surface 13B. The plurality of radial portions 1653 are electrically connected to each of the first electrode pads S of the plurality of chips 13a-13d, for example, by forming an electrical connection using a bonding material. The second electrode pads are electrically connected to the power region 112a, for example, by welding or sintering using a bonding material. The second terminal 17 is electrically connected to the power region 112a, for example, by welding or sintering using a bonding material. The at least one resistor 14 is disposed on the side of the first driving region 112b facing away from the insulating layer 110. The third terminal 18 is connected to the first driving region 112b via a metal bonding wire BW. The third electrode pad G of at least one chip is connected to the surface of the at least one resistor 14 facing away from the conductive layer 112 via a metal bonding wire BW. For example, taking a field-effect transistor as an example, the first electrode pad S is, for example, the source pad, the second electrode pad is, for example, the drain pad, and the third electrode pad G is, for example, the gate pad.

[0040] As described above, the conductive layer 112 can be made of metal materials such as Cu and Al, and serves as a conductive circuit, connecting chips 13a-13d, the first terminal 15, and the second terminal 17, etc.; the heat dissipation layer 114 can be made of metal materials such as Cu and Al, providing large-area heat dissipation. The insulating layer 110 can be made of various ceramic materials with high insulation, thermal conductivity, and mechanical strength, such as Al2O3, Si3N4, AlN, etc. The connecting material can be a welding material, such as high-performance welding materials like SnSb5 and SAC305, which can be welded in the form of solder sheets or solder paste, with a thickness of, for example, 50-300 micrometers (μm); or, the connecting material can be a sintered material, such as Ag or Cu, which forms a high-performance connecting layer after sintering, with a thickness of, for example, 20-50 μm.

[0041] Figure 5 and Figure 8Each chip shows four resistors 14 and four chips 13a-13d, with each third electrode pad G connected to one resistor 14. It is worth noting that in some embodiments, only some chips may have their third electrode pads G connected to the surface of the resistor 14 facing away from the conductive layer 112, while other chips may have their third electrode pads G connected, for example, to the surface of the first driving region 112b of the conductive layer 112, or even some chips may not have any third electrode pads G.

[0042] In some embodiments, the resistor 14 is, for example, a resistor with two electrodes on its upper and lower surfaces, exhibiting a fixed resistance value between the electrodes, such as 1-20 ohms (Ω), with dimensions of 0.5mm×0.5mm-2mm×2mm, and a thickness of 0.1-1mm. It is worth noting that in actual production, the inherent parameters between chips may differ. For example, the internal resistance of the chip may vary in gate parameters. In practical use, these parameter differences can lead to significant differences in the turn-on / turn-off characteristics of different chips within the same device, resulting in a bottleneck effect. Therefore, by adding resistor 14 to provide a resistance between the external device and chips 13a-13d, this difference can be reduced, and the current sharing effect between chips can be improved.

[0043] In some embodiments, see Figures 5 to 10 The conductive layer 112 further includes a second driving region 112c, and the first driving region 112b is located between the power region 112a and the second driving region 112c, and the first driving region 112b is spaced apart from the power region 112a and the second driving region 112c respectively; the power semiconductor package structure further includes a fourth terminal 19, the fourth terminal 19 is located between the first terminal 15 and the third terminal 18, and is connected to the second driving region 112c through a metal bonding wire BW; the upper surface 13T of each chip 13a-13d is also provided with a fourth electrode pad K (e.g., a Kelvin electrode pad), the fourth electrode pad K is connected to the second driving region 112c through a metal bonding wire BW; the first driving region 112b is, for example, elongated, and a recess 1120 is formed in the middle portion of the side away from the power region 112a (see Figure 6 The second driving region 112c is, for example, elongated, and a protrusion 1122 is formed in the middle portion of the side facing the first driving region 112b (see...). Figure 6It is understood that in other embodiments, the first driving region 112b may have a protrusion 1122 and the second driving region 112c may have a recess 1120. The protrusion-recessed fit between the second driving region 112c and the first driving region 112b helps the power region 112a to obtain a larger whole area, thereby allowing multiple chips 13a-13d to be placed in parallel for current flow, improving the device current rating.

[0044] In some embodiments, see Figures 1 to 10 The power semiconductor package structure further includes a package body 12, which encapsulates the conductive layer 112 and the insulating layer 110 of the substrate 11, the plurality of chips 13a-13d, a portion of the first terminal 15, the connecting clip 16, a portion of the second terminal 17, a portion of the third terminal 18, and the resistor 14. The bottom surface 12B of the package body 12 has an annular boss 121 (see...). Figures 2 to 4 The annular protrusion 121 exposes at least a portion of the surface 114B of the heat dissipation layer 114 that faces away from the insulating layer 110. The height of the annular protrusion 121 relative to the bottom surface 12B in the first direction A1 is, for example, greater than or equal to 0.2 mm, such as 0.2 mm, 0.5 mm, or 1 mm, preferably 0.2-0.5 mm. In this embodiment, by configuring the annular protrusion 121 at the bottom of the package 12, the annular protrusion 121 provides, on the one hand, a connection interface between the heat dissipation surface of the power semiconductor package structure (i.e., the portion of the surface 114B of the heat dissipation layer 114 exposed outside the package 12) and the heat sink (not shown). On the other hand, the raised distance also provides a greater creepage distance, thereby increasing the device's insulation capability under high voltage conditions. Furthermore, it is worth mentioning that the package 12 can, on the one hand, protect the internal chips 13a-13d and the substrate 11, and on the other hand, serve as a seal to prevent external moisture, dust, corrosive gases, etc., from entering the interior, increasing device reliability. Additionally, it can increase the insulation distance, thereby increasing device reliability. During the formation of the package 12, a pre-designed mold is used, for example, to... Figure 5 or Figure 8 After the structure shown is placed, the encapsulation material, such as plastic sealant, is melted and injected into the mold by injection molding. The molten plastic sealant will fill the gap between the mold and the structure to be encapsulated. After cooling, the plastic sealant hardens and solidifies, and finally, it is demolded.

[0045] In some embodiments, each of the chips 13a-13d may be a chip with different functions made of semiconductor materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), such as metal oxide semiconductor field-effect transistor (MOSFET), insulated gate bipolar transistor (IGBT), Schottky barrier diode (SBD), fast recovery diode (FRD), etc., but the embodiments of the present invention are not limited thereto.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A power semiconductor packaging structure, characterized in that, include: substrate; Multiple chips are respectively disposed on the substrate; First terminal; The connector includes: a main body, a aggregation part, multiple connecting parts, and multiple radiating parts. A first terminal is connected to a first end of the main body, the aggregation part is connected to a second end of the main body opposite to the first end, the multiple radiating parts are electrically connected to the multiple chips one-to-one, the multiple connecting parts correspond to the multiple radiating parts one-to-one, the multiple connecting parts extend from different positions on the circumferential sidewall of the aggregation part in a direction away from the aggregation part, and the end of each connecting part away from the aggregation part is connected to a corresponding radiating part.

2. The power semiconductor packaging structure according to claim 1, characterized in that, The difference between the distance from each of the radiating parts to the geometric center of the aggregation part and the distance from any other radiating part to the geometric center of the aggregation part is less than 5%.

3. The power semiconductor packaging structure according to claim 2, characterized in that, The distance from each of the radiating parts to the geometric center of the converging part is equal.

4. The power semiconductor packaging structure according to claim 2, characterized in that, The plurality of radial portions are arranged in a circular pattern, and each of the connecting portions extends along a straight line from the geometric center of the aggregation portion to the boundary point of the aggregation portion in a direction away from the aggregation portion.

5. The power semiconductor packaging structure according to claim 4, characterized in that, The aggregation portion is circular, and each of the connecting portions extends along the diameter direction of the aggregation portion in a direction away from the aggregation portion; or The aggregate portion is a polygon, and each of the connecting portions extends along the line connecting the geometric center of the aggregate portion and the vertex of the polygon in a direction away from the aggregate portion.

6. The power semiconductor packaging structure according to claim 2, characterized in that, The multiple radiating portions are distributed on opposite sides of the main stem.

7. The power semiconductor packaging structure according to claim 6, characterized in that, The number of chips, connectors, and radiating parts is even. The plurality of radiating parts are symmetrically distributed on opposite sides of the main body, and the plurality of connectors are symmetrically distributed on opposite sides of the main body. Each of the radiating portions is located on the side of the corresponding chip away from the substrate in a first direction, and the orthographic projection of each of the radiating portions on the substrate is located within the orthographic projection of the corresponding chip on the substrate, wherein the first direction is from the substrate to the chip.

8. The power semiconductor packaging structure according to claim 7, characterized in that, The number of the chip, the connection part, and the radiation part are all four; The four radial portions are symmetrically distributed on opposite first and second sides of the main body, and the four connecting portions are symmetrically distributed on the first and second sides of the main body; One of the chips located on the first side of the main stem and one of the chips located on the second side of the main stem are symmetrical about the geometric center of the aggregation part, and the other chip located on the first side of the main stem and the other chip located on the second side of the main stem are symmetrical about the geometric center of the aggregation part.

9. The power semiconductor packaging structure according to claim 1, characterized in that, The connecting clip is integrally formed with the first terminal.

10. The power semiconductor packaging structure according to claim 1, characterized in that, The power semiconductor package structure includes a second terminal, a third terminal, and at least one resistor; The substrate includes an insulating layer and conductive and heat dissipation layers disposed on opposite sides of the insulating layer. The conductive layer includes a power region and a first driving region spaced apart. The plurality of chips are respectively disposed on the side of the power region away from the insulating layer. Each chip has an upper surface away from the conductive layer and a lower surface facing the conductive layer. The upper surface of each chip is provided with a first electrode pad and a third electrode pad, and the lower surface of each chip is provided with a second electrode pad. The plurality of radial portions are electrically connected to each of the first electrode pads of the plurality of chips in a one-to-one correspondence. The second electrode pads are electrically connected to the power region by welding or sintering through a connecting material. The second terminal is electrically connected to the power region by welding or sintering through a connecting material. The at least one resistor is disposed on the side of the first driving region away from the insulating layer. The third terminal is connected to the first driving region through a metal bonding wire. The third electrode pads of at least one chip are connected to the surface of the at least one resistor away from the conductive layer in a one-to-one correspondence through metal bonding wires.

11. The power semiconductor packaging structure according to claim 10, characterized in that, The dimensions of a single resistor are 0.5mm×0.5mm-2mm×2mm, the thickness is 0.1mm-1mm, and the resistance is 1Ω-20Ω.

12. The power semiconductor packaging structure according to claim 10, characterized in that, The conductive layer further includes a second driving region, the first driving region is located between the power region and the second driving region, and the first driving region is spaced apart from the power region and the second driving region respectively; The power semiconductor package structure further includes a fourth terminal, which is located between the first terminal and the third terminal and is connected to the second driving region via a metal bonding wire; the upper surface of each chip is also provided with a fourth electrode pad, which is connected to the second driving region via a metal bonding wire; The first driving region is elongated and has one of a depression and a protrusion formed in the middle portion of the side facing away from the power region. The second driving region is elongated and has the other of a depression and a protrusion formed in the middle portion of the side facing the first driving region.

13. The power semiconductor packaging structure according to claim 10, characterized in that, The power semiconductor package structure further includes a package body that encapsulates the conductive layer and the insulating layer of the substrate, the plurality of chips, a portion of the first terminal, the connector clip, a portion of the second terminal, a portion of the third terminal, and the at least one resistor. The bottom surface of the package body has an annular protrusion that exposes at least a portion of the surface of the heat dissipation layer facing away from the insulating layer.

14. The power semiconductor packaging structure according to any one of claims 1 to 13, characterized in that, Each of the connecting portions is a bent portion, and the aggregation portion and each of the radiating portions are spaced apart in a first direction, the first direction being the direction from the substrate to the chip.

15. A power semiconductor packaging structure, characterized in that, include: substrate; Multiple chips are respectively disposed on the substrate and electrically connected to the substrate; First terminal; The connector includes: a main body, a aggregation part, and a plurality of radial connectors. A first terminal is connected to a first end of the main body, and the aggregation part is connected to a second end of the main body opposite to the first end. The plurality of radial connectors are spaced apart from each other along the circumference of the aggregation part. Each radial connector corresponds to a plurality of chips. One end of each radial connector is connected to the circumferential sidewall of the aggregation part, and the other end of each radial connector extends toward and is electrically connected to the corresponding chip. The second terminal is electrically connected to the substrate; and The package encapsulates at least a portion of the substrate, the plurality of chips, a portion of the first terminal, the connector clip, and a portion of the second terminal.

16. The power semiconductor packaging structure according to claim 15, characterized in that, The polymerization portion is spaced apart from each of the chips in a first direction from the substrate to the chip; And / or, The plurality of radial connectors are arranged in a circular pattern, and each radial connector extends along a straight line from the geometric center of the polymer to the boundary point of the polymer in a direction away from the polymer. The extension trajectory and extension length of each radial connector are the same.

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