Deep trench for stealth dicing on a microelectromechanical system wafer

Abstract

The present disclosure relates to deep trenches on a microelectromechanical system wafer for stealth dicing. A die includes a substrate; an insulating layer disposed on the substrate; a device layer disposed on the insulating layer, a microelectromechanical system (MEMS) device is defined within the device layer, the MEMS device having an opening into one or more internal cavities; a shelf surrounding an exterior of the die, the shelf defining a change in cross-sectional width of the die; and a weakened structure region disposed below the shelf and proximate to the exterior of the die. The shelf is disposed at a predefined depth of the die such that the shelf is disposed at the device layer, at the insulating layer, or at the substrate.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 696,955, filed September 20, 2024, entitled "Deep Trenches on Microelectromechanical System Wafers for Stealth Dicing". The disclosure of that prior art application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to optical microelectromechanical systems (MEMS) dies and methods for manufacturing optical MEMS dies. Background Technology

[0004] Monolithization is a semiconductor manufacturing process in which a wafer containing many individual circuits or dies is divided into individual units for use in electronic devices. Each individual unit can correspond to a specific die. The goal of monolithization is to precisely separate the dies while minimizing damage to each die. Given the required precision, monolithization is carefully controlled to avoid damage or contamination, which could affect device performance. Summary of the Invention

[0005] In some implementations, a die includes: a substrate; an insulating layer disposed on the substrate; a device layer disposed on the insulating layer, wherein a microelectromechanical system (MEMS) device is defined within the device layer, the MEMS device having an opening into one or more cavities; a shelf disposed around the exterior of the die, wherein the shelf defines a variation in the cross-sectional width of the die, and wherein the shelf is disposed at a predefined depth of the die, at the device layer, at the insulating layer, or at the substrate; and a weakened structural region disposed below the shelf and close to the exterior of the die.

[0006] In some implementations, a wafer includes: a substrate; an insulating layer disposed on the substrate; a plurality of device layers disposed on the insulating layer, the plurality of device layers including an upper device layer; a trench extending from the upper device layer into the wafer and defining a die assembly in the wafer, the trench having a trench bottom; and a region disposed below the trench bottom, the region including an alignment structure weakening portion, wherein each die in the die assembly has an optical MEMS surface in the upper device layer and one or more cavities below the optical MEMS surface.

[0007] In some implementations, a method of fabricating multiple optical MEMS dies includes: forming an unreleased wafer assembly comprising a wafer substrate, an insulating layer formed on the wafer substrate, and multiple device layers formed on the insulating layer, wherein the multiple device layers include an upper device layer and one or more cavities, wherein the one or more cavities house particle-sensitive MEMS actuation structures, and wherein the upper device layer of the multiple device layers is sealed such that the one or more cavities are closed; after forming the unreleased wafer assembly and before opening the one or more cavities, [the method involves] tracing along the defining optical MEMS dies within the unreleased wafer assembly. The monolithic channels of the chip form deep trenches, wherein each deep trench extends at least partially into the depth of multiple device layers from the upper device layer; after forming the deep trenches, one or more cavities of the unreleased wafer assembly are opened by unsealing the upper device layer to form multiple optical MEMS devices in the multiple device layers to form a released wafer assembly; after forming the released wafer assembly, one or more laser beams are emitted into the wafer substrate to generate defect regions within the monolithic channels of the wafer substrate; and after emitting one or more laser beams, the released wafer assembly is separated into multiple optical MEMS dies through the defect regions in the wafer substrate. Attached Figure Description

[0008] Figures 1A-1F This is a diagram illustrating an example of a method for manufacturing multiple optical MEMS dies.

[0009] Figure 2 A cross-section of an optical MEMS die according to one or more implementations is shown.

[0010] Figure 3 This is a flowchart of an example process associated with forming deep trenches on a microelectromechanical system (MEMS) wafer for stealth dicing. Detailed Implementation

[0011] The following example implementation is described in detail with reference to the accompanying drawings. The same reference numerals in different drawings can identify the same or similar elements.

[0012] Semiconductor fabrication technology can be used to manufacture MEMS dies. Multiple MEMS dies can be formed on a wafer and then monolithically processed into individual MEMS dies. A MEMS die may include one or more MEMS devices whose internal MEMS device structures are sensitive to particles (such as microparticles) and contaminants. For example, an optical MEMS die may include one or more optical MEMS devices, such as one or more MEMS mirror devices. Each MEMS mirror device may include an optical structure (e.g., including a reflective layer or mirror) configured to rotate or pivot about one or more axes, and an actuation structure configured to actuate the movement of the optical structure about one or more axes. The operation of each actuation structure is extremely sensitive to particles and contaminants, which can cause errors in the actuation of the optical structure and / or errors in the rotational position of the optical structure about one or more axes. Therefore, exposing the internal MEMS device structure to particles and contaminants during manufacturing can negatively impact the yield of many MEMS dies produced. Therefore, protecting the internal MEMS device structure from particles and contaminants during manufacturing is crucial.

[0013] Traditional cutting techniques (such as saw-based cutting, scribing and fracturing, etching (e.g., deep reactive ion etching), and laser ablation) can be used for monolithic (e.g., separation) of MEMS dies. However, these techniques generate a large number of particles that can deposit on or near one or more surfaces of the MEMS die. These particles can also enter one or more cavities within the MEMS die and may interfere with internal MEMS device structures, such as actuation structures used to actuate the movement of optical structures around one or more axes. This is particularly problematic when the entry point of the MEMS die's cavity is close to the monolithic channel. For example, non-conductive particles or contaminants that are close to or larger than the internal MEMS device structure can severely impact MEMS functionality and performance compared to non-conductive particles or contaminants smaller than the internal MEMS device structure. Conductive particles or contaminants are more detrimental to MEMS functionality and performance than non-conductive particles or contaminants. Since most MEMS fine structures are in the micrometer or submicrometer range, it is essential to prevent submicrometer or smaller particles or contaminants from entering the internal cavity. Inside the cavity, particles or contaminants may come into contact with the internal MEMS device structure and negatively impact the operation of the MEMS device.

[0014] Stealth dicing has been used in the semiconductor industry to monolithize individual chips from wafer assemblies typically made of materials such as silicon. Stealth dicing uses a laser to create internal modifications within the wafer assembly along a monolithization channel without cutting through the wafer assembly. These internal modifications form weakened structural regions. In other words, stealth dicing uses a laser to create a modification layer beneath the surface of the wafer assembly along a monolithization channel. This modification layer can include weakened structural regions. After the laser process creates the internal modifications, the wafer assembly undergoes a mechanical separation process, which can include using a band expander, stretching the strip attached to the wafer assembly, etc. During the mechanical separation process, the wafer assembly is stretched or stressed, causing microcracks to propagate along the monolithization channel through or near the modification layer or weakened structural regions and slit the wafer assembly, resulting in the separation of individual dies.

[0015] While stealth dicing does not generate particles or other contaminants during internal modification, the mechanical separation of the die in the later stages of the stealth dicing process does generate particles, increasing the risk of particle contamination in the internal MEMS device structure. Although the amount of particle contamination generated by stealth dicing is far lower than that of conventional dicing techniques (e.g., saw-based cutting, scribing and fracture, etching, deep reactive ion etching, or laser ablation), particle count remains a significant issue for high-particle-sensitivity MEMS dies. For example, the yield of MEMS dies manufactured using semiconductor processes is extremely sensitive to conductive particles that can be generated during the mechanical separation process of the low-resistivity top device layer of the wafer assembly.

[0016] Manufacturing techniques that reduce the amount of particles generated during monolithization (e.g., wafer separation particles) can lower the likelihood of particle contamination. Furthermore, manufacturing techniques that protect the internal MEMS device structure from particle exposure can also reduce the likelihood of particle contamination. Therefore, there is a need for manufacturing techniques capable of reducing the amount of particles generated during monolithization, particularly conductive particles from the low-resistivity top device layer, and / or better protecting the internal MEMS device structure from particle contamination.

[0017] Some implementations disclosed herein relate to dies, wafers, and fabrication techniques for reducing the amount of particles on or within a MEMS device in a die or wafer. For example, some implementations relate to a die comprising a substrate, an insulating layer disposed on the substrate, and one or more device layers disposed on the insulating layer. The die includes a MEMS device, such as an optical MEMS device, defined within one or more device layers. The MEMS device includes openings into one or more cavities defined by the device layers. Furthermore, the MEMS device includes internal MEMS device structures, such as actuation structures or other electrically driven mechanisms, disposed within one or more cavities that are sensitive to particle contamination. One or more cavities may be particle-free. Therefore, the MEMS device can be particle-free, which improves the operation of the MEMS device. The die can be fabricated using a manufacturing process described elsewhere herein that prevents particles from entering one or more cavities.

[0018] The die also includes shelves extending outwards around the die. The shelves define variations in the cross-sectional width of the die. For example, above the shelves, the die may have a first cross-sectional width, while below the shelves, the die may have a second cross-sectional width greater than the first cross-sectional width. The shelves are arranged at a predefined depth of the die, defined by an extension from the top surface of the die (e.g., the top surface of one or more device layers) toward the bottom surface of the die (e.g., the bottom surface of a substrate). For example, the shelves are arranged at a device layer, an insulating layer, or a substrate within one or more device layers. In some examples, the shelves are the bottom of a trench.

[0019] In some examples, the shelf is arranged on the upper surface of the substrate or within the substrate. The substrate may be made of a uniform crystalline semiconductor material whose surface can be tuned or otherwise treated to achieve high optical smoothness and is horizontal. The shelf may be arranged on the surface of the substrate that has been treated with high optical smoothness. In other words, the shelf formed on the substrate is an optically smooth surface configured to reduce optical scattering of the laser beam. For example, the shelf may receive the laser beam at the optically smooth surface, and the optically smooth surface may allow the laser beam to pass through the shelf and into the substrate while limiting optical scattering and back reflection of the laser beam. Due to the limitation of optical scattering and back reflection of the laser beam, the shelf allows the laser beam to enter the substrate with a desired direction, depth, and optical power. The die may be manufactured using the fabrication processes described elsewhere herein.

[0020] Some implementations involve a wafer, the non-wafer including a substrate, an insulating layer disposed on the substrate, and multiple device layers disposed on the insulating layer. The wafer also includes trenches extending from an upper device layer of the multiple device layers into the wafer to define a die assembly within the wafer. In other words, the trenches may be formed along a monolithic channel where the die assembly is separated during a mechanical die separation process. The trenches have trench bottoms located at a predefined depth within the wafer. Each die has an optical MEMS surface in the upper device layer and one or more cavities below the optical MEMS surface. Furthermore, each die includes internal MEMS device structures, such as actuation structures, disposed in at least one cavity within the cavity and sensitive to particulate contamination.

[0021] The wafer's internal cavity may be particle-free. For example, trenches are configured to trap particles originating from the substrate and / or device layers, preventing the particles from falling onto the upper surface or entering the wafer's internal cavity. The trenches are sized such that the particles are trapped within the trenches and do not exit the trenches in a manner that would allow them to fall onto the upper surface or enter the wafer's internal cavity.

[0022] In some implementations, the trench extends into the substrate, allowing the device layer and insulating layer to be removed at the monolithic channel to form the trench. In other words, the bottom of the trench is located at the substrate, which has several advantages.

[0023] First, removing the device layer and insulating layer to form trenches prevents the formation of particles during mechanical die separation, as those layers are missing due to removal. Therefore, having a trench bottom at the substrate reduces the amount of wafer separation particles generated during mechanical die separation. Reducing the amount of wafer separation particles generated during mechanical die separation lowers the likelihood of particle contamination at the die, particularly within the wafer's internal cavity. As a result, the yield of operable dies can be improved.

[0024] Secondly, the resistivity of the device layer can be very low (e.g., as low as 0.02 Ω·cm). Therefore, if the device layer is present in the monolithization channel during the mechanical die separation process, conductive particles may be generated from the device layer. By forming trenches to remove the device layer from the monolithization channel, conductive particles from the device layer are not generated during the mechanical die separation process, which helps to reduce the amount of conductive particles (and total particles) generated during the mechanical die separation process. In some cases, the generation of conductive particles during the mechanical die separation process can be prevented. Reducing the amount of conductive particles (and total particles) generated during the mechanical die separation process can reduce the likelihood of particle contamination at the die, especially within the wafer cavity. As a result, the yield of operable dies can be improved.

[0025] Third, having a trench bottom on the substrate allows the trench bottom (e.g., the substrate surface defining the trench bottom) to be tuned or otherwise treated to achieve high optical smoothness and remain horizontal. The substrate is made of a uniform crystalline semiconductor material whose surface can be tuned to achieve high optical smoothness. Therefore, the trench bottom formed on the substrate can be an optically smooth surface configured to reduce optical scattering of one or more laser beams emitted during stealth dicing. For example, the trench bottom, as an optically smooth surface, can receive the laser beam, and the trench bottom allows the laser beam to pass through the trench bottom and enter the substrate while limiting optical scattering and back reflection of the laser beam. Due to the limitation of optical scattering and back reflection of the laser beam, the trench bottom allows each laser beam to enter the substrate with a desired direction, depth, and optical power.

[0026] During stealth dicing, a laser beam can be fired into the substrate to create defect regions (e.g., weakened structural regions) aligned with the monolithic channels. These defect regions can be formed at varying depths within the substrate. To provide clean, smooth, and precise die separation during the mechanical die separation process, the defect regions should be vertically aligned and formed at an optimized depth. Misalignment and / or formation of defect regions at unoptimized depths (e.g., too close or too far) can lead to cracking, breakage, and / or fragmentation at the die edges during mechanical die separation. In some cases, misalignment of defect regions can result in reduced die yield due to cracking, breakage, and / or fragmentation.

[0027] As described above, the trench bottom can be optically smooth and horizontal to limit optical scattering and back reflection of the laser beam, allowing the laser beam to be emitted into the substrate with the desired direction, depth, and power. Therefore, the trench bottom ensures that defect regions are vertically aligned and formed at the desired depth with the desired power, resulting in cleaner, smoother, and more precise separation during the wafer separation process. Consequently, the edges of the substrate (e.g., the die edges) are straight and smooth after the mechanical die separation process. Furthermore, the likelihood of substrate edges (e.g., die edges) cracking, breaking, and / or fracturing is reduced, thereby improving the yield of operable dies. The wafer can be manufactured using the manufacturing processes described elsewhere herein.

[0028] Therefore, some implementations can aim to reduce the amount of particles accumulated on MEMS wafers and / or MEMS dies, and reduce the amount of particles entering one or more cavities within the MEMS wafers and / or MEMS dies where particles interfere with the internal MEMS device structure. As a result, the reliability of each MEMS die can be improved. Furthermore, the yield of MEMS dies produced from wafers is increased. In some implementations, the manufacturing techniques used to produce dies or wafers can combine aspects of both conventional dicing and stealth dicing processes.

[0029] Some implementations involve a method for manufacturing multiple optical MEMS dies. This manufacturing method can be used to produce the aforementioned wafers and dies. The method may include forming an unreleased wafer assembly, wherein the upper layer of the unreleased wafer assembly is sealed, thereby enclosing the internal cavity of the unreleased wafer assembly. Forming the unreleased wafer assembly may include disposing an insulating layer on a substrate (e.g., a uniform crystalline semiconductor substrate) and disposing multiple device layers (e.g., silicon layers) on the insulating layer. Multiple device layers may be processed to define an internal cavity in which internal MEMS device structures, such as actuation structures, are disposed. The upper layer is the upper device layer among the multiple device layers. Because the upper layer of the unreleased wafer assembly is sealed, the internal MEMS device structures disposed within the internal cavity of the unreleased wafer assembly are protected from particles and other contaminants.

[0030] After forming the unreleased wafer assembly and before opening the cavity, the method may further include forming deep trenches in the unreleased wafer assembly along monolithic channels defining the optical MEMS die. As described above, forming deep trenches can ultimately reduce the amount of wafer separation particles generated during the separation process steps (e.g., mechanical die separation processes). Furthermore, the deep trenches can act as particle traps during the separation process steps to prevent particles from diffusing above the upper layers and / or entering the cavity. The dimensions of the deep trenches ensure that particles are trapped within them. For example, the aspect ratio of the deep trenches is sufficient to trap particles and prevent them from diffusing above the upper layers and entering the cavity. Additionally, the deep trenches are wider than the stealth dicing laser beam to ensure that the device layers do not interfere with the laser beam emitted during stealth dicing. The deep trenches can be formed around the periphery of each MEMS die to ensure that particles are trapped on all sides of the MEMS die.

[0031] After forming the deep trench, the method may further include forming a released wafer assembly by opening the cavity of the unreleased wafer assembly through unsealing the upper layer to form multiple optical MEMS devices within the released wafer assembly. Unsealing the upper layer releases multiple optical MEMS devices from the upper layer, enabling the functionality of the multiple optical MEMS devices. For example, releasing multiple optical MEMS devices from the upper layer can allow the multiple optical MEMS devices to rotate or pivot about one or more axes. However, releasing multiple optical MEMS devices from the upper layer also opens the cavity, exposing it to the risk of contamination, such as particles generated in subsequent processing steps (e.g., separation process steps). Cleaning the optical MEMS devices after opening (releasing) the cavity is generally not recommended. For example, the cavity may become contaminated during such cleaning, or the released optical MEMS devices may be damaged. If cleaning is performed after opening the cavity, particles on the upper surface may displace during cleaning and enter the cavity, where they may come into contact with the internal MEMS device structure. Furthermore, cleaning within the cavity to remove particles is generally not possible. For example, the cavity is difficult to access for cleaning. Furthermore, the internal MEMS device structure is very fragile and can be easily damaged by the cleaning process applied to the cavity.

[0032] After forming the release wafer assembly, the method may further include firing one or more laser beams into the wafer substrate of the release wafer assembly to create defect regions within monolithic channels of the wafer substrate. In some implementations, firing one or more laser beams may be part of a stealth dicing process. After firing one or more laser beams, the method may further include a separation process step, which includes separating the release wafer assembly into optical MEMS dies through the defect regions in the wafer substrate.

[0033] The purpose of deep trenches is to reduce the amount of particles generated during the separation process of the wafer assembly. For example, by forming deep trenches through the device layer, particles generated by the device layer during the separation process can be reduced or prevented. This is particularly important because the device layer is made of a material with very low resistivity, and conductive particles may be generated during the separation process. Therefore, forming deep trenches through the device layer reduces the amount of conductive particles generated during the separation process and reduces the likelihood of conductive particles entering the cavity where they might come into contact with internal MEMS device structures, such as actuation structures or other electrically driven mechanisms.

[0034] Furthermore, deep trenches act as particle traps to prevent particles from diffusing onto the upper surface of the optical MEMS die and / or into the internal cavity where the internal MEMS device structure is located. Therefore, deep trenches protect the upper surface and internal cavity of the optical MEMS die from particle influence (e.g., by significantly reducing the chance of particles leaving the deep trenches during separation process steps).

[0035] Figures 1A-1F This is a diagram illustrating an example of a method for manufacturing multiple optical MEMS dies.

[0036] like Figure 1A As shown, an unreleased wafer assembly 100A can be provided. However, as described above, the manufacturing method may include forming the unreleased wafer assembly 100A. One or more monolithic channels may define optical MEMS dies 101a and 101b in the unreleased wafer assembly 100A. Although Figures 1A-1F Only two optical MEMS dies are shown, but the unreleased wafer assembly 100A may include three or more optical MEMS dies, which are to be monolithized into individual optical MEMS dies through a separation process. Furthermore, although... Figures 1A-1F Only one monolithic channel is shown, but multiple monolithic channels can be used to monolithize multiple optical MEMS dies. For example, the peripheries of optical MEMS dies 101a and 101b can be surrounded by a monolithic channel.

[0037] The unreleased wafer assembly 100A may include a wafer substrate 102, an insulating layer 104 (e.g., multiple insulating layers 104) formed on the wafer substrate 102, and multiple device layers 106 formed on the insulating layer 104. The wafer substrate 102 may be made of a uniform crystalline semiconductor material such as silicon. In some examples, the insulating layer 104 may be a silicon dioxide layer. In some cases, the insulating layer 104 may be a buried oxide layer. The multiple device layers 106 may include semiconductor layers, such as silicon layers, having a low resistivity (e.g., as low as 0.02 Ω·cm). In some embodiments, the unreleased wafer assembly 100A may be a silicon-on-insulator (SOI) wafer.

[0038] Multiple device layers 106 may include at least two device layers arranged in a stacked manner. For example, multiple device layers 106 may include a lower device layer 106a and an upper device layer 106b made of semiconductor material. For example, multiple device layers 106 may be formed by etching. Device layers 106 contain features of MEMS devices. When in the unreleased wafer assembly 100A state, some of these features are fully formed, while others are not fully formed. For example, in the unreleased wafer assembly 100A, multiple device layers 106 include an inner cavity 108 and an internal MEMS device structure 110. The internal MEMS device structure 110 may include an actuation structure or other electrically driven mechanism for operating the respective optical MEMS devices 101a and 101b. Furthermore, the multiple device layers 106 of the unreleased wafer assembly 100A may be formed to partially define portions of a MEMS mirror body 112 of a respective optical MEMS device. Each MEMS mirror body 112 may be disposed over a respective inner cavity 108. For each optical MEMS die 101, the peripheral portion of the upper device layer 106b can be used as a rotationally fixed frame 113. Therefore, each MEMS mirror 112 is attached to the corresponding frame 113.

[0039] The upper device layer 106b of the unreleased wafer assembly 100A can be sealed so that the inner cavity 108 is closed (e.g., not exposed to particulate contamination), thereby preventing particles from entering the inner cavity 108 and protecting the internal MEMS device structure 110 from the influence of particles.

[0040] The internal MEMS device structure 110 includes an actuation structure or other electrically driven mechanism for driving the MEMS mirror body 112 about one or more axes. In some examples, the actuation structure may include interdigitated electrodes made of interdigitated mirror combs and frame combs, to which a drive voltage, current, or other electrical signal (e.g., an actuation signal or a drive signal) is applied. In some embodiments, applying a potential difference between the interdigitated mirror combs and the frame combs generates a driving force between the mirror combs and the frame combs, which in turn generates a torque on the MEMS mirror body 112 about a desired axis and causes the MEMS mirror body 112 to rotate. In some implementations, other actuation methods, such as electromagnetic actuation, piezoelectric actuation, or thermal actuation, may be used.

[0041] As described above, the internal MEMS device structure 110, including the actuation structure, is extremely sensitive to particulate contamination. Conductive particles from device layer 106 can be particularly detrimental to the operation of the internal MEMS device structure 110. For example, in some examples, particles may cause electrical short circuits or other electrical damage at the internal MEMS device structure 110, including at the actuation structure and / or at drive signal traces that interfere with the electrical operation of the actuation structure. Particles in contact with the actuation structure can cause errors in the actuation of the MEMS mirror 112 and / or errors in the rotational position of the MEMS mirror 112 about one or more rotation axes. In some examples, particles may interfere with the movement of the actuation structure and / or damage the actuation structure.

[0042] Optical surfaces 114 and bonding pads 116 can be formed on the upper surface 118 of the upper device layer 106b. Optical surfaces 114 can be made of aluminum (Al), gold (Au), silver (Ag), copper (Cu), or another material suitable for reflecting light. Each optical surface 114 can be formed on a corresponding MEMS mirror body 112. Therefore, each optical surface 114 can be a reflective surface or a mirror surface used to receive and guide light during operation.

[0043] Bonding pads 116 are formed on the frame 113 of each optical MEMS die 101. Bonding pads 116 can be made of aluminum (Al), gold (Au), silver (Ag), copper (Cu), or another material suitable for conducting electrical signals. In some implementations, the optical surface 114 and bonding pads 116 can be made of the same material, allowing the optical surface 114 and bonding pads 116 to be formed in the same process step. A corresponding set of bonding pads 116 can be provided for each optical MEMS die 101a and 101b. The bonding pads 116 are electrically connected to the internal MEMS device structure 110 via device layer 106. During the manufacturing process, the electrical connections for connecting the bonding pads 116 to the internal MEMS device structure 110 are formed together with the internal MEMS device structure 110. The function of the bonding pads 116 is to electrically connect external signals to the internal MEMS device structure 110. For example, during operation, the bonding pad 116 can be used to provide an actuation signal to the internal MEMS device structure 110 to actuate and drive the operation of the optical MEMS device. For example, the actuation signal can be used to cause the optical MEMS device to rotate about one or more axes during operation.

[0044] like Figure 1B As shown, after forming the unreleased wafer assembly 100A, if combined with Figure 1A As stated above, and before opening one or more cavities, as follows: Figure 1CAs described above, a deep trench 120 can be formed in the unreleased wafer assembly 100A along a monolithic channel defining multiple optical MEMS dies. The deep trench 120 can be formed using, for example, one or more etchants according to one or more etching processes. It is important to note that during the formation of the deep trench 120, the cavity 108 remains partially sealed by the upper device layer 106b. Therefore, the cavity 108 does not have debris generated by the formation of the deep trench 120. As described above, since only one monolithic channel defining the optical MEMS dies 101a and 101b is shown, therefore... Figure 1B Only one deep trench 120 is shown; however, deep trenches 120 may exist around all sides of each optical MEMS die 101.

[0045] Each deep trench 120 may extend at least partially from the upper device layer 106b (e.g., from the upper surface 118) into the plurality of device layers 106. For example, in some cases, each deep trench 120 may extend only partially through the plurality of device layers 106. In other words, the deep trench 120 may not extend into the insulating layer 104. However, removing some of the device layers 106 can reduce the amount of wafer separation particles generated during wafer separation processes (e.g., separation process steps). For example, portions of the device layers 106 present in the monolithization channel during the wafer separation process may generate conductive particles, which can be extremely detrimental to the function of the internal MEMS device structure 110. By forming deep trenches 120 in the monolithization channel to remove at least some of the device layers 106, the amount of conductive particles generated during the wafer separation process can be reduced, thereby reducing the likelihood of conductive particles entering the cavity 108 in which they may come into contact with the internal MEMS device structure 110.

[0046] Furthermore, the deep trench 120 can serve as a particle trap, thereby reducing or, in some cases, preventing particle drift above the upper surface 118 during the wafer separation process. By reducing or preventing particle drift above the upper surface 118 during the wafer separation process, the likelihood of particles entering the inner cavity 108 is reduced. The wafer separation process will combine Figure 1F To describe in more detail.

[0047] To form the deep trench 120, a controlled portion of the device layer 106 can be removed using a first etchant that is reactive to it. For example, deep reactive ion etching (DRIE) can be used to form the deep trench 120 in the device layer 106. The deep trench 120 is formed without opening the cavity 108. Therefore, the cavity 108 can remain closed during the formation of the deep trench 120. Thus, particles generated during the formation of the deep trench can be removed from the upper surface 118 (e.g., cleaned) without contaminating the cavity 108, as the cavity remains sealed. In some embodiments, the deep trench 120 can be formed using photolithography and etching processes such that the deep trench 120 is aligned on a corresponding monolithic channel, away from the cavity 108. Thus, during the formation of the deep trench 120, the internal MEMS device structure 110 is protected from particles and other contaminants.

[0048] The depth of the deep trench 120 can be defined by its aspect ratio. The aspect ratio is crucial for ensuring that the deep trench 120 traps particles and prevents wafer separation particles generated during the wafer separation process from drifting above the upper surface 118 and entering the inner cavity 108. In some implementations, each deep trench 120 has an aspect ratio greater than 5, such that the deep trench 120 is configured to trap particles generated during the wafer separation process. In other words, the aspect ratio can be large enough (e.g., greater than 5) to trap wafer separation particles within the deep trench 120 and prevent particles from escaping the deep trench 120. The depth of each deep trench 120 is defined by the trench bottom 124.

[0049] In some implementations, each deep trench 120 may extend from an upper device layer (e.g., from the upper surface 118) completely through multiple device layers 106 to an insulating layer 104. Therefore, the trench bottom 124 may be defined on the insulating layer 104. The insulating layer 104 may serve as a stop layer for etching of the device layers 106. For example, the insulating layer 104 may be non-reactive or resistant to a first etchant, and the insulating layer 104 may be used to control the depth of the deep trench 120.

[0050] Forming the deep trench 120 into the insulating layer 104 can further reduce the amount of wafer separation particles generated during the wafer separation process, and can improve the deep trench 120 into a particle trap. By completely removing the device layer 106 from the monolithic channel, the amount of conductive particles generated by the device layer 106 during the wafer separation process can be further reduced (or eliminated), thereby reducing the likelihood of conductive particles entering the cavity 108, in which conductive particles may come into contact with the internal MEMS device structure 110. Furthermore, forming the deep trench 120 into the insulating layer 104 can increase the aspect ratio of the deep trench 120, thereby improving the ability of the deep trench 120 to trap particles within the deep trench 120 and prevent particles from escaping the deep trench 120 in a manner that could drift above the upper surface 118 and enter the cavity 108.

[0051] In some implementations, each deep trench 120 may extend from an upper device layer (e.g., from the upper surface 118) through multiple device layers 106 and at least partially enter the insulating layer 104. Thus, the trench bottom 124 may be defined within the insulating layer 104. Forming the deep trench 120 may include performing a first etch using a first etchant that etches the multiple device layers 106, and a second etch using a second etchant that etches the insulating layer 104. The first etchant may be different from the second etchant. For example, the second etchant may be hydrofluoric acid. Therefore, the insulating layer 104 may be non-reactive or resistant to the first etchant and may serve as a first stop layer for the first etch. By removing at least some of the insulating layer 104, the amount of wafer separation particles generated during wafer separation processes (e.g., separation process steps) can be reduced. Furthermore, forming a deep trench 120 that at least partially penetrates the insulating layer 104 can increase the aspect ratio of the deep trench 120, thereby improving the ability of the deep trench 120 to capture particles within the deep trench 120 and prevent particles from escaping the deep trench 120 in a manner that could drift above the upper surface 118 and enter the inner cavity 108.

[0052] In some implementations, each deep trench 120 may extend from an upper device layer (e.g., from the upper surface 118) through multiple device layers 106, through an insulating layer 104, and to a wafer substrate 102. Therefore, the wafer substrate 102 may serve as the trench bottom 124 of each deep trench 120. In other words, the wafer substrate 102 may define the trench bottom 124 of the deep trench 120. Forming the deep trench 120 may include performing a first etching with a first etchant used to etch the multiple device layers 106, and a second etching with a second etchant used to etch the insulating layer 104, wherein the first etchant and the second etchant are different etchants. The insulating layer 104 may be non-reactive or resistant to the first etchant and may serve as a first stop layer for the first etch. The multiple device layers 106 and the wafer substrate 102 may be non-reactive or resistant to the second etchant, and the wafer substrate 102 may serve as a second stop layer for the second etch. Therefore, when the insulating layer 104 is etched with the second etchant, the wafer substrate 102 can be used to control the depth of the deep trench 120, such that the bottom of the trench 124 is located at the wafer substrate 102.

[0053] By completely removing the device layer 106 and insulating layer 104 from the monolithic channel, the amount of wafer separation particles generated by the device layer 106 and insulating layer 104 during the wafer separation process can be further reduced (or eliminated), thereby reducing the likelihood of wafer separation particles entering the cavity 108, where they might come into contact with the internal MEMS device structure 110. Furthermore, forming a deep trench 120 into the wafer substrate 102 can increase the aspect ratio of the deep trench 120, thereby improving the ability of the deep trench 120 to trap particles within it and prevent particles from escaping the deep trench 120 in a manner that could drift above the upper surface 118 and enter the cavity 108.

[0054] Furthermore, another advantage of forming deep trenches 120 on the wafer substrate 102 includes forming trench bottoms 124 with enhanced optical properties, such as high optical smoothness, which enables increased laser emission during the stealth dicing process steps. The stealth dicing process steps (e.g., the laser emission process of the stealth dicing process) are combined with... Figure 1DTo describe in more detail. Therefore, forming the trench bottom 124 at the wafer substrate 102 may include processing the trench bottom 124 to be optically smooth and horizontal, so that a laser beam emitted during the stealth dicing process can pass through the trench bottom 124 and enter the wafer substrate 102 with a desired direction, depth, and optical power. For example, the bottom surface of the deep trench 120 corresponding to the trench bottom 124 may be processed to reduce (or prevent) optical scattering and back reflection of the laser beam emitted during the laser emission process (e.g., the laser emission process of the stealth dicing process). As a result, the trench bottom 124 located at the wafer substrate 102 can ensure that weakened structural regions (e.g., internal modifications or defect regions of stealth dicing) generated during the stealth dicing process are vertically aligned and formed at a desired depth with a desired optical power, enabling cleaner, smoother, and more precise separation during the wafer separation process. As a result, after the separation process step, the edges of the wafer substrate 102 (e.g., the edges of the optical MEMS die 101) are straight and smooth. Furthermore, it reduces the likelihood of cracking, breakage, and / or fragmentation at the edges of the wafer substrate 102 (e.g., the edges of the optical MEMS die 101), thereby improving the yield of operable optical MEMS dies.

[0055] In some examples, a second etch extending into or partially penetrating the wafer substrate 102 may form a trench bottom 124 at the wafer substrate 102, which may result in optical smoothing of the surface of the trench bottom 124 to reduce optical scattering of the laser beam. Reduction in optical scattering can improve beam focusing during laser emission, which can lead to more precise laser emission from the wafer substrate 102 (e.g., more precise formation of weakened structural regions within the wafer substrate 102) and cleaner, smoother, and more precise separation during the wafer separation process. Furthermore, reduction in optical scattering can result in fewer particles being generated during the wafer separation process. In some embodiments, the surface of the trench bottom 124 may be processed separately (e.g., after) from the step of forming the deep trench 120 to improve the optical performance of the laser beam (e.g., one or more laser beams) passing through that surface.

[0056] Furthermore, the trench width of each deep trench 120 can be greater than the laser beam width to ensure that the device layer 106 does not interfere with the laser beam. Interference with the device layer 106 may cause scattering, shearing, focus deviation, non-uniform beam power, and / or other non-uniformities in the laser beam, which may negatively affect the accuracy of forming weakened structure regions within the wafer substrate 102 during the laser emission process in the stealth dicing step. Interference with the device layer 106 may cause vertical misalignment, incorrectly positioned depth, and / or insufficient weakening of the weakened structure regions, which may lead to cracking, breakage, and / or fragmentation at the edges of the wafer substrate 102 during the separation process step and reduce manufacturing yield.

[0057] Furthermore, as a result of the etching processes used to form the deep trench 120, the trench sidewalls of the deep trench 120 can have structures with horizontal surface patterns. For example, these structures can extend horizontally along the y-axis. The surface patterns of the trench sidewalls produced by etching are several orders of magnitude larger than the internal modifications formed in the wafer substrate 102 by stealth dicing. The deep trench 120 is formed in multiple device layers 106 without forming weakening structural regions. For example, after the formation of the deep trench 120, the multiple device layers 106 may not have weakening structural regions such as microcracks, delamination, thermal stress damage, local phase transitions, phase transitions, fracture surfaces, and / or subsurface defects.

[0058] After the deep trench 120 is formed and before the unreleased wafer assembly is released, any particles accumulated on the upper device layer 106b can be removed, thereby preventing particles from contaminating the upper device layer structure and / or entering the inner cavity 108.

[0059] like Figure 1C As shown, after forming the deep trench 120, if combined with Figure 1B The release wafer assembly 100B can be formed by opening the upper device layer 106b, thereby opening one or more cavities 108 of the unreleased wafer assembly 100A to form a plurality of optical MEMS devices 126 (e.g., optical MEMS devices 126a and 126b) in the plurality of device layers 106. The optical MEMS device 126 is a MEMS mirror device including a mechanically moving mirror (e.g., MEMS mirror body 112) integrated on the optical MEMS die 101.

[0060] Opening the upper device layer 106b may include etching the upper device layer 106b to form an opening 128 extending from the upper surface 118 into the inner cavity 108. Etching typically does not generate particles. Therefore, the opening 128 can be formed such that the risk of particles entering the inner cavity is minimal.

[0061] An opening 128 is formed to define a MEMS mirror body 112 for a plurality of optical MEMS devices 126, and the MEMS mirror body 112 is released from the upper device layer 106b of the optical MEMS die 101. Specifically, releasing the MEMS mirror body 112 from the upper device layer 106b includes releasing (e.g., separating) the MEMS mirror body 112 from the frame 113 so that the MEMS mirror body 112 can rotate about one or more axes.

[0062] The opening 128 is also formed to define a suspension system within the upper device layer 106b. The suspension system includes suspension structures 129 that attach each MEMS mirror 112 to a corresponding frame 113 and suspend each MEMS mirror 112 over a corresponding cavity 108. For example, a set of suspension structures 129 attaches each MEMS mirror 112 to a rotationally fixed corresponding frame 113. This set of suspension structures 129 (such as torsion beams, linkages, or hinges) allows the MEMS mirror 112 to rotate about one or more axes of rotation. Therefore, opening the upper device layer 106b includes forming the opening 128 through the upper device layer 106b to each corresponding cavity 108 to release each MEMS mirror 112 and enable the MEMS functionality of each optical MEMS device 126.

[0063] Each MEMS mirror 112 can be attached to the frame 113 via a pair of opposing suspension structures 129. Figure 1C In the example shown, the suspension structure 129 extends along the y-axis (e.g., see the attached drawing page). A corresponding pair of suspension structures 129 may extend at least partially along the corresponding axis of rotation. For example, another pair of suspension structures may extend along the x-axis. Thus, even when the opening 128 releases the MEMS mirror 112 from the frame 113 to allow rotational movement about one or more axes, the MEMS mirror 112 remains attached to the frame 113 via the suspension structure 129.

[0064] While forming the opening 128 enables the MEMS functionality of each optical MEMS device 126, the opening 128 exposes the inner cavity 108 to the external environment. Therefore, it is crucial that the optical MEMS devices 126 operate to prevent particles from entering the inner cavity 108 after the upper device layer 106b is opened, in which particles could come into contact with the internal MEMS device structure 110.

[0065] like Figure 1D As shown, after forming the release chip assembly 100B, as combined Figure 1C The laser beam can be emitted along a monolithic channel into one or more layers located below the trench bottom 124 of the deep trench 120. The laser beam is used to target a defect region 130 within one or more layers below the trench bottom 124. The defect region 130 is a weakened structural region that allows the optical MEMS die 101 to be separated during a separation process step. Therefore, a laser emission process (e.g., stealth dicing) can be performed.

[0066] In some examples, a trench bottom 124 is disposed at a wafer substrate 102, and a laser beam is focused at different depths within the wafer substrate 102 to form defect regions 130 at different depths within the wafer substrate 102. The defect regions 130 are laser-induced modifications within the wafer substrate 102. For example, each laser beam may create a modified region with weakening structural aspects within the wafer substrate 102 (or another layer below the trench bottom 124) along a corresponding monolithic channel. Therefore, the defect regions 130 are weakened structural regions where the wafer will be separated to form individual dies. The defect regions 130 may include alignment structures located within the released wafer assembly 100B. The alignment structures may include at least one of microcracks, delamination, thermal stress damage, local phase transitions, phase transitions, fracture surfaces, or subsurface defects, enabling the dies to be separated along a defined profile corresponding to the monolithic channel.

[0067] like Figure 1E As shown, by focusing a laser beam at different depths within the release wafer assembly 100B, multiple defect regions 130 can be formed at different depths. The defect regions 130 can be vertically aligned along a defined profile corresponding to a monolithic channel. Thus, a wafer 100C is formed. The wafer 100C can be a modified release wafer assembly, similar to the release wafer assembly 100B, except that it has the defect regions 130. The wafer 100C includes a substrate (e.g., wafer substrate 102), an insulating layer 104 disposed on the substrate, and multiple device layers 106 disposed on the insulating layer 104. The wafer 100C includes a deep trench 120 extending from an upper device layer 106b of the multiple device layers 106 into the wafer 100C to define a die assembly (e.g., optical MEMS dies 101a and 101b) within the wafer 100C. The deep trench 120 has a trench bottom 124 (e.g., a bottom surface). The deep trench 120 may have a sidewall 122 having a structure with a horizontal surface pattern generated during the formation of the deep trench 120.

[0068] The defect region 130 located below the trench bottom 124 of the deep trench 120 includes an alignment structure weakening portion. For example, the defect region 130 may be located within an internal volume of the wafer substrate 102 and / or within other layers below the trench bottom 124 of the deep trench 120. The alignment structure weakening portion may be vertically aligned. The deep trench 120 helps ensure that the defect region 130 is vertically aligned along the intended monolithic channel. For example, the trench bottom 124 may reduce optical scattering of the laser beam to ensure that the defect region 130 is vertically aligned and formed at the intended depth. The alignment structure weakening portion may include at least one of microcracks, delamination, thermal stress damage, local phase transition, phase transition, fracture surface, or subsurface defects induced by the laser beam. In other words, the alignment structure weakening portion is a laser-induced modification within the wafer 100C (e.g., within the wafer substrate 102 and / or within other layers below the trench bottom 124 of the deep trench 120).

[0069] Each optical MEMS die 101 has an optical MEMS surface (e.g., optical surface 114) and one or more cavities 108 disposed below the optical MEMS surface. The upper device layer 106b includes openings 128 into the one or more cavities 108. The trench bottom 124 of the deep trench 120 may be optically smoothed or otherwise treated to reduce optical scattering and back reflection.

[0070] Above the trench bottom 124 of the deep trench 120, the wafer 100C does not have a weakening structure region. For example, the outer edge of the device layer 106 does not have a weakening structure region. Furthermore, as combined with... Figure 1B As the upper device layer 106b is sealed during the formation of the deep trench 120, the inner cavity 108 does not contain debris, such as particles, from the deep trench 120.

[0071] like Figure 1F As shown, after emitting one or more laser beams, as combined Figure 1D and Figure 1E The wafer 100C (e.g., a modified release wafer assembly) can be separated into multiple optical MEMS dies 101a and 101b via the defect region 130. For example, a wafer separation process can be used to separate the wafer 100C, which includes applying an external force, such as expanding the wafer substrate 102 by stretching a band applied beneath it. This external force may cause the wafer 100C to break cleanly along a weakened monolithic channel. The defect region 130 can act as a stress point to guide the break through the intended monolithic channel, ensuring that the optical MEMS dies 101a and 101b are cleanly separated without damaging them.

[0072] Although the amount of particles generated during the wafer separation process may be reduced by the formation of the deep trench 120, some particles will still be generated during the wafer separation process in which the optical MEMS die 101 is pulled apart. The deep trench 120 acts as a particle trap during the wafer separation process, thereby preventing particles from entering the cavity 108 where the internal MEMS device structure 110 is located (e.g., through the opening 128). For example, the deep trench 120 has a sufficient aspect ratio to trap particles and prevent particles from escaping the deep trench 120, which may land on the upper surface 118 and / or enter the cavity 108 of the wafer 110C. Therefore, the deep trench 120 significantly reduces the likelihood of one or more particles entering the cavity 108. As a result, the deep trench 120 protects the internal MEMS device structure 110, including the actuation structure, from particle contamination, thereby preventing operational errors and damage, and improving the reliability of the optical MEMS die 101.

[0073] After monolithization (e.g., after separation), the sidewalls of optical MEMS dies 101a and 101b below the trench bottom 124 of the deep trench 120 and corresponding to the defect region 130 (e.g., the region modified by the laser beam) can have vertical surface patterns. For example, the sidewalls of optical MEMS dies 101 and 101b below the trench bottom 124 of the deep trench 120 can have a structure with a vertical surface pattern extending along the z-axis.

[0074] Furthermore, after monolithization, the trench bottom 124 is divided between adjacent optical MEMS dies 101 and becomes a shelf at the periphery of each optical MEMS die 101. The shelf extends around the exterior of the optical MEMS die 101 and defines a variation in the cross-sectional width of the optical MEMS die 101. For example, above the shelf, the optical MEMS die 101 has a first cross-sectional width, while below the shelf, the optical MEMS die 101 has a second cross-sectional width greater than the first cross-sectional width. The shelf can be optically smooth to reduce optical scattering and back reflection, such that the shelf is configured to allow a laser beam to pass through the shelf and enter the wafer substrate 102 with a desired direction, depth, and optical power.

[0075] As mentioned above, Figures 1A-1F Provided as an example only. Other examples may be combined with it. Figures 1A-1F The differences are as described. For example, while these examples refer to optical MEMS chips and dies, the combination... Figures 1A-1F The described manufacturing method can be applied to other types of MEMS wafers and dies with one or more cavities in which particle-sensitive elements are arranged and protected from particles during manufacturing.

[0076] Figure 2A cross-section of an optical MEMS die 200 according to one or more implementations is shown. In combination Figure 1F Following the described wafer separation process, the optical MEMS die 200 can correspond to either optical MEMS die 101a or optical MEMS die 101b. In other words, the optical MEMS die 200 can be used in conjunction with... Figures 1A-1F The manufacturing method described is used to manufacture it.

[0077] The optical MEMS die 200 may include a substrate 202, an insulating layer 204 disposed on the substrate 202, and a plurality of device layers 206 disposed on the insulating layer 204. The substrate 202, the insulating layer 204, and the plurality of device layers 206 may correspond to the above-described combination. Figures 1A-1F The wafer substrate 102, insulating layer 104, and multiple device layers 106 are described. Furthermore, the optical MEMS die 200 includes an optical MEMS device 208 having an opening 210 for accessing one or more cavities 212 defined within the multiple device layers 206.

[0078] The optical MEMS device 208 includes a MEMS mirror 214 formed in the upper device layer of device layer 206 and an internal MEMS device structure 216 disposed within a cavity 212. The internal MEMS device structure 216 includes an actuation structure highly sensitive to particulate contamination. The actuation structure drives the MEMS mirror 214 about one or more rotation axes. Based on the combination... Figures 1A-1F The described process fabricates the optical MEMS die 200, and the cavity 212 can be manufactured without particulate contamination. As a result, the internal MEMS device structure 216 can operate reliably without being affected by particulate contamination.

[0079] Suspension structure 217 mechanically attaches MEMS mirror body 214 to frame portion 218 of device layer 206 to suspend MEMS mirror body 214 above cavity 212. Suspension structure 217 also allows MEMS mirror body 214 to rotate about one or more rotation axes. Optical surface 219 can be arranged on MEMS mirror body 214 to form MEMS mirror. MEMS mirror body 214 and optical surface 219 can be arranged between corresponding openings in openings 210 in one or more cavities 212. Openings 210 realize the MEMS function of optical MEMS device 208, as described above. Figure 1C As stated above.

[0080] The optical MEMS die 200 may include a shelf 220 extending around the outer or periphery of the optical MEMS die 200. In some examples, the shelf 220 may extend around the entire periphery of the optical MEMS die 200. Therefore, the shelf 220 may extend around all sides of the optical MEMS die 200. The shelf 220 may be disposed in one of the device layer 206, the insulating layer 204, or the substrate 202, at a predefined depth of the optical MEMS die 200. For example, the shelf 220 may correspond to the bottom of one or more trenches (e.g., the bottom 124 of a deep trench 120). For example, the shelf 220 may correspond to a combination... Figures 1B-1F The described deep groove 120 is a portion of the groove bottom 124. In other words, the shelf 220 may include the bottom of an assembly of one or more grooves. Furthermore, the shelf 220 may be optically smooth or treated to reduce optical scattering and back reflection.

[0081] In some examples, a shelf 220 corresponding to the bottom of one or more deep trenches 120 may be formed on the upper surface of the substrate 202. The shelf 220 may be processed to be optically smooth and horizontal to reduce optical scattering of the laser beam transmitted through the upper surface of the shelf 220 (e.g., through the substrate 202) and into the substrate 202 during the laser emission process of the stealth dicing process. The horizontal, smooth, and / or processed surface of the shelf 220 ensures that the laser beam is not deflected in an unintended direction as it transmits through the shelf 220. Therefore, the shelf 220 can be optimized for optical transmission such that the laser beam passes through the shelf 220 and enters the substrate 202 with a desired direction, depth, and optical power. For example, the shelf 220 has an optically smooth surface configured to reduce optical scattering and back reflection of one or more laser beams. The shelf 220 is configured to receive the laser beam at the optically smooth surface, and the optically smooth surface is configured to allow the laser beam to pass through the shelf 220 and enter the substrate 202 with a desired (target) direction, depth, and optical power. In some examples, the optically smooth surface is the upper surface of the substrate 202.

[0082] The reduction in optical scattering at shelf 220 improves beam focusing onto substrate 202 during laser emission, enabling more precise laser emission from substrate 202 (e.g., more precise formation of weakened structural regions within substrate 202) and cleaner, smoother, and more precise separation during wafer separation processes. For example, the reduction in optical scattering at shelf 220 ensures that defect regions 130 are vertically aligned and formed at the desired depth, enabling cleaner, smoother, and more precise separation during wafer separation processes. As a result, the edges of substrate 202 are straight and smooth.

[0083] Shelf 220 defines a change in the cross-sectional width of optical MEMS die 200. For example, optical MEMS die 200 has a first cross-sectional width W1 above shelf 220 (e.g., between the top surface of optical MEMS die 200 and shelf 220) and a second cross-sectional width W2 below shelf 220 (e.g., between the bottom surface of optical MEMS die 200 and shelf 220). Therefore, the cross-sectional width of optical MEMS die 200 changes from the first cross-sectional width W1 to the second cross-sectional width W2 at shelf 220. Thus, shelf 220 provides a stepped transition between the first cross-sectional width W1 and the second cross-sectional width W2. For example, when shelf 220 is located at the upper surface of substrate 202, insulating layer 204 and multiple device layers 206 may have the first cross-sectional width W1, and substrate 202 may have the second cross-sectional width W2. Therefore, the shelf 220 is arranged at a predefined depth of the optical MEMS die 200, at a device layer (e.g., in one of device layers 106), at an insulating layer (e.g., in one of insulating layers 204), or at the substrate 202. Furthermore, the difference between the second cross-sectional width W2 and the first cross-sectional width W1 (e.g., W2-W1) is greater than the width of the stealth dicing laser beam to ensure that the sidewall above the shelf 220 does not interfere with the laser beam emitted during the laser emission process of the stealth dicing process. The predefined depth at which the shelf 220 is arranged from the top surface of the optical MEMS die 200 can be greater than five times the difference between the second cross-sectional width and the first cross-sectional width (e.g., shelf depth > 5 × (W2-W1)). Therefore, the portion of the optical MEMS die 200 above the shelf 220 can be designed to trap particles originating from the edge of the die 220 below the shelf 220 and prevent particles from drifting above the top surface of the optical MEMS die 200. As a result, the predefined depth of the shelf arrangement 220 can prevent particles from entering the cavity 212 where the internal MEMS device structure 216 is located.

[0084] The optical MEMS die 200 may have a first sidewall 222 and a second sidewall 224. The first sidewall 222 may be disposed above the shelf 220 and extend between the shelf 220 and the top surface of the plurality of device layers 206. The second sidewall 224 may be disposed below the shelf 220 and extend between the shelf 220 and the bottom surface of the substrate 202. The first sidewall 222 may be formed by one or more trenches (e.g., deep trench 120). In other words, the first sidewall 222 can be formed by bonding Figure 1BThe process described for forming the deep trench 120 is used for manufacturing. For example, the first sidewall 222 can be manufactured according to an etching process. Thus, the first sidewall 222 can correspond to the trench sidewall of the deep trench 120. As a result, the first sidewall 222 can have a structure with a horizontal surface pattern. The structure of the first sidewall 222 can be formed as a horizontal surface pattern (e.g., fan-shaped). For example, the horizontal surface pattern can include a plurality of fan-shaped recesses arranged vertically along the first sidewall 222 in a vertical direction (e.g., along the z-axis), each fan-shaped recess being arranged at a corresponding vertical depth along the first sidewall 222. Each fan-shaped recess can be a structure of the horizontal surface pattern that extends horizontally along the first sidewall 222 parallel to the y-axis. The shape and size of the structure of the horizontal surface pattern can be determined by a specific etching process applied to form the deep trench 120. In some examples, the horizontal surface pattern can correspond to an iteration of a photolithography or etching process.

[0085] The second sidewall 224 can be combined Figure 1D and Figure 1E The laser emission process and its combination Figure 1F The wafer separation process described above is used to form the second sidewall 224. In some implementations, the second sidewall 224 can be formed by a stealth dicing process. Therefore, the second sidewall 224 can correspond to a stealth dicing sidewall. As a result, the second sidewall 224 can have a structure forming a vertical surface pattern. The structure of the second sidewall 224 can be a vertically oriented internal modification or weakening structural region (e.g., stripes). Therefore, the structure of the second sidewall 224 can be arranged horizontally along the second sidewall 224 in the horizontal direction (e.g., along the y-axis), with each structure arranged at a corresponding lateral position along the second sidewall 224. Each structure of the vertical surface pattern extends vertically along a portion of the second sidewall 224 parallel to the z-axis. The shape and size of the structure of the vertical surface pattern can be determined by the process applied to form the internal modification or weakening structural region and separate the die. In some examples, the vertical surface pattern can correspond to an iteration of the stealth dicing process. Furthermore, the optical MEMS die 200 can have a weakening structural region 226 below the shelf 220 and near the exterior of the optical MEMS die 200 (e.g., near the second sidewall 224). The weakened structural region 226 corresponds to the defect region 130 (e.g., internal modification) formed by one or more laser beams during the laser emission process. The weakened structural region 226 can be combined as follows... Figure 1D and Figure 1E The formation is described above. The weakened structure region 226 can be a laser-induced modification of the interior of the optical MEMS die 200 (e.g., inside the substrate 202). For example, the weakened structure region 226 can be a subsurface region located within the substrate 202, and in conjunction with... Figure 1F The wafer separation process described is retained afterward.

[0086] The weakened structure region 226 may include alignment structures within the optical MEMS die 200. Alignment structures may include at least one of microcracks, delamination, thermal stress damage, local phase transitions, phase transitions, fracture surfaces, or subsurface defects. Similar to internal modification, the shape and size of the weakened structure region can be determined by the applied process. Therefore, in some embodiments, while the optical MEMS die 200 includes the weakened structure region 226 below the shelf 220, the optical MEMS die 200 does not have the same weakened structure region 226 above the shelf 220. In other words, above the shelf 220, the optical MEMS die 200 does not have a weakened structure region, nor does it have a structure characteristically similar to the weakened structure region arranged below the shelf 220. For example, if the shelf is located on the substrate 202, the insulating layer 204 and the device layer 206 may not have the weakened structure region 226. In this context, "similar in features" refers to features indicating laser-induced modifications that are similar in size, width, length, and structure to the weakened structural region arranged below shelf 220.

[0087] Therefore, when considering the die 200, the sidewall 222 above the shelf 220 and the sidewall 224 below the shelf 220 have different surface patterns: a structure with a horizontal pattern formed above the shelf 220 and other structures with a vertical pattern formed below the shelf 220. Furthermore, the dimensions (e.g., repetition period) of these patterns can differ. The vertical repetition period of the horizontal surface pattern can correspond to the vertical dimension of the fan-shaped recess on the first sidewall 222, for example, 100 nm to 500 nm. Simultaneously, the horizontal repetition period of the vertical surface pattern can correspond to the horizontal spacing between the weakened structural regions (or internal modifications) on (or in) the second sidewall 224, for example, 1 μm to 3 μm (1000 nm to 3000 nm). Typically, the horizontal surface pattern can have a repetition rate at least one order of magnitude smaller than that of the vertical surface pattern.

[0088] As mentioned above, Figure 2 Provided as an example only. Other examples may be combined with it. Figure 2 The differences mentioned above.

[0089] Figure 3 This is a flowchart of an example process 300 associated with forming deep trenches on a microelectromechanical system (MEMS) wafer for stealth dicing. In some implementations, Figure 3 One or more process blocks are executed by a manufacturing system for producing multiple dies (e.g., optical MEMS dies). The manufacturing system can implement various semiconductor manufacturing processes for producing multiple dies, as described elsewhere in this document.

[0090] like Figure 3As shown, process 300 may include forming an unreleased wafer assembly (block 310). For example, the unreleased wafer assembly may be configured to be coupled with... Figure 1A It is formed in a similar manner as described above.

[0091] like Figure 3 As further shown, process 300 may include forming a deep trench (box 320) in the unreleased wafer assembly along a monolithic channel defining the optical MEMS die. For example, the deep trench may be configured in accordance with... Figure 1B It is formed in a similar manner as described above.

[0092] like Figure 3 As further shown, process 300 may include forming a release wafer assembly (block 330). For example, the release wafer assembly may be configured to be coupled with... Figure 1C It is formed in a similar manner as described above.

[0093] like Figure 3 As further shown, process 300 may include emitting one or more laser beams into the release wafer assembly (box 340). For example, it may be performed in accordance with [the following description is missing from the original text] and [the following description is missing from the original text] Figure 1D and Figure 1E One or more laser beams are emitted in a similar manner as described above.

[0094] like Figure 3 As further shown, process 300 may include separating the release wafer assembly into an optical MEMS die (block 350). For example, the release wafer assembly may be configured to... Figure 1F The same method described above is used to separate optical MEMS chips.

[0095] Process 300 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0096] although Figure 3 An example box of process 300 is shown, but in some implementations, process 300 includes... Figure 3 The examples shown are compared to more boxes, fewer boxes, different boxes, or boxes arranged differently.

[0097] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit implementations to the precise forms disclosed. Modifications and variations can be made based on the foregoing disclosure, or derived from the practice of implementation. Furthermore, any implementation described herein can be composed unless the foregoing disclosure expressly provides a reason why one or more implementations cannot be composed.

[0098] Although specific combinations of features are referenced in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features can be combined in ways not specifically referenced in the claims and / or not disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes combinations of each dependent claim with every other claim in the claim set. As used herein, the phrase “at least one” in the list of referenced items refers to any combination of these items, including single members. For example, “at least one of a, b, or c” is intended to cover combinations of a, b, c, ab, ac, bc, and abc, as well as combinations of multiple items within the same item.

[0099] When a component or one or more components (e.g., a laser emitter or one or more laser emitters) is described or claimed (within a single claim or across multiple claims) to perform or be configured to perform multiple operations, this language is intended to broadly cover a wide range of architectures and environments. For example, unless explicitly claimed otherwise (e.g., by using "first component" and "second component" in the claims or other language distinguishing components), this language is intended to cover a single component performing or being configured to perform all operations, a group of components jointly performing or being configured to perform all operations, a first component performing or being configured to perform a first operation and a second component performing or being configured to perform a second operation, or any combination of components performing or being configured to perform operations. For example, when a claim takes the form "one or more components are configured to: perform X; perform Y; and perform Z," the claim should be interpreted as "one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (possibly different) components are configured to perform Z."

[0100] Unless explicitly stated otherwise, no element, action, or instruction used herein should be construed as critical or necessary. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and may be used interchangeably with “one or more.” Furthermore, as used herein, the article “described” is intended to include one or more items referenced in conjunction with the article “described” and may be used interchangeably with “one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and may be used interchangeably with “one or more.” If only one item is intended to be used, the phrase “only one” or similar language is used. Furthermore, as used herein, the terms “having,” “having,” “containing,” etc., are intended to be open-ended terms. Furthermore, unless explicitly stated otherwise, the word “based on” is intended to mean “at least partially based on.” Furthermore, as used herein, the term “or” is inclusive when used in series and may be used interchangeably with “and / or” unless explicitly stated otherwise (e.g., if used in conjunction with “any one of…” or “only one of…”). Furthermore, for ease of description, spatial relative terms (such as “below,” “lower,” “above,” “upper,” etc.) may be used herein to describe the relationship of an element or feature to other elements or features shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to cover different orientations of devices, equipment, and / or elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

Claims

1. A die, comprising: Substrate; An insulating layer is disposed on the substrate; A device layer is disposed on the insulating layer, wherein a microelectromechanical system (MEMS) device is defined within the device layer, the MEMS device having an opening for access into one or more cavities; Shelves are arranged around the outside of the tube core. The shelf defines the variation in the cross-sectional width of the tube, and The shelf is arranged at a predefined depth of the die, and the shelf is arranged at the device layer, the insulating layer, or the substrate; as well as The weakened structural area is located below the shelf and close to the outside of the tube core.

2. The tube according to claim 1, wherein the shelf extends around all sides of the tube.

3. The core of claim 1, wherein the shelf comprises the bottom of an assembly of one or more grooves.

4. The die according to claim 1, wherein the shelf is disposed on the substrate, and The shelf is smooth to reduce optical scattering, and is configured such that a laser beam can pass through the shelf and enter the substrate to form the weakened structure region.

5. The die of claim 1, wherein the shelf has an optically smooth surface configured to reduce optical scattering of the laser beam.

6. The core according to claim 1, wherein above the shelf, the core does not have a structure that is characteristically similar to the weakened structural region arranged below the shelf.

7. The die according to claim 1, wherein the weakened structural region includes an alignment structure within the die, and The alignment structure includes at least one of the following: microcracks, delamination, thermal stress damage, local phase transformation, phase transition, fracture surface, subsurface defects, or laser-induced modification.

8. The die according to claim 1, further comprising: A first sidewall extends between the shelf and the top surface of the tube, wherein the first sidewall includes a structure having a horizontal surface pattern; as well as A second sidewall extends between the shelf and the bottom surface of the core, wherein the second sidewall includes a structure having a vertical surface pattern.

9. The core according to claim 8, wherein the first sidewall does not have a structure characteristically similar to the weakened structural region arranged below the shelf, and The weakened structure region located below the shelf is situated on or near the second sidewall.

10. The tube according to claim 1, wherein above the shelf, between the top surface of the tube and the shelf, the tube has a first cross-sectional width. Below the shelf, between the bottom surface of the tube and the shelf, the tube has a second cross-sectional width, which is greater than the first cross-sectional width. The shelf is positioned at a predefined depth from the top surface of the tube core that is greater than five times the difference between the width of the second section and the width of the first section.

11. The die according to claim 1, further comprising: Suspension structure, The MEMS device includes a mirror, which is disposed on the device layer, and The suspension structure suspends the reflector above the cavity in one or more cavities.

12. A chip, comprising: Substrate; An insulating layer is disposed on the substrate; Multiple device layers are arranged on the insulating layer, and the multiple device layers include an upper device layer; A trench extends from the upper device layer into the wafer and defines a die assembly in the wafer, the trench having a trench bottom; as well as The region located below the bottom of the trench includes an alignment structure weakening portion. Each die in the die assembly has an optical microelectromechanical system (MEMS) surface in the upper device layer and one or more cavities below the optical MEMS surface.

13. The wafer of claim 12, wherein the trench is configured to trap particles originating from the wafer and disposed below the bottom of the trench.

14. The wafer of claim 12, wherein the trench bottom is optically smooth to reduce optical scattering, such that the trench bottom is configured to allow one or more laser beams to pass through the trench bottom and into the substrate in a desired direction, depth and optical power.

15. The wafer of claim 12, wherein the trench sidewalls of the trench do not have weakening structural regions.

16. The wafer of claim 12, wherein the alignment structure weakening portion comprises at least one of the following: microcracks, delamination, thermal stress damage, local phase transition, phase transition, fracture surface, or subsurface defect.

17. The wafer according to claim 12, wherein the alignment structure weakening portion is laser-induced modification within the wafer.

18. The wafer of claim 12, wherein the trench has sidewalls, the sidewalls comprising a structure having a horizontal surface pattern, and The weakened portion of the alignment structure is vertically aligned.

19. A method for manufacturing multiple optical microelectromechanical system (MEMS) dies, the method comprising: An unreleased wafer assembly is formed, the unreleased wafer assembly including a wafer substrate, an insulating layer formed on the wafer substrate, and a plurality of device layers formed on the insulating layer. The plurality of device layers include an upper device layer and one or more internal cavities. The one or more cavities therein house a particle-sensitive MEMS actuation structure, and The upper device layer of the plurality of device layers is sealed, thereby enclosing the one or more cavities; After the unreleased wafer assembly is formed and before the one or more cavities are opened, a deep trench is formed in the unreleased wafer assembly along a separation channel that defines the optical microelectromechanical system die. Each deep trench extends from the upper device layer to at least partially into the depth of the plurality of device layers; After forming the deep trench, the released wafer assembly is formed by unsealing the upper device layer, thereby opening the one or more cavities of the unreleased wafer assembly to form a plurality of optical MEMS devices in the plurality of device layers; After the release wafer assembly is formed, one or more laser beams are fired into the wafer substrate to create defect regions within the separation channels of the wafer substrate; as well as After emitting the one or more laser beams, the released wafer assembly is separated into the plurality of optical MEMS dies through the defect region in the wafer substrate.

20. The method of claim 19, wherein unpacking the upper device layer comprises: The upper device layer is etched to define the mirror bodies of the plurality of optical MEMS devices, thereby opening the one or more cavities of the unreleased wafer assembly and releasing the mirror bodies from the upper device layer.

21. The method of claim 19, wherein each deep trench has an aspect ratio greater than 5.

22. The method of claim 19, wherein each deep trench has a trench width greater than the width of the one or more laser beams.

23. The method of claim 19, wherein each of the plurality of optical MEMS devices comprises a MEMS mirror disposed above a respective cavity in one or more of the cavities, and The upper device layer described in Kaifeng includes: Multiple openings are formed, which pass through the upper device layer to reach each corresponding cavity, so as to release each MEMS mirror body and enable the MEMS function of each optical MEMS device.

24. The method of claim 19, wherein each deep trench extends from the upper device layer and through the plurality of device layers. The formation of the deep trench includes: A first etching is performed using a first etchant, which etches the plurality of device layers. as well as A second etching is performed using a second etchant, which at least partially etches into or through the insulating layer and at least partially into the substrate, wherein the first etchant is different from the second etchant, and The insulating layer thereon is the stop layer of the first etching.

25. The method of claim 19, wherein forming the deep trench includes forming a bottom surface of the deep trench to reduce scattering of the one or more laser beams during emission of the one or more laser beams.

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