Method and device for simulating faults of a power consumption information collection terminal with embedded simulation switches

Abstract

The disclosure provides a kind of embedded simulation switch's power utilization information acquisition terminal fault simulation method and device, specifically, terminal receives remote host instruction, obtains switch trigger mask, trigger target value, state precondition, fault data template and reset condition by parsing;Current global state vector of terminal is generated, and it is compared by being operated with precondition mask and expected value, if it is satisfied, then according to trigger mask and target value, update global state vector, flip or set corresponding logic switch;When logic switch enters trigger state, locate to the data cache area of key function node, first backup original target data, then execute bit by bit exclusive or operation to cache area data and fault template, complete the generation and injection of fault data;Reset condition is monitored continuously during simulation execution, reset all logic switches to default state, and using backup data restores data cache area to original state, clear simulation trace, terminate fault simulation process.

Description

Technical Field

[0001] This disclosure pertains to the field of fault simulation, and particularly relates to a fault simulation method and device for an electricity information acquisition terminal with an embedded simulation switch. Background Technology

[0002] The long-term stability and reliability of electricity information collection terminals are crucial to the accuracy of power grid billing, load management, and fault diagnosis. Therefore, comprehensive fault simulation testing of these terminals is essential during their R&D, network access testing, and on-site maintenance. This testing verifies the terminals' fault tolerance, self-healing capabilities, and the emergency response strategies of the main station system in the face of various hardware and software anomalies. Existing fault simulation methods, such as applying abnormal voltages with probes or simulating communication line interruptions, are complex, costly, have poor repeatability, and can easily cause permanent damage to the equipment. Simulating software anomalies by modifying the terminal firmware code requires repeated compilation and flashing of the firmware for different fault scenarios, resulting in long testing cycles, low efficiency, and the implanted test code may interfere with the normal execution of the terminal's original business logic, introducing new uncertainties and making it difficult to achieve remote and flexible testing of large-scale, distributed terminals.

[0003] While existing remote testing technologies can achieve some remote control functions, such as restarting or parameter configuration, they fall short in simulating complex fault scenarios strongly correlated with specific internal operating states of the terminal. For example, current technologies struggle to accurately inject pre-set error data at critical nodes in a specific business process to verify the system's anomaly handling capabilities. Any form of remote fault injection mechanism must consider security; without reliable authentication and command verification mechanisms, the test interface could be maliciously exploited, becoming a backdoor to attack the system and posing a serious threat to power grid security. Furthermore, ensuring the terminal safely and automatically recovers from a fault state to normal business mode after the simulation task is completed is a major challenge for existing technologies. This typically requires manual intervention or a hard reboot, lacking automatic reset and cleanup mechanisms, thus affecting the continuity of testing. Therefore, a non-intrusive, secure, and controllable remote fault simulation method that supports state condition triggering and has automatic recovery capabilities is urgently needed. Summary of the Invention

[0004] This addresses the problem that existing technologies cannot achieve non-intrusive, safe, controllable, condition-triggered, and automatically recoverable remote fault simulation.

[0005] In the first aspect, this disclosure proposes a fault simulation method for an electricity information acquisition terminal with an embedded simulation switch, comprising the following steps: Receive a sequence of instructions sent by a remote master station. The sequence of instructions includes a generation timestamp, an instruction check hash, and an instruction body. Parse the instruction body that has passed the verification to obtain the switch trigger mask, the switch trigger target value, the state precondition mask, the state precondition expected value, the fault data injection template, and the simulation automatic reset condition. Collect the current state of all preset logic switches in the terminal and generate a current global state vector; perform a bitwise AND operation between the current global state vector and the state precondition mask; if the operation result is equal to the expected value of the state precondition, update the current global state vector according to the switch trigger mask and the switch trigger target value, and change the state of the corresponding logic switch. When the state of any logic switch is updated to a preset trigger state, the data buffer of the key functional node associated with the switch is located, the original target data in the buffer is backed up, and the fault data injection template is XORed with the original target data in the buffer to generate and inject simulation fault data. During simulation execution, system events or timers associated with the simulation automatic reset condition are continuously monitored; when the reset condition is detected to be met, all preset logic switches are restored to their initial default state, and the data buffer of the key functional node is restored to the original target data, thus terminating the current fault simulation process.

[0006] Preferably, the verification process is as follows: Parse the generated timestamp to determine if it is within a preset valid time window; if it is within the window, calculate the hash value of the instruction body based on the shared key preset in the terminal and the generated timestamp; when the calculated hash value is consistent with the instruction verification hash, the verification is successful.

[0007] Preferably, parsing the verified instruction body includes: Based on the predefined data structure, the switch trigger mask, switch trigger target value, state precondition mask, state precondition expected value, fault data injection template, and simulation automatic reset condition are extracted from the instruction body.

[0008] Preferably, the current states of all preset logic switches within the acquisition terminal are used to generate a current global state vector, including: Each preset logic switch is assigned a unique bit in the current global state vector, and the value of the corresponding bit is set according to the current state of each logic switch.

[0009] Preferably, updating the current global state vector based on the switch trigger mask and the switch trigger target value includes: The corresponding bits of the current global state vector are cleared using the switch trigger mask, and the switch trigger target value is written into the corresponding bits to generate an updated and determined current global state vector.

[0010] Preferably, the data cache area located to the key functional node associated with the switch includes: Based on the identifier of the logic switch, the target data cache corresponding to the switch is located and determined through a preset mapping relationship; during data read and write operations, the target data cache is locked to prevent concurrent access conflicts.

[0011] Preferably, the step of continuously monitoring system events or timers associated with the simulation automatic reset condition during simulation execution includes: At the start of the simulation, a hardware watchdog or high-priority software timer, independent of the main system task, is started, and its duration is determined by the parameters in the simulation automatic reset condition. When the timer ends or an abnormal system restart event is detected, the reset condition is determined to be met.

[0012] Preferably, restoring all preset logic switches to their initial default state and restoring the data cache of the key functional nodes to the original target data includes: Reset the current global state vector to a preset initial state value; The original target data backed up in step 1 is used to overwrite the current data cache, or the bitwise XOR inverse operation with the fault data injection template is performed again to eliminate the impact of the simulated fault data on normal business.

[0013] In the second aspect, this disclosure proposes a fault simulation device for an electricity information acquisition terminal with an embedded simulation switch, comprising the following modules: The receiving unit is used to receive the instruction sequence issued by the remote master station. The instruction sequence includes a generation timestamp, an instruction check hash, and an instruction body. The verified instruction body is parsed to obtain the switch trigger mask, the switch trigger target value, the state precondition mask, the state precondition expected value, the fault data injection template, and the simulation automatic reset condition. The state acquisition unit is used to acquire the current state of all preset logic switches in the terminal and generate a current global state vector; the current global state vector is bitwise ANDed with the state precondition mask; if the result of the operation is equal to the expected value of the state precondition, the current global state vector is updated according to the switch trigger mask and the switch trigger target value, and the state of the corresponding logic switch is changed. The injection unit is used to locate the data buffer of the key functional node associated with the switch when the state of any logic switch is updated to a preset trigger state, back up the original target data in the buffer, and perform a bitwise XOR operation between the fault data injection template and the original target data in the buffer to generate and inject simulated fault data. The simulation unit is used to continuously monitor system events or timers associated with the simulation automatic reset condition during simulation execution; when the reset condition is detected to be met, all preset logic switches are restored to their initial default state, and the data buffer of the key functional node is restored to the original target data, thus terminating the current fault simulation process.

[0014] Preferably, the verification process is as follows: Parse the generated timestamp to determine if it is within a preset valid time window; if it is within the window, calculate the hash value of the instruction body based on the shared key preset in the terminal and the generated timestamp; when the calculated hash value is consistent with the instruction verification hash, the verification is successful.

[0015] Preferably, parsing the verified instruction body includes: Based on the predefined data structure, the switch trigger mask, switch trigger target value, state precondition mask, state precondition expected value, fault data injection template, and simulation automatic reset condition are extracted from the instruction body.

[0016] Preferably, the current states of all preset logic switches within the acquisition terminal are used to generate a current global state vector, including: Each preset logic switch is assigned a unique bit in the current global state vector, and the value of the corresponding bit is set according to the current state of each logic switch.

[0017] Preferably, updating the current global state vector based on the switch trigger mask and the switch trigger target value includes: The corresponding bits of the current global state vector are cleared using the switch trigger mask, and the switch trigger target value is written into the corresponding bits to generate an updated and determined current global state vector.

[0018] Preferably, the data cache area located to the key functional node associated with the switch includes: Based on the identifier of the logic switch, the target data cache corresponding to the switch is located and determined through a preset mapping relationship; during data read and write operations, the target data cache is locked to prevent concurrent access conflicts.

[0019] Preferably, the step of continuously monitoring system events or timers associated with the simulation automatic reset condition during simulation execution includes: At the start of the simulation, a hardware watchdog or high-priority software timer, independent of the main system task, is started, and its duration is determined by the parameters in the simulation automatic reset condition. When the timer ends or an abnormal system restart event is detected, the reset condition is determined to be met.

[0020] Preferably, restoring all preset logic switches to their initial default state and restoring the data cache of the key functional nodes to the original target data includes: Reset the current global state vector to a preset initial state value; The original target data backed up in step 1 is used to overwrite the current data cache, or the bitwise XOR inverse operation with the fault data injection template is performed again to eliminate the impact of the simulated fault data on normal business.

[0021] This disclosure provides a method for simulating faults in an electricity information acquisition terminal. By employing a shared key and timestamp for dual verification of remote command sequences, the legality and timeliness of simulation commands are ensured, preventing illegal command injection and replay attacks, thus enhancing the security and reliability of the simulation process. By setting preconditions, strict constraints are placed on the timing of simulation triggering, ensuring that faults are activated only under preset specific system states, avoiding arbitrariness and uncontrollability in testing. Using switch trigger masks and fault data injection templates, data in specific key functional nodes within the terminal can be accurately tampered with, enabling targeted and quantitative simulation of specific fault scenarios, improving the accuracy and reproducibility of simulation results. The built-in automatic reset mechanism automatically restores the terminal to normal operating status after preset conditions are met, ensuring high availability of the terminal after simulation, simplifying the testing process, and reducing the complexity and risk of manual intervention. Attached Figure Description

[0022] Figure 1 This is a flowchart of the first embodiment. Detailed Implementation

[0023] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0024] See Figure 1This disclosure proposes a fault simulation method for an electricity information acquisition terminal with an embedded simulation switch, comprising the following steps: S1, Receive the instruction sequence sent by the remote master station. The instruction sequence includes a generation timestamp, instruction verification hash and instruction body. Parse the verified instruction body to obtain the switch trigger mask, switch trigger target value, state precondition mask, state precondition expected value, fault data injection template and simulation automatic reset condition. The terminal's communication module, such as GPRS or NB-IoT, receives TCP / UDP data packets from the master station. The MCU extracts the generation timestamp contained in the instruction sequence from the packet header. The MCU first reads the local RTC real-time clock and calculates the absolute value of the difference between the local time and the generation timestamp. If the difference exceeds a preset threshold, such as 300 seconds, the instruction is discarded directly; if it is within the allowable range, the shared key preset in the secure storage area is used as the key for the HMAC-SHA256 algorithm, and the byte stream concatenated with the generation timestamp and the instruction body is used as the message input to calculate the hash value. The MCU compares the calculated hash value with the check hash carried in the instruction; if they match, the instruction passes. Subsequently, according to the protocol structure, the MCU sequentially parses the switch trigger mask, switch trigger target value, state precondition mask, state precondition expected value, fault data injection template, and simulation automatic reset condition from the instruction body and temporarily stores them in RAM.

[0025] It should be noted that this invention is particularly suitable for fault simulation during the normal operation of the electricity information collection terminal, that is, online fault simulation. Compared with fault simulation before leaving the factory or before installation, this invention can be performed in real time through a remote host, avoiding the problem that the electricity information collection terminal cannot be simulated or tested during daily operation.

[0026] In an optional embodiment, the verification process is as follows: Parse the generated timestamp to determine if it is within a preset valid time window; if it is within the window, calculate the hash value of the instruction body based on the shared key preset in the terminal and the generated timestamp; when the calculated hash value is consistent with the instruction verification hash, the verification is successful.

[0027] The shared key is a pre-defined hexadecimal string, such as 1A2B... The generation timestamp is a Unix timestamp generated by the master station and carried in the instruction sequence, such as 1678886400. The instruction body is structured data containing specific simulation parameters. The generation timestamp is appended to the beginning or end of the instruction body to form the input message M. The HMAC-SHA256 algorithm is used, with the shared key K, to perform the operation on message M: Hash = HMAC - SHA256(K, Timestamp + Body), ensuring the integrity and non-repudiation of the instruction content and generation time.

[0028] In an optional embodiment, parsing the verified instruction body includes: Based on the predefined data structure, the switch trigger mask, switch trigger target value, state precondition mask, state precondition expected value, fault data injection template, and simulation automatic reset condition are extracted from the instruction body.

[0029] Parsing relies on a predefined TLV or structure layout. The data structure must contain six core fields: the trigger mask `switch_trigger_mask`, the trigger target value `switch_trigger_target`, the precondition mask `state_precondition_mask`, the precondition expected value `state_precondition_expected`, the XOR data template `fault_injection_template`, and `auto_reset_condition`. The parser extracts these fields one by one; for example, if the mask is 0x0001, the target value is 0x0001, and the precondition expected value is 0x0000 (meaning all bits of interest must be 0), the parser loads the extracted parameters into the registers of the fault simulation controller.

[0030] S2, collect the current state of all preset logic switches in the terminal and generate the current global state vector; perform a bitwise AND operation between the current global state vector and the state precondition mask; if the operation result is equal to the expected value of the state precondition, update the current global state vector according to the switch trigger mask and the switch trigger target value, and change the state of the corresponding logic switch. The MCU reads the global status word variable from memory. First, a condition check is performed: the ALU executes `Result = Current_Vector & Precondition_Mask`, comparing `Result` with `Precondition_Expected`. If they are not equal, the process terminates; if they are equal, a status update is performed: the MCU first inverts the bits of `Switch_Trigger_Mask`, then performs a bitwise AND operation with `Current_Vector` to clear the corresponding bits; it then performs a bitwise AND operation between `Switch_Trigger_Target` and the original `Switch_Trigger_Mask` to ensure data validity, and finally performs a bitwise OR operation with the result of the previous step. The calculated new state vector is written back to memory, completing the determined state setting operation.

[0031] In an optional embodiment, updating the current global state vector based on the switch trigger mask and the switch trigger target value includes: The corresponding bits of the current global state vector are cleared using the switch trigger mask, and the switch trigger target value is written into the corresponding bits to generate an updated and determined current global state vector.

[0032] Define the global state vector as a 64-bit integer. Assume we need to force the Nth switch to turn on, i.e., set it to 1. Regardless of whether the current Nth bit is 0 or 1, the operation is as follows: Construct a trigger mask, with the Nth bit set to 1 and the rest to 0; construct the trigger target value, with the Nth bit set to 1. The MCU execution logic is: New_Vector = (Old_Vector & (~Mask)) | (Target & Mask). The & (~Mask) operation forces the Nth bit to zero, leaving the other bits unchanged; the | (Target & Mask) operation sets the Nth bit to the target value, thus executing the same instruction multiple times, maintaining the state at the expected target value.

[0033] S3, when the state of any logic switch is updated to a preset trigger state, locate the data buffer of the key functional node associated with the switch, back up the original target data in the buffer, and perform a bitwise XOR operation between the fault data injection template and the original target data in the buffer to generate and inject simulation fault data. When a state change is detected, the MCU locks the RAM address pointer of the target functional node according to the mapping table. Before modifying the data, the MCU allocates a temporary memory segment as a backup buffer and completely copies the original data at the target address to the backup buffer for storage. The MCU loads the fault data injection template and executes `Injected_Data = Original_Data XORTemplate`. The calculated result `Injected_Data` is written to the target RAM address, overwriting the original data, thereby achieving fault injection.

[0034] In an optional embodiment, the data cache area located to the key functional node associated with the switch includes: Based on the identifier of the logic switch, the target data cache corresponding to the switch is located and determined through a preset mapping relationship; during data read and write operations, the target data cache is locked to prevent concurrent access conflicts.

[0035] A static mapping table is established between logic switch IDs and memory addresses. When a fault needs to be injected, the MCU queries the mapping table to obtain the target address 0xFF004C20. Before performing a read-modify-write operation, the MCU calls the real-time operating system's OS_Mutex_Pend or enters a critical section to lock this memory region. This ensures that during the microsecond-level fault injection process, normal service acquisition tasks will not read data in the intermediate state, and no other tasks will write to it simultaneously, causing data corruption. After the operation is completed, the lock is released or interrupts are enabled.

[0036] S4. During the simulation execution, continuously monitor system events or timers associated with the simulation automatic reset condition; when the reset condition is detected, restore all preset logic switches to their initial default state, restore the data buffer of the key functional node to the original target data, and terminate the current fault simulation process.

[0037] The terminal starts a hardware timer or monitoring task. When the reset condition is met, such as the timer ending or a reset event being detected, the reset interrupt service routine is triggered. The program first performs a data recovery operation: reads the backup buffer data saved in step S3, forces it to be written back to the target RAM address of the critical functional node, or performs an inverse XOR operation: Data=Current_Data XOR Template, ensuring business data recovery. The global state switch variable is reset to its default value, such as 0x00, and the simulation mode flag is cleared, and the system resumes normal operation. After fault injection, the terminal reports abnormal business data through the communication interface, such as sudden power changes, voltage exceeding limits, or abnormal behaviors. The master station system or test equipment obtains these behaviors through the conventional data acquisition process and uses them to verify the accuracy of the upper-layer master station's fault diagnosis and early warning algorithm, i.e., whether it can identify faults, and to evaluate the software robustness of the acquisition terminal under abnormal data conditions, i.e., whether it will cause crashes or logical confusion. This allows for low-cost verification of the reliability and resilience of the entire system without damaging the hardware.

[0038] In an optional embodiment, the step of continuously monitoring system events or timers associated with the simulation automatic reset condition during simulation execution includes: At the start of the simulation, a hardware watchdog or high-priority software timer, independent of the main system task, is started, and its duration is determined by the parameters in the simulation automatic reset condition. When the timer ends or an abnormal system restart event is detected, the reset condition is determined to be met.

[0039] At the moment the simulation begins, the MCU activates a separate hardware watchdog or high-priority timer, setting its overflow time to equal the simulation auto-reset condition parameter, such as 5000ms. This timer runs independently of the main loop. If the simulation causes the main program to deadlock or crash, the hardware watchdog will forcibly trigger a system reset or a non-maskable interrupt (NMI) when the timer expires. The NMI handler will then forcibly execute data rollback and state reset logic.

[0040] In an optional embodiment, restoring all preset logic switches to their initial default state and restoring the data cache of the key functional nodes to the original target data includes: Reset the current global state vector to a preset initial state value; The original target data backed up in step 1 is used to overwrite the current data cache, or the bitwise XOR inverse operation with the fault data injection template is performed again to eliminate the impact of the simulated fault data on normal business.

[0041] The predefined INITIAL_STATE_VECTOR constant is used to reset the state of all logical switches. Simultaneously, for the tampered data cache, a memory copy operation memcpy is performed, directly overwriting the current faulty data with the previously backed-up original clean data; alternatively, if no backup area is allocated, the reflexivity of the XOR operation is used to XOR the fault template with the current data again to restore the original data.

[0042] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0043] The above description of the disclosed embodiments enables those skilled in the art to make or use this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fault simulation method for an electricity information acquisition terminal with an embedded simulation switch, characterized in that, Includes the following steps: Receive a sequence of instructions sent by a remote master station. The sequence of instructions includes a generation timestamp, an instruction check hash, and an instruction body. Parse the instruction body that has passed the verification to obtain the switch trigger mask, the switch trigger target value, the state precondition mask, the state precondition expected value, the fault data injection template, and the simulation automatic reset condition. Collect the current state of all preset logic switches in the terminal and generate a current global state vector; perform a bitwise AND operation between the current global state vector and the state precondition mask; if the operation result is equal to the expected value of the state precondition, update the current global state vector according to the switch trigger mask and the switch trigger target value, and change the state of the corresponding logic switch. When the state of any logic switch is updated to a preset trigger state, the data buffer of the key functional node associated with the switch is located, the original target data in the buffer is backed up, and the fault data injection template is XORed with the original target data in the buffer to generate and inject simulation fault data. During simulation execution, system events or timers associated with the simulation automatic reset condition are continuously monitored; when the reset condition is detected to be met, all preset logic switches are restored to their initial default state, and the data buffer of the key functional node is restored to the original target data, thus terminating the current fault simulation process.

2. The method according to claim 1, characterized in that, The verification process is as follows: Parse the generated timestamp to determine if it is within a preset valid time window; if it is within the window, calculate the hash value of the instruction body based on the shared key preset in the terminal and the generated timestamp; when the calculated hash value is consistent with the instruction verification hash, the verification is successful.

3. The method according to claim 1, characterized in that, The parsing of the verified instruction body includes: Based on the predefined data structure, the switch trigger mask, switch trigger target value, state precondition mask, state precondition expected value, fault data injection template, and simulation automatic reset condition are extracted from the instruction body.

4. The method according to claim 3, characterized in that, The current state of all preset logic switches within the acquisition terminal is used to generate a current global state vector, including: Each preset logic switch is assigned a unique bit in the current global state vector, and the value of the corresponding bit is set according to the current state of each logic switch.

5. The method according to claim 1, characterized in that, The step of updating the current global state vector based on the switch trigger mask and the switch trigger target value includes: The corresponding bits of the current global state vector are cleared using the switch trigger mask, and the switch trigger target value is written into the corresponding bits to generate an updated and determined current global state vector.

6. The method according to claim 1, characterized in that, The data cache area located to the key functional node associated with the switch includes: Based on the identifier of the logic switch, the target data cache corresponding to the switch is located and determined through a preset mapping relationship; during data read and write operations, the target data cache is locked to prevent concurrent access conflicts.

7. The method according to claim 1, characterized in that, The continuous monitoring of system events or timers associated with the simulation's automatic reset condition during simulation execution includes: At the start of the simulation, a hardware watchdog or high-priority software timer, independent of the main system task, is started, and its duration is determined by the parameters in the simulation automatic reset condition. When the timer ends or an abnormal system restart event is detected, the reset condition is determined to be met.

8. The method according to claim 6, characterized in that, The step of restoring all preset logic switches to their initial default state and restoring the data cache of the key functional nodes to the original target data includes: Reset the current global state vector to a preset initial state value; The original target data backed up in step 1 is used to overwrite the current data cache, or the bitwise XOR inverse operation with the fault data injection template is performed again to eliminate the impact of the simulated fault data on normal business.

9. A fault simulation device for an electricity information acquisition terminal with an embedded simulation switch, characterized in that, Includes the following units: The receiving unit is used to receive the instruction sequence issued by the remote master station. The instruction sequence includes a generation timestamp, an instruction check hash, and an instruction body. The verified instruction body is parsed to obtain the switch trigger mask, the switch trigger target value, the state precondition mask, the state precondition expected value, the fault data injection template, and the simulation automatic reset condition. The state acquisition unit is used to acquire the current state of all preset logic switches in the terminal and generate a current global state vector; the current global state vector is bitwise ANDed with the state precondition mask; if the result of the operation is equal to the expected value of the state precondition, the current global state vector is updated according to the switch trigger mask and the switch trigger target value, and the state of the corresponding logic switch is changed. The injection unit is used to locate the data buffer of the key functional node associated with the switch when the state of any logic switch is updated to a preset trigger state, back up the original target data in the buffer, and perform a bitwise XOR operation between the fault data injection template and the original target data in the buffer to generate and inject simulated fault data. The simulation unit is used to continuously monitor system events or timers associated with the simulation automatic reset condition during simulation execution; when the reset condition is detected to be met, all preset logic switches are restored to their initial default state, and the data buffer of the key functional node is restored to the original target data, thus terminating the current fault simulation process.

10. The apparatus according to claim 9, characterized in that, The verification process is as follows: Parse the generated timestamp to determine if it is within a preset valid time window; if it is within the window, calculate the hash value of the instruction body based on the shared key preset in the terminal and the generated timestamp; when the calculated hash value is consistent with the instruction verification hash, the verification is successful.

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