A memory power consumption configuration method, device, equipment and readable storage medium
By dynamically adjusting the memory frequency through SMI interrupts and SMM callback functions, the problem of resource waste in server memory under low load is solved, and memory power consumption optimization is achieved without restarting the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XINHUASAN INFORMATION TECH CO LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-05
AI Technical Summary
The server memory continues to operate at the same rated frequency and power as under high load even under low load, resulting in wasted resources and an inability to dynamically adjust the frequency to control power consumption without restarting the operating system.
Entering System Management Mode (SMM) via SMI interrupt, configuring the function fields of the memory power consumption register, dynamically adjusting the memory operating frequency based on CPU utilization, and gradually configuring the memory operating frequency using SMM callback functions to set gradient changes to avoid sudden power consumption changes.
It enables dynamic adjustment of memory frequency without restarting the system, reducing memory power consumption waste and improving system resource utilization efficiency.
Smart Images
Figure CN122152237A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of communication technology, and in particular to a memory power consumption configuration method, apparatus, device, and readable storage medium. Background Technology
[0002] During server operation, under high load, the server memory operates at its rated frequency and rated power. However, when business is relatively idle and the server memory is under low load, the server still operates at the same rated frequency and rated power as under high load.
[0003] Typically, memory operates at lower frequencies with lower power consumption. However, the memory frequency cannot be dynamically adjusted while it is in operation; changing the operating frequency to control power consumption requires restarting the operating system. In real-world applications, business requirements often preclude restarting the operating system solely for power control. Therefore, memory needs to maintain its standard rated power when the CPU is idle, resulting in some resource waste. Summary of the Invention
[0004] In view of this, this specification provides a memory power consumption configuration method, apparatus, electronic device, and readable storage medium to improve the problem of wasted memory power consumption when services are idle.
[0005] Specifically, the technical solution is as follows: This specification provides a memory power consumption configuration method for CPUs, the method comprising: In response to the SMI interrupt, enter System Management Mode (SMM) and write the function field for configuring memory power to the memory power register; Configure memory power consumption limits according to the target power parameters in the function field; If the CPU utilization is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter; the idle threshold is preset. If the CPU utilization is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
[0006] Furthermore, the writing of the functional field for configuring memory power includes: Execute the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register; The SMM callback function is executed to write the function field used to configure memory power to the memory power register. The functional fields include the memory power consumption register address, the Flag bit, and the target power parameter.
[0007] Furthermore, configuring memory power consumption limits based on power parameters in the function field also includes: The memory operating frequency is gradually configured to the second rated operating frequency according to the gradient. The value of the gradient is preset.
[0008] Furthermore, the method includes: Prior to responding to the SMI interrupt, the memory power consumption configuration function switch state is set in the BIOS; Based on the enabled state of the memory power consumption configuration function switch, in response to the SMI interrupt, subsequent steps are executed.
[0009] Furthermore, the method also includes: Before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register, it is determined whether to execute the SMM callback function for subsequent steps based on the source of the SMI interrupt. If the source of the SMI interrupt is related to the CPU utilization, then continue executing the SMM callback function for subsequent steps; If the SMI interrupt originates from a source unrelated to the CPU utilization, the SMM callback function returns.
[0010] This specification also provides a memory power consumption configuration device, the device comprising: The interrupt response module is used to respond to SMI interrupts, enter system management mode (SMM), and write the function field for configuring memory power to the memory power register. The power consumption configuration module is used to configure memory power consumption limits based on the target power parameters in the function field. The judgment module is used to determine whether the CPU utilization rate is lower than the idle threshold; the idle threshold is preset. If the CPU utilization is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter. If the CPU utilization is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
[0011] Furthermore, the interrupt response module also includes: The query module is used to execute the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register; The write module is used to execute the SMM callback function to write the function field for configuring memory power to the memory power register; The functional fields include the memory power consumption register address, the Flag bit, and the target power parameter.
[0012] Furthermore, the power consumption configuration module also includes: The memory operating frequency is gradually configured to the second rated operating frequency according to the gradient. The value of the gradient is preset.
[0013] Furthermore, the device includes: The function switch setting module is used to set the memory power consumption configuration function switch state in the BIOS before responding to the SMI interrupt; and to execute subsequent steps in response to the SMI interrupt based on the enabled state of the memory power consumption configuration function switch.
[0014] Furthermore, the device includes: The interrupt source determination module is used to determine whether to execute the SMM callback function for subsequent steps based on the SMI interrupt source before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register. If the source of the SMI interrupt is related to the CPU utilization, then continue executing the SMM callback function for subsequent steps; If the SMI interrupt originates from a source unrelated to the CPU utilization, the SMM callback function returns.
[0015] This specification also provides an electronic device, including a processor and a readable storage medium storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned memory power consumption configuration method.
[0016] This specification also provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned memory power consumption configuration method.
[0017] The technical solutions provided in this specification offer at least the following beneficial effects: Memory frequency can be configured without restarting the system, dynamically adjusting the memory operating frequency and allowing the memory to work at lower power consumption when business is idle, reducing memory power waste. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this specification.
[0019] Figure 1 This is a flowchart of a memory power consumption configuration method in one embodiment of this specification; Figure 2 This is a flowchart of a memory power consumption configuration method in one embodiment of this specification; Figure 3 This is a structural diagram of a memory power consumption configuration device according to one embodiment of this specification; Figure 4 This is a hardware structure diagram of an electronic device according to one embodiment of this specification. Detailed Implementation
[0020] The terminology used in the embodiments described herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The singular forms “a,” “described,” and “the” as used in this specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.
[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."
[0022] During server operation, under high load, the server memory operates at its rated frequency and rated power. However, when business is relatively idle and the server memory is under low load, the server still operates at the same rated frequency and rated power as under high load.
[0023] Typically, memory operates at lower frequencies with lower power consumption. Currently, the memory frequency cannot be dynamically adjusted; changing the frequency to control power consumption requires restarting the operating system. In real-world applications, business requirements often preclude restarting the operating system solely for power consumption control. Memory needs to maintain its standard rated power even when the CPU is idle, resulting in resource waste. If dynamic power consumption adjustment could be implemented, power savings could be achieved without restarting the system.
[0024] In view of this, this specification provides a memory power consumption configuration method, apparatus, electronic device, and readable storage medium to improve the aforementioned problem of wasted memory power consumption.
[0025] Specifically, the technical solution is described below.
[0026] In response to the SMI interrupt, enter System Management Mode (SMM) and write the function field for configuring memory power to the memory power register; Configure memory power consumption limits according to the target power parameters in the function field; If the CPU utilization is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter; the idle threshold is preset. If the CPU utilization is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
[0027] In one embodiment, writing the function field for configuring memory power includes: executing an SMM callback function to query the address of the memory power register in the CPU and obtaining the Flag bit of the memory power register; executing the SMM callback function to write the function field for configuring memory power to the memory power register; the function field includes the address of the memory power register, the Flag bit, and the target power parameter.
[0028] In one embodiment, configuring memory power consumption limits according to power parameters in the function field further includes: gradually configuring the memory operating frequency to the second rated operating frequency according to a gradient; the value of the gradient is preset.
[0029] In one embodiment, prior to responding to an SMI interrupt, the memory power configuration function switch state is set in the BIOS; based on the enabled state of the memory power configuration function switch, subsequent steps are executed in response to the SMI interrupt.
[0030] In one embodiment, the SMM callback function further includes: before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register, determining whether to execute the SMM callback function for subsequent steps based on the source of the SMI interrupt; if the source of the SMI interrupt is related to the CPU utilization, then the SMM callback function continues to be executed for subsequent steps; if the source of the SMI interrupt is unrelated to the CPU utilization, then the SMM callback function returns.
[0031] Specifically, such as Figure 1 This includes the following steps: Step S11: In response to the SMI interrupt, enter System Management Mode (SMM) and write the function field for configuring memory power to the memory power register.
[0032] The SMI interrupt can be generated in various ways, including but not limited to internal hardware event triggering, external controller triggering, software triggering, and power management / device management interface event triggering. Furthermore, the SMI interrupt can be triggered periodically at preset time intervals, or the user can actively select the trigger time.
[0033] Taking the SMI interrupt triggered by the Baseboard Management Controller (BMC) as an example. If the chip model does not support BMC triggering SMI interrupts, the hardware circuit pins need to be reconstructed so that the BMC can trigger SMI interrupts. In chips that support BMC triggering SMI interrupts, the BMC can trigger SMI interrupts by connecting a GPIO port or dedicated control pin of the BMC to the system management interrupt signal line of the main chipset (Southbridge or Platform Control Center PCH) via a circuit. Adding a thread trigger to the BMC's core program, taking the common SMI# signal line (the signal line that triggers SMI by a low level) as an example, the triggering process can be: set_GPIO_mode(GPIO_SMI, OUTPUT); set_GPIO_value(GPIO_SMI, LOW); delay(10ms); set_GPIO_value(GPIO_SMI, HIGH); The above code demonstrates the process of switching GPIO to output mode, pulling the SMI# signal line low to trigger SMI, and releasing the signal level after a period of time (10ms in this example, which can be adjusted according to the actual situation).
[0034] Step S12: Configure memory power consumption limits according to the target power parameters in the function field.
[0035] The target power parameter can be a target power value, a corresponding operating frequency value, or other values that have a unique mapping relationship with the target power value. In this embodiment, the target power value is used as the target power parameter for illustrative purposes only. The process of configuring memory power consumption limits is implemented by constructing an SMM callback function.
[0036] Step S13: If the CPU utilization rate is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter; the idle threshold is preset.
[0037] When CPU utilization is equal to or higher than the idle threshold, the CPU is not in an idle state. The first power parameter can be directly taken as the parameter corresponding to the standard rated power, i.e., the standard rated power or standard rated frequency, etc. CPU utilization can be obtained by the BIOS by reading monitoring sensor data provided by the management engine.
[0038] The idle threshold is preset by the user. For example, if the user sets the idle threshold to 5%, it means that when the CPU utilization is greater than or equal to 5%, the CPU is not in an idle state; conversely, when the CPU utilization is less than 5%, the CPU is in an idle state.
[0039] Step S14: If the CPU utilization rate is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
[0040] When CPU utilization is below the idle threshold, the CPU is in an idle state. At this time, a second power parameter is written. The memory power corresponding to the second power parameter is lower than the memory power corresponding to the first power parameter; that is, configuring memory power reduces memory power consumption.
[0041] Taking BMC periodically triggering SMI as an example, Figure 2 A flowchart of an embodiment of this solution is shown. With the Mem SMI function enabled, the BMC actively triggers the SMI signal. The BIOS obtains the CPU utilization by acquiring the Me sensor and determines whether the CPU is idle. If idle, the memory frequency is reduced using the method described in this solution; if not idle, the standard rated operating frequency is restored or maintained. The above steps are repeated during the next BMC polling cycle.
[0042] In one embodiment, writing the function field for configuring memory power includes: executing an SMM callback function to query the address of the memory power register in the CPU and obtaining the Flag bit of the memory power register; executing the SMM callback function to write the function field for configuring memory power to the memory power register; the function field includes the address of the memory power register, the Flag bit, and the target power parameter.
[0043] For example, taking a certain CPU as an example, the SMM callback function needs to construct the following functionality: 1. Locate the memory power consumption register address.
[0044] 2. Obtain the memory power consumption register address Flag bit.
[0045] 3. Write the function field for configuring memory power to the memory power register.
[0046] For example, suppose that in this CPU, the memory power consumption register address is 0x618 and the Flag bit is 0x58. If the target power is 21W, write 0x5880a8 to the memory power consumption register address 0x618. Here, 0x58 is the Flag bit, the following 8 bits are enable bits (i.e., 0100, which is used as the set enable bit in this embodiment), and 0a8 indicates that the target power limit is 21W.
[0047] In this embodiment, there is a fixed mapping relationship between 0a8 and 21W. This mapping relationship can be reference data provided by the manufacturer or conclusive data obtained through other means. The fixed mapping relationship may differ in different chips and devices. Generally, to ensure normal memory operation, the target power value should fall within the rated power range provided by the manufacturer. Simultaneously, the target power value limits the power of a single memory module. When calculating the total power, the power of a single memory module needs to be multiplied by the number of memory modules.
[0048] In one embodiment, configuring memory power consumption limits according to power parameters in the function field further includes: gradually configuring the memory operating frequency to the second rated operating frequency according to a gradient; the value of the gradient is preset.
[0049] When configuring memory power, changes in memory power (and frequency) must be gradual and incremental. Directly changing power consumption from the current level to the target level carries a high risk of data loss or malfunction. To avoid this risk, a frequency gradient is set, allowing the memory operating frequency to change slowly, thus improving system reliability and security. For example, a gradient of 1W, 2W, 0.5W, etc., can be set to progressively configure the memory power consumption until the target value is reached.
[0050] In one embodiment, prior to responding to an SMI interrupt, the memory power configuration function switch state is set in the BIOS; based on the enabled state of the memory power configuration function switch, subsequent steps are executed in response to the SMI interrupt.
[0051] Add a memory power consumption configuration switch to the BIOS to control whether this scheme is enabled or disabled. This switch can be set to enabled by default. When the BIOS receives an SMI interrupt, it initiates the SMM callback function to execute subsequent steps.
[0052] In one embodiment, before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register, it is determined whether to execute the SMM callback function for subsequent steps based on the source of the SMI interrupt; if the source of the SMI interrupt is related to the CPU utilization, the SMM callback function is executed for subsequent steps; if the source of the SMI interrupt is unrelated to the CPU utilization, the SMM callback function returns.
[0053] Before executing specific functions through the SMM callback function, considering that the SMI interrupt may be triggered by other functional requirements, the SMM callback function determines whether the source of the SMI interrupt is related to CPU utilization. The determination method varies depending on the specific chip model and may include querying the signal pin source and related registers. If the SMI interrupt source is related to the CPU utilization, it is assumed that the purpose of the SMI interrupt includes configuring memory power, and the SMM callback function continues to execute to implement the configuration method described in this solution. If the SMI interrupt originates from a source unrelated to CPU utilization, the SMM callback function returns; that is, the SMM callback function no longer executes the subsequent content used to implement the configuration method described in this solution.
[0054] If the CPU returns from an idle state to a busy, non-idle state, writing the target power consumption parameter using the method described in this solution can configure the power consumption back to the original standard rated power. The process principle is similar to this solution and will not be repeated here.
[0055] By applying the above solution, the memory frequency can be dynamically adjusted without restarting the system. In idle business scenarios, the memory can operate at lower power consumption, reducing memory power waste.
[0056] This specification provides a memory power consumption configuration device 301, such as... Figure 3 As shown, the device, applied to a CPU, includes: Interrupt response module 302 is used to respond to SMI interrupt, enter system management mode SMM, and write a function field for configuring memory power to the memory power register. The power consumption configuration module 303 is used to configure memory power consumption limits according to the target power parameters in the function field; The judgment module 304 is used to determine whether the CPU utilization rate is lower than the idle threshold; the idle threshold is preset. If the CPU utilization is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter. If the CPU utilization is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
[0057] In one embodiment, the interrupt response module further includes: The query module is used to execute the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register; The write module is used to execute the SMM callback function to write the function field for configuring memory power to the memory power register; The functional fields include the memory power consumption register address, the Flag bit, and the target power parameter.
[0058] In one embodiment, the power consumption configuration module further includes: The memory operating frequency is gradually configured to the second rated operating frequency according to the gradient. The value of the gradient is preset.
[0059] In one embodiment, the memory power consumption configuration device further includes: The function switch setting module is used to set the memory power consumption configuration function switch state in the BIOS before responding to the SMI interrupt; and to execute subsequent steps in response to the SMI interrupt based on the enabled state of the memory power consumption configuration function switch.
[0060] In one embodiment, the memory power consumption configuration device further includes: The interrupt source determination module is used to determine whether to execute the SMM callback function for subsequent steps based on the SMI interrupt source before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register. If the source of the SMI interrupt is related to the CPU utilization, then continue executing the SMM callback function for subsequent steps; If the SMI interrupt originates from a source unrelated to the CPU utilization, the SMM callback function returns.
[0061] The implementation methods of the apparatus are the same as or similar to the corresponding implementation methods, and will not be described in detail here.
[0062] In one embodiment, this specification provides an electronic device 401, including a processor 402 and a readable storage medium 403. The readable storage medium stores machine-executable instructions 404 that can be executed by the processor. The processor executes the machine-executable instructions to implement the aforementioned memory power consumption configuration method. From a hardware perspective, a hardware architecture diagram can be found... Figure 4 As shown.
[0063] In one embodiment, this specification provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned memory power consumption configuration method.
[0064] Here, a readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, a readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.
[0065] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.
[0066] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.
[0067] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0068] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments thereof. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0069] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0070] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0071] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0072] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.
Claims
1. A method for configuring memory power consumption, characterized in that, Applied to a CPU, the method includes: In response to the SMI interrupt, enter System Management Mode (SMM) and write the function field for configuring memory power to the memory power register; Configure memory power consumption limits according to the target power parameters in the function field; If the CPU utilization is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter; the idle threshold is preset. If the CPU utilization is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
2. The method according to claim 1, characterized in that, The function field for configuring memory power includes: Execute the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register; The SMM callback function is executed to write the function field used to configure memory power to the memory power register. The functional fields include the memory power consumption register address, the Flag bit, and the target power parameter.
3. The method according to claim 1, characterized in that, The configuration of memory power consumption limits based on the power parameters in the function field also includes: The memory operating frequency is gradually configured to the second rated operating frequency according to the gradient. The value of the gradient is preset.
4. The method according to claim 1, characterized in that, The method includes: Prior to responding to the SMI interrupt, the memory power consumption configuration function switch state is set in the BIOS; Based on the enabled state of the memory power consumption configuration function switch, in response to the SMI interrupt, subsequent steps are executed.
5. The method according to claim 2, characterized in that, The method further includes: Before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register, it is determined whether to execute the SMM callback function for subsequent steps based on the source of the SMI interrupt. If the source of the SMI interrupt is related to the CPU utilization, then continue executing the SMM callback function for subsequent steps; If the SMI interrupt originates from a source unrelated to the CPU utilization, the SMM callback function returns.
6. A memory power consumption configuration device, characterized in that, Applied to a CPU, the device includes: The interrupt response module is used to respond to SMI interrupts, enter system management mode (SMM), and write the function field for configuring memory power to the memory power register. The power consumption configuration module is used to configure memory power consumption limits based on the target power parameters in the function field. The judgment module is used to determine whether the CPU utilization rate is lower than the idle threshold; the idle threshold is preset. If the CPU utilization is equal to or higher than the idle threshold, the first power parameter is written as the target power parameter, and the memory runs at the first rated operating frequency corresponding to the first power parameter. If the CPU utilization is lower than the idle threshold, the second power parameter is written as the target power parameter, and the memory operating frequency is configured so that the memory operates at the second rated operating frequency corresponding to the second power parameter; the second rated operating frequency is lower than the first rated operating frequency.
7. The apparatus according to claim 6, characterized in that, The interrupt response module also includes: The query module is used to execute the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register; The write module is used to execute the SMM callback function to write the function field for configuring memory power to the memory power register; The functional fields include the memory power consumption register address, the Flag bit, and the target power parameter.
8. The apparatus according to claim 6, characterized in that, The power consumption configuration module also includes: The memory operating frequency is gradually configured to the second rated operating frequency according to the gradient. The value of the gradient is preset.
9. The apparatus according to claim 6, characterized in that, The device includes: The function switch setting module is used to set the memory power consumption configuration function switch state in the BIOS before responding to the SMI interrupt; and to execute subsequent steps in response to the SMI interrupt based on the enabled state of the memory power consumption configuration function switch.
10. The apparatus according to claim 7, characterized in that, The device includes: The interrupt source determination module is used to determine whether to execute the SMM callback function for subsequent steps based on the SMI interrupt source before executing the SMM callback function to query the address of the memory power consumption register in the CPU and obtain the Flag bit of the memory power consumption register. If the source of the SMI interrupt is related to the CPU utilization, then continue executing the SMM callback function for subsequent steps; If the SMI interrupt originates from a source unrelated to the CPU utilization, the SMM callback function returns.
11. An electronic device, characterized in that, include: A processor and a readable storage medium storing machine-executable instructions that can be executed by the processor to implement the method of any one of claims 1-5.
12. A readable storage medium, characterized in that, The readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method described in any one of claims 1-5.