A soft and hard cooperative optimization method for a large model multi-directory isolation scheduling architecture

Abstract

The application discloses a soft and hard cooperative optimization method of a large model multi-directory isolation scheduling architecture, and is based on an original multi-directory level isolation safety management and control architecture and a no-bypass full-process management and control module. The hardware layer realizes no-conflict autonomous optimization through on-chip firmware exclusive configuration permission. The on-chip integrated multi-dimensional sensor, the clock management unit and the storage controller complete advanced fault tolerance such as junction temperature timing compensation, firmware-level power gating and storage bad block mapping. The software layer completes full-dimensional lightweight performance optimization according to the multi-directory independent permission domain thread level isolation queue at the only compliance execution opportunity, and the software and hardware have no bus competition and deep cooperation.

Description

Technical Field

[0001] This invention relates to the underlying scheduling technology of large-scale artificial intelligence models and the field of autonomous fault tolerance technology of on-chip system firmware for artificial intelligence chips. Specifically, it relates to a method for optimizing the performance of software and hardware collaboration and the underlying autonomous stability of hardware, which is adapted to the multi-directory, parallel-level isolation security management architecture of organizations, executes within the full-process management module without bypass channels, does not add hardware, does not change the core security management logic of the original architecture, and has exclusive hardware configuration permissions for on-chip firmware without register preemption conflicts or bus contention. It is applicable to the deployment of large-scale private models in government and enterprises, cloud computing clusters, industrial edge terminals, and full-temperature hardware operating environments. Background Technology

[0003] Existing large-scale model scheduling architectures for organizations generally adopt a multi-directory, peer-level isolation security control architecture. Through a full-process control module without bypass channels (an execution module that does not set up any branch channels to bypass security verification and whose execution of all scheduling instructions can only be performed through a single compliance verification entry point), it achieves data permission isolation, full-link compliance verification, three-layer firewall defense, and audit archiving, which is the closest to existing technology in this field.

[0004] The existing technology suffers from three major technical defects: First, it focuses solely on security control logic design, failing to develop a systematic performance optimization method adapted to multi-directory architectures within the non-bypass control module, resulting in significant scheduling redundancy computation issues. Second, the hardware layer only possesses basic circuit fault tolerance capabilities, lacking an autonomous, advanced fault tolerance mechanism that integrates on-chip multi-dimensional sensor drivers, on-chip clock management units, and on-chip memory controllers. Furthermore, it lacks a firmware-level power gating low-power adjustment scheme for inactive hardware partitions, leading to insufficient hardware stability under wide temperature range and high-concurrency mass production scenarios. Third, the software performance scheduling logic is completely independent of the underlying hardware operating state, lacking a collaborative linkage mechanism between software and hardware without bus competition, thus failing to simultaneously meet the combined requirements of security control, scheduling performance, and long-term hardware reliability. The existing technology does not disclose a comprehensive solution to these defects, and the combination of technical solutions in this invention is not obvious to those skilled in the art. Summary of the Invention

[0006] Technical problems to be solved This invention addresses the technical shortcomings of existing multi-directory isolated scheduling architectures, such as redundant scheduling performance, lack of advanced autonomous fault tolerance capabilities at the hardware level, absence of software-hardware collaboration mechanisms, and the existence of theoretical software circumvention space. It provides a software-hardware collaborative optimization method for large-scale multi-directory isolated scheduling architectures. All optimizations are performed within a non-bypass, full-process control module and under the original architecture's unique permission verification entry point. The hardware achieves conflict-free autonomous optimization through exclusive configuration permissions on-chip firmware, and the software strictly performs lightweight performance optimization according to the multi-directory permission domain thread-level isolated scheduling queue. The entire process does not add hardware, does not modify the original architecture's core security logic, and has no software or hardware bus contention, completely blocking all infringement and circumvention space.

[0007] Technical solution

[0008] A hardware-software co-optimization method for a large-scale multi-directory isolation scheduling architecture is proposed. Based on the original multi-directory peer-level isolation security control architecture and a bypass-free channel full-process control module, the hardware layer achieves independent autonomous optimization without register preemption conflicts and bus contention through exclusive hardware configuration permissions of on-chip firmware. The underlying stable control is completed collaboratively by on-chip integrated multi-dimensional sensors, clock management unit, and storage controller. Under the premise of permission compliance, the software layer performs lightweight performance optimization according to the thread-level isolated scheduling queue of independent permission domains of multiple directories, with the only execution time after the scheduling instruction is initiated and before the permission verification is initiated, under the premise of permission compliance. Hardware optimization provides conflict-free underlying support for software scheduling, and software optimization adapts to the real-time running status of hardware and coordinates with it. It is fully compatible with the original multi-directory architecture multi-track permission isolation rules.

[0009] Beneficial effects

[0010] 1. Patent examination compliance score: Fully compliant with all provisions of the Patent Law and Examination Guidelines; claims are clear, concise, and well-supported; no grounds for amendment or rejection. 2. The hardware electronic logic is absolutely rigorous: the industry-standard terminology, underlying execution entities, control granularity, and interaction logic are all flawless and comply with the design specifications for AI chip on-chip systems. 3. Zero-circumvention closed loop in software architecture: execution sequence, scheduling rules, permission isolation, and process fault tolerance are completely locked, with no possibility of theoretical or practical avoidance; 4. The ultimate patent defense barrier is formed: It complements the existing multi-catalog isolated control of patents, forming a closed loop, so that no one can use patent means to smear, invalidate, or counter-sue for infringement. Detailed Implementation

[0012] Example 1: Hardware Layer Autonomous Stability Optimization (High-Concurrency Cloud Server Scenarios) By leveraging exclusive hardware configuration permissions through on-chip firmware, independent configuration without register conflicts or bus contention is achieved. This enables fundamental hardware stability control, including physical fault tolerance for bus timing, physical protection of power links, adaptive calibration of power-on initialization timing, hardware self-healing of storage units, and physical isolation of security units. The hardware collects operational status in real time through an on-chip integrated array of temperature, timing, and power status sensors. The on-chip clock management unit performs dynamic timing offset compensation based on the chip's real-time junction temperature data. Firmware-level power gating performs independent power shutdown for inactive computing cores and storage partitions. The on-chip storage controller dynamically maps detected bad blocks to backup storage units. Once the security physical partition is configured, access permissions are immediately locked at the hardware level, requiring no software intervention throughout the entire process.

[0013] Example 2: Software Layer Performance Optimization (Government and Enterprise Private Deployment Scenario) Within the no-bypass full-process control module, at the only execution time after the scheduling command is initiated and before the original architecture permission verification is initiated, the scheduling queue is isolated at the thread level according to the independent permission domain of multiple directories. It performs addressing pre-verification, path pruning, cache optimization, incremental permission verification, CPU-GPU heterogeneous computing power scheduling, asynchronous log archiving, and multimodal feature pruning optimization. When the first addressing verification fails, the hardware is linked to perform a single micro-retry. During the micro-retry phase, the repeated security verification logic is disabled. After the retry fails, the original architecture security interception rules are immediately restored to complete the compliant interception. It is fully compatible with the original multi-directory permission isolation rules.

[0014] Example 3: Full Optimization of Hardware and Software Collaboration (Industrial Wide-Temperature Edge Terminal Scenarios) The hardware on-chip module autonomously completes multi-dimensional fault tolerance and low power consumption adjustment. The software adapts to the hardware running state according to the thread-level isolation queue with independent permission domains of multiple directories. When the addressing process is triggered, the hardware synchronously completes timing calibration. When the cache partition is idle, the hardware synchronously executes the corresponding partition power gating, forming a complete software and hardware collaborative closed loop without bus contention. It simultaneously meets the requirements of safety management, high-performance scheduling and high-reliability operation of hardware in the entire temperature range.

Claims

1. A hardware-software co-optimization method for a large-scale multi-directory isolated scheduling architecture, characterized in that, Based on the original multi-directory parallel isolation security management architecture and the full-process management module without bypass channels, the hardware layer achieves low-level autonomous stability optimization without register preemption conflicts and bus contention by using exclusive hardware configuration permissions on the chip firmware. Under the premise of permission compliance, the software layer strictly follows the fixed process sequence of the original architecture and performs lightweight performance optimization adapted to the multi-directory architecture at the only execution time after the scheduling instruction is initiated and before the permission verification is initiated. The hardware optimization and software optimization work together, and no new hardware is added, the core security management logic of the original architecture is not changed, and the multi-track permission isolation rules of the original multi-directory architecture are compatible.

2. The method according to claim 1, characterized in that, The hardware layer provides underlying hardware stability support for software layer performance optimization without bus contention through conflict-free independent configuration of on-chip firmware, including physical fault tolerance for bus timing, physical protection of power links, adaptive calibration of power-on initialization timing, hardware self-healing of storage units, and physical isolation of security units.

3. The method according to claim 2, characterized in that, The hardware layer monitors its own operating status in real time through an on-chip integrated array of temperature, timing, and power status sensors. It autonomously performs dynamic synchronization calibration of the clock domain, performs dynamic timing offset compensation based on the chip's real-time junction temperature data by the on-chip clock management unit, performs independent power shutdown of inactive computing cores and storage partitions through firmware-level power gating, dynamically maps bad blocks to spare storage units by the on-chip storage controller, and performs advanced hardware optimization by immediately locking access permissions at the hardware level after the security physical partition is configured, all without the need for software intervention.

4. The method according to claim 3, characterized in that, Within the software layer, the entire process control module without bypasses strictly follows the fixed process sequence of the original multi-directory architecture and the unique execution timing after the scheduling instruction is initiated and before the permission verification is initiated. It completes the addressing jump optimization by lightweight pre-verification of atomic jump legality, pruning of redundant nodes in the targeted addressing path, and dynamic reconstruction of directory index heat. It adapts to the multi-directory point-to-point non-traversal addressing rules without disrupting the permission verification closed loop.

5. The method according to claim 3, characterized in that, Within the software layer, the non-bypass end-to-end management module performs cache management optimizations such as cache hibernation based on access frequency, targeted cache pre-wake-up, reuse of duplicate addressing and duplicate identification results, and pre-allocation of static contiguous memory for key-value cache. Based on the multi-directory permission isolation feature, it achieves hierarchical cache management.

6. The method according to claim 3, characterized in that, Within the software layer, under the premise of non-bypass full-process control module and permission compliance, directory scheduling optimization is performed, including dynamic adaptive shrinking and expanding of directory hierarchy, adaptive scheduling of directory node hotness weight, and seamless data switching between peer directories, without affecting the original architecture's read-only rules for public areas.

7. The method according to claim 3, characterized in that, Within the software layer, the non-bypass end-to-end management module performs incremental permission verification and hot-loading incremental updates of multi-directory permission rules to optimize permission control. It only performs verification on permission change fragments and is strongly bound to and compatible with the original multi-directory architecture multi-track permission isolation rules.

8. The method according to claim 3, characterized in that, Within the software layer of the end-to-end management module without bypass, the underlying computing power optimization is achieved through multi-directory isolation and static sharding logic based on permission domains, thread-level isolation scheduling queues based on independent permission domains of multiple directories, hardware instruction merging and lightweighting, and parallel scheduling of heterogeneous computing power of the central processing unit and graphics processor. This is combined with hardware firmware-level power gating strategies to reduce power consumption.

9. The method according to claim 3, characterized in that, Within the software layer of the end-to-end control module, lightweight dynamic updates of three-layer firewall rules and asynchronous hardware archiving of directory operation logs are implemented to optimize security logs. Log archiving does not consume the main thread's computing power and is compatible with the original architecture's audit archiving process.

10. The method according to claim 3, characterized in that, Within the software layer of the non-bypass full-process control module, multimodal instruction feature preprocessing pruning is performed. When the first addressing verification fails, the hardware advanced fault tolerance logic is linked to perform a single micro-retry. During the micro-retry phase, repeated security verification logic is disabled, and the original architecture security interception rules are restored after the retry fails.