Capacitance configuration method, device and equipment of power distribution network, and storage medium
By establishing an equivalent circuit model of the power distribution network and optimizing the number of decoupling capacitors, the problems of capacitor waste and layout difficulties in the power distribution network are solved, achieving a balance between cost-effectiveness and electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LCFC HEFEI ELECTRONICS TECH
- Filing Date
- 2026-02-02
- Publication Date
- 2026-06-05
Smart Images
Figure CN122154172A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and in particular to a capacitor configuration method, apparatus, device, and storage medium for a power distribution network. Background Technology
[0002] Currently, in the design process of power distribution networks, it is generally believed that the more decoupling capacitors around the integrated circuit (IC) the better. Device manufacturers also often require the addition of a large number of capacitors to the power supply pins, which leads to the prominent problem of over-design of decoupling capacitors. Excessive use of capacitors not only brings meaningless cost expenditures, but also easily leads to corresponding layout and routing difficulties. Summary of the Invention
[0003] This disclosure provides a capacitor configuration method, apparatus, device, and storage medium for a power distribution network, to at least solve the above-mentioned technical problems existing in the prior art.
[0004] A first aspect of this disclosure provides a capacitor configuration method for a power distribution network, the method comprising:
[0005] The equivalent circuit model of the power distribution network to be configured is determined based on the operating parameters of the target chip. The power distribution network to be configured is a power distribution network without the target capacitor, and the target capacitor is the decoupling capacitor on the board. The target capacitor circuit corresponding to the equivalent circuit model is determined by a preset capacitor configuration model. The target capacitor circuit is a circuit composed of at least the target capacitor. The capacitor configuration model is constructed according to a preset objective function and constraints. The cost of the target capacitor circuit is determined by the objective function. The constraints characterize the electrical performance that the target capacitor circuit needs to meet. After adding the target capacitor circuit to the equivalent circuit model, impedance simulation is performed. The target power distribution network is obtained based on the simulation results. The target power distribution network is the distribution network with the target capacitor added.
[0006] In one possible implementation, before determining the target capacitor circuit corresponding to the equivalent circuit model using a preset capacitor configuration model, the method further includes: Determine the corresponding objective function based on the preset minimum capacitor cost target; The corresponding constraints are determined based on the impedance relationship between the target decoupling capacitor impedance and the total impedance of the equivalent circuit model and the target impedance. Generate the corresponding capacitor configuration model based on the objective function and the constraints.
[0007] In one possible implementation, the constraint is that the total impedance of the decoupling capacitor and the equivalent circuit model connected in parallel on the decoupling frequency band is less than the target impedance.
[0008] In one possible implementation, determining the equivalent circuit model of the power distribution network to be configured based on the operating parameters of the target chip includes: Determine the target impedance corresponding to the decoupling frequency band based on the operating parameters of the target chip; In response to the DC impedance of the power distribution network to be configured being lower than or equal to the target impedance, frequency domain impedance simulation is performed on the power distribution network to be configured, and the target network parameters are determined based on the frequency domain impedance simulation results. An equivalent circuit model of the power distribution network to be configured is generated based on the target network parameters.
[0009] In one possible implementation, in response to the DC impedance of the power distribution network to be configured being higher than the target impedance, the method further includes: The power distribution network to be configured is optimized until the DC impedance is lower than the target impedance.
[0010] In one possible implementation, adding the target capacitor circuit to the equivalent circuit model includes: Determine the location where the target capacitor circuit will be added in the equivalent circuit model; Based on the requirements of the capacitor mounting component, the target capacitor circuit is added to the corresponding addition position of the equivalent circuit model to obtain the initial power distribution network model. Impedance simulation was performed on the initial power distribution network to obtain simulation results.
[0011] In one possible implementation, obtaining the target capacitor circuit based on simulation results includes: The impedance curve obtained by impedance simulation of the initial power distribution network is compared with the target impedance. In response to the fact that the impedance at each frequency point within the decoupling band is lower than the target impedance, the initial power distribution network is used as the target power distribution network.
[0012] A second aspect of this disclosure provides a capacitor configuration device for a power distribution network, the device comprising: The equivalent circuit model determination module is used to determine the equivalent circuit model of the power distribution network to be configured based on the operating parameters of the target chip. The power distribution network to be configured is a power distribution network without the target capacitor, and the target capacitor is a decoupling capacitor on the board. A capacitor combination determination module is used to determine the target capacitor circuit corresponding to the equivalent circuit model through a preset capacitor configuration model. The target capacitor circuit is a circuit composed of at least the target capacitor. The capacitor configuration model is constructed according to a preset objective function and constraints. The cost of the target capacitor circuit is determined by the objective function. The constraints characterize the electrical performance that the target capacitor circuit needs to meet. The target capacitor determination module is used to add the target capacitor circuit to the equivalent circuit model and perform impedance simulation. Based on the simulation results, the target power distribution network is obtained, which is the distribution network with the target capacitor added.
[0013] A third aspect of this disclosure provides an electronic device, characterized in that it comprises: At least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the capacitor configuration method of the power distribution network described in any of the preceding claims.
[0014] A fourth aspect of this disclosure provides a computer-readable storage medium storing a computer program for performing the capacitor configuration method of the power distribution network described in any of the preceding claims.
[0015] This disclosure discloses a capacitor configuration method for a power distribution network. It establishes an equivalent circuit model of the power distribution network without on-board decoupling capacitors, and then determines the target capacitor circuit corresponding to the equivalent circuit model based on solving constraints and an objective function. The objective function is established with the goal of meeting the cost requirements of on-board decoupling capacitors, optimizing the number of decoupling capacitors and avoiding cost waste due to over-design. The constraints are established with the goal of ensuring the impedance of the on-board decoupling capacitors meets electrical performance requirements, ensuring that while saving capacitor costs, the configured capacitors still meet actual impedance requirements. Impedance simulation of the equivalent circuit model with the target capacitor circuit is performed to further verify whether the target capacitor circuit meets the requirements, ensuring that the final target power distribution network achieves ideal decoupling effect without over-design.
[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0017] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
[0018] Figure 1 This illustration shows a schematic flow diagram of the implementation of a capacitor configuration method for a power distribution network according to an embodiment of the present disclosure. Figure 1 ; Figure 2 A schematic diagram of the structure of a power distribution network to be configured according to an embodiment of the present disclosure is shown; Figure 3 This diagram illustrates a structural schematic of an equivalent circuit model connected to a target capacitor circuit according to an embodiment of the present disclosure. Figure 4 A schematic diagram of the structure of a target power distribution network according to an embodiment of the present disclosure is shown; Figure 5 A schematic diagram of a capacitor configuration device for a power distribution network according to an embodiment of the present disclosure is shown. Figure 6 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation
[0019] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0020] This disclosure provides a capacitor configuration method for a power distribution network, such as... Figure 1 As shown, the method includes: S101. Determine the equivalent circuit model of the power distribution network to be configured based on the operating parameters of the target chip. The power distribution network to be configured is the power distribution network without the target capacitor, and the target capacitor is the decoupling capacitor on the board.
[0021] In this step, the target chip is the chip to be configured with the target capacitor. The power distribution network (PDN) to be configured is the actual hardware structure that supplies power to the target chip and is also the mounting carrier for the target capacitor. It includes a voltage regulator module, a planar capacitor module, a chip packaging module, and a chip decoupling capacitor module.
[0022] like Figure 2As shown, the voltage regulator module VRM is a combination of a series resistor and an inductor, and the voltage regulator module can be equivalently modeled as a series-connected voltage regulator resistor Rvrm and voltage regulator inductor Lvrm. The values of the voltage regulator resistor and voltage regulator inductor can be obtained from the VRM manufacturer. The planar capacitor module includes a series-connected planar equivalent capacitor Cpl and equivalent resistor Rpl. The first terminal of the planar equivalent capacitor Cpl (the terminal not connected to the voltage regulator resistor Rvrm) is connected to the first terminal of the voltage regulator resistor Rvrm (the terminal not connected to the voltage regulator inductor Lvrm), and the first terminal of the equivalent resistor Rpl (the terminal not connected to the planar equivalent capacitor Cpl) is connected to the first terminal of the voltage regulator inductor Lvrm (the terminal not connected to the voltage regulator resistor Rvrm).
[0023] In addition, the chip packaging module includes an equivalent inductance Lp, an equivalent resistance Rp, a trace parasitic inductance Lsv, and a trace parasitic resistance Rsv for the packaging leads, as well as a chip decoupling capacitor Cpkg and its corresponding equivalent series inductance Lpkg and equivalent series resistance Rpkg. Specifically, the trace parasitic resistance Rsv, trace parasitic inductance Lsv, equivalent resistance Rp, and equivalent inductance Lp are connected in series sequentially. The end of the equivalent inductance Lp not connected to the equivalent resistance Rp is connected to the first end of the equivalent series inductance Lpkg. The second end of the equivalent series inductance Lpkg is connected to the first end of the chip decoupling capacitor Cpkg. The second end of the chip decoupling capacitor Cpkg is connected to the first end of the equivalent series resistance Rpkg. The second end of the equivalent series resistance Rpkg is connected to the first end of the voltage regulator resistor Rvrm. The end of the trace parasitic resistance Rsv not connected to the trace parasitic inductance Lsv is connected to the first end of the voltage regulator inductance Lvrm.
[0024] The chip decoupling capacitor module includes a chip decoupling capacitor Cchp and an equivalent series resistance Rchp connected in series. The end of the chip decoupling capacitor Cchp that is not connected to the equivalent series resistance Rchp is connected to the first end of the equivalent series inductance Lpkg, and the end of the equivalent series resistance Rchp that is not connected to the chip decoupling capacitor Cchp is connected to the second end of the equivalent series resistance Rpkg.
[0025] Therefore, the power distribution network to be configured in this step includes all components used to supply power to the target chip, except for the on-board decoupling capacitors. These components are typically inherent to the chip manufacturer and cannot be modified by the user, while the on-board decoupling capacitors refer to the capacitors that are to be configured and can be selected by the user. Since the inherent impedance of the power distribution network itself cannot meet the target impedance requirements of the target chip, it is necessary to determine the corresponding on-board decoupling capacitors to meet the impedance requirements of the target chip.
[0026] The equivalent circuit model in this step involves impedance simulation of the power distribution network to be configured using simulation tools, including the measurement of S-parameters to obtain the S-parameters of the PCB. The simulation tools then convert the single-ended passive network parameters (S-parameters) into the equivalent circuit model of the power distribution network to be configured. The S-parameters characterize the frequency domain impedance of the power distribution network to be configured. The simulation tools extract the S-parameters and convert them into an equivalent circuit model to provide a reference basis for the subsequent selection of the target capacitor.
[0027] S102. Determine the target capacitor circuit corresponding to the equivalent circuit model through the preset capacitor configuration model. The target capacitor circuit is a circuit composed of at least the target capacitor. The capacitor configuration model is constructed according to the preset objective function and constraints. The cost of the target capacitor circuit is determined by the objective function. The constraints characterize the electrical performance that the target capacitor circuit needs to meet.
[0028] In this step, the capacitor configuration model is constructed based on a preset objective function and constraints. Solving this capacitor configuration model using the objective algorithm determines the corresponding target capacitor circuit. One capacitor unit in the target capacitor circuit can be modeled as a series circuit of on-board decoupling capacitor, equivalent series inductor, equivalent series resistance, and mounting inductor. The target capacitor circuit is a circuit formed by multiple capacitor units connected in parallel, and the actual capacitor parameters can be obtained from the manufacturer.
[0029] It should be noted that in this step, the objective function is established based on the premise that the cost of the target capacitor circuit meets the preset target, to prevent over-design of capacitors and resulting in wasted costs. Constraints are also established based on the premise that the electrical performance of the target capacitor circuit meets the electrical performance requirements, ensuring that the decoupling effect of the target capacitor circuit meets the chip's operational needs. The capacitor configuration model established based on the objective function and constraints is solved using a particle swarm optimization algorithm. This allows the selection of the configuration scheme that minimizes the objective function value among all capacitor configuration schemes that satisfy the constraints, thereby determining the number of decoupling capacitors to be added to the board, thus obtaining the target capacitor circuit that meets the requirements.
[0030] S103. After adding the target capacitor circuit to the equivalent circuit model, perform impedance simulation. Based on the simulation results, obtain the target power distribution network, which is the distribution network with the target capacitor added.
[0031] In this step, the target capacitor circuit obtained in step S102 is added to the corresponding position in the equivalent circuit model, such as... Figure 3As shown, impedance simulation is performed on the equivalent circuit model with the target capacitor circuit added to determine whether the target capacitor circuit is the optimal capacitor circuit. Specifically, by performing frequency domain impedance analysis on the equivalent circuit model with the target capacitor circuit added, the total impedance after connecting the target capacitor circuit and the equivalent circuit model in parallel is verified to meet the impedance requirements, thus achieving closed-loop verification of the overall design.
[0032] This disclosure discloses a capacitor configuration method for a power distribution network. It establishes an equivalent circuit model of the power distribution network without on-board decoupling capacitors, and then determines the target capacitor circuit corresponding to the equivalent circuit model based on solving constraints and an objective function. The objective function is established with the goal of meeting the cost requirements of on-board decoupling capacitors, optimizing the number of decoupling capacitors and avoiding cost waste due to over-design. The constraints are established with the goal of ensuring the impedance of the on-board decoupling capacitors meets electrical performance requirements, ensuring that while saving capacitor costs, the configured capacitors still meet actual impedance requirements. Impedance simulation is then performed on the equivalent circuit model with the target capacitor circuit added to further verify whether the target capacitor circuit meets the requirements, ensuring that the final target power distribution network achieves ideal decoupling effect without over-design.
[0033] In one possible implementation, before determining the target capacitor circuit corresponding to the equivalent circuit model through a preset capacitor configuration model, the method further includes: Determine the corresponding objective function based on the preset minimum capacitor cost target; The corresponding constraints are determined based on the impedance relationship between the target decoupling capacitor impedance and the total impedance of the equivalent circuit model and the target impedance. Generate the corresponding capacitor configuration model based on the objective function and constraints.
[0034] In this embodiment, an objective function is established with the goal of minimizing the total cost of the decoupling capacitors on the board. The objective function is as follows:
[0035] In the formula, The number of type i capacitors. This is the unit price of type i capacitors.
[0036] Furthermore, this embodiment determines the corresponding constraints based on the impedance relationship between the target decoupling capacitor impedance and the total impedance of the equivalent circuit model and the target impedance. It should be noted that the constraints in this embodiment refer to the requirement that regardless of the final configuration of the target capacitor circuit obtained by solving the model, the total impedance of the target capacitor circuit connected in parallel with the equivalent circuit model must be lower than the target impedance. After constructing the capacitor configuration model based on the objective function and constraints, the target capacitor circuit that satisfies both cost and impedance requirements can be determined by solving this model.
[0037] It should be noted that the objective function and constraints exist as known, pre-defined input conditions when constructing the capacitor configuration model. The essence of solving the capacitor configuration model using the particle swarm optimization algorithm is to determine the configuration scheme that minimizes the objective function value among all capacitor configuration schemes that satisfy the constraints, thus obtaining the corresponding target capacitor circuit.
[0038] In one possible implementation, the constraint is that the total impedance of the decoupling capacitor and the equivalent circuit model connected in parallel on the decoupling frequency band is less than the target impedance.
[0039] In this embodiment, the constraints are as follows:
[0040] In the formula, In frequency The target impedance at that location, This is the total impedance of the decoupling capacitors on the board. The total impedance of the equivalent circuit model is given by n, which represents the constraint conditions being checked at a+1 frequency points, where a+1 frequency points are the decoupling frequency bands. The selected frequency points.
[0041] The constraint in this embodiment is that it is in the decoupling frequency band. Within this network, a+1 frequency points are selected, and each frequency point must meet the aforementioned impedance requirements. Specifically, for each frequency point, the overall total impedance of the equivalent circuit model after adding the on-board decoupling capacitors needs to be less than the target impedance for that frequency point. This ensures that the electrical performance of the final power distribution network meets the electrical requirements of the target chip. The total impedance of the on-board decoupling capacitors is as follows:
[0042] In the formula, This is one of the on-board decoupling capacitors in the target capacitor circuit. To and Equivalent series resistance in series To and Equivalent series inductance in series, To and Series-connected inductors.
[0043] It should be noted that the target capacitor circuit includes several on-board decoupling capacitors. The number of on-board decoupling capacitors is the number that minimizes the total cost of the on-board decoupling capacitors while ensuring that the total resistance within the decoupling frequency band is lower than the target impedance. That is, optimization algorithms (such as Particle Swarm Optimization (PSO) generate multiple candidate target capacitor circuits during the solution process. Each candidate target capacitor circuit corresponds to a set of values [m1, m2, m3, ...]. For each candidate target capacitor circuit, the cost of all on-board decoupling capacitors in that circuit is calculated. , and then with Parallel connection is used to determine if the total impedance meets the above constraints. Candidate target capacitor circuits that do not meet the constraints are eliminated. For the candidate target capacitor circuits that meet the constraints, their total cost (COST) is calculated. The candidate target capacitor circuit with the lowest total cost is selected as the final target capacitor circuit. The corresponding values [m1, m2, m3, ...] are the final determined number of decoupling capacitors on the board. Furthermore, the determined decoupling capacitors on the board are connected in parallel, with each decoupling capacitor connected in series with a mounting inductor. Install inductors Specific parameters can be obtained from the manufacturer. That is, the decoupling capacitors and corresponding mounting inductors on each board. The series circuits are then connected in parallel to obtain the final target capacitor circuit.
[0044] Therefore, this embodiment establishes an objective function with the goal of minimizing the cost of decoupling capacitors when determining the number of decoupling capacitors on the board, thereby optimizing the number of decoupling capacitors. Compared with related technologies that connect too many decoupling capacitors in parallel around the target chip to improve power quality, this embodiment can prevent over-design of capacitors while ensuring that the impedance of the power distribution network meets the requirements.
[0045] In one possible implementation, the equivalent circuit model of the power distribution network to be configured is determined based on the operating parameters of the target chip, including: Determine the target impedance corresponding to the decoupling frequency band based on the operating parameters of the target chip; In response to the DC impedance of the power distribution network to be configured being lower than or equal to the target impedance, frequency domain impedance simulation is performed on the power distribution network to be configured, and the target network parameters are determined based on the frequency domain impedance simulation results. Generate an equivalent circuit model of the power distribution network to be configured based on the target network parameters.
[0046] In this embodiment, the operating parameters of the target chip refer to the actual electrical conditions of the target chip, including supply voltage, clock frequency, noise spectrum, maximum instantaneous current, etc., and the corresponding decoupling frequency band is determined based on these parameters. and the acceptable target impedance within the decoupling frequency band. This refers to the maximum impedance value. The frequency range requiring decoupling is determined based on the target chip's clock frequency and noise spectrum. The corresponding target impedance is determined based on the target chip's voltage tolerance and maximum current fluctuation. .
[0047] Furthermore, using simulation tools such as ADS, the DC impedance of the power distribution network to be configured without the added on-board decoupling capacitors is simulated. If the DC impedance simulation result is lower than or equal to the target impedance, it indicates that the DC power supply path of the power distribution network to be configured without the added on-board decoupling capacitors has no resistance bottleneck, and the DC voltage drop is less than or equal to the maximum allowable power supply ripple voltage of the target chip, which meets the DC power supply baseline requirements of the target chip. This provides the necessary prerequisites for subsequent frequency domain impedance simulation, equivalent circuit model construction, and high-frequency impedance optimization of the on-board decoupling capacitors.
[0048] In one possible implementation, in response to the DC impedance of the power distribution network to be configured being higher than the target impedance, the method further includes: Optimize the power distribution network to be configured until the DC impedance is lower than the target impedance.
[0049] In this embodiment, if the DC impedance of the power distribution network to be configured is higher than the target impedance, it indicates that there is a problem with the DC path of the power distribution network to be configured, such as excessively high trace resistance. In this case, the PCB layout needs to be optimized, such as widening the traces, so that the DC impedance is lower than the target impedance, thereby ensuring that the DC power supply path of the power distribution network to be configured meets the requirements.
[0050] In one possible implementation, adding the target capacitor circuit to the equivalent circuit model includes: Determine the location to add the target capacitor circuit in the equivalent circuit model; Based on the requirements of capacitor mounting, the target capacitor circuit is added to the corresponding addition position in the equivalent circuit model to obtain the initial power distribution network model. Impedance simulation was performed on the initial power distribution network, and the simulation results were obtained.
[0051] In this embodiment, when adding the target capacitor circuit to the equivalent circuit model, it is first necessary to determine the position of the target capacitor circuit in the equivalent circuit model. In this embodiment, the target capacitor circuit is connected in parallel between the voltage regulator module and the planar capacitor module in the equivalent circuit model.
[0052] It should be noted that in the equivalent circuit of this embodiment, the first terminal of the voltage regulator module is connected to the first terminal of the planar capacitor module, the second terminal of the voltage regulator module is connected to the second terminal of the planar capacitor module, and the first terminal of the target capacitor circuit is connected in the same path as the first terminals of the voltage regulator module and the planar capacitor module. Correspondingly, the second terminal of the target capacitor circuit is connected in the same path as the second terminals of the voltage regulator module and the planar capacitor module. That is, the voltage regulator module, the target capacitor circuit, and the planar capacitor module are connected in parallel.
[0053] In addition, the method for adding the target capacitor circuit to the equivalent circuit model is further determined based on the requirements of the capacitor components. Different types of capacitors may have differences in capacitance and packaging. To effectively transfer energy, for on-board decoupling capacitors, the smaller the capacitance value, the closer the mounting position should be to the target chip, preferably between λ / 40 and λ / 50, where λ is the wavelength corresponding to the capacitor's resonant frequency. Simultaneously, when paralleling the target capacitor circuit into the equivalent circuit model, the actual routing and vias on the PCB need to be considered. Specifically, it is necessary to ensure that the power pins and ground pins (GND pins) of the on-board decoupling capacitors have sufficient return vias close to their respective pads, and to use wider connection traces and larger via diameters to reduce parasitic inductance. For example, the connection trace width is typically not less than 0.2 mm (approximately 8 mil), and the via diameter is typically not less than 0.3 mm (approximately 12 mil).
[0054] Based on the above requirements for capacitor mounting, after adding the target capacitor circuit to the equivalent circuit model, impedance simulation is performed on the obtained initial power distribution network to determine the final decoupling capacitor configuration scheme and verify whether the impedance of the initial power distribution network meets the actual requirements. If not, the combination or layout of the corresponding target capacitor circuit is further adjusted, and impedance simulation is performed again to obtain the target capacitor circuit that meets the actual requirements.
[0055] In one possible implementation, the target capacitor circuit is obtained based on simulation results, including: The impedance curve obtained by impedance simulation of the initial power distribution network is compared with the target impedance. Since the impedance at each frequency point within the decoupling band is lower than the target impedance, the initial power distribution network is used as the target power distribution network.
[0056] In this embodiment, impedance simulation of the initial power distribution network configured with the target capacitor circuit is performed using simulation tools to obtain the corresponding impedance curve. Accordingly, the impedance in the decoupling frequency band is verified. Within the impedance curve, is the impedance at each frequency point lower than the target impedance? If all are below the target impedance Then the initial power distribution network is the final target power distribution network, such as... Figure 4 As shown, the target capacitor circuit configured on it can reduce the amount of decoupling capacitors used on the board, reduce production and maintenance costs, and meet the actual impedance requirements of the target chip.
[0057] In summary, the method disclosed herein can achieve impedance optimization of power distribution networks based on low decoupling capacitor costs, without the need for repeated simulations and adjustments. It allows for the direct quantitative selection of various types of decoupling capacitors based on the optimized scheme, ensuring ideal decoupling performance without over-design.
[0058] To implement the above method, one example of this application also provides a capacitor configuration device 500 for a power distribution network, such as... Figure 5 As shown, the device includes: The equivalent circuit model determination module 501 is used to determine the equivalent circuit model of the power distribution network to be configured based on the operating parameters of the target chip. The power distribution network to be configured is the power distribution network without the target capacitor, and the target capacitor is the decoupling capacitor on the board. The capacitor combination determination module 502 is used to determine the target capacitor circuit corresponding to the equivalent circuit model through a preset capacitor configuration model. The target capacitor circuit is a circuit composed of at least the target capacitor. The capacitor configuration model is constructed according to the preset objective function and constraints. The cost of the target capacitor circuit is determined by the objective function. The constraints characterize the electrical performance that the target capacitor circuit needs to meet. The target capacitor determination module 503 is used to add the target capacitor circuit to the equivalent circuit model and perform impedance simulation. Based on the simulation results, the target power distribution network is obtained, which is the distribution network with the target capacitor added.
[0059] In one possible implementation, a model building module is also included, which is used to determine the corresponding objective function based on a preset minimum capacitor cost target; The corresponding constraints are determined based on the impedance relationship between the target decoupling capacitor impedance and the total impedance of the equivalent circuit model and the target impedance. Generate the corresponding capacitor configuration model based on the objective function and constraints.
[0060] In one possible implementation, the constraint is that the total impedance of the decoupling capacitor and the equivalent circuit model connected in parallel on the decoupling frequency band is less than the target impedance.
[0061] In one embodiment, the equivalent circuit model determination module 501 is further configured to determine the target impedance corresponding to the decoupling frequency band based on the operating parameters of the target chip. In response to the DC impedance of the power distribution network to be configured being lower than or equal to the target impedance, frequency domain impedance simulation is performed on the power distribution network to be configured, and the target network parameters are determined based on the frequency domain impedance simulation results. Generate an equivalent circuit model of the power distribution network to be configured based on the target network parameters.
[0062] In one embodiment, in response to the DC impedance of the power distribution network to be configured being higher than the target impedance, the equivalent circuit model determination module 501 is further configured to optimize the power distribution network to be configured until the DC impedance is lower than the target impedance.
[0063] In one possible implementation, the target capacitor determination module 503 is used to determine the addition position of the target capacitor circuit in the equivalent circuit model. Based on the requirements of capacitor mounting, the target capacitor circuit is added to the corresponding addition position in the equivalent circuit model to obtain the initial power distribution network model. Impedance simulation was performed on the initial power distribution network, and the simulation results were obtained.
[0064] In one embodiment, the target capacitance determination module 503 is further configured to compare the impedance curve obtained by impedance simulation of the initial power distribution network with the target impedance. Since the impedance at each frequency point within the decoupling band is lower than the target impedance, the initial power distribution network is used as the target power distribution network.
[0065] By way of example, this application also provides an electronic device, including: processor; Memory used to store processor-executable instructions; A processor is used to read executable instructions from memory and execute the instructions to implement the capacitor configuration method of the power distribution network described above.
[0066] By way of example, this application also provides a computer-readable storage medium storing a computer program for performing the capacitor configuration method of the power distribution network described above.
[0067] Figure 6A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0068] like Figure 6 As shown, device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 602 or a computer program loaded from storage unit 608 into random access memory (RAM) 603. RAM 603 may also store various programs and data required for the operation of device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.
[0069] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of monitors, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0070] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as a capacitor configuration method for a power distribution network. For example, in some embodiments, a capacitor configuration method for a power distribution network can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the capacitor configuration method for a power distribution network described above can be performed. Alternatively, in other embodiments, the computing unit 601 may be configured by any other suitable means (e.g., by means of firmware) to perform a capacitor configuration method for a power distribution network.
[0071] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0072] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0073] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0074] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0075] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.
[0076] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.
[0077] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.
[0079] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A capacitor configuration method for a power distribution network, characterized in that, The method includes: The equivalent circuit model of the power distribution network to be configured is determined based on the operating parameters of the target chip. The power distribution network to be configured is a power distribution network without the target capacitor, and the target capacitor is the decoupling capacitor on the board. The target capacitor circuit corresponding to the equivalent circuit model is determined by a preset capacitor configuration model. The target capacitor circuit is a circuit composed of at least the target capacitor. The capacitor configuration model is constructed according to a preset objective function and constraints. The cost of the target capacitor circuit is determined by the objective function. The constraints characterize the electrical performance that the target capacitor circuit needs to meet. After adding the target capacitor circuit to the equivalent circuit model, impedance simulation is performed. The target power distribution network is obtained based on the simulation results. The target power distribution network is the distribution network with the target capacitor added.
2. The capacitor configuration method for a power distribution network according to claim 1, characterized in that, Before determining the target capacitor circuit corresponding to the equivalent circuit model through a preset capacitor configuration model, the method further includes: Determine the corresponding objective function based on the preset minimum capacitor cost target; The corresponding constraints are determined based on the impedance relationship between the target decoupling capacitor impedance and the total impedance of the equivalent circuit model and the target impedance. Generate the corresponding capacitor configuration model based on the objective function and the constraints.
3. The method for configuring decoupling capacitors in a power distribution network according to claim 2, characterized in that, The constraint condition is that the total impedance of the decoupling capacitor and the equivalent circuit model connected in parallel on the decoupling frequency band is less than the target impedance.
4. The capacitor configuration method for a power distribution network according to claim 1, characterized in that, The step of determining the equivalent circuit model of the power distribution network to be configured based on the operating parameters of the target chip includes: Determine the target impedance corresponding to the decoupling frequency band based on the operating parameters of the target chip; In response to the DC impedance of the power distribution network to be configured being lower than or equal to the target impedance, frequency domain impedance simulation is performed on the power distribution network to be configured, and the target network parameters are determined based on the frequency domain impedance simulation results. An equivalent circuit model of the power distribution network to be configured is generated based on the target network parameters.
5. The capacitor configuration method for a power distribution network according to claim 4, characterized in that, In response to the DC impedance of the power distribution network to be configured being higher than the target impedance, the method further includes: The power distribution network to be configured is optimized until the DC impedance is lower than the target impedance.
6. The capacitor configuration method for a power distribution network according to claim 1, characterized in that, Adding the target capacitor circuit to the equivalent circuit model includes: Determine the location where the target capacitor circuit will be added in the equivalent circuit model; Based on the requirements of the capacitor mounting component, the target capacitor circuit is added to the corresponding addition position of the equivalent circuit model to obtain the initial power distribution network model. Impedance simulation was performed on the initial power distribution network to obtain simulation results.
7. The capacitor configuration method for a power distribution network according to claim 6, characterized in that, The process of obtaining the target capacitor circuit based on simulation results includes: The impedance curve obtained by impedance simulation of the initial power distribution network is compared with the target impedance. In response to the fact that the impedance at each frequency point within the decoupling band is lower than the target impedance, the initial power distribution network is used as the target power distribution network.
8. A capacitor configuration device for a power distribution network, characterized in that, The device includes: The equivalent circuit model determination module is used to determine the equivalent circuit model of the power distribution network to be configured based on the operating parameters of the target chip. The power distribution network to be configured is a power distribution network without the target capacitor, and the target capacitor is a decoupling capacitor on the board. A capacitor combination determination module is used to determine the target capacitor circuit corresponding to the equivalent circuit model through a preset capacitor configuration model. The target capacitor circuit is a circuit composed of at least the target capacitor. The capacitor configuration model is constructed according to a preset objective function and constraints. The cost of the target capacitor circuit is determined by the objective function. The constraints characterize the electrical performance that the target capacitor circuit needs to meet. The target capacitor determination module is used to add the target capacitor circuit to the equivalent circuit model and perform impedance simulation. Based on the simulation results, the target power distribution network is obtained, which is the distribution network with the target capacitor added.
9. An electronic device, characterized in that, include: At least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform claim 1. The capacitor configuration method for the power distribution network as described in any one of the 7.
10. A computer-readable storage medium storing a computer program for performing the capacitor configuration method of a power distribution network according to any one of claims 1-7.