Chip configuration method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a chip configuration method and device, electronic equipment and storage medium, which relates to the field of chips, and the main technical features include: determining an error value based on the hardware environment difference between a target test platform and a target product board; obtaining the minimum working voltage change of the chip before and after testing; wherein the error value and the minimum working voltage before and after testing are obtained based on the target test case matching the target application scenario; and configuring the working parameters of the chip on the target product board based on the error value and the minimum working voltage change.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a method and apparatus for configuring a chip, an electronic device, and a storage medium. Background Technology

[0002] In system-level applications of chips, in order to ensure stable operation of the chip throughout its entire life cycle, it is usually necessary to configure the chip's operating parameters: an additional voltage protection band is set on top of the reference operating voltage to offset the chip performance degradation caused by factors such as device aging.

[0003] Currently, related technologies typically use high-temperature operating life (HTOL) accelerated aging tests to simulate the full lifecycle degradation of chips, and employ automated testing equipment to collect minimum operating voltage data of the chip before and after aging to determine the voltage protection band. However, the voltage protection band determined by this method has errors compared to actual application requirements, thus reducing the accuracy of chip operating parameter configuration. Summary of the Invention

[0004] This disclosure provides a chip configuration method and apparatus, an electronic device, and a storage medium. Its main objective is to address the problem of low configuration accuracy of chip operating parameters in the prior art.

[0005] According to a first aspect of this disclosure, a method for configuring a chip is provided, comprising:

[0006] The error value is determined based on the hardware environment differences between the target test platform and the target product board. Obtain the minimum operating voltage change of the chip before and after the test; wherein the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario; Based on the error value and the minimum operating voltage variation, configure the operating parameters of the chip on the target product board.

[0007] In some embodiments, obtaining the minimum operating voltage change of the chip before and after the test includes: Based on the target test cases, the minimum operating voltage of the chip before accelerated aging and the minimum operating voltage after accelerated aging were tested respectively. The change in minimum operating voltage is determined based on the difference between the minimum operating voltage after accelerated aging and the minimum operating voltage before accelerated aging.

[0008] In some embodiments, determining the error value based on the hardware environment differences between the target test platform and the target product board includes: The minimum operating voltage of the unaged chip is tested on the target test platform and the target product board using the target test cases. The error value is determined based on the difference between the minimum operating voltage measured on the target product board and the minimum operating voltage measured on the target test platform.

[0009] In some embodiments, before determining the error value based on the hardware environment differences between the target test platform and the target product board, the method further includes: Based on the workload characteristics of the chip on the target product board, the target test cases that match the target application scenario are determined.

[0010] In some embodiments, configuring the operating parameters of the chip on the target product board based on the error value and the minimum operating voltage variation includes: Obtain at least one additional margin from the voltage compensation amount corresponding to manufacturing process deviation, voltage compensation amount corresponding to environmental noise, and voltage compensation amount corresponding to temperature change. The error value, the minimum operating voltage change, and the additional margin are added together to obtain the superposition result; Configure the operating parameters of the chip on the target product board based on the superposition result.

[0011] In some embodiments, the operating parameter is the operating voltage protection band of the chip on the target product board.

[0012] According to a second aspect of this disclosure, a chip configuration apparatus is provided, comprising: The first determining unit is used to determine the error value based on the hardware environment differences between the target test platform and the target product board. An acquisition unit is used to acquire the minimum operating voltage change of the chip before and after the test; wherein the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario; A configuration unit is used to configure the operating parameters of the chip on the target product board based on the error value and the minimum operating voltage variation.

[0013] In some embodiments, the acquiring unit includes: The first test module is used to test the minimum operating voltage of the chip before accelerated aging and the minimum operating voltage after accelerated aging, based on the target test cases. The first determining module is used to determine the change in minimum operating voltage based on the difference between the minimum operating voltage after accelerated aging and the minimum operating voltage before accelerated aging.

[0014] In some embodiments, the first determining unit includes: The second test module is used to perform minimum operating voltage tests on the unaged chip on the target test platform and the target product board respectively using the target test cases. The second determining module is used to determine the error value based on the difference between the minimum operating voltage measured on the target product board and the minimum operating voltage measured on the target test platform.

[0015] In some embodiments, the apparatus further includes: The second determining unit is used to determine the target test case that matches the target application scenario based on the workload characteristics of the chip on the target product board, before the first determining unit determines the error value based on the hardware environment differences between the target test platform and the target product board.

[0016] In some embodiments, the configuration unit includes: The acquisition module is used to acquire at least one additional margin among the voltage compensation amount corresponding to manufacturing process deviation, voltage compensation amount corresponding to environmental noise, and voltage compensation amount corresponding to temperature change. The superposition module is used to superimpose the error value, the minimum operating voltage change, and the additional margin to obtain the superposition result; A configuration module is used to configure the operating parameters of the chip on the target product board based on the superposition result.

[0017] In some embodiments, the operating parameter is the operating voltage protection band of the chip on the target product board.

[0018] According to a third aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0019] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0020] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0021] In summary, the chip configuration method, apparatus, electronic device, and storage medium provided in this disclosure include: determining an error value based on the hardware environment differences between a target test platform and a target product board; obtaining the minimum operating voltage change of the chip before and after testing; wherein the error value and the minimum operating voltage before and after testing are obtained by testing with target test cases matching the target application scenario; and configuring the chip's operating parameters on the target product board based on the error value and the minimum operating voltage change. Compared with related technologies, the solution of this disclosure can improve the accuracy of chip operating parameter configuration by reducing the errors introduced by the differences in hardware environment between the test platform and the product board, as well as the mismatch between test cases and application scenarios.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0023] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 A schematic flowchart illustrating a chip configuration method provided in an embodiment of this disclosure; Figure 2 This is a schematic flowchart illustrating another chip configuration method provided in an embodiment of the present disclosure; Figure 3 This is a schematic flowchart illustrating another chip configuration method provided in an embodiment of the present disclosure; Figure 4 A schematic diagram illustrating the differences in hardware structure between a target product board and a target test platform provided in an embodiment of this disclosure; Figure 5 This is a schematic flowchart illustrating another chip configuration method provided in an embodiment of the present disclosure; Figure 6 This is a schematic flowchart illustrating another chip configuration method provided in an embodiment of the present disclosure; Figure 7 This is a comparative schematic diagram of a working voltage protection band configuration provided in an embodiment of the present disclosure; Figure 8 This is a comparative schematic diagram of a working voltage setting configuration provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the structure of a chip configuration device provided in an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the structure of another chip configuration device provided in an embodiment of this disclosure; Figure 11This is a schematic block diagram of an example electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0025] The following description, with reference to the accompanying drawings, outlines a chip configuration method and apparatus, an electronic device, and a storage medium according to embodiments of the present disclosure.

[0026] Figure 1 This is a schematic flowchart illustrating a chip configuration method provided in an embodiment of the present disclosure.

[0027] like Figure 1 As shown, the method includes steps 101-103.

[0028] Step 101: Determine the error value based on the hardware environment differences between the target test platform and the target product board.

[0029] In some embodiments, the target test platform is a hardware system used to test the chip, and the target product board is the circuit board on which the chip is ultimately installed and operated. There are hardware environment differences between the target test platform and the target product board in terms of power network impedance, clock signal quality, thermal environment, and chip-board contact methods. These differences can cause a deviation between the minimum operating voltage measured for the same chip on the target test platform and the actual minimum operating voltage required on the target product board. To quantify this deviation, the error value can be determined by comparing the minimum operating voltage test results of the same chip under the two hardware environments. The error value reflects the degree to which the hardware environment differences affect the minimum operating voltage test results.

[0030] The above method can quantify the hardware environment differences between the target test platform and the target product board into a specific error value, providing a basis for correcting the configuration of subsequent working parameters.

[0031] Step 102: Obtain the minimum operating voltage change of the chip before and after the test; wherein, the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario.

[0032] In some embodiments, "before and after testing" refers to the state of the chip before and after experiencing a certain stress or time, including but not limited to the state of the chip before and after accelerated aging testing. The minimum operating voltage change refers to the difference between the minimum operating voltage of the chip after testing and the minimum operating voltage before testing. To obtain this change, target test cases matching the target application scenario are needed. The target application scenario refers to the actual workload of the chip when it is running on the target product board (e.g., the chip's operating mode when the target functional module is activated). Target test cases are test programs or test sequences constructed based on the characteristics of the target application scenario, which enable the chip to exhibit the same or similar signal toggle rate, activated functional modules, and duty cycle as in actual applications during testing. Before testing, the minimum operating voltage of the chip is tested using the target test cases, and the pre-test value is recorded; after testing, the same minimum operating voltage of the same chip is tested again using the same target test cases, and the post-test value is recorded; the minimum operating voltage change is obtained by subtracting the pre-test value from the post-test value.

[0033] The above method can be used to obtain the minimum operating voltage change that reflects the performance degradation of the chip in actual application scenarios. This change is obtained based on test cases that match the target application scenario and conforms to the change pattern of the chip in real use environment.

[0034] Step 103: Based on the error value and the minimum operating voltage variation, configure the operating parameters of the chip on the target product board.

[0035] In some embodiments, operating parameters may include supply voltage-related parameters required for the chip to operate on the target product board, including but not limited to voltage protection bands, voltage compensation values, or voltage offsets. Configuring operating parameters refers to determining the final voltage setting or voltage adjustment amount applied to the chip based on the error value and the minimum operating voltage variation. Specifically, the error value and the minimum operating voltage variation can be superimposed to obtain a comprehensive compensation amount; then, based on this comprehensive compensation amount, the reference operating voltage of the chip on the target product board is adjusted to form the final operating parameter configuration. The configured operating parameters are written into the power management unit of the target product board, enabling the chip to obtain a corrected supply voltage during operation.

[0036] The above method can simultaneously compensate for test deviations caused by differences in hardware environment and increases in minimum operating voltage caused by chip performance degradation, thereby configuring the chips on the target product board with operating parameters that meet actual needs.

[0037] In summary, the chip configuration method provided in this disclosure can improve the accuracy of chip operating parameter configuration by reducing errors caused by differences between the test platform and the product board hardware environment and mismatches between test cases and application scenarios.

[0038] Figure 2 A flowchart illustrating a chip configuration method provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 102. Figure 2 This may include the following steps: Step 201: Based on the target test case, test the minimum operating voltage of the chip before accelerated aging and the minimum operating voltage after accelerated aging.

[0039] In some embodiments, accelerated aging refers to subjecting a chip to a physical degradation process equivalent to prolonged normal use within a short period of time by applying stress higher than normal operating conditions. Specific methods of accelerated aging include, but are not limited to, high-temperature operating life testing. "Before accelerated aging" refers to the initial state of the chip before it has experienced accelerated aging stress. "After accelerated aging" refers to the state of the chip after experiencing accelerated aging stress. To obtain the minimum operating voltage variation, minimum operating voltage tests are performed on the chip before and after accelerated aging. Both tests use the same target test case, which matches the target application scenario. During testing, the target test case is run on the target test platform, while the chip's supply voltage is gradually changed. The chip's output is monitored to ensure it meets timing and functional requirements. The minimum supply voltage required for the chip to operate normally is recorded, thus obtaining the minimum operating voltage before and after accelerated aging.

[0040] Step 202: Determine the change in minimum operating voltage based on the difference between the minimum operating voltage after accelerated aging and the minimum operating voltage before accelerated aging.

[0041] In some embodiments, the minimum operating voltage after accelerated aging is subtracted from the minimum operating voltage before accelerated aging, and the difference is the change in minimum operating voltage. This change reflects the degree of impact of the accelerated aging process on the chip's minimum operating voltage, that is, the increase in the minimum supply voltage required by the chip after aging degradation relative to its initial state.

[0042] Using the above method, the minimum operating voltage can be tested before and after accelerated aging based on the target test cases, and the quantified change in the minimum operating voltage can be obtained by calculating the difference, providing a numerical basis for subsequent configuration of operating parameters that reflects the degree of chip aging and degradation.

[0043] Figure 3A flowchart illustrating a chip configuration method provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 101. Figure 3 This may include the following steps: Step 301: Perform minimum operating voltage tests on the unaged chips on the target test platform and the target product board using the target test cases.

[0044] In some embodiments, an unaged chip refers to a chip that has not yet undergone accelerated aging stress or other treatments that lead to performance degradation, and whose physical characteristics are in their initial state. To determine the error introduced by the hardware environment differences between the target test platform and the target product board, the same unaged chip is used to perform minimum operating voltage tests on both the target test platform and the target product board. Both tests use the same target test case, which is matched to the target application scenario.

[0045] Figure 4 This diagram illustrates the differences in hardware structure between a target product board and a target test platform provided in an embodiment of this disclosure. Figure 4 As shown, on the target product board, the chip is directly soldered to the printed circuit board (PCB). A thermal interface material (TIM) is placed between the chip and the heat sink, which is fixed above the chip for heat dissipation in the actual working environment. On the target test platform, the chip is connected to the PCB via a fixture and probes. A fan is placed above the chip for heat dissipation, forming a pluggable test interface structure. These structural differences lead to differences between the target test platform and the target product board in terms of power network impedance, signal transmission path length, contact resistance, heat dissipation efficiency, and thermal environment. Specifically, the contact resistance between the probes and the chip in the target test platform, and the parasitic capacitance introduced by the fixture, affect power supply noise and signal integrity; while the soldered connection in the target product board has lower contact resistance and more stable electrical characteristics. Furthermore, the difference in heat dissipation methods also results in different temperature environments for the chip during testing, thus affecting the test results for the minimum operating voltage.

[0046] When testing on the target test platform, the chip is installed in the test socket of the target test platform, and electrical connection is established through the test socket and probes. The target test cases are run, and the supply voltage is gradually adjusted. The minimum voltage at which the chip can operate normally is recorded. When testing on the target product board, the same chip is soldered or installed on the target product board, and the same target test cases are run. Similarly, the supply voltage is gradually adjusted, and the minimum voltage at which the chip can operate normally is recorded. It should be noted that, apart from the difference in hardware environment, all other conditions (such as test cases, ambient temperature, power supply adjustment steps, etc.) must be kept consistent for these two tests.

[0047] Step 302: Determine the error value based on the difference between the minimum operating voltage measured on the target product board and the minimum operating voltage measured on the target test platform.

[0048] In some embodiments, the minimum operating voltage measured on the target product board is subtracted from the minimum operating voltage measured on the target test platform, and the resulting difference is the error value. This error value quantifies the deviation in minimum operating voltage testing caused by differences in the hardware environment between the target test platform and the target product board. The error value can be positive, negative, or zero, depending on whether the hardware environment of the target product board is more demanding or less demanding than that of the target test platform. Typically, factors such as the power network impedance and clock jitter of the target product board may require a higher supply voltage, resulting in a positive error value. This error value is used in subsequent steps to correct the operating parameters to eliminate the impact of hardware environment differences.

[0049] Using the above method, the impact of hardware environment differences between the target test platform and the target product board on the minimum operating voltage test results can be directly measured using unaged chips and the same target test cases, providing a reliable basis for the accurate configuration of subsequent operating parameters.

[0050] Figure 5 A flowchart illustrating a chip configuration method provided in an embodiment of this disclosure is further shown, such as... Figure 5 As shown, the method includes steps 401-404.

[0051] Step 401: Based on the workload characteristics of the chip on the target product board, determine the target test cases that match the target application scenario.

[0052] In some embodiments, the workload characteristics of the chip on the target product board refer to the operating mode exhibited by the chip during actual operation, including but not limited to the types of functional modules activated by the chip, the frequency and distribution of signal switching, and the ratio of the time the chip is in the working state to the idle state. The target application scenario refers to the operating environment in which the chip performs tasks on the target product board, such as the operating state of the chip when performing tasks such as video decoding, data communication, and standby wake-up.

[0053] To obtain target test cases that match the target application scenario, it is necessary to first analyze the workload characteristics of the chip on the target product board. Specifically, representative operating mode characteristics can be extracted by monitoring parameters such as signal activity, power consumption changes, and temperature response when the chip runs actual applications on the target product board. These characteristics include, for example, which functional modules inside the chip are activated, the signal toggle rate level, and the duty cycle.

[0054] Based on the extracted workload characteristics, target test cases are determined. A target test case is a set of programs or instruction sequences that can be executed on the target test platform, and the resulting chip operating state is consistent with the workload characteristics of the target application scenario.

[0055] Methods for determining target test cases include, but are not limited to: 1. Directly porting actual applications from the target product board as test cases, such as running video playback programs or game programs on the operating system of the target test platform; 2. Writing automated scripts to simulate user operation sequences, causing the chip to activate different functional modules in a preset time sequence, generating a workload with locality, burstiness, and low duty cycle characteristics; 3. Synthesizing standardized test loads, and converting the extracted key parameters (such as the set of activated functional modules, signal toggle rate, and duty cycle) into a repeatable test vector sequence.

[0056] Step 402: Determine the error value based on the hardware environment differences between the target test platform and the target product board.

[0057] Step 403: Obtain the minimum operating voltage change of the chip before and after the test; wherein the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario.

[0058] Step 404: Based on the error value and the minimum operating voltage variation, configure the operating parameters of the chip on the target product board.

[0059] For explanations of steps 402 to 404, please refer to [link / reference needed]. Figure 1 The detailed description of the relevant steps will not be repeated here.

[0060] By using the above method, target test cases that match the target application scenario can be determined in advance before determining the error value and obtaining the minimum operating voltage change. This allows subsequent tests on the target test platform to truly reflect the chip's working state in actual use, thereby reducing errors caused by inconsistencies between the test content and the actual application.

[0061] Figure 6 A flowchart illustrating a chip configuration method provided in this disclosure embodiment is further shown, based on... Figure 1 The illustrated embodiment further explains step 103 as follows: Figure 6 As shown, the method includes the following steps: Step 501: Obtain at least one additional margin from the following: voltage compensation amount corresponding to manufacturing process deviation, voltage compensation amount corresponding to environmental noise, and voltage compensation amount corresponding to temperature change.

[0062] In some embodiments, the voltage compensation amount corresponding to manufacturing process deviation refers to the additional voltage margin that needs to be reserved in the operating parameters due to the performance differences between chips caused by random fluctuations during chip manufacturing (such as transistor threshold voltage and non-uniformity of channel length). The voltage compensation amount corresponding to environmental noise refers to the voltage margin that needs to be reserved due to the power supply voltage fluctuations caused by factors such as power network impedance, ripple, and electromagnetic interference on the target product board. The voltage compensation amount corresponding to temperature change refers to the voltage margin that needs to be reserved due to the performance changes of the chip at different operating temperatures (such as decreased carrier mobility at high temperatures and increased threshold voltage at low temperatures). The above three additional margins can be obtained through empirical data, statistical models, or design specifications. In practical applications, at least one of the above three additional margins can be selected for subsequent superposition according to the specific design requirements of the target product board and the application environment of the chip. For example, for consumer electronics products that are cost-sensitive and have a stable operating environment, only the voltage compensation amount corresponding to manufacturing process deviation can be selected; for automotive or industrial control chips, all three additional margins can be selected simultaneously.

[0063] Step 502: The error value, the minimum operating voltage change, and the additional margin are superimposed to obtain the superposition result.

[0064] In some embodiments, the error value reflects the impact of hardware environment differences between the target test platform and the target product board on the minimum operating voltage. The minimum operating voltage change reflects the increase in minimum operating voltage due to chip aging and degradation. Additional margin reflects the impact of other factors such as manufacturing processes, environmental noise, and temperature variations on the chip's power supply requirements. Adding these quantities together means summing the error value, the minimum operating voltage change, and at least one additional margin to obtain a comprehensive compensation amount. Specifically, if the error value is denoted as... The minimum operating voltage variation is denoted as The additional margin obtained is denoted as follows: (Corresponding to manufacturing process deviations) (Environmental noise response) (corresponding to temperature changes), then the superposition result It should be noted that the summation operation is not limited to simple addition; weighted summation or other combinations can also be used as needed.

[0065] Step 503: Configure the operating parameters of the chip on the target product board based on the superposition result.

[0066] In some embodiments, configuring operating parameters based on the superposition result means combining the superimposed comprehensive compensation amount with the chip's reference operating voltage to form the final voltage setting value applied to the target product board. Specifically, the reference operating voltage of the chip on the target product board (i.e., the theoretical supply voltage required by the chip without considering any compensation) can be obtained, and then the superposition result can be added to the reference operating voltage to obtain the configured operating parameters.

[0067] By using the above methods, additional margins such as manufacturing process deviations, environmental noise, and temperature changes can be introduced on top of the error value and minimum operating voltage variation, so that the final configured operating parameters are comprehensive and accurate, meeting the chip reliability requirements of different application scenarios.

[0068] Optionally, based on any of the above embodiments or alternative methods, the operating parameters are the operating voltage protection band of the chip on the target product board.

[0069] In some embodiments, the operating voltage protection band refers to an additional voltage margin beyond the chip's reference operating voltage, reserved to ensure stable operation of the chip throughout its entire lifecycle on the target product board. This operating voltage protection band is used to offset the minimum operating voltage increase caused by various factors, including hardware environment differences, chip aging and degradation, manufacturing process deviations, environmental noise, and temperature variations. Specifically, after determining the error value, the minimum operating voltage change, and the additional margin through the aforementioned steps, the summation result of these values ​​is the value of the operating voltage protection band. Adding this operating voltage protection band to the chip's reference operating voltage yields the actual operating voltage that the chip should be configured with on the target product board. By specifying the operating parameter as the operating voltage protection band, the method of this disclosure can be directly applied to the power management unit of the target product board to set the actual supply voltage of the chip.

[0070] In some implementations, the above method is performed separately for multiple operating frequency points of the chip to obtain the error value and minimum operating voltage variation corresponding to each frequency point, i.e., the operating voltage protection band. Then, corresponding operating parameters are configured for each frequency point. When the chip is running on the target product board, the corresponding operating parameters are dynamically selected for power supply based on the current operating frequency. Figure 7 This is a comparative schematic diagram of a working voltage protection band configuration provided in an embodiment of this disclosure. Figure 7 As shown, the horizontal axis represents the chip's operating frequency in megahertz (MHz); the vertical axis represents the configured operating voltage protection band in millivolts (mV). Figure 7 The document illustrates the operating voltage protection band values ​​configured by two methods at different frequencies: the operating voltage protection band configured by other methods is 10.0mV at all frequency points; the operating voltage protection band configured by the method provided in this disclosure is 15.0mV at 800MHz and 900MHz, and 10.0mV at 1000MHz and 1050MHz. By configuring corresponding operating voltage protection bands for different frequency points, the chip obtains a larger protection band value at lower frequencies and a smaller protection band value at higher frequencies. Through this method, a matching voltage protection band can be configured for each frequency point based on the actual aging and degradation differences of the chip at different operating frequencies, avoiding chip malfunction due to insufficient voltage protection band at low frequencies, and avoiding unnecessary power consumption waste due to excessive voltage protection band at high frequencies.

[0071] Figure 8 This is a comparative schematic diagram of a working voltage setting configuration provided in an embodiment of this disclosure. Figure 8 As shown, the horizontal axis represents the chip's operating frequency in megahertz (MHz); the vertical axis represents the configured operating voltage setting in millivolts (mV). Figure 8 The diagram illustrates the values ​​of a reference voltage, a voltage setting configured by other methods, and a voltage setting configured by the method provided in embodiments of this disclosure at different frequencies. Figure 8 It can be seen that the voltage setting value configured by the method provided in this embodiment is no lower than the voltage setting value configured by other methods at different frequencies, and the difference is greater at lower frequencies. Through the above method, more accurate voltage setting values ​​can be configured for the chip at different operating frequencies, ensuring reliable operation throughout the chip's lifecycle while avoiding functional failures due to insufficient voltage setting values.

[0072] Corresponding to the chip configuration method described above, this invention also proposes a chip configuration apparatus. Since the apparatus embodiments of this invention correspond to the method embodiments described above, details not disclosed in the apparatus embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0073] Figure 9 This is a schematic diagram of the structure of a chip configuration device provided in an embodiment of the present disclosure, as shown below. Figure 9 As shown, the device includes: The first determining unit 71 is used to determine the error value based on the hardware environment differences between the target test platform and the target product board. The acquisition unit 72 is used to acquire the minimum operating voltage change of the chip before and after the test; wherein the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario; Configuration unit 73 is used to configure the operating parameters of the chip on the target product board based on the error value and the minimum operating voltage variation.

[0074] This device can improve the accuracy of chip operating parameter configuration by reducing errors caused by differences in the hardware environment between the test platform and the product board, as well as mismatches between test cases and application scenarios.

[0075] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the acquisition unit 72 includes: The first test module 721 is used to test the minimum operating voltage of the chip before accelerated aging and the minimum operating voltage after accelerated aging, based on the target test cases. The first determining module 722 is used to determine the change in minimum operating voltage based on the difference between the minimum operating voltage after accelerated aging and the minimum operating voltage before accelerated aging.

[0076] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the first determining unit 71 includes: The second test module 711 is used to perform minimum operating voltage tests on the unaged chip on the target test platform and the target product board respectively using the target test cases. The second determining module 712 is used to determine the error value based on the difference between the minimum operating voltage measured on the target product board and the minimum operating voltage measured on the target test platform.

[0077] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the device further includes: The second determining unit 74 is used to determine the target test case that matches the target application scenario based on the workload characteristics of the chip on the target product board before the first determining unit 71 determines the error value based on the hardware environment difference between the target test platform and the target product board.

[0078] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the configuration unit 73 includes: The acquisition module 731 is used to acquire at least one additional margin among the voltage compensation amount corresponding to manufacturing process deviation, voltage compensation amount corresponding to environmental noise, and voltage compensation amount corresponding to temperature change. The superposition module 732 is used to superimpose the error value, the minimum operating voltage change, and the additional margin to obtain the superposition result; Configuration module 733 is used to configure the operating parameters of the chip on the target product board based on the superposition result.

[0079] Furthermore, in one possible implementation of this disclosure embodiment, the operating parameter is the operating voltage protection band of the chip on the target product board.

[0080] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0081] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0082] Figure 11 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0083] like Figure 11As shown, the electronic device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 902 or a computer program loaded from storage unit 908 into RAM (Random Access Memory) 903. The RAM 903 can also store various programs and data required for the operation of the electronic device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. An I / O (Input / Output) interface 905 is also connected to bus 904.

[0084] Multiple components in electronic device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of displays, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows electronic device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0085] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as chip configuration methods. For example, in some embodiments, the chip configuration methods may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the configuration method of the aforementioned chip by any other suitable means (e.g., by means of firmware).

[0086] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0087] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0088] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0089] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0090] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0091] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0092] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0093] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0094] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for configuring a chip, characterized in that, include: The error value is determined based on the hardware environment differences between the target test platform and the target product board. Obtain the minimum operating voltage change of the chip before and after the test; wherein the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario; Based on the error value and the minimum operating voltage variation, configure the operating parameters of the chip on the target product board.

2. The method according to claim 1, characterized in that, The acquisition of the minimum operating voltage change of the chip before and after the test includes: Based on the target test cases, the minimum operating voltage of the chip before accelerated aging and the minimum operating voltage after accelerated aging were tested respectively. The change in minimum operating voltage is determined based on the difference between the minimum operating voltage after accelerated aging and the minimum operating voltage before accelerated aging.

3. The method according to claim 1, characterized in that, The determination of error values ​​based on the hardware environment differences between the target test platform and the target product board includes: The minimum operating voltage of the unaged chip is tested on the target test platform and the target product board using the target test cases. The error value is determined based on the difference between the minimum operating voltage measured on the target product board and the minimum operating voltage measured on the target test platform.

4. The method according to any one of claims 1-3, characterized in that, Before determining the error value based on the hardware environment differences between the target test platform and the target product board, the method further includes: Based on the workload characteristics of the chip on the target product board, the target test cases that match the target application scenario are determined.

5. The method according to claim 1, characterized in that, The step of configuring the chip's operating parameters on the target product board based on the error value and the minimum operating voltage variation includes: Obtain at least one additional margin from the voltage compensation amount corresponding to manufacturing process deviation, voltage compensation amount corresponding to environmental noise, and voltage compensation amount corresponding to temperature change. The error value, the minimum operating voltage change, and the additional margin are added together to obtain the superposition result; Configure the operating parameters of the chip on the target product board based on the superposition result.

6. The method according to claim 5, characterized in that, The operating parameters refer to the operating voltage protection band of the chip on the target product board.

7. A chip configuration device, characterized in that, include: The first determining unit is used to determine the error value based on the hardware environment differences between the target test platform and the target product board. An acquisition unit is used to acquire the minimum operating voltage change of the chip before and after the test; wherein the error value and the minimum operating voltage before and after the test are obtained by testing based on target test cases that match the target application scenario; A configuration unit is used to configure the operating parameters of the chip on the target product board based on the error value and the minimum operating voltage variation.

8. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-6.

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