Pixel circuit and display device thereof

Abstract

Disclosed are a pixel circuit according to an embodiment and a display device including the same. A pixel circuit includes a light emitting element, a driving element configured to drive the light emitting element, a compensation circuit including a first capacitor including a first electrode and a second electrode, a first data voltage being applied to the first capacitor via a data line, the second electrode being connected to a gate electrode of the driving element, a first switching element to which a predetermined second data voltage is supplied via the data line, and a second capacitor including a first electrode connected to a second electrode of the first switching element and a second electrode connected to a power supply line to which a common voltage is applied.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0179039, filed on December 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a pixel circuit and a display device including the same. Background Technology

[0004] Variable viewing angle technology is being applied to display devices. Variable viewing angle technology can present video content or visual information reproduced on a display device to only users within a narrow viewing angle range or to multiple users within a wide viewing angle range.

[0005] With the expansion of the market for future vehicles (such as electric vehicles and autonomous vehicles), the demand for vehicle display devices is rapidly increasing. Research is underway on methods that divide the screen of a vehicle display device and control one part of the screen to have a narrow viewing angle while controlling another part to have a wide viewing angle. This technology can drive pixels with a narrow viewing angle arranged in one area of ​​the screen to display personal content or information that only a specific user can view, while simultaneously driving pixels with a wide viewing angle arranged in another area of ​​the screen to display shared content that multiple users can view together.

[0006] In automotive display devices, display panels for organic light-emitting diodes (OLEDs) are attracting significant attention. OLEDs include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), which offer advantages such as fast response times, high luminous efficiency and brightness, and wide viewing angles. OLEDs boast fast response times, excellent luminous efficiency, brightness, and viewing angles, and provide superior contrast and color reproduction because they can represent black grayscale levels with perfect black. Because OLED display panels can be flexible and curved, curved surfaces can be easily achieved. Due to these advantages, the market share of OLEDs in automotive display devices is rapidly increasing. Summary of the Invention

[0007] Each pixel used in automotive displays comprises two lenses with different viewing angles and two light-emitting elements. Because the two light-emitting elements are connected to a single transistor, the size of the light-emitting elements is reduced, resulting in a shorter lifespan for them.

[0008] This disclosure aims to address all the aforementioned necessities and issues.

[0009] The present invention provides a pixel circuit capable of adjusting the light viewing angle using a light-emitting element and a display device using the same.

[0010] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0011] The pixel circuit according to embodiments of this disclosure may include: a light-emitting element; a driving element configured to drive the light-emitting element; a compensation circuit including a first capacitor, the first capacitor including a first electrode to which a first data voltage is applied via a data line and a second electrode connected to a gate electrode of the driving element; a first switching element to which a predetermined second data voltage is provided via a data line; and a second capacitor including a first electrode connected to the second electrode of the first switching element and a second electrode connected to a power line to which a common voltage is applied.

[0012] A display device according to an embodiment of the present disclosure may include a display panel including a display area having a plurality of sub-pixels, wherein the display panel includes: a substrate; a circuit layer disposed above the substrate; a light-emitting element layer disposed above the circuit layer; an encapsulation layer disposed above the light-emitting element layer; and a liquid crystal lens layer including: a first electrode comprising a plurality of electrode patterns spaced apart from each other above the encapsulation layer; a liquid crystal layer covering the first electrode; and a second electrode disposed above the liquid crystal layer, wherein a predetermined data voltage is applied to each of the plurality of electrode patterns disposed in the first electrode, and a predetermined common voltage is applied to the second electrode.

[0013] According to embodiments of this disclosure, a light-emitting element is provided for each pixel, a liquid crystal lens layer is formed above the light-emitting element layer in which the light-emitting element is disposed, and a data voltage is selectively applied to the liquid crystal lens layer. Therefore, a single light-emitting element can be used instead of two lenses and two light-emitting elements to adjust the viewing angle.

[0014] According to embodiments of this disclosure, since each pixel uses one light-emitting element, it is not necessary to reduce the size of the light-emitting element, thus extending the lifespan of the light-emitting element.

[0015] According to embodiments of this disclosure, liquid crystal lens layers can be implemented in various forms, either by pixel or by region.

[0016] According to embodiments of this disclosure, the lifespan of the light-emitting element is improved, and therefore, low-power driving can be achieved.

[0017] The effects of this specification are not limited to those described above, and other effects not mentioned will be readily understood by those skilled in the art from the following description and the appended claims. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0019] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0021] Figure 3A and 3B This is an explanation Figure 2 The diagram shows the specific mode drive waveform of the pixel circuit described in the text;

[0022] Figures 4A to 4D It shows the basis Figure 3B A diagram illustrating the operating principle of a pixel circuit;

[0023] Figure 5 It is shown Figure 1 A cross-sectional view of the pixels in the display panel shown;

[0024] Figure 6A and Figure 6B It is shown Figure 5 A diagram showing the shape of the first electrode;

[0025] Figures 7A to 7C It is shown Figure 5 The diagram shows the liquid crystal lens layer;

[0026] Figure 8 This diagram illustrates the principle of adjusting the light viewing angle in pixels.

[0027] Figure 9A and Figure 9B This is a diagram showing the shape of the electrode pattern formed by sub-pixels;

[0028] Figure 10A and Figure 10B It is shown Figure 5 Diagrams showing different shapes of the first electrode;

[0029] Figure 11 This diagram illustrates the principle of adjusting the light angle based on the region.

[0030] Figures 12A to 12D This is a diagram illustrating the mode switching principle of an embodiment according to the present disclosure;

[0031] Figure 13 This is a schematic diagram of the pixel circuit according to the second embodiment of the present invention;

[0032] Figure 14A and Figure 14B It is shown Figure 13 A diagram showing the specific mode driving waveform of the pixel circuit; and

[0033] Figures 15A to 15D It shows the basis Figure 14B A diagram illustrating the operating principle of a pixel circuit. Detailed Implementation

[0034] The advantages and features of this specification, as well as methods of implementing them, will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this specification is not limited to the embodiments described below, and may be implemented in various forms. These embodiments are provided only to fully disclose this disclosure and to fully convey its scope to those skilled in the art, and this specification is defined by the disclosed claims.

[0035] Since the shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings used to describe embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals denote the same parts. Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the essence of this disclosure.

[0036] When using terms such as "comprising," "having," or "consisting of" in this specification, additional parts may be added unless used exclusively. Unless otherwise expressly stated, the singular form of a component includes the plural form.

[0037] When explaining components, it should be understood that the range of error is included, even if there is no separate explicit description.

[0038] When describing positional relationships, such as when the positional relationship between two parts is described as "on top of", "in the upper part", "in the lower part", "next to", etc., one or more other parts may be located between the two parts unless "adjacent" or "direct" is used.

[0039] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the "first component" mentioned below can also be the "second component."

[0040] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0041] The following implementations may be combined or integrated with each other in part or in whole, and may be connected and operated in various technical ways. The implementations may be performed independently or in connection with each other.

[0042] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0043] In the display device disclosed herein, the pixel circuit and gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs including low-temperature polycrystalline silicon (LTPS), etc.

[0044] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow out from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor (PMOS)), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the contents of this disclosure are not limited by the source and drain of the transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0045] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage.

[0046] A transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be a high gate voltage, and the gate off-voltage can be a low gate voltage. In the case of a p-channel transistor, the gate on-voltage can be a low gate voltage, and the gate off-voltage can be a high gate voltage.

[0047] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0048] Reference Figure 1The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0049] The display panel 100 may be, but is not limited to, a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be an irregularly shaped panel in which at least a portion is curved or elliptical.

[0050] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines that are commonly connected to the pixels. The power lines may be commonly connected to pixel circuitry to supply the voltage required to drive the pixels 101.

[0051] Each of the pixels 101 can be divided into red sub-pixels, green sub-pixels, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gate lines, and power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0052] The display area AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the line direction (X-axis direction) of the pixel array in the display panel 100. Pixels arranged in a pixel line share a gate line 103. Sub-pixels arranged along the data line direction in the column direction Y share the same data line 102. A horizontal period is the time obtained by dividing the period of one frame by the total number of pixel lines L1 to Ln.

[0053] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and a real object in the background is visible. The display panel 100 can be made of a flexible display panel.

[0054] Power supply 150 receives an input voltage applied from host system 200 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) via the DC-DC converter, such as gate on-state voltage, gate off-state voltage, pixel drive voltage, cathode voltage, reference voltage, and display panel driving circuitry IC drive voltage. Gate on-state voltage and gate off-state voltage can be provided to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage can be provided to pixel 101 via a power line commonly connected to pixel 101.

[0055] The power supply 150 may also include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs multiple gamma reference voltages divided at specific intervals on a preset gamma curve (e.g., a 2.2 gamma curve). These gamma reference voltages are provided to the data driver 110. In the data driver 110, the gamma reference voltages are further subdivided into grayscale voltages by a voltage divider circuit. The gamma voltage generator can be implemented using a programmable gamma circuit that can adjust the voltage of each gamma reference voltage according to digital data. The timing controller 130, the host system 200, or a separate external device can update the digital data stored in the registers of the programmable gamma circuit via a communication interface.

[0056] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0057] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not included. Figure 1 As shown in the diagram, the data driver 110 and the touch sensor driver can be integrated into a single source driver IC.

[0058] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each grayscale level through a voltage divider circuit. The gamma compensation voltage for each grayscale level is provided to a digital-to-analog converter (hereinafter referred to as "DAC") located in each channel of the data driver 110.

[0059] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes the pixel data of the input image. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0060] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gate driver 120 may be disposed in at least one of the left and right non-display areas NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA.

[0061] Under the control of timing controller 130, gate driver 120 sequentially outputs gate signal pulses to gate line 103. Gate driver 120 can sequentially supply gate signals to gate line 103 by shifting the gate signal pulses using shift registers. When multiple gate signals are applied to each pixel, gate driver 120 may include multiple shift registers. Gate signals may include scan signals and emission signals (or EM signals) input to the pixel circuit through multiple gate lines.

[0062] The gate driver 120 can be disposed in the non-display area as a gate in panel (GIP) or between sub-pixels SP in the display area AA as a gate in active area (GIA).

[0063] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal period (1H).

[0064] The timing controller 130 can control the display panel driving circuit by generating data timing control signals for controlling the operation timing of the data driver 110 and gate timing control signals for controlling the operation timing of the gate driver 120 based on timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0065] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 via the level shifter 140. The level shifter 140 can convert the voltage of the gate timing control signal received from the timing controller 130 into a swing width between the gate on-voltage and the gate off-voltage, and provide it to the gate driver 120.

[0066] The timing controller 130 analyzes the input image for each frame and generates control signals for selectively outputting gate signals based on the analysis results. The generated control signals can be provided to the shift register of the gate driver 120 via the level shifter 140.

[0067] The host system 200 may include a motherboard of one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, or wearable terminal. The host system 200 can scale the image signal from the video source according to the resolution of the display panel 100 and can send it along with a timing signal to the timing controller 130.

[0068] Figure 2 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure.

[0069] Reference Figure 2 The pixel circuit according to the first embodiment of this disclosure includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a compensation circuit 10 including a first capacitor Cst, a switching element T1, and a second capacitor Csel. The compensation circuit 10 also includes a plurality of switching elements T2 to T6. The driving element DT and the plurality of switching elements T1 to T6 can be implemented by p-channel transistors, but this disclosure is not limited thereto.

[0070] The driving element DT generates current based on the gate-source voltage Vgs and drives the light-emitting element EL. The driving element DT includes a first electrode connected to a first power line PL1 to which the pixel driving voltage VDD is applied, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0071] The light-emitting element (EL) can be implemented as an organic light-emitting diode (OLED). The EL includes an anode, a cathode, and an organic compound layer formed between the anode and cathode. The anode of the EL is connected to a fourth node n4, and its cathode is connected to a second power line PL2 to which the pixel base voltage VSS is applied. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emissive layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the embodiments described in this disclosure are not limited thereto. The EL can be implemented in a series structure in which multiple emissive layers are stacked. A series-structured EL can improve pixel brightness and lifetime.

[0072] A first switching element T1 is connected between the fifth node n5 and the data line DL. The first switching element T1 is turned on according to the gate turn-on voltage VGL of the third scan signal SCAN3, and connects the fifth node n5 to the data line DL to which the second data voltage Vdata2 is applied. The first switching element T1 includes a first electrode connected to the data line DL, a gate electrode to which the third scan signal SCAN3 is applied, and a second electrode connected to the fifth node n5.

[0073] The second switching element T2 is connected between the data line DL and the first node n1. The second switching element T2 is turned on according to the gate turn-on voltage VGL of the first scan signal SCAN1, and applies the data voltage Vdata of the pixel data to the first node n1. The second switching element T2 includes a first electrode connected to the data line DL, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the first node n1.

[0074] The third switching element T3 is connected between the second node n2 and the third node n3. The third switching element T3 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN2, and connects the gate electrode of the driving element DT to the second electrode. The third switching element T3 includes a first electrode connected to the second node n2, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0075] A fourth switching element T4 is connected between the first node n1 and the third power supply line PL3. The fourth switching element T4 is turned on according to the gate on-state voltage VGL of the light emission control signal EM, and connects the first node n1 to the third power supply line PL3, which is subject to an applied reference voltage Vref. The fourth switching element T4 includes a first electrode connected to the first node n1, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the third power supply line PL3.

[0076] A fifth switching element T5 is connected between the third node n3 and the fourth node n4. The fifth switching element T5 is turned on according to the gate on-state voltage VGL of the light emission control signal EM, connecting the third node n3 to the fourth node n4. The fifth switching element T5 includes a first electrode connected to the third node n3, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the fourth node n4.

[0077] A sixth switching element T6 is connected between the fourth node n4 and the third power supply line PL3. The sixth switching element T6 is turned on according to the gate on-state voltage VGL of the second scan signal SCAN2, and connects the fourth node n4 to the third power supply line PL3, which is subject to an applied reference voltage Vref. The sixth switching element T6 includes a first electrode connected to the third power supply line PL3, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the fourth node n4.

[0078] The first capacitor Cst is connected between the first node n1 and the second node n2. The second capacitor Csel is connected between the fifth node n5 and the fourth power line PL4, which is subject to the common voltage VCOM.

[0079] When the second switching element T2 is turned on, the first data voltage Vdata1 applied via the data line DL can charge the first capacitor Cst, and when the first switching element T1 is turned on, the second data voltage Vdata2 can charge the second capacitor Csel.

[0080] Figure 3A and Figure 3B yes Figure 2 The diagram shows a specific mode driving waveform of the pixel circuit. Figures 4A to 4D yes Figure 3B The diagram shows the operating principle of the pixel circuit.

[0081] refer to Figure 3A and Figure 3B In the first and second modes, the pixel circuit is driven in the order of initialization period Ti, data writing and sensing period Tw / s, selection period Tsel and emission period Tem.

[0082] In the first mode, light emitted from the light-emitting element can be emitted with a wide viewing angle, while in the second mode, light emitted from the light-emitting element can be emitted with a narrow viewing angle.

[0083] Reference Figure 4A During the initialization period Ti, the first switching element T1 and the second switching element T2 are turned off, and the third switching element T3 through the sixth switching element T6 are turned on. Then, a reference voltage Vref is applied to the first node n1 and the second node n2.

[0084] refer to Figure 4B During the data writing and sensing cycle Tw / s, the first switching element T1, the fourth switching element T4, and the fifth switching element T5 are turned off, while the second switching element T2, the third switching element T3, and the sixth switching element T6 are turned on. Then, the first data voltage Vdata1 of the pixel data is applied to the first node n1, and the pixel driving voltage VDD is applied to the driving element. Therefore, the threshold voltage Vth of the sensing driving element is measured, resulting in the voltage of the second node n2 becoming VDD + Vth. Furthermore, the reference voltage Vref is applied to the fourth node n4.

[0085] Reference Figure 4C During the selected time period Tsel, in the first mode, the first switching element T1 to the sixth switching element T6 are turned off, and in the second mode, the second switching element T2 to the sixth switching element T6 are turned off and the first switching element T1 is turned on. Then, the second data voltage Vdata2 is applied to the fifth node n5.

[0086] The data write and sensing period Tw / s and the selection period Tsel are the periods during which different data voltages are applied. Therefore, in order to change the data voltage, the selection period Tsel can start at least 1 hour after the end of the data write and sensing period Tw / s.

[0087] Reference Figure 4D During the light emission cycle Tem, the first switching element T1 to the third switching element T3 and the sixth switching element T6 are turned off, while the fourth switching element T4 and the fifth switching element T5 are turned on. Then, the current generated according to the gate-source voltage of the driving element DT is supplied to the light-emitting element EL, and light is emitted from the light-emitting element EL. As a result, the voltage of the first node n1 becomes "Vref", and the voltage of the second node n2 becomes "Vref-Vdata+VDD+Vth".

[0088] During the emission period Tem, in the first mode, the optical viewing angle remains wide because the second data voltage Vdata2 is not applied to the second capacitor Csel. In the second mode, the optical viewing angle narrows due to the second data voltage Vdata2 and the common voltage VCOM applied to the second capacitor Csel.

[0089] Figure 5 It is shown Figure 1 The diagram shown is a cross-sectional view of the pixels in the display panel. Figure 6A and Figure 6B It is shown Figure 5 The diagram shows the shape of the first electrode. Figures 7A to 7C It is shown Figure 5 The diagram shows the liquid crystal lens layer.

[0090] Please refer to Figure 5 The display panel 100 of the present invention may include a substrate 10, a circuit layer 12, a light-emitting element layer 14, an encapsulation layer 16, and a liquid crystal lens layer 18.

[0091] The substrate 10 may be made of a flexible plastic. For example, the substrate 10 may be manufactured as a single-layer or multi-layer substrate made of a material selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, polyarylate, polysulfone, and cyclic olefin copolymers, but this disclosure is not limited thereto. For example, the substrate 10 may be a ceramic substrate or a glass substrate.

[0092] Circuit layer 12 may include pixel circuitry connected to wires such as data lines, gate lines, and power lines; gate drivers connected to the gate lines; a demultiplexer array; and circuitry (not shown) for automated probe testing. The wires and circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers interposed therebetween, and an active layer comprising semiconductor material. All transistors formed in circuit layer 12 may be implemented using TFTs comprising n-channel oxide semiconductors, but this disclosure is not limited thereto.

[0093] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL in the light-emitting element layer 14 may be covered with a protective layer comprising an organic film and a protective film.

[0094] Encapsulation layer 16 covers light-emitting element layer 14 to encapsulate circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. Inorganic films block the penetration of moisture or oxygen. Organic films planarize the surface of inorganic films. When organic and inorganic films are stacked in various layers, the movement path of moisture or oxygen is lengthened compared to a single layer, thus effectively preventing the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0095] A liquid crystal lens layer 18 may be formed on the encapsulation layer 16. The liquid crystal lens layer 18 is used to adjust the light viewing angle. The liquid crystal lens layer 18 includes a first glass layer GL1, a first electrode E1, a liquid crystal layer LCL, a second electrode E2, a second glass layer GL2, and a spacer SPA.

[0096] A first glass layer GL1 may be provided above the encapsulation layer 16. A first electrode E1 may be disposed above the first glass layer GL1, and a liquid crystal layer LCL may be disposed covering the first electrode E1. A second electrode E2 may be disposed above the liquid crystal layer LCL. A second glass layer GL2 may be disposed above the second electrode E2.

[0097] The first electrode E1 includes multiple electrode patterns P1, P2, and P3, and these multiple electrode patterns P1, P2, and P3 are not electrically connected to each other. The multiple electrode patterns P1, P2, and P3 can have the following characteristics: Figure 6A The circular shape in the middle, or it can have the shape of a ring .... Figure 6B The shape is a quadrilateral ring, but this disclosure is not limited thereto.

[0098] Multiple electrode patterns P1, P2, and P3 may include a first electrode pattern P1, a second electrode pattern P2, and a third electrode pattern P3. The size of the first electrode pattern P1 may be larger than the size of the second electrode pattern P2, and the size of the second electrode pattern P2 may be larger than the size of the third electrode pattern P3. The first electrode pattern P1, the second electrode pattern P2, and the third electrode pattern P3 may have the same thickness D.

[0099] The second electrode pattern P2 can be disposed inside the first electrode pattern P1 and spaced apart from the first electrode pattern P1 by a given distance L, and the third electrode pattern P3 can be disposed inside the second electrode pattern P2 and spaced apart from the second electrode pattern P2 by a given distance L.

[0100] Unlike the first electrode, the second electrode E2 can be formed as an electrode in the display area.

[0101] Spacers SPA can divide the liquid crystal layer in units of pixels where the light viewing angle is adjusted, but the embodiments of this disclosure are not limited thereto. For example, spacers SPA can separate the liquid crystal layer in units of regions.

[0102] A second data voltage can be applied to the first electrode E1, and a common voltage can be applied to the second electrode E2. As a result, the refractive index of the liquid crystal material in the liquid crystal layer can be different, and the viewing angle can be different.

[0103] In this embodiment, different second data voltages are applied to the first electrode pattern P1, the second electrode pattern P2, and the third electrode pattern P3 of the first electrode, such that the refractive index of the liquid crystal material is as follows: Figure 7AThe levels of the second data voltage applied to each of the first to third electrode patterns can decrease from the center region of the pixel toward the outer region. The highest first level second data voltage Vdata2_B can be applied to the third electrode pattern P3 located in the center region, a second data voltage Vdata2_G lower than the first level can be applied to the second electrode pattern P2, and a second data voltage Vdata2_R lower than the second level can be applied to the third electrode pattern P1 located in the outermost region.

[0104] A common voltage is applied to the second electrode, and different levels of second data voltages are applied to each of the electrode patterns from the first electrode to the third electrode. Then, the refractive index of the liquid crystal material can be made different according to the region where each of the first to third electrode patterns is set, such as... Figure 7B As shown by the dashed line in the image.

[0105] For example, a minimum refractive index is formed in the region where the first electrode pattern is provided, a medium refractive index is formed in the region where the second electrode pattern is provided, and a maximum refractive index is formed in the region where the third electrode pattern is provided.

[0106] In detail, when the second data voltage is not applied to the first electrode E1, such as Figure 7C As shown, no electric field is applied to the liquid crystal material in the liquid crystal layer LCL. Therefore, the liquid crystal molecules in the liquid crystal material have a first axial direction, i.e., the X-axis direction, which is horizontal with the first glass layer GL1. As a result, the light emitted from the light-emitting element is scattered and the light viewing angle is widened.

[0107] On the other hand, when a predetermined second data voltage is applied to the first electrode E1, since the second data voltage is applied to the first electrode E1 and a common voltage is applied to the second electrode E2, an electric field is applied to the liquid crystal material of the liquid crystal layer LCL. Therefore, the liquid crystal molecules in the liquid crystal material have a second axial direction perpendicular to the first glass layer GL1, i.e., the Y-axis direction. As a result, the light emitted from the light-emitting element remains straight, and the viewing angle narrows.

[0108] In this case, the orientation of the liquid crystal molecules can vary depending on the level of the second data voltage. That is, as the level of the second data voltage increases, the liquid crystal molecules can move closer to the Y-axis direction.

[0109] Figure 8 This diagram illustrates the principle of adjusting the light viewing angle in pixels. Figure 9A and Figure 9B This is a diagram showing the form of an electrode pattern formed by sub-pixels.

[0110] Reference Figure 8 Multiple electrode patterns P1, P2, and P3 can be formed for each of the sub-pixels R, G, and B, and a wide optical viewing angle can be formed when the second data voltage is not applied to the multiple electrode patterns P1, P2, and P3.

[0111] On the other hand, when a second data voltage is applied to multiple electrode patterns P1, P2 and P3, but different data voltages are applied to multiple electrode patterns P1, P2 and P3 so that these regions have different refractive indices as shown by the dashed lines, a narrow optical viewing angle can be formed.

[0112] In this implementation, the first electrodes can be arranged pixel-wise. For example, as... Figure 9A As shown, a first electrode can be set for each of the red sub-pixel R, green sub-pixel G, and blue sub-pixel B, and the light angle can be adjusted on a pixel-by-pixel basis.

[0113] The second data voltage Vdata2_R applied to the red sub-pixel R is applied to the first electrode pattern of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B. The second data voltage Vdata_G applied to the green sub-pixel G is applied to the second electrode pattern, and the second data voltage Vdata_B applied to the blue sub-pixel B is applied to the third electrode pattern.

[0114] As another example, such as Figure 9B As shown, a first electrode is provided for each of the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W. The first electrode includes four electrode patterns: a first electrode pattern P1, a second electrode pattern P2, a third electrode pattern P3, and a fourth electrode pattern P4, and the light viewing angle can be adjusted in units of pixels.

[0115] The second data voltage Vdata2_W applied to the white sub-pixel W is applied together to the first electrode pattern P1 of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W. The second data voltage Vdata2_R applied to the red sub-pixel R is applied together to the second electrode pattern P2. The second data voltage Vdata_G applied to the green sub-pixel G is applied together to the third electrode pattern P3. And the second data voltage Vdata_B applied to the blue sub-pixel B is applied together to the fourth electrode pattern P4.

[0116] When each pixel includes, as Figure 9B When the four sub-pixels are shown, each pixel includes, as shown in the figure, Figure 9A Compared to the case of three sub-pixels shown, the number of electrode patterns is larger, and a smoother distribution of refractive index can be formed. The electrode patterns described herein are merely examples, and this disclosure is not limited thereto.

[0117] Figure 10A and Figure 10B It is shown Figure 5 The diagram shows different shapes of the first electrode.

[0118] refer to Figure 10A and Figure 10B Multiple electrode patterns P1, P2, and P3 can be formed for each predetermined region having multiple sub-pixels R, G, and B, and different second data voltages Vdata2_R, Vdata2_G, and Vdata2_B can be applied to the multiple electrode patterns P1, P2, and P3. Therefore, the optical viewing angle can be adjusted on a region-by-region basis.

[0119] Multiple electrode patterns P1, P2, and P3 can have the following characteristics: Figure 9A The circular shape shown, or may have the following characteristics: Figure 9B The quadrilateral ring shape shown is not limited to this.

[0120] The size of the first electrode pattern P1 can be larger than the size of the second electrode pattern P2, and the size of the second electrode pattern P2 can be larger than the size of the third electrode pattern P3. The first electrode pattern P1, the second electrode pattern P2, and the third electrode pattern P3 can have the same thickness D.

[0121] The second electrode pattern P2 can be disposed inside the first electrode pattern P1 and spaced apart from the first electrode pattern P1 by a given distance L, and the third electrode pattern P3 can be disposed inside the second electrode pattern P2 and spaced apart from the second electrode pattern P2 by a given distance L.

[0122] Here, while an example of setting three subpixels R, G, and B as a region has been described, this disclosure is not limited thereto. For example, when the display area is divided into n regions, multiple electrode patterns P1, P2, and P3 can be formed for each of the n regions.

[0123] Figure 11 This diagram illustrates the principle of adjusting the light viewing angle based on the region.

[0124] Reference Figure 11 When multiple electrode patterns P1, P2, and P3 are formed for each predetermined region having multiple sub-pixels R, G, and B, and a second data voltage is not applied to the multiple electrode patterns P1, P2, and P3, a wide optical viewing angle can be formed.

[0125] On the other hand, when a second data voltage is applied to multiple electrode patterns P1, P2 and P3, but different data voltages are applied to multiple electrode patterns P1, P2 and P3 so that the region has different refractive indices as indicated by the dashed lines, a narrow optical viewing angle can be formed.

[0126] Figures 12A to 12D This is a diagram illustrating the mode switching principle of an embodiment according to the present disclosure.

[0127] Reference Figure 12A In embodiments of this disclosure, when the display area is divided into nine regions, multiple electrode patterns P1, P2, and P3 can be formed for each of the nine regions. Each of the nine regions divided in this way can be driven in a first mode and a second mode.

[0128] As an example, the nine regions can be divided as follows: Figure 12B Two parts, six regions A11, A12, A13, A21, A22 and A23, can be driven in the first mode, and the remaining three regions A31, A32 and A33 can be driven in the second mode.

[0129] As another example, the nine regions can be divided as follows: Figure 12C The two parts, six regions A11, A21, A31, A12, A22 and A32, can be driven in the first mode, and the remaining three regions A13, A23 and A33 can be driven in the second mode.

[0130] As another example, the nine regions can be divided as follows: Figure 12D The two parts, eight regions A11, A12, A13, A21, A23, A31, A32 and A33, can be driven in the first mode, and the remaining region A22 can be driven in the second mode.

[0131] The reason various forms of driving can be implemented is because mode switching can be performed pixel-wise or region-wise. The illustrations described in this article are merely examples, and this disclosure is not limited thereto.

[0132] Figure 13 This is a schematic diagram of the pixel circuit according to the second embodiment of the present invention.

[0133] Reference Figure 13 The pixel circuit according to the second embodiment of this disclosure includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a compensation circuit 10 including a first capacitor Cst, a switching element T1, and a second capacitor Csel. The compensation circuit 10 also includes a plurality of switching elements T2 to T10. The driving element DT and the plurality of switching elements T1 to T9 can be implemented by p-channel transistors, but this disclosure is not limited thereto.

[0134] The driving element DT generates current based on the gate-source voltage Vgs and drives the light-emitting element EL. The driving element DT includes a first electrode connected to the third node n3, a gate electrode connected to the fourth node n4, and a second electrode connected to the fifth node n5.

[0135] The light-emitting element (EL) can be implemented as an organic light-emitting diode (OLED). The EL includes an anode, a cathode, and an organic compound layer formed between the anode and cathode. The anode of the EL is connected to a sixth node n6, and its cathode is connected to a second power line PL2 to which the pixel base voltage VSS is applied. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emissive layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the embodiments described in this disclosure are not limited thereto. The EL can be implemented in a series structure in which multiple emissive layers are stacked. A series-structured EL can improve pixel brightness and lifetime.

[0136] A first switching element T1 is connected between the data line DL and the seventh node n7. The first switching element T1 is turned on according to the gate turn-on voltage VGL of the third scan signal SCAN3, and applies the data voltage Vdata to the seventh node n7. The first switching element T1 includes a first electrode connected to the data line DL, a gate electrode to which the third scan signal SCAN3 or a mode selection signal is applied, and a second electrode connected to the seventh node n7.

[0137] The second switching element T2 is connected between the first power supply line PL1 and the first node n1. The second switching element T2 is turned on according to the gate on-state voltage VGL of the first scan signal SCAN1, and it applies the pixel driving voltage VDD to the first node n1. The second switching element T2 includes a first electrode connected to the first node n1, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the first power supply line PL1 to which the pixel driving voltage VDD is applied.

[0138] The third switching element T3 is connected between the third power supply line PL3 and the fourth node n4. The third switching element T3 is turned on according to the gate turn-on voltage VGL of the first scan signal SCAN1 and applies the initialization voltage Vini to the fourth node n4. The third switching element T3 includes a first electrode connected to the fourth node n4, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the third power supply line PL3 to which the initialization voltage Vini is applied.

[0139] A fourth switching element T4 is connected between the data line DL and the third node n3. The fourth switching element T4 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN2, and applies the data voltage Vdata to the third node n3. The fourth switching element T4 includes a first electrode connected to the third node n3, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the data line DL to which the data voltage Vdata is applied.

[0140] The fifth switching element T5 is connected between the fourth node n4 and the fifth node n5. The fifth switching element T5 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN2, and connects the gate electrode of the driving element DT to the second electrode. The fifth switching element T5 includes a first electrode connected to the fourth node n4, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0141] A sixth switching element T6 is connected between the fourth power supply line PL4 and the first node n1. The sixth switching element T6 is turned on according to the gate on-state voltage VGL of the second scan signal SCAN2, and applies a reference voltage Vref to the first node n1. The sixth switching element T6 includes a first electrode connected to the fourth power supply line PL4 to which the reference voltage Vref is applied, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the first node n1.

[0142] The seventh switching element T7 is connected between the third power supply line PL3 and the sixth node n6. The seventh switching element T7 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN2 and applies the initialization voltage Vini to the sixth node n6. The seventh switching element T7 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vini is applied, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the sixth node n6.

[0143] The eighth switching element T8 is connected between the first power line PL1 and the third node n3. The eighth switching element T8 is turned on according to the gate turn-on voltage VGL of the light emission control signal EM, and connects the first power line PL1 to the third node n3. The eighth switching element T8 includes a first electrode connected to the first power line PL1, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the third node n3.

[0144] A ninth switching element T9 is connected between the first power line PL1 and the second node n2. The ninth switching element T9 is turned on according to the gate on-state voltage VGL of the light emission control signal EM, and applies the pixel driving voltage VDD to the second node n2. The ninth switching element T9 includes a first electrode connected to the first power line PL1, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the second node n2.

[0145] The tenth switching element T10 is connected between the fifth node n5 and the sixth node n6. The tenth switching element T10 is turned on according to the gate turn-on voltage VGL of the light emission control signal EM, and connects the fifth node n5 and the sixth node n6. The tenth switching element T10 includes a first electrode connected to the fifth node n5, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the sixth node n6.

[0146] The first capacitor Cst is connected between the second node n2 and the fourth node n4. The second capacitor Csel is connected between the seventh node n7 and the fifth power line PL5, which is subject to a common voltage.

[0147] Figure 14A and Figure 14B It is shown Figure 13 The diagram shows the specific mode driving waveform of the pixel circuit. Figures 15A to 15D It shows the basis Figure 14B A diagram illustrating the operating principle of a pixel circuit.

[0148] refer to Figure 14A and Figure 14B In the first and second modes, the pixel circuit is driven in the order of initialization period Ti, data writing and sensing period Tw / s, selection period Tsel and emission period Tem.

[0149] Reference Figure 15A During the initialization period Ti, the first switching element T1 and the fourth to tenth switching elements T10 are turned off, while the second switching element T2 and the third switching element T3 are turned on. Then, a pixel driving voltage is applied to the first node n1, and an initialization voltage is applied to the second node n2.

[0150] refer to Figure 15BDuring the data writing and sensing cycle Tw / s, the first switching element T1 to the third switching element T3 and the eighth switching element T8 to the tenth switching element T10 are turned off, while the fourth switching element T4 to the seventh switching element T7 are turned on. Then, the first data voltage Vdata1 is applied to the driving element. Therefore, the threshold voltage Vth of the sensing driving element is measured, and as a result, the voltage at the second node n2 becomes Vdata1 + Vth. Furthermore, a reference voltage Vref is applied to the first node n1, and an initialization voltage Vini is applied to the sixth node n6.

[0151] Reference Figure 15C During the selected time period Tsel, in the first mode, the first switching element T1 to the tenth switching element T10 are turned off, and in the second mode, the second switching element T2 to the tenth switching element T10 are turned off and the first switching element T1 is turned on. Then, the second data voltage Vdata2 is applied to the seventh node n7. Therefore, the voltage at the seventh node n7 becomes "Vdata2".

[0152] The data write and sensing period Tw / s and the selection period Tsel are the periods during which different data voltages are applied. Therefore, in order to change the data voltage, the selection period Tsel can start at least 1 hour after the end of the data write and sensing period Tw / s.

[0153] refer to Figure 15D During the light-emitting cycle Tem, the first switching element T1 to the seventh switching element T7 are turned off, and the eighth switching element T8 to the tenth switching element T10 are turned on. Then, the current generated according to the gate-source voltage of the driving element DT is supplied to the light-emitting element EL, and light is emitted from the light-emitting element EL. Therefore, the voltage of the second node n2 becomes "VDD", and the voltage of the fourth node n4 becomes "VDD-Vref+Vdata+Vth".

[0154] During the emission period Tem, in the first mode, the optical viewing angle remains wide because the second data voltage Vdata2 is not applied to the second capacitor Csel. In the second mode, the optical viewing angle narrows due to the second data voltage Vdata2 and the common voltage VCOM applied to the second capacitor Csel.

[0155] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A pixel circuit, comprising: Light-emitting elements; A driving element is configured to drive the light-emitting element; The compensation circuit includes a first capacitor, the first capacitor including a first electrode to which a first data voltage is applied via a data line and a second electrode connected to the gate electrode of the driving element; A first switching element, wherein a predetermined second data voltage is provided to the first switching element via the data line; as well as The second capacitor includes a first electrode connected to the second electrode of the first switching element and a second electrode connected to a power line to which a common voltage is applied.

2. The pixel circuit of claim 1, wherein the light-emitting element is covered with a liquid crystal lens layer and is configured to emit light in a first mode at a first viewing angle and in a second mode at a second viewing angle narrower than the first viewing angle, depending on whether the second data voltage is supplied.

3. The pixel circuit according to claim 2, wherein the second data voltage is applied to an electrode disposed in the liquid crystal lens layer to change the refractive index of the liquid crystal material in the liquid crystal lens layer.

4. The pixel circuit of claim 2, wherein the first switching element is off in the first mode and on in the second mode.

5. The pixel circuit of claim 2, wherein the first switching element comprises a first electrode connected to the data line, a gate electrode to which a gate signal is applied, and a second electrode connected to the first electrode of the second capacitor.

6. The pixel circuit according to claim 5, wherein: The driving element includes a first electrode connected to a power line to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node. The first capacitor is connected between the first node and the second node, and The compensation circuit includes: The second switching element includes a first electrode connected to the data line, a gate electrode to which a first scan signal is applied, and a second electrode connected to the first node; The third switching element includes a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode connected to the third node; The fourth switching element includes a first electrode connected to the first node, a gate electrode to which a light emission control signal is applied, and a second electrode connected to a power supply line to which a reference voltage is applied. The fifth switching element includes a first electrode connected to the third node, a gate electrode to which the light-emitting control signal is applied, and a second electrode connected to the fourth node; and The sixth switching element includes a first electrode connected to the power line to which the reference voltage is applied, a gate electrode to which the second scan signal is applied, and a second electrode connected to the fourth node.

7. The pixel circuit according to claim 6, wherein: The pixel circuit is driven in the order of initialization, data writing and sensing, selection and emission. During the data writing and sensing steps, the second switching element, the third switching element, and the sixth switching element are turned on, and the first data voltage is applied to the first electrode of the first capacitor. In the selection step following the data writing and sensing steps, the first switching element is turned on, and the second data voltage is applied to the first electrode of the second capacitor.

8. The pixel circuit of claim 7, wherein the selection step is driven when a predetermined time has elapsed after the data writing and sensing steps have ended.

9. The pixel circuit according to claim 5, wherein: The driving element includes a first electrode connected to a third node, a gate electrode connected to a fourth node, and a second electrode connected to a fifth node. The first capacitor is connected between the second node and the fourth node, and The compensation circuit includes: The second switching element includes a first electrode connected to the first node, a gate electrode to which a first scan signal is applied, and a second electrode connected to a power line to which a pixel driving voltage is applied. The third switching element includes a first electrode connected to the fourth node, a gate electrode to which the first scan signal is applied, and a second electrode connected to a power line to which an initialization voltage is applied. The fourth switching element includes a first electrode connected to the third node, a gate electrode to which a second scan signal is applied, and a second electrode connected to the data line; The fifth switching element includes a first electrode connected to the fourth node, a gate electrode to which the second scan signal is applied, and a second electrode connected to the fifth node; The sixth switching element includes a first electrode connected to a power supply line to which a reference voltage is applied, a gate electrode to which the second scan signal is applied, and a second electrode connected to the first node; The seventh switching element includes a first electrode connected to the power line to which the initialization voltage is applied, a gate electrode to which the second scan signal is applied, and a second electrode connected to the anode electrode of the light-emitting element; The eighth switching element includes a first electrode connected to the power line to which the pixel driving voltage is applied, a gate electrode to which a light emission control signal is applied, and a second electrode connected to the third node; The ninth switching element includes a first electrode connected to the power line to which the pixel driving voltage is applied, a gate electrode to which the light emission control signal is applied, and a second electrode connected to the second node; and The tenth switching element includes a first electrode connected to the fifth node, a gate electrode to which the light-emitting control signal is applied, and a second electrode connected to the anode electrode of the light-emitting element.

10. The pixel circuit according to claim 1, wherein the number of light-emitting elements is one.

11. A display device, comprising: The display panel includes a display area with multiple sub-pixels. The display panel includes: substrate; A circuit layer is disposed above the substrate; A light-emitting element layer is disposed above the circuit layer; An encapsulation layer is disposed above the light-emitting element layer; and A liquid crystal lens layer includes a first electrode, a liquid crystal layer, and a second electrode. The first electrode includes a plurality of electrode patterns spaced apart from each other above the encapsulation layer. The liquid crystal layer covers the first electrode, and the second electrode is disposed above the liquid crystal layer. A predetermined data voltage is applied to each of the plurality of electrode patterns disposed in the first electrode, and a predetermined common voltage is applied to the second electrode.

12. The display device of claim 11, wherein the plurality of sub-pixels includes a first sub-pixel to a third sub-pixel, and The plurality of electrode patterns include: The first electrode pattern, the data voltage applied to the first sub-pixel is applied to the first electrode pattern; The second electrode pattern, the data voltage applied to the second sub-pixel is applied to the second electrode pattern; as well as The third electrode pattern, the data voltage applied to the third sub-pixel is applied to the third electrode pattern.

13. The display device according to claim 12, wherein the plurality of electrode patterns have a circular shape or a quadrilateral shape.

14. The display device according to claim 13, wherein: The second electrode pattern is formed inside the first electrode pattern and spaced apart from the first electrode pattern, and The third electrode pattern is disposed inside the second electrode pattern and spaced apart from the second electrode pattern.

15. The display device of claim 14, wherein the data voltage applied to the second electrode pattern is higher than the data voltage applied to the first electrode pattern and lower than the data voltage applied to the third electrode pattern.

16. The display device of claim 12, wherein the plurality of electrode patterns are formed for each sub-pixel or for each plurality of sub-pixels.

17. The display device of claim 16, wherein the liquid crystal lens layer is formed for each sub-pixel or for each plurality of sub-pixels.

18. The display device of claim 11, wherein each of the sub-pixels comprises: Light-emitting elements; A driving element is configured to drive the light-emitting element; The compensation circuit includes a first capacitor, the first capacitor including a first electrode to which a first data voltage is applied via a data line and a second electrode connected to the gate electrode of the driving element; A first switching element, wherein a predetermined second data voltage is provided to the first switching element via the data line; as well as The second capacitor includes a first electrode connected to the second electrode of the first switching element and a second electrode connected to a power line to which a common voltage is applied.

19. The display device according to claim 18, wherein the number of light-emitting elements is one.

20. The display device of claim 18, wherein the light-emitting element is covered with a liquid crystal lens and is configured to emit light in a first viewing angle in a first mode, depending on whether the second data voltage is provided, and to emit light in a second mode in a second viewing angle narrower than the first viewing angle.

21. The display device according to claim 20, wherein the first switching element is disconnected in the first mode and turned on in the second mode.

22. The display device of claim 21, wherein the first switching element includes a first electrode connected to the data line, a gate electrode to which a gate signal is applied, and a second electrode connected to the first electrode of the second capacitor.

23. A pixel circuit for driving a pixel, the pixel comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the pixel circuit comprising a first sub-pixel circuit for the first sub-pixel, a second sub-pixel circuit for the second sub-pixel, and a third sub-pixel circuit for the third sub-pixel, each of the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit comprising: Light-emitting elements; A driving element is configured to drive the light-emitting element; The compensation circuit includes a first capacitor, the first capacitor including a first electrode to which a first data voltage is applied via a data line and a second electrode connected to the gate electrode of the driving element; A first switching element, wherein a predetermined second data voltage is provided to the first switching element via the data line; as well as The second capacitor includes a first electrode connected to the second electrode of the first switching element and a second electrode connected to a power supply line to which a common voltage is applied. The second data voltages applied by the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit are different from each other.

24. The pixel circuit of claim 23, wherein the light-emitting elements of the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit are collectively covered with a liquid crystal lens layer, and are configured to emit light in a first mode at a first viewing angle and in a second mode at a second viewing angle narrower than the first viewing angle, depending on whether the second data voltage of the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit is supplied.

25. The pixel circuit of claim 24, wherein the liquid crystal lens layer includes electrodes having a plurality of electrode patterns, the plurality of electrode patterns including: The first electrode pattern, the second data voltage of the first sub-pixel circuit is applied to the first electrode pattern; The second electrode pattern, the second data voltage of the second sub-pixel circuit is applied to the second electrode pattern; as well as The third electrode pattern, to which the data voltage of the third sub-pixel circuit is applied.

26. The pixel circuit according to claim 25, wherein: The second electrode pattern is formed inside the first electrode pattern and spaced apart from the first electrode pattern, and The third electrode pattern is disposed inside the second electrode pattern and spaced apart from the second electrode pattern.

27. The pixel circuit of claim 26, wherein the second data voltage of the second sub-pixel circuit is higher than the second data voltage of the first sub-pixel circuit, and the second data voltage of the third sub-pixel circuit.

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