Memory system and semiconductor memory device

Abstract

A memory system and a semiconductor storage device capable of reducing a circuit area are provided. The memory system includes a plurality of semiconductor storage devices and a control device. Each of the plurality of semiconductor storage devices includes a first memory cell array, a second memory cell array, a first data signal input / output terminal usable for output of data read out from the first memory cell array, a second data signal input / output terminal usable for output of data read out from the second memory cell array, and a first control terminal capable of receiving a switching signal from the control device when outputting data read out from at least one of the first memory cell array and the second memory cell array. The control device switches the signal of the first control terminal at a substantially constant frequency regardless of whether or not input / output of data via the first data signal input / output terminal and the second data signal input / output terminal is being performed.

Description

Technical Field

[0001] This embodiment relates to a memory system and a semiconductor memory device. Background Technology

[0002] A memory system having multiple semiconductor memory devices and control devices is known. The semiconductor memory devices include a memory cell array comprising multiple first memory cell transistors connected in series. Summary of the Invention

[0003] The present invention provides a memory system and semiconductor memory device that can reduce circuit area.

[0004] One embodiment of the memory system includes multiple semiconductor memory devices and a control device. Each of the multiple semiconductor memory devices includes: a first memory cell array comprising a plurality of first memory cell transistors connected in series; a second memory cell array comprising a plurality of second memory cell transistors connected in series; a first data signal input / output terminal, usable for outputting data read from the first memory cell array and inputting data written to the first memory cell array; a second data signal input / output terminal, usable for outputting data read from the second memory cell array and inputting data written to the second memory cell array; and a first control terminal, capable of receiving a switching signal from the control device when outputting data read from at least one of the first and second memory cell arrays. The control device switches the signal of the first control terminal at a substantially constant frequency, regardless of whether data input / output is being performed via the first and second data signal input / output terminals. Attached Figure Description

[0005] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10.

[0006] Figure 2 This is a schematic side view showing an example of the configuration of the packaged PKG included in the memory system 10.

[0007] Figure 3 This is a schematic top view showing an example of the configuration of the packaged PKG included in the memory system 10.

[0008] Figure 4 This is a schematic exploded perspective view showing an example of the configuration of a memory die (MD).

[0009] Figure 5 This indicates that chip C M A schematic bottom view of the composition example.

[0010] Figure 6 This indicates that chip C PA schematic top view of the constituent examples.

[0011] Figure 7 This is a schematic circuit diagram representing a portion of the memory cell array (MCA).

[0012] Figure 8 This is a schematic circuit diagram representing a portion of the memory block BLK.

[0013] Figure 9 It is a schematic block diagram showing the configuration of the peripheral circuit PC.

[0014] Figure 10 It is a schematic circuit diagram representing a portion of the peripheral circuit PC.

[0015] Figure 11 This is a schematic block diagram illustrating the signal path of user data Dat on the memory die MD in the first embodiment.

[0016] Figure 12 This is a schematic block diagram illustrating the signal path of the user data Dat on the memory die MD' of the comparative example.

[0017] Figure 13 This is a schematic diagram used to illustrate the function of the signal input / output terminals and control terminals in a memory die (MD).

[0018] Figure 14 It is a schematic waveform diagram used to illustrate the operation of a memory die (MD).

[0019] Figure 15 It is a schematic table used to illustrate the operation of the memory die (MD).

[0020] Figure 16 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0021] Figure 17 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0022] Figure 18 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0023] Figure 19 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0024] Figure 20 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0025] Figure 21 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0026] Figure 22 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0027] Figure 23 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0028] Figure 24 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0029] Figure 25 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0030] Figure 26 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0031] Figure 27 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0032] Figure 28 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0033] Figure 29 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD.

[0034] Figure 30 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD. Detailed Implementation

[0035] Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. For ease of explanation, some components may be omitted. Additionally, common parts in multiple embodiments may be labeled with the same reference numerals, and descriptions may be omitted.

[0036] Furthermore, in this specification, the term "memory system" sometimes refers to systems containing controller dies, such as memory cards and SSDs (Solid State Drives). Additionally, it sometimes refers to components including host computers, such as smartphones, tablets, and personal computers.

[0037] Furthermore, in this specification, when the first component and the second component are referred to as "electrically connected," the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is still "electrically connected" to the third transistor.

[0038] Furthermore, in this specification, when referring to the first component as "connected" "between" the second and third components, it is intended to mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0039] Furthermore, in this specification, the specified direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0040] [Implementation Method]

[0041] [Memory System 10]

[0042] Figure 1 This is a schematic block diagram illustrating the configuration of the memory system 10 in the embodiment.

[0043] The memory system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host 20. The memory system 10 may be, for example, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes multiple packaged memory modules (PKGs) and a controller die CD connected to these PKGs and the host 20. Each packaged PKG contains multiple memory dies (MDs). Each memory die CD can store user data. The controller die CD may include, for example, a processor and RAM (Random Access Memory), and performs processes such as logical address to physical address conversion, bit error detection / correction, garbage collection (compression), and wear leveling.

[0044] Figure 2 This is a schematic side view showing an example of the configuration of the packaged PKG included in the memory system 10 of this embodiment. Figure 3is a schematic top view showing a configuration example of a package PKG included in the memory system 10 of the present embodiment. For ease of explanation, in Figure 2 and Figure 3 a part of the configuration is omitted.

[0045] As Figure 2 shown, the package PKG of the present embodiment includes a memory die mounting substrate MSB and a plurality of memory dies MD stacked on the memory die mounting substrate MSB. Pad electrodes P are provided in end regions in the Y direction on the upper surface of the memory die mounting substrate MSB, and a part of the other regions is bonded to the lower surface of the memory die MD via an adhesive or the like. Pad electrodes P are provided in end regions in the Y direction on the upper surface of the memory die MD, and the other regions are bonded to the lower surface of other memory dies MD via an adhesive or the like. The corresponding pad electrodes P between the plurality of memory dies MD are commonly connected by bonding wires B. Electrode terminals T are provided on the lower surface of the memory die mounting substrate MSB. The pad electrodes P on the upper surface of the memory die mounting substrate MSB are respectively connected to the electrode terminals T on the lower surface. The memory die mounting substrate MSB may also be, for example, a grid array substrate. On the upper surface of the memory die mounting substrate MSB, the plurality of memory dies MD and the bonding wires B are covered with a sealing resin (not shown), for example.

[0046] In addition, as Figure 3 shown, the memory die mounting substrate MSB and each of the plurality of memory dies MD include a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P of each memory die MD respectively correspond to control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, / WP, data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS, / DQS, and terminals RY / / BY described later. [[ID=~]]

[0047] The memory die mounting substrate MSB and the plurality of pad electrodes P provided on the plurality of memory dies MD are respectively connected to each other via bonding wires B. For example, the pad electrodes P corresponding to the control terminal CA1 (CLE) among the plurality of memory dies MD are connected to each other, and the pad electrodes P corresponding to the control terminal CA0 (ALE) are connected to each other. The same applies to other terminals. In addition, the pad electrodes P of each memory die MD inside the package PKG are connected to the outside of the package PKG via the electrode terminals T on the lower surface of the memory die mounting substrate MSB.

[0048] In addition, Figure 2 and Figure 3 The configurations shown are only examples, and the specific configurations can be adjusted appropriately. For example, in Figure 2In the example shown, multiple memory dies (MDs) are stacked, and these are connected by bonding lines B. However, multiple memory dies (MDs) can also be interconnected via through electrodes or the like, without bonding lines B.

[0049] [Memory Die MD]

[0050] Figure 4 This is a schematic exploded perspective view showing an example of the configuration of the memory die (MD) in this embodiment. Figure 4 As shown, the memory die MD has a chip C on the memory cell array side. M , and the chip C on the peripheral circuit side P .

[0051] In chip C M The upper surface is provided with multiple external pad electrodes P that can be connected to bonding lines (not shown). X Furthermore, in chip C M Multiple bonding electrodes P are set on the lower surface. I1 Furthermore, in chip C P Multiple bonding electrodes P are set on the upper surface. I2 The following is about chip C. M Multiple bonding electrodes P will be set. I1 The side referred to as the front side will have multiple external pad electrodes P set on it. X The side facing out is called the back side. Furthermore, regarding chip C... P Multiple bonding electrodes P will be set. I2 The side facing out is called the front side, and the side opposite the front side is called the back side. In the example shown, chip C P The front side is set at the chip C P On the back, further up, chip C M The back is set on the chip C M Above and on the front.

[0052] Chip C M and chip C P Configured as chip C M The front of the chip C P The front faces each other. Multiple bonding electrodes P I1 Each with multiple bonding electrodes P I2 Corresponding settings, configured to be compatible with multiple bonding electrodes P I2 The bonding location. Bonding electrode P I1 With the bonding electrode PI2 as used to attach the chip C M With chip C P The bonding electrodes, which are attached and electrically conductive, function.

[0053] In addition, Figure 4 In the example, chip CM The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0054] Figure 5 This indicates that chip C M A schematic bottom view of the component example. Chip C M For example, Figure 5 As shown, the chip has two memory cell arrays, MCA0 and MCA1, arranged along the X direction. Multiple memory blocks BLK are arranged along the Y direction within the memory cell arrays MCA0 and MCA1. Furthermore, chip C... M It has an outer region R located at one end of the two memory cell arrays MCA0 and MCA1, further along the Y direction. P Additionally, in the following description, memory cell arrays MCA0 and MCA1 may be referred to as memory cell array MCA. Furthermore, memory cell arrays MCA0 and MCA1 may be referred to as planar PLN0 and PLN1.

[0055] Figure 6 This indicates that chip C P A schematic top view illustrating the configuration of a chip C. P For example, Figure 5 As shown, it has two circuit regions R located opposite to the two memory planes MP0 and MP1. PC0 R PC1 Circuit region R PC0 R PC1 Each chip possesses sensing amplifiers SA0 and SA1, and line decoders RD0 and RD1, as described later. Furthermore, chip C... P Equipped to be set in two circuit regions R PC0 R PC1 Circuit region R on the side closer to the Y direction PC2 In circuit region R PC0 R PC1 R PC2 Configure the peripheral circuit.

[0056] [Composition of a Memory Cell Array (MCA)]

[0057] Figure 7This is a schematic circuit diagram representing a portion of a memory cell array (MCA). As described above, the MCA comprises multiple memory blocks (BLK). Each of these memory blocks (BLK) comprises multiple string cells (SU). Each of these string cells (SU) comprises multiple memory strings (MS). One end of each of these memory strings (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). Furthermore, the other end of each of these memory strings (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0058] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes simply referred to as selection transistor STD and STS, respectively.

[0059] A memory cell (MC) is a field-effect transistor (FET) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. The memory cell (MC) stores one or more bits of user data. Additionally, word lines (WL) are connected to the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS). These word lines (WL) are collectively connected to all memory strings (MS) within a memory block (BLK).

[0060] Select transistors STD and STS are field-effect transistors with a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines SGD and SGS are connected to the gate electrodes of select transistors STD and STS, respectively. On the drain side, the select gate line SGD corresponds to the string cell SU and is connected to all memory strings MS in one string cell SU. On the source side, the select gate line SGS is connected to all memory strings MS in the memory block BLK.

[0061] Figure 8 This is a schematic circuit diagram representing a portion of a memory block BLK. For example, ... Figure 8 As shown, the memory block BLK is located in chip C. P Above the semiconductor substrate Sub. Furthermore, multiple transistors Tr constituting the peripheral circuit PC are disposed on the main surface of the semiconductor substrate Sub.

[0062] The memory block BLK includes a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor pillars 120 extending along the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0063] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0064] Furthermore, one or more of the uppermost conductive layers 110 among the multiple conductive layers 110 serve as the source-side selected gate line (SGS). Figure 7 ) and multiple source-side selection transistors (STS) connected to it. Figure 7 The gate electrode of the memory block BLK functions. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0065] In addition, multiple conductive layers 110 located below it serve as word lines WL ( Figure 7 ) and multiple storage units MC connected to it Figure 7 The gate electrode of the memory block BLK functions. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0066] Furthermore, one or more conductive layers 110 located below it serve as drain-side selected gate lines SGD and multiple drain-side selected transistors STD connected thereto. Figure 7 The gate electrode of the conductive layer 110 functions. The width of these multiple conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110.

[0067] A semiconductor layer 112 is disposed above the conductive layer 110. The semiconductor layer 112 may contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the semiconductor layer 112 and the conductive layer 110.

[0068] Semiconductor layer 112 serves as the source line SL ( Figure 7 It performs its function. For example, the source line SL is configured commonly for all memory blocks BLK contained in the memory cell array MCA.

[0069] Semiconductor pillars 120 are arranged in a prescribed pattern in the X and Y directions. The semiconductor pillars 120 serve as a memory string (MS). Figure 7 The multiple memory cells MC and the channel regions of the selection transistors STD and STS contained therein function. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has a generally bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central portion. In addition, the outer peripheral surfaces of the semiconductor pillar 120 are surrounded by conductive layers 110, which face each other.

[0070] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via the contacts Ch and Cb.

[0071] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a blocking insulating film laminated between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the blocking insulating film are insulating films such as silicon oxide (SiO2), for example. The charge storage film is a film capable of storing charges such as silicon nitride (Si3N4), for example. The tunnel insulating film, the charge storage film, and the blocking insulating film have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120 except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0072] In addition, the gate insulating film 130 may include, for example, a floating gate such as polysilicon containing N-type or P-type impurities.

[0073] [Configuration of Peripheral Circuit PC]

[0074] Figure 9 It is a schematic block diagram showing the configuration of the peripheral circuit PC. Figure 10 It is a schematic circuit diagram showing a part of the configuration of the peripheral circuit PC. For ease of explanation, in Figure 9 and Figure 10 a part of the configuration is omitted.

[0075] In addition, in Figure 9 etc., a plurality of control terminals and the like are shown. These plurality of control terminals may be shown as control terminals corresponding to high-active signals (positive logic signals), may be shown as control terminals corresponding to low-active signals (negative logic signals), or may be shown as control terminals corresponding to both high-active signals and low-active signals. In Figure 9 the symbol of the control terminal corresponding to the low-active signal includes an overbar (overline). In this specification, the symbol of the control terminal corresponding to the low-active signal includes a slash (“ / ”). In addition, Figure 9 the description of

[0076] is an example, and the specific form can be appropriately adjusted. For example, a part or all of the high-active signals may be set as low-active signals, or a part or all of the low-active signals may be set as high-active signals. Figure 9 In addition, next to the plurality of control terminals shown in Figure 9 arrows indicating the input / output direction are shown. In Figure 9In the diagram, the control terminals marked with arrows from right to left can be used to output data or other signals from the memory die (MD) to the controller die (CD). Figure 9 The control terminals marked with bidirectional arrows can be used to input data or other signals from the controller die CD to the memory die MD, and to output data or other signals from the memory die MD to the controller die CD.

[0077] For example, Figure 9 As shown, the peripheral circuit PC includes line decoders RD0 and RD1, and sense amplifiers SA0 and SA1, which are respectively connected to the memory cell arrays MCA0 and MCA1. Furthermore, the peripheral circuit PC includes a driver circuit DRV, a voltage generation circuit VG, and a sequence generator SQC. In addition, the peripheral circuit PC also includes input / output control circuits (I / O), logic circuits CTR, address register ADR, instruction register CMR, status register STR, and data output timing adjustment unit TCT. In the following description, line decoders RD0 and RD1 will sometimes be referred to as line decoders RD, and sense amplifiers SA0 and SA1 will sometimes be referred to as sense amplifiers SA.

[0078] The row decoder RD decodes the row address RA in the address data Add, thereby enabling all word lines WL contained in one of the multiple memory blocks BLK. Figure 7 It is connected to the driver circuit DRV.

[0079] Sensing amplifiers SA0 and SA1 each have sensing amplifier modules SAM0 and SAM1, and high-speed cache memories CM0 and CM1. High-speed cache memories CM0 and CM1 each have latch circuits XDL0 and XDL1.

[0080] Additionally, in the following description, the sense amplifier modules SAM0 and SAM1 will be referred to as sense amplifier modules SAM, the cache memories CM0 and CM1 will be referred to as cache memories CM, and the latch circuits XDL0 and XDL1 will be referred to as latch circuits XDL.

[0081] The sensing amplifier module (SAM) for example has multiple bit lines (BL) respectively. Figure 7 The sensing circuit is electrically connected, and multiple latching circuits are connected to the sensing circuit.

[0082] The cache memory CM has multiple latch circuits XDL. Each latch circuit XDL is electrically connected to a latch circuit within the sense amplifier module SAM. For example, user data Dat written to or read from the memory cell MC is stored in the latch circuit XDL.

[0083] The voltage generation circuit VG includes, for example, a buck circuit such as a regulator and a boost circuit such as a charge pump. These buck and boost circuits are respectively connected to the supplied power supply voltage V. CC The voltage supply line and the supplied ground voltage V SS The voltage supply lines are connected. These voltage supply lines are, for example, connected to the reference. Figure 2 , Figure 3 The pad electrode P connection is described. The voltage generation circuit VG, for example, generates and outputs various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines SGD and SGS during read, write, and erase operations of the memory cell array MCA, according to control signals from the sequence generator SQC. These various operating voltages are appropriately adjusted according to the control signals from the sequence generator SQC.

[0084] The driver circuit DRV decodes the row address RA in the address data Add, enabling one of the multiple word lines WL to conduct with the voltage supply line corresponding to the selected word line, and enabling the other word lines WL to conduct with the voltage supply lines corresponding to the non-selected word lines. Furthermore, it enables one of the multiple drain-side select gate lines SGD to conduct with a specified voltage supply line, and enables the other drain-side select gate lines SGD to conduct with the other voltage supply lines.

[0085] Furthermore, the driver circuit DRV, according to the control signal from the sequence generator SQC, appropriately supplies voltage to the voltage supply lines corresponding to the selected word lines, the voltage supply lines corresponding to the non-selected word lines, the specified voltage supply lines, and other voltage supply lines, as well as the buck circuit, the boost circuit, and the supplied power supply voltage V. CC The voltage supply line, or the voltage V supplied to the ground SS The voltage supply line is turned on.

[0086] Sequence generator SQC ( Figure 4 According to the instruction data Cmd stored in the instruction register CMR, the internal control signals are output to the line decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, the driver circuit DRV, and the voltage generation circuit VG. In addition, the sequence generator SQC appropriately outputs the status data Stt, representing the status of the memory die MD, to the status register STR. The status of the memory die MD includes its ready / busy state. Furthermore, the ready / busy state will be referred to as "ready-busy state" in the following cases.

[0087] In addition, the sequence generator SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY is in the "L" state during operations that supply voltage to the memory cell array MCA, such as read operations, write operations, erase operations, and the get feature and set feature operations described later; otherwise, it is in the "H" state. Furthermore, even when performing operations that do not supply voltage to the memory cell array MCA, such as data output operations and status reads, the terminal RY / / BY is not in the "L" state. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is essentially prohibited. Conversely, during the period when the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. Additionally, the terminal RY / / BY is, for example, referenced... Figure 2 , Figure 3 The pad electrode P is described in the description.

[0088] In addition, the sequence generator SQC has a feature register FR. The feature register FR is a register that stores feature data Fd. Feature data Fd may contain, for example, control parameters of the memory die MD.

[0089] The address register (ADR) is connected to the input / output control circuit (I / O) and stores the address data (Add) input from the I / O circuit. The address register (ADR) may have multiple 8-bit register columns. These register columns store the address data (Add) corresponding to the internal operation performed during execution, such as read, write, or erase operations.

[0090] Additionally, the address data Add may contain, for example, the column address CA ( Figure 4 ) and row address RA ( Figure 4 The row address RA, for example, contains the memory block BLK (). Figure 4 The block address of the memory cell array (MCA) is determined, the page address of the string cell (SU) and word line (WL) is determined, the plane address of the memory cell array (MCA) is determined, and the chip address of the memory die (MD) is determined.

[0091] The instruction register (CMR) is connected to the input / output control circuit (I / O) and stores the instruction data (Cmd) input from the I / O. The instruction register CMR, for example, has at least one set of 8-bit register columns. After storing the instruction data Cmd in the instruction register CMR, a control signal is sent to the sequence generator (SQC).

[0092] The status register STR is connected to the input / output control circuit (I / O) and stores status data Stt for output to the I / O circuit. The status register STR may have multiple 8-bit register columns. These register columns, for example, store status data Stt related to internal operations such as read, write, or erase during execution. Furthermore, the register columns may store ready / busy information indicating the ready / busy status of memory cell arrays MCA0 and MCA1.

[0093] The data output timing adjustment unit (TCT) is connected to the bus wiring DB between the cache memories CM0 and CM1 and the input / output control circuit (I / O). For example, when continuously performing data output operations on the cache memories CM0 and CM1, the TCT adjusts the start timing of the data output operation for the cache memory CM1 after the data output operation of the cache memory CM0 is completed, so as not to start the data output operation of the cache memory CM1 immediately after the idle time.

[0094] The input / output control circuit (I / O) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and / DQS, a shift register, a buffer circuit, and a connection change circuit SW.

[0095] Data signal input / output terminals DQ0~DQ7 and data strobe signal input / output terminals DQS, / DQS, for example, via reference Figure 2 , Figure 3 The pad electrode P is described above. User data Dat, input via data signal input / output terminals DQ0 to DQ7, is input from the buffer circuit to the cache memory CM according to the internal control signal from the logic circuit CTR. Furthermore, user data Dat output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0096] Signals input via data strobe input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used, for example, when user data Dat is input via data signal input / output terminals DQ0 to DQ7. The user data Dat input via data signal input / output terminals DQ0 to DQ7 is extracted into a shift register within the input / output control circuit I / O at the timing of the rising edge of the voltage at data strobe input / output terminal DQS and the falling edge of the voltage at data strobe input / output terminal / DQS, and at the timing of the falling edge of the voltage at data strobe input / output terminal DQS and the rising edge of the voltage at data strobe input / output terminal / DQS.

[0097] Furthermore, the data strobe signal input / output terminals DQS and / DQS are also used, for example, when outputting user data Dat via data signal input / output terminals DQ0 to DQ7. The user data Dat output via data signal input / output terminals DQ0 to DQ7 is switched according to the timing of the rising edge of the voltage at data strobe signal input / output terminal DQS and the falling edge of the voltage at data strobe signal input / output terminal / DQS, and the timing of the falling edge of the voltage at data strobe signal input / output terminal DQS and the rising edge of the voltage at data strobe signal input / output terminal / DQS.

[0098] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS and / DQS is, for example, Figure 10 As shown, it is connected to input circuit 201 and output circuit 202. Input circuit 201 is, for example, a receiver such as a comparator. Output circuit 202 is, for example, a driver such as an OCD (Off-Chip Driver) circuit.

[0099] The logic circuit CTR has multiple control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, and logic circuits connected to these control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, and outputs internal control signals to the input / output control circuit (I / O) based on these signals.

[0100] Control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, for example Figure 10 As shown, it is connected to the input circuit 201. In addition, the control terminals CA1 (CLE) and CA0 (ALE) are connected to the output circuit 202 in addition to the input circuit 201. The control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, and RE are connected, for example, via reference... Figure 2 , Figure 3 The pad electrode P is described in the description.

[0101] Signals input via the control terminal / CE (e.g., chip start signal) are used when selecting the memory die MD. A memory die MD input with "L" to the control terminal / CE is in a state where it can input / output user data Dat, instruction data Cmd, address data Add, and status data Stt (hereinafter simply referred to as "data"). A memory die MD input with "H" to the control terminal / CE is in a state where it cannot input / output data.

[0102] The functions of control terminals CA1 (CLE), CA0 (ALE), and CA_clk ( / WE) will be described later.

[0103] Signals input via control terminals / RE and RE (e.g., read start signal and its complementary signal) are used when inputting and outputting data to the memory die MD. Here, as described later, the controller die CD inputs multiple instruction sets, instructions, etc. to the memory die MD. In addition, the controller die CD obtains user data Dat, etc., from the memory die MD. During this period, regardless of whether user data Dat is being input / output via data signal input / output terminals DQ0 to DQ7, the controller die CD continuously inputs "L" state signals and "H" state signals to the control terminals / RE and RE at a roughly constant rhythm. That is, the controller die CD continuously switches the input signals to the control terminals / RE and RE at a roughly constant frequency. The user data Dat output from the data signal input / output terminals DQ0 to DQ7 switches according to the timing of the falling edge of the voltage at the control terminal / RE and the rising edge of the voltage at the control terminal RE, and the timing of the rising edge of the voltage at the control terminal / RE and the falling edge of the voltage at the control terminal RE.

[0104] [Signal path of user data Dat in the memory die MD of the first embodiment]

[0105] Figure 11 This is a schematic block diagram illustrating the signal path of user data Dat on the memory die MD in the first embodiment.

[0106] The memory cell arrays MCA0 and MCA1 each have, for example, 16 × 1024 × 8 (=131,072) bit lines BL. The sense amplifier modules SAM0 and SAM1 each have 16 × 1024 × 8 latch circuits corresponding to them. The cache memories CM0 and CM1 also each have 16 × 1024 × 8 latch circuits XDL0 and XDL1 corresponding to them.

[0107] In the memory die MD of the first embodiment, when outputting user data Dat, the user data Dat is transmitted from the cache memories CM0 and CM1 to the data signal input / output terminals DQ0 to DQ7 at a substantially constant speed (4096 MHz in the illustrated example).

[0108] For example, cache memories CM0 and CM1 are connected to the column decoder COLD. The cache memories CM0 and CM1 are connected to the column decoder COLD, for example, via a 512-bit bus. The input / output of user data Dat between the cache memories CM0 and CM1 and the column decoder COLD is performed, for example, at 8MHz.

[0109] The column decoder COLD is connected to the multiplexer MPX. The column decoder COLD and the multiplexer MPX are connected, for example, via a 128-bit bus. The input / output of user data Dat between the column decoder COLD and the multiplexer MPX is performed, for example, at 32MHz.

[0110] The input / output control circuit (I / O) includes buffer circuits GFIFO, LFIFO, and driver circuit OCD corresponding to the memory cell array MCA0, as well as buffer circuits GFIFO, LFIFO, and driver circuit OCD corresponding to the memory cell array MCA1.

[0111] The multiplexer MPX is connected to the buffer circuit GFIFO. The multiplexer MPX and the buffer circuit GFIFO are connected, for example, via a 128-bit bus. The input and output of user data Dat between the multiplexer MPX and the buffer circuit GFIFO are performed, for example, at 32MHz.

[0112] The buffer circuit GFIFO is connected to the buffer circuit LFIFO. The buffer circuits GFIFO and LFIFO are connected via, for example, a 16-bit bus. The input / output of user data Dat between the buffer circuits GFIFO and LFIFO is performed, for example, at 256MHz.

[0113] The driver circuit OCD corresponding to the memory cell array MCA0 includes four output circuits 202 corresponding to the data signal input / output terminals DQ0 to DQ3. Figure 10 In other words, the user data Dat read from the memory cell array MCA0 is output via data signal input / output terminals DQ0 to DQ3. Data signal input / output terminals DQ0 to DQ3 have a signal path for the user data Dat between the memory cell array MCA0 and the memory cell array MCA1, but do not have a signal path for the user data Dat between the memory cell array MCA1 and the memory cell array MCA1.

[0114] The driver circuit OCD corresponding to the memory cell array MCA1 includes four output circuits 202 corresponding to the data signal input / output terminals DQ4 to DQ7. Figure 10 In other words, the user data Dat read from the memory cell array MCA1 is output via data signal input / output terminals DQ4 to DQ7. Data signal input / output terminals DQ4 to DQ7 have a signal path for the user data Dat between the memory cell array MCA1 and the memory cell array MCA0, but do not have a signal path for the user data Dat between the memory cell array MCA0 and the memory cell array MCA1.

[0115] The input / output of user data Dat between the buffer circuit LFIFO and the driver circuit OCD is performed, for example, at 512MHz. Furthermore, the driver circuit OCD communicates with the controller bare CD (…). Figure 1 The input and output of user data Dat between the data signal input / output terminals DQ0 to DQ7 is performed, for example, at 1024MHz.

[0116] [Signal path of user data Dat on the memory die MD' in the comparative example]

[0117] Figure 12 This is a schematic block diagram illustrating the signal path of the user data Dat on the memory die MD' of the comparative example.

[0118] The comparative example driver circuit OCD includes eight output circuits 202 corresponding to the data signal input / output terminals DQ0 to DQ7. Figure 10 These eight output circuits 202 correspond to the memory cell arrays MCA0 and MCA1. That is, in the comparative example, when outputting user data Dat read from memory cell array MCA0, all data signal input / output terminals DQ0 to DQ7 are used. Similarly, when outputting user data Dat read from memory cell array MCA1, all data signal input / output terminals DQ0 to DQ7 are used.

[0119] Here, in the memory die MD' of the comparative example, when outputting user data Dat, the user data Dat is also transmitted from the cache memory CM0, CM1 to the data signal input / output terminals DQ0 to DQ7 at a roughly constant speed (4096MHz in the illustrated example).

[0120] Therefore, in the comparative example's memory die MD', the input / output of user data Dat between the cache memories CM0, CM1 and the column decoder COLD is executed at a speed several times faster, for example, 16MHz, compared to the first embodiment. Therefore, the comparative example's cache memories CM0, CM1 and column decoder COLD are configured to include transistors that operate at a speed several times faster than in the first embodiment. For example, the comparative example's cache memories CM0, CM1 and column decoder COLD are composed of transistors with a larger channel width compared to the first embodiment.

[0121] Furthermore, the column decoder COLD and the multiplexer MPX are connected via a bus width that is several times larger than that in the first embodiment, such as 256 bits.

[0122] [Effects of the Memory Die (MD) in the First Embodiment]

[0123] In the memory die MD of the first embodiment, the input / output of user data Dat between the cache memories CM0 and CM1 and the column decoder COLD is performed at half the speed compared to the comparative example. Therefore, the cache memories CM0 and CM1 and the column decoder COLD of the first embodiment can be implemented using transistors with smaller channel widths compared to the comparative example. As a result, the circuit area can be reduced.

[0124] Furthermore, in the memory die MD of the first embodiment, the column decoder COLD and the multiplexer MPX are connected via a bus with half the bus width compared to the comparative example. Therefore, the circuit area can be reduced.

[0125] [Signal input method from controller die CD to memory die MD]

[0126] Next, the signal input method from the controller die CD to the memory die MD in this embodiment will be described.

[0127] [Function of each terminal]

[0128] Figure 13 This is a schematic diagram illustrating the function of the signal input / output terminals and control terminals in a memory die (MD). Additionally, in the following description, data signal input / output terminals DQ0 to DQ7 may sometimes be referred to as data signal input / output terminals DQ<7:0>.

[0129] The memory die MD in this embodiment is, for example, as follows: Figure 13As shown, the data signal input / output terminals DQ<7:0> are used for the input and output of user data Dat, but not for the input of instruction data Cmd and address data Add, or the output of status data Stt. Furthermore, in the memory die MD of this embodiment, the control terminals CA1 (CLE) and CA0 (ALE) are used for the input of instruction data Cmd and address data Add, and the output of status data Stt, etc.

[0130] Additionally, in the following description, a portion of the signals input / output via control terminals CA1 (CLE) and CA0 (ALE) is sometimes referred to as a header. Furthermore, the combination of headers constituting such signals is sometimes referred to as a header set. A header set contains a 4-bit signal that is time-division multiplexed and divided into two cycles.

[0131] Furthermore, there are cases where a portion of the instruction data Cmd, address data Add, status data Stt, feature data Fd, etc., input / output following the header is referred to as the subject. Additionally, there are cases where a combination of subjects constituting such data or a portion thereof is referred to as a subject set. A subject set contains 8 bits of data divided into 4 cycles and time-division multiplexing inputs.

[0132] In addition, there are cases where a combination of a header set and a body set is called a frame.

[0133] The data from control terminals CA1 (CLE) and CA0 (ALE) is extracted into a register (not shown) of the logic circuit CTR based on the rising and falling edges of the voltage at control terminal CA_clk ( / WE). In other words, the data from control terminals CA1 (CLE) and CA0 (ALE) is extracted into the register (not shown) of the logic circuit CTR according to the toggle of the signal input to control terminal CA0 (ALE). In this specification, one rise or fall of the voltage at control terminal CA0 (ALE) is defined as one cycle for inputting or outputting 2 bits of data via control terminals CA1 (CLE) and CA0 (ALE). For example, if the voltage at control terminal CA_clk ( / WE) rises once and then falls further, 4 bits of data are input or output via control terminals CA1 (CLE) and CA0 (ALE). This is defined as two cycles.

[0134] [Example of header set input]

[0135] Figure 14 This is a schematic waveform diagram used to illustrate the operation of the memory die MD in the first embodiment. Figure 15 It is a schematic table used to illustrate the operation of the memory die (MD).

[0136] exist Figure 14In the example, with the "L" state signal input to the control terminal / CE, the control terminal CA_clk( / WE) is input with both "L" state signals and "H" state signals at a roughly constant rhythm. That is, with the input signal to the control terminal / CE in the "L" state, the input signal to the control terminal CA_clk( / WE) repeatedly switches between "L" rising to "H" and falling back to "L" (two switching cycles).

[0137] exist Figure 14 In the example, at timings t100 and t101, a 4-bit header set is input corresponding to the rising and falling edges of the signal input to the control terminal CA_clk( / WE). More specifically, at timings t100 and t101, the controller die CD will... Figure 15 The 4-bit header set shown is input to the memory die MD in two cycles, with 2 bits input per cycle. For example, in the case of the input instruction data Cmd (CMD), the voltages of control terminals CA1 (CLE) and CA0 (ALE) are set in the header of the first cycle based on bits "1" and "0". At the rising edge (when the control terminal CA_clk ( / WE) rises from "L" to "H"), the header of the first cycle is fetched into a register (not shown) of the logic circuit CTR. In the header of the second cycle, the voltages of control terminals CA1 (CLE) and CA0 (ALE) are set based on bits "0" and "0". At the falling edge (when the control terminal CA_clk ( / WE) falls from "H" to "L"), the header of the second cycle is fetched into a register (not shown) of the logic circuit CTR.

[0138] In addition, Figure 14In the example, during timings t102 to t105, an 8-bit body set is input corresponding to the rising and falling edges of the signal input to the control terminal CA_clk ( / WE). More specifically, during timings t102 to t105, the controller die CD inputs the 8-bit body set corresponding to the 4-bit header set (entry condition) into the memory die MD in four cycles, with 2 bits input per cycle. For example, the 8-bit instruction data Cmd is set to bits "0" to "7". First, in the body (data) of the first cycle, the voltages of the control terminals CA1 (CLE) and CA0 (ALE) are set according to bits "1" and "0". The body of the first cycle is extracted at the rising edge when the control terminal CA_clk ( / WE) rises from "L" to "H". In the body (data) of the second cycle, the voltages of the control terminals CA1 (CLE) and CA0 (ALE) are set according to bits "3" and "2". The main body of the second cycle is extracted at the falling edge when the control terminal CA_clk( / WE) drops from "H" to "L". Similarly, in the main bodies of the third and fourth cycles, the voltages of control terminals CA1(CLE) and CA0(ALE) are set according to bits "5", "4" and bits "7", "6", respectively. The main bodies of the third and fourth cycles are extracted at the rising edge and falling edge when the control terminal CA_clk( / WE) rises.

[0139] In addition, such as Figure 15 As shown, when indicating that data is output via control terminals CA1 (CLE) and CA0 (ALE) (DOUT), bits "0" and "0" are entered in the header of the first cycle, and bits "0" and "0" are entered in the header of the second cycle. This header set is used, for example, when outputting status data Stt or feature data Fd.

[0140] Furthermore, when data is input via control terminals CA1 (CLE) and CA0 (ALE) (DIN), bits "0" and "0" are entered in the header of the first cycle, and bits "0" and "1" are entered in the header of the second cycle. This header set is used, for example, when inputting feature data Fd.

[0141] In addition, when the instruction is to input address data Add (ADD), enter bits “0” and “1” in the header of the first cycle, and enter bits “0” and “0” in the header of the second cycle.

[0142] Furthermore, in this embodiment, when user data Dat is input or output via data signal input / output terminals DQ0 to DQ7, the controller die CD inputs an SCE (Select Chip Enable) command to the memory die MD. When the SCE command is input, bits "1" and "1" are entered in the header of the first cycle, and bits "1" and "0" are entered in the header of the second cycle.

[0143] The subject set (“SCE target”) corresponding to the SCE instruction includes, for example, a 4-bit chip address to specify the memory die MD, a 1-bit data to specify the input or output, and a 1-bit data to specify the data signal input / output terminals DQ0 to DQ3 or the data signal input / output terminals DQ4 to DQ7 (or to specify the plane PLN0 or plane PLN1).

[0144] Furthermore, in this embodiment, when the input or output of user data Dat via data signal input / output terminals DQ0 to DQ7 is completed, the controller die CD inputs an SCT (Select Chip Terminate) command to the memory die MD. When the SCT command is input, bits "1" and "1" are entered in the header of the first cycle, and bits "1" and "1" are entered in the header of the second cycle.

[0145] The subject set corresponding to the SCT instruction (“SCT target”) includes, for example, a 4-bit chip address to specify the memory die MD, a 1-bit data to specify the input or output, and a 1-bit data to specify the data signal input / output terminals DQ0 to DQ3 or the data signal input / output terminals DQ4 to DQ7 (or to specify the plane PLN0 or plane PLN1).

[0146] in addition, Figure 15 The header rising edge shown indicates the first 2-bit header input corresponding to the rising edge of the signal input to the header, i.e., the control terminal CA_clk( / WE), in the first cycle. Similarly, the header falling edge indicates the second 2-bit header input corresponding to the falling edge of the signal input to the header, i.e., the control terminal CA_clk( / WE), in the second cycle.

[0147] [action]

[0148] Next, the operation of the memory die MD will be explained.

[0149] The memory die (MD) is configured to perform a read operation. The read operation involves reading user data (Dat) from the memory cell array (MCA) via the sense amplifier module (SAM) and transmitting the read user data (Dat) to the latch circuit (XDL). During the read operation, the user data (Dat) read from the memory cell array (MCA) is transmitted to the latch circuit (XDL) via the bit line (BL) and the sense amplifier module (SAM).

[0150] Furthermore, the memory die MD is configured to perform data output operations. The data output operation is the action of outputting the user data Dat contained in the latch circuit XDL to the controller die CD. In the data output operation, a prefetch operation is performed first. During the prefetch operation, the user data Dat in the latch circuit XDL is referenced... Figure 11 The column decoder COLD, multiplexer MPX, and bus wiring DB transmit data to the input / output control circuit I / O. Next, the user data Dat from the input / output control circuit I / O is output to the controller die CD via data signal input / output terminals DQ0 to DQ7.

[0151] Furthermore, the memory die MD is configured to perform status reads. A status read is the operation of outputting the status data Stt contained in the status register STR to the controller die CD. During a status read, the status data Stt contained in the status register STR is output to the controller die CD via the logic circuit CTR.

[0152] Furthermore, the memory die MD is configured to perform a write operation. The write operation is the process of inputting user data Dat from the controller die CD to the memory die MD via data signal input / output terminals DQ0 to DQ7, and writing the user data Dat into the memory cell array MCA.

[0153] [Read the action]

[0154] Figure 16 and Figure 17 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD. Figure 16 The diagram shows the timing of the read operation corresponding to the memory die MD0. Figure 17 The diagram shows the timing of the read operation corresponding to the memory die MD1.

[0155] exist Figure 16 Before timing t110, although the diagram is omitted, the voltage at the control terminal / CE drops from "H" to "L".

[0156] Next, the controller die CD inputs the read operation instruction set to the memory die MD at timings t110 to t135. That is, the controller die CD inputs the instruction data Cmd used to indicate the read operation to the memory die MD at timings t110 to t115, the address data Add of the page to be read at timings t120 to t127, and the instruction data Cmd used to start the read operation at timings t130 to t135.

[0157] More specifically, during timing t110 to t111, the controller die CD inputs a header set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). This header set consists of a header representing the first cycle of bits "1" and "0" and a header representing the second cycle of bits "0" and "0". For example... Figure 15 As shown, the header set is a header set indicating the input instruction data Cmd, which is input sequentially at the rising and falling edges of the signal input to the control terminal CA_clk( / WE). In other words, during timing t110 to t111, the portion of the header set (4 bits of information) in the frame corresponding to the instruction data Cmd that constitutes the read operation is input to the memory die MD according to the two toggle cycles of the signal input to the control terminal CA_clk( / WE).

[0158] Furthermore, during timings t112 to t115, the controller die CD inputs 8 bits of data representing 00h (00000000) into the memory die MD via control terminals CA1 (CLE) and CA0 (ALE), setting it to a subject set consisting of 4 subjects. 00h is the instruction data Cmd used to indicate the read operation. In other words, during timings t112 to t115, the portion (8 bits of information) corresponding to the subject set in the frame corresponding to the instruction data Cmd constituting the read operation instruction set is input into the memory die MD based on 4 toggle cycles of the signal input to the control terminal CA_clk ( / WE).

[0159] Furthermore, during timings t120 to t121, the controller die CD inputs a header set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). This header set consists of a header representing the first cycle of bits "0" and "1" and a header representing the second cycle of bits "0" and "0". For example... Figure 15As shown, the header set is a header set indicating the input address data Add, which is input sequentially at the rising and falling edges of the signal input to the control terminal CA_clk( / WE). In other words, during timing t120 to t121, the portion of the header set (4 bits of information) in one of the four frames corresponding to the instruction data Cmd that constitutes the instruction set for the read operation is input to the memory die MD according to the two toggle cycles of the signal input to the control terminal CA_clk( / WE).

[0160] Furthermore, during timings t122 ​​to t125, the controller die CD inputs the 8-bit data in the address data Add to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE), setting it to a subject set consisting of four subjects. In other words, during timings t122 ​​to t125, the portion (8 bits of information) corresponding to the subject set in the frame corresponding to the address data Add constituting the instruction set for the read operation is input to the memory die MD based on four toggle cycles of the signal input to the control terminal CA_clk ( / WE).

[0161] Furthermore, during timings t126 to t127, the same actions as those during timings t120 to t125 are executed multiple times. This results in all frames corresponding to the address data Add of the instruction set constituting the read operation being input into the memory die MD.

[0162] In addition, during timing t130 to t131, the controller die CD inputs a header set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE), consisting of a header for the first cycle representing bits "1" and "0" and a header for the second cycle representing bits "0" and "0".

[0163] Furthermore, during timings t132 to t135, the controller die CD inputs 8 bits representing 30h (00110000) into the memory die MD via control terminals CA1 (CLE) and CA0 (ALE), setting it to a set of 4 main data points. 30h is the instruction data Cmd used to indicate the start of the read operation.

[0164] Through the actions of timings t110 to t135, a set of instructions for instructing read operations is input from the controller die CD to the memory die MD. Simultaneously, the read operation begins in the memory die MD. In the illustrated example, the address data Add corresponds to plane PLN0. In this case, as... Figure 16 As shown, the ready / busy signal RY / / BY (PLN0) corresponding to plane PLN0 drops from "H" to "L".

[0165] Furthermore, it can execute readout operations for plane PLN0 and plane PLN1 in parallel. For example, when executing reference... Figure 16 After the action described, such as Figure 17 As illustrated, during timings t136-t137, when a set of instructions for instructing a read operation for plane PLN1 is input from the controller die CD to the memory die MD, a read operation corresponding to plane PLN1 begins in the memory die MD. Furthermore, along with this, the ready / busy signal RY / / BY(PLN1) corresponding to plane PLN1 decreases from "H" to "L".

[0166] In the illustrated example, at timing t138, the readout action corresponding to plane PLN0 ends, and the ready / busy signal RY / / BY(PLN0) corresponding to plane PLN0 rises from "L" to "H".

[0167] [Status Reading]

[0168] Figure 18 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD. Figure 18 The diagram below shows the timing of the status read.

[0169] Here, as for reference Figure 9 As explained, the memory die MD has a terminal RY / / BY that outputs a ready / busy signal. Therefore, the controller die CD can confirm whether the read operation has ended via the ready / busy signal output from the terminal RY / / BY. However, only one terminal RY / / BY is provided for each memory die MD. Basically, a NOR signal corresponding to the ready / busy signal RY / / BY(PLN0) for plane PLN0 and the ready / busy signal RY / / BY(PLN1) for plane PLN1 is output from the terminal RY / / BY. Therefore, even if the output signal of the terminal RY / / BY is checked, it is essentially impossible to individually confirm whether the read operation corresponding to plane PLN0 has ended and whether the read operation corresponding to plane PLN1 has ended. Therefore, in the illustrated example, when inputting the reference... Figure 16 and Figure 17 After describing the instruction set for the read action, a status read is performed to confirm whether the read action corresponding to plane PLN0 has ended.

[0170] In the illustrated example, the controller die CD inputs instruction data Cmd to the memory die MD at timing t140 to indicate the status read.

[0171] The input of the instruction data Cmd is performed in roughly the same way as the input of the instruction data Cmd used to indicate the read action. However, as the main input, 70h (01110000) is used instead of 00h.

[0172] Furthermore, in the illustrated example, at timing t141, the voltages of control terminals CA1 (CLE) and CA0 (ALE) are switched to an intermediate value between the voltage corresponding to "0" and the voltage corresponding to "1".

[0173] Furthermore, in the illustrated example, at timing t142, the voltages of control terminals CA1 (CLE) and CA0 (ALE) are switched to the voltages corresponding to "0".

[0174] Furthermore, in the illustrated example, at timing t143, the controller die CD begins switching the control terminal CA_clk( / WE).

[0175] Furthermore, in the illustrated example, at timing t144, the status data Stt is output via control terminal CA1 (CLE). In the illustrated example, the status data Stt is output bit by bit via control terminal CA1 (CLE) according to the rising edge of control terminal / RE. Additionally, the signal of control terminal CA0 (ALE) is switched during the switching timing of the status data Stt.

[0176] In addition, during timings t145, t146 to t147, t148, the controller die CD acquires the status data Stt bit by bit from the memory die MD via the control terminal CA1 (CLE).

[0177] [Data Output Action]

[0178] Figures 19-26 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD. Figures 19-22 and Figure 25 The diagram shows the timing of the data output operation corresponding to memory die MD0. Figure 23 , Figure 24 and Figure 26 The diagram shows the timing of the data output actions corresponding to the memory die MD1.

[0179] exist Figure 19 In the example, the controller die CD starts inputting the instruction set for the data output action to the memory die MD at timing t149. That is, the controller die CD first inputs the instruction data Cmd, which indicates the data output action, to the memory die MD; secondly, it inputs the address data Add, which will be the page to which the data output action is to be input to the memory die MD; and finally, it inputs the instruction data Cmd, which is used to start the data output action, to the memory die MD.

[0180] The input of instruction data Cmd, which indicates the data output action, is performed in roughly the same way as the input of instruction data Cmd, which indicates the read action. However, the main input is 05h (00000101) instead of 00h.

[0181] The input of the instruction data Cmd used to start the data output action is performed in roughly the same way as the input of the instruction data Cmd used to start the read action. However, as the main input, E0h (11100000) is used instead of 30h.

[0182] Therefore, the prefetching operation begins, and the user data Dat in the latch circuit XDL0 is transmitted to the input / output control circuit I / O.

[0183] Next, the controller bare CD is in Figure 20 The timing t150 starts inputting the SCE instruction to the memory die MD.

[0184] After the signal of the control terminal / RE is switched multiple times from the input SCE command, the user data Dat corresponding to the plane PLN0 is output via the data signal input / output terminals DQ0 to DQ3. In the illustrated example, at the fourth falling edge of the SCE command corresponding to the input control terminal / RE (e.g., at the end of the SCE target period in timing t151'), the voltage of the data strobe signal input / output terminal DQS drops. Furthermore, at timing t152 corresponding to the next rising edge of the control terminal / RE, the user data Dat read from the plane PLN0 is output in 4-bit increments via the data signal input / output terminals DQ0 to DQ3. Additionally, the signal of the data strobe signal input / output terminal DQS is switched during the timing corresponding to the switching of user data Dat in the plane PLN0.

[0185] Additionally, in timing t152, for example... Figure 21 As shown, user data Dat(true data: real data) can be output immediately, for example, Figure 22 As shown, pseudo-data can also be output before the user data Dat. For example, data for a specified number of cycles (e.g., 4 cycles) can also be pseudo-data instead of the user data Dat. This allows the user data Dat to be successfully sent to the controller die CD. Furthermore, it enables the output circuit 202 ( Figure 10 The output is stabilized. Additionally, the number of bits in the pseudo-data may differ when performing a readout operation corresponding to plane PLN0 versus when performing a readout operation corresponding to plane PLN1.

[0186] In addition, Figure 20In the example, at timing t151, the read operation corresponding to plane PLN1 ends, and the ready / busy signal RY / / BY(PLN1) corresponding to plane PLN1 rises from "L" to "H". Furthermore, at timing t153, the controller die CD begins inputting instruction data Cmd, indicating the status read, to the memory die MD. Although the illustration is omitted, after receiving the instruction data Cmd indicating the status read, as... Figure 18 As shown in the timing diagram t143~t148, the controller die CD obtains the status data Stt bit by bit from the memory die MD via the control terminal CA1 (CLE). Thus, the controller die CD can confirm that the read operation corresponding to plane PLN1 has ended.

[0187] Here, data output actions for plane PLN0 and data output actions for plane PLN1 can be executed in parallel.

[0188] For example, such as Figure 23 As shown, at timing t154, when the controller die CD starts inputting the instruction set used to indicate the data output operation for plane PLN1 to the memory die MD, the prefetch operation begins, and the user data Dat in the latch circuit XDL1 is transferred to the input / output control circuit I / O.

[0189] Next, in Figure 24 At timing t155, the SCE instruction is started to be input to the memory die MD. In the illustrated example, at timing t156, corresponding to the rising edge of the specified timing of the control terminal / RE (e.g., the next falling edge after the fourth falling edge starting from the final cycle of the SCE target received in timing t155'), the user data Dat read from plane PLN1 is output in 4-bit increments via data signal input / output terminals DQ4 to DQ7. Furthermore, when switching the timing corresponding to the user data Dat of plane PLN1, the signal of the data strobe signal input / output terminal DQS is switched.

[0190] After acquiring the user data Dat corresponding to plane PLN0, the controller bare die CD is in Figure 25 The timing t157 begins inputting the SCT instruction to the memory die MD.

[0191] After the signal of the control terminal / RE is switched multiple times from the input SCT command, the output of user data Dat via data signal input / output terminals DQ0 to DQ3 ends. In the illustrated example, at the fourth falling edge of the SCT command corresponding to the input control terminal / RE (e.g., at the end of the cycle of accepting the SCT target at timing t157'), the output of user data Dat corresponding to plane PLN0 via data signal input / output terminals DQ0 to DQ3 ends. However, in the illustrated example, the output of user data Dat corresponding to plane PLN1 via data signal input / output terminals DQ4 to DQ7 does not end. Therefore, even after timing t158, the signal of the data strobe signal input / output terminal DQS continues to switch.

[0192] Similarly, upon completion of acquiring the user data Dat corresponding to plane PLN1, the controller bare die CD... Figure 26 At timing t159, an SCT instruction is input to the memory die MD. Therefore, in the illustrated example, at timing t160, at the fourth falling edge of the SCT instruction corresponding to the input control terminal / RE (e.g., at the end of the cycle when timing t159' receives the SCT target), the output of user data Dat corresponding to plane PLN1 via data signal input / output terminals DQ4 to DQ7 ends. Furthermore, in the illustrated example, at this timing, the output of user data Dat from the memory die MD completely ends. Therefore, the signal output from the data strobe signal input / output terminal DQS also ends. In the illustrated example, the voltage of the data strobe signal input / output terminal DQS is fixed at an intermediate value between the voltage corresponding to "0" and the voltage corresponding to "1".

[0193] In addition, in this embodiment, from Figure 16 Timing t110 to Figure 26 At timing t160, the controller die CD continuously switches the input signal to the control terminal / RE at a roughly constant frequency.

[0194] [Write action]

[0195] Figures 27-30 It is a schematic waveform diagram representing the input and output signals between the controller die CD and the memory die MD. Figures 27-30 The diagram shows the timing of the write operation corresponding to memory die MD1.

[0196] The input of the instruction set for the write operation to plane PLN0 can be executed in parallel with the read operation, data output operation, or write operation to plane PLN1. Similarly, the write operation to plane PLN1 can be executed in parallel with the read operation, data output operation, or write operation to plane PLN0. Here, the instruction set for the write operation includes user data Dat. That is, in this embodiment, the input for writing user data Dat to plane PLN0 can be executed in parallel with the output of user data Dat read from plane PLN1 and the input of user data Dat written to plane PLN1. Similarly, the input for writing user data Dat to plane PLN1 can be executed in parallel with the output of user data Dat read from plane PLN0 and the input of user data Dat written to plane PLN0.

[0197] exist Figures 27-30 The following example is provided for reference: Figures 16-18 As explained, after performing the readout action corresponding to plane PLN0, as Figure 20 The process begins by executing a data output action corresponding to plane PLN0, and during the execution of the data output action, a write action corresponding to plane PLN1 is executed.

[0198] exist Figure 27 In the example, the controller die CD starts inputting the instruction set for write operations to the memory die MD at timing t201. That is, the controller die CD first inputs the instruction data Cmd indicating the write operation to the memory die MD, then inputs the address data Add of the page to be written to the memory die MD, and finally inputs the instruction data Cmd indicating the end of the address data Add input to the memory die MD. Next, as... Figure 28 and Figure 29 As shown, the controller die CD inputs user data Dat, used to write to the memory die MD, into the memory cell array MCA. Next, as... Figure 30 As illustrated, the controller die CD inputs instruction data Cmd to the memory die MD to initiate the write operation.

[0199] exist Figure 27 In the example, the controller die CD inputs instruction data Cmd to the memory die MD at timing t201 to indicate a write operation.

[0200] The input of instruction data Cmd, which indicates a write operation, is performed in roughly the same way as the input of instruction data Cmd, which indicates a read operation. However, the main input is 85h (10000101) instead of 00h.

[0201] The input of instruction data Cmd, which indicates the end of address data Add, is performed in roughly the same way as the input of instruction data Cmd used to indicate the read action. However, as the main input, 12h (00010010) is used instead of 00h.

[0202] Next, the controller bare CD is in Figure 28 The timing t202 begins to input the SCE instruction to the memory die MD.

[0203] After switching the control terminal / RE signal a specified number of times following the input of the SCE command, user data Dat corresponding to plane PLN1 is input via data signal input / output terminals DQ4 to DQ7. In the illustrated example, during timing t203 between the fourth falling edge and the subsequent rising edge of the SCE command from the input of the control terminal / RE signal, the user data Dat written to plane PLN1 is input in 4-bit increments via data signal input / output terminals DQ4 to DQ7.

[0204] Additionally, in timing t203, pseudo-data can also be input before the user data Dat. For example, data for a specified number of cycles (e.g., 4 cycles) can be pseudo-data instead of user data Dat. This allows user data Dat to be smoothly input into the memory die MD. Furthermore, it enables input circuit 201 ( Figure 10 The output is stabilized. Additionally, the number of bits in the pseudo-data may differ when performing a write operation corresponding to plane PLN0 versus when performing a write operation corresponding to plane PLN1.

[0205] Next, the controller bare CD is in Figure 29 The timing t204 begins inputting the SCT instruction to the memory die MD.

[0206] After the signal of the control terminal / RE is switched multiple times following the input of the SCT command, the output of user data Dat via data signal input / output terminals DQ0 to DQ3 ends. In the illustrated example, at timing t205 corresponding to the fourth falling edge of the SCT command that corresponds to the input of the control terminal / RE signal, the output of user data Dat corresponding to plane PLN0 via data signal input / output terminals DQ0 to DQ3 ends. Furthermore, in the illustrated example, in this timing, the output of user data Dat from the memory die MD completely ends. Therefore, the signal output from the data strobe signal input / output terminal DQS also ends.

[0207] Next, the controller bare CD is in Figure 30 The timing t206 begins inputting the SCT instruction to the memory die MD.

[0208] After the signal of switching the control terminal / RE a specified number of times following the input of the SCT command, the input of user data Dat via the data signal input / output terminals DQ4 to DQ7 ends. In the illustrated example, at timing t207 corresponding to the fourth falling edge of the SCT command that corresponds to the input of the control terminal / RE signal, the output of user data Dat corresponding to plane PLN1 via the data signal input / output terminals DQ4 to DQ7 ends.

[0209] Next, at timing t207, the controller die CD begins to input instruction data Cmd to the memory die MD to initiate the write operation.

[0210] The input of the instruction data Cmd used to initiate the write operation is performed in roughly the same way as the input of the instruction data Cmd used to indicate the read operation. However, the main input is 10h (00010000) instead of 00h.

[0211] In addition, in this embodiment, from Figure 16 Timing t110 to Figure 30 With timing t207, the controller die CD continuously switches the input signal to the control terminal / RE at a roughly constant frequency.

[0212] [Other Implementation Methods]

[0213] The memory system and memory die MD of the first embodiment have been described above. However, the first embodiment is merely an example, and the specific configuration can be adjusted accordingly.

[0214] For example, as referenced Figure 5 As explained, the memory die MD of the first embodiment has two memory cell arrays (MCAs). However, the memory die MD may also have three or more memory cell arrays (MCAs). For example, when the memory die MD has four memory cell arrays (MCAs), data signal input / output terminals DQ0 and DQ1 can be assigned to the first memory cell array (MCA), data signal input / output terminals DQ2 and DQ3 can be assigned to the second memory cell array (MCA), data signal input / output terminals DQ4 and DQ5 can be assigned to the third memory cell array (MCA), and data signal input / output terminals DQ6 and DQ7 can be assigned to the fourth memory cell array (MCA).

[0215] Furthermore, in the memory die MD of the first embodiment, data signal input / output terminals DQ0 to DQ7 are each assigned to only one memory cell array MCA. That is, in the memory die MD of the first embodiment, data signal input / output terminals DQ0 to DQ3 are assigned only to the first memory cell array MCA1, and data signal input / output terminals DQ4 to DQ7 are assigned only to the second memory cell array MCA. However, data signal input / output terminals DQ0 to DQ7 can be assigned to two or more memory cell array MCAs. For example, when the memory die MD has four memory cell array MCAs, data signal input / output terminals DQ0 to DQ3 can be assigned to the first and second memory cell array MCAs, and data signal input / output terminals DQ4 to DQ7 can be assigned to the third and fourth memory cell array MCAs.

[0216] Furthermore, in the memory die MD of the first embodiment, the input of user data Dat written to plane PLN0 can be performed in parallel with the output of user data Dat read from plane PLN1 and the input of user data Dat written to plane PLN1. Similarly, the input of user data Dat written to plane PLN1 can be performed in parallel with the output of user data Dat read from plane PLN0 and the input of user data Dat written to plane PLN0. However, this configuration is merely an example, and the specific configuration can be adjusted appropriately.

[0217] For example, the function that can execute the input of user data Dat written to plane PLN0 in parallel with the output of user data Dat read from plane PLN1 is not a necessary function. Similarly, the function that can execute the input of user data Dat written to plane PLN0 in parallel with the output of user data Dat read from plane PLN0 is also not a necessary function. These functions can be omitted as needed.

[0218] [other]

[0219] While some embodiments of the invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention as described in the claims and their equivalents.

[0220] [Explanation of Symbols]

[0221] CD controller bare die

[0222] / CE,CA1(CLE),CA0(ALE),CA_clk( / WE), / RE,RE, / WP control terminals

[0223] MC (Memory Cell Transistor)

[0224] MCA storage cell array

[0225] MD memory die

[0226] PC peripheral circuits

[0227] ADR Address Register

[0228] CMR instruction register.

Claims

1. A memory system comprising: Multiple semiconductor memory devices; and Control device; and Each of the plurality of semiconductor memory devices comprises: The first memory cell array contains multiple first memory cell transistors connected in series; The second memory cell array contains multiple second memory cell transistors connected in series; The first data signal input / output terminal can be used for outputting data read from the first memory cell array and inputting data written to the first memory cell array; The second data signal input / output terminal can be used for outputting data read from the second memory cell array and inputting data written to the second memory cell array; and The first control terminal, when outputting data read from at least one of the first storage cell array and the second storage cell array, can accept switching signals from the control device; and The control device Regardless of whether data is being input or output via the first data signal input / output terminal and the second data signal input / output terminal, the signal of the first control terminal is switched at a substantially constant frequency.

2. The memory system according to claim 1, wherein The first data signal input / output terminal It has a signal path for data between itself and the first storage cell array. It lacks a signal path for data between itself and the second storage unit array, and The second data signal input / output terminal It has a signal path for data between itself and the second storage cell array. There is no signal path for data between it and the first storage cell array.

3. The memory system according to claim 1, wherein Data read from the first storage cell array is output from the first data signal input / output terminal, but not from the second data signal input / output terminal; Data read from the second storage cell array is output from the second data signal input / output terminal, and not from the first data signal input / output terminal.

4. The memory system according to claim 1, wherein The control device The signal of the first control terminal is switched at a substantially constant frequency from the timing of the input of the instruction set instructing the semiconductor memory device to perform a read operation to the timing of the input of the instruction set instructing the semiconductor memory device to perform a data output operation.

5. The memory system according to claim 1, wherein When the control device starts the data output operation, it inputs a set of instructions and a first instruction to the semiconductor memory device to indicate the data output operation. After the semiconductor memory device switches the first control terminal multiple times starting from the input of the first instruction, it begins to output data.

6. The memory system according to claim 1, wherein When the control device starts the data output operation, it inputs a set of instructions and a first instruction to the semiconductor memory device to indicate the data output operation. After the semiconductor memory device switches the first control terminal multiple times starting from the input of the first instruction, it outputs pseudo data and then begins to output data.

7. The memory system according to claim 5, wherein When the data output action ends, the control device inputs a second instruction to the semiconductor memory device; After the semiconductor storage device switches the first control terminal multiple times starting from the input of the second instruction, it ends the data output.

8. The memory system according to claim 6, wherein When the data output action ends, the control device inputs a second instruction to the semiconductor memory device; After the semiconductor storage device switches the first control terminal multiple times starting from the input of the second instruction, it ends the data output.

9. The memory system according to claim 1, wherein Each of the plurality of semiconductor memory devices also has a data strobe signal input / output terminal, and During data output, the data output via at least one of the first data signal input / output terminal and the second data signal input / output terminal is switched at the falling edge and rising edge of the voltage of the data strobe signal input / output terminal.

10. The memory system of claim 1, wherein Each of the plurality of semiconductor memory devices also has a data strobe signal input / output terminal, and The data output operation corresponding to the first memory cell array begins in the first timing sequence; The data output operation corresponding to the second storage cell array begins in the second timing sequence, which is later than the first timing sequence; The data output action corresponding to the first storage cell array ends in the third timing sequence, which is later than the second timing sequence; In the case where the data output operation corresponding to the second memory cell array ends in the fourth timing sequence, which is later than the third timing sequence, The signals at the data strobe signal input / output terminals continuously switch from the first timing sequence to the fourth timing sequence.

11. The memory system of claim 1, wherein The input of data to be written to the first storage cell array can be executed in parallel with the output of data read from the second storage cell array and the input of data written to the second storage cell array.

12. A semiconductor memory device comprising: The first memory cell array contains multiple first memory cell transistors connected in series; The second memory cell array contains multiple second memory cell transistors connected in series; The first data signal input / output terminal can be used for outputting data read from the first memory cell array and inputting data written to the first memory cell array; and The second data signal input / output terminal can be used for outputting data read from the second memory cell array and inputting data written to the second memory cell array; and The first data signal input / output terminal It has a signal path for data between itself and the first storage cell array. It lacks a signal path for data between itself and the second storage unit array, and The second data signal input / output terminal, It has a signal path for data between itself and the second storage cell array. There is no signal path for data between it and the first storage cell array.

13. The semiconductor memory device according to claim 12, wherein Data read from the first storage cell array is output from the first data signal input / output terminal, but not from the second data signal input / output terminal; Data read from the second storage cell array is output from the second data signal input / output terminal, and not from the first data signal input / output terminal.

14. The semiconductor memory device according to claim 12, further comprising: The first control terminal, and After the semiconductor memory device switches the first control terminal multiple times starting from the input of the first instruction, it begins to output data.

15. The semiconductor memory device according to claim 12, further comprising: The first control terminal, and After the semiconductor memory device switches the first control terminal multiple times starting from the input of the first instruction, it outputs pseudo data and then begins to output data.

16. The semiconductor memory device of claim 14, wherein After the semiconductor storage device switches the first control terminal multiple times starting from the input of the second instruction, it ends the data output.

17. The semiconductor memory device according to claim 15, wherein After the semiconductor storage device switches the first control terminal multiple times starting from the input of the second instruction, it ends the data output.

18. The semiconductor memory device according to claim 12, further comprising: Data strobe signal input / output terminals, and During data output, the data output via at least one of the first data signal input / output terminal and the second data signal input / output terminal is switched at the falling edge and rising edge of the voltage of the data strobe signal input / output terminal.

19. The semiconductor memory device according to claim 12, further comprising: Data strobe signal input / output terminals, and The data output operation corresponding to the first memory cell array begins in the first timing sequence; The data output operation corresponding to the second storage cell array begins in the second timing sequence, which is later than the first timing sequence; The data output action corresponding to the first storage cell array ends in the third timing sequence, which is later than the second timing sequence; In the case where the data output operation corresponding to the second memory cell array ends in the fourth timing sequence, which is later than the third timing sequence, The signals at the data strobe signal input / output terminals continuously switch from the first timing sequence to the fourth timing sequence.

20. The semiconductor memory device of claim 12, wherein... The input of data to be written to the first storage cell array can be executed in parallel with the output of data read from the second storage cell array and the input of data written to the second storage cell array.

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