A synchronous rectification signal timing adaptive correction device and method

Abstract

The application provides a synchronous rectification signal timing adaptive correction device and method, which is connected in series between a synchronous rectification control strategy output end and a synchronous rectification power device, and comprises a software control unit and a hardware correction circuit; the software control unit is used for detecting the edge timing deviation of an actual driving signal output by the synchronous rectification control strategy relative to an ideal synchronous rectification reference signal, determining the type and deviation amount of the edge timing deviation, and generating a correction control signal; the input end of the hardware correction circuit receives the actual driving signal, the control end receives the correction control signal, and the output end outputs the corrected driving signal to the synchronous rectification power device; the hardware correction circuit responds to the correction control signal, enables a timing correction module corresponding to the type of the edge timing deviation, adjusts the resistance value of the charging resistor in the corresponding timing correction module, matches the time length for charging the voltage of the charging capacitor from the initial state to the input threshold value with the deviation amount, and completes the timing correction of the actual driving signal.

Description

Technical Field

[0001] This invention belongs to the field of power electronic power conversion technology, specifically relating to a synchronous rectification signal timing adaptive correction device and method, applicable to the synchronous rectification control of various power conversion topologies such as LLC and its derivative topologies, flyback, phase-shifted full bridge, BOOST, BUCK, etc. Background Technology

[0002] Synchronous rectification technology is a key means to improve the energy conversion efficiency of power electronic converters and has been widely used in various power conversion topologies such as LLC and its derivative topologies, flyback converters, and phase-shifted full-bridge converters. In existing technologies, such as the solutions proposed in patents CN202510048843, CN202310396064, CN202510058648, and CN202410886570, their core control architectures share a common feature: the synchronous rectification drive signal SR is directly generated by the control strategy. ref This signal is used for synchronous rectifier power devices (as per the instruction manual). Figure 1 As shown in the figure, synchronous rectification control is achieved.

[0003] In engineering practice, power devices inherently exhibit parameter dispersion, and their switching characteristics drift over long periods due to factors such as operating time and temperature. Both of these factors can cause synchronous rectification drive timing to deviate from the theoretical design, reducing system efficiency and reliability. Currently, the mainstream solution in the industry to address timing deviations is to adjust drive timing parameters by modifying the control strategy in software. However, this approach has significant technical limitations and cannot meet the high-precision and high-reliability application requirements of the power electronics field.

[0004] (i) Poor compatibility and stability: Modifying mature control strategies requires full-condition verification, which is costly and can easily damage the original system logic, making it difficult to achieve universal adaptation across topologies and platforms.

[0005] (ii) Insufficient adjustment precision: Due to the limitations of processor speed and execution cycle, the software adjustment step size is difficult to break through the level of hundreds of nanoseconds, which cannot match the high-precision timing requirements of MHz-level high-frequency applications;

[0006] (iii) Lack of full life cycle adaptability: The fixed parameters calibrated at the factory cannot compensate for the long-term drift of the device in real time, resulting in the accumulation of timing deviations over time. Furthermore, the method of software calibration for each device significantly increases the difficulty of mass production and subsequent maintenance.

[0007] Therefore, there is an urgent need for a synchronous rectification timing correction scheme that can achieve high precision and full life cycle self-adaptation without changing the original control strategy, so as to overcome the shortcomings of the existing technology. Summary of the Invention

[0008] To address the shortcomings and deficiencies of existing technologies, this invention provides a synchronous rectification signal timing adaptive correction device and method, aiming to solve the core problems of existing synchronous rectification timing correction schemes, such as poor compatibility and stability due to reliance on software modification of control strategies, insufficient adjustment accuracy that cannot adapt to high-frequency applications, lack of full life cycle adaptability, and high mass production and maintenance costs. This invention employs a collaborative architecture combining software decision-making control with hardware execution correction. The core correction device is connected in series between the output of the synchronous rectification control strategy and the synchronous rectification power device, enabling online adaptive correction of the drive signal timing without altering the original synchronous rectification control strategy. The hardware correction circuit adopts a modular design with cascaded connections, featuring independent timing correction modules corresponding to four typical timing deviation types: rising edge lead, rising edge lag, falling edge lead, and falling edge lag of the synchronous rectification drive signal. Each module is connected in parallel with a bypass switch, allowing for directional correction of single or compound timing deviations through switch on / off combinations. Each timing correction module integrates an RC delay unit with a resistor adjustment array and a logic gate output unit with threshold detection. By combining the on / off states of multiple switches, multiple independent equivalent resistances are formed, changing the RC charging and discharging duration to generate a timing compensation amount matching the timing deviation. This achieves nanosecond-level high-precision timing correction, breaking through the accuracy bottleneck of traditional software adjustment and adapting to MHz-level high-frequency synchronous rectification applications. This invention avoids the system risk of overcorrection in the early stages of correction through a hardware-differentiated default safety setting design. It uses software closed-loop adaptive control logic to detect, determine, and iteratively adjust timing deviations, compensating in real time for timing deviations caused by the inherent parameter dispersion of power devices and long-term parameter drift. This maintains optimal efficiency and reliability of the synchronous rectification system throughout its entire lifecycle. The solution effectively reduces the conduction and switching losses of synchronous rectification power devices, significantly improving the energy conversion efficiency of the power conversion system. It also avoids risks such as abnormal device conduction and overheating damage caused by timing misalignments. It has good topology versatility, adapting to various power conversion topologies such as LLC and its derivatives, flyback, phase-shifted full-bridge, BOOST, and BUCK. The core hardware can be implemented using domestically produced components, eliminating the need for complex software calibration on a per-product basis, significantly reducing mass production and subsequent maintenance costs. It possesses excellent engineering feasibility and industrialization value.

[0009] The specific technical solution adopted by this invention to solve its technical problem is as follows:

[0010] A synchronous rectification signal timing adaptive correction device is connected in series between the output of the synchronous rectification control strategy and the synchronous rectification power device, including a software control unit and a hardware correction circuit.

[0011] The software control unit is used to detect the edge timing deviation of the actual drive signal output by the synchronous rectification control strategy relative to the ideal synchronous rectification reference signal, determine the type and amount of the edge timing deviation, and generate a correction control signal.

[0012] The input terminal of the hardware correction circuit receives the actual drive signal, the control terminal receives the correction control signal, and the output terminal outputs the corrected drive signal to the synchronous rectifier power device.

[0013] The hardware correction circuit includes multiple timing correction modules, each corresponding to a different edge timing deviation type. Each timing correction module includes an RC delay unit and a logic gate output unit.

[0014] The RC delay unit includes a charging resistor, a charging capacitor, and a base path resistor that provides a continuous charging path for the charging capacitor.

[0015] The logic gate output unit is provided with a signal input terminal and a threshold detection terminal. The signal input terminal receives the actual driving signal or its derived logic signal, and the threshold detection terminal is connected to the common node of the charging resistor and the charging capacitor. The logic gate output unit is used to switch the output state when the voltage of the charging capacitor reaches its input threshold.

[0016] The hardware correction circuit responds to the correction control signal, activates the timing correction module corresponding to the edge timing deviation type, and adjusts the resistance value of the charging resistor in the corresponding timing correction module so that the time for the voltage of the charging capacitor to charge from the initial state to the input threshold matches the deviation amount, thereby completing the timing correction of the actual drive signal.

[0017] Furthermore, the timing correction module includes four functionally independent units, which correspond to four edge timing deviation types of synchronous rectification drive signal: rising edge leading, rising edge lagging, falling edge leading, and falling edge lagging. The four timing correction modules adopt a modular design of being cascaded in series.

[0018] Each timing correction module is connected in parallel with a bypass switch. When the bypass switch is closed, the corresponding timing correction module is bypassed and does not participate in signal processing. When the bypass switch is open, the corresponding timing correction module is put into operation. By controlling the on / off combination of each bypass switch, directional correction of single or compound edge timing deviations can be achieved.

[0019] Furthermore, the charging resistor of the RC delay unit adopts a resistor adjustment array architecture. The resistor adjustment array is composed of a basic path resistor and a fixed resistor independently controlled by a multiplexer connected in parallel. By controlling the on and off combinations of the multiplexer, multiple independent and non-repeating equivalent resistances are formed.

[0020] Furthermore, the timing correction module that adapts to rising edge lead and falling edge lead timing deviations has its resistor adjustment array multiplexer normally closed by default, the equivalent resistance of the charging resistor is at its minimum value, and the corresponding lead correction amplitude is at its minimum level.

[0021] The timing correction module is adapted to timing deviations of rising edge lag and falling edge lag. Its resistor adjustment array multiplexer is normally open by default, the equivalent resistance of the charging resistor is at its maximum value, and the corresponding lag correction range is at its minimum level.

[0022] Furthermore, the RC delay unit also includes a discharge switch in parallel with the charging capacitor. The discharge switch is turned on when the synchronous rectification drive signal is low, so that the charging capacitor discharges quickly, preparing for the timing correction of the next switching cycle.

[0023] The basic path resistor is used to avoid loop disturbances during the switching process and improve the working stability of the RC charging and discharging circuit.

[0024] Furthermore, the timing correction module corresponding to the rising edge lead timing deviation is the basic correction module, and its logic gate output unit adopts AND gate logic circuit;

[0025] The timing correction module for rising edge lag timing deviation adds NAND gate logic circuits and OR gate logic circuits to the basic correction module.

[0026] The timing correction module for falling edge lead timing deviation adds two NAND gate logic circuits to the basic correction module.

[0027] The timing correction module for falling edge lag timing deviation adds two NAND gate logic circuits and one OR gate logic circuit to the basic correction module.

[0028] The logic inversion function in the timing correction module is implemented by shorting the two input terminals of the 2-input NAND gate logic circuit to form an equivalent NOT gate.

[0029] Furthermore, the software control unit presets a correction threshold. The software control unit compares the detected edge timing deviation with the correction threshold, and generates a correction control signal only when the timing deviation is greater than the correction threshold. After adjusting the resistance value of the charging resistor in the corresponding timing correction module, the software control unit verifies whether the absolute value of the difference between the timing compensation amount and the timing deviation is less than or equal to the correction threshold. If it does not meet the requirement, the resistance value of the charging resistor is readjusted until the requirement is met, thus forming a closed-loop adaptive correction.

[0030] And, a synchronous rectification signal timing adaptive correction system, characterized in that it includes a synchronous rectification control strategy module, a synchronous rectification power device, and a synchronous rectification signal timing adaptive correction device as described above.

[0031] The synchronous rectification signal timing adaptive correction device is connected in series between the output of the synchronous rectification control strategy module and the synchronous rectification power device. It is used to correct the timing of the drive signal output by the synchronous rectification control strategy module and then output it to the synchronous rectification power device.

[0032] Furthermore, a synchronous rectified signal timing adaptive correction method includes the following steps:

[0033] The edge timing deviation of the actual drive signal output by the synchronous rectification control strategy relative to the ideal synchronous rectification reference signal is detected, and the type and amount of the edge timing deviation are determined.

[0034] A correction control signal is generated based on the type and amount of the edge timing deviation;

[0035] Based on the correction control signal, the timing correction module corresponding to the edge timing deviation type is activated, and the resistance value of the charging resistor in the corresponding timing correction module is adjusted so that the time for the voltage of the charging capacitor in the timing correction module to charge from the initial state to the input threshold of the logic gate output unit matches the deviation amount, thereby completing the timing correction of the actual drive signal.

[0036] The corrected drive signal is output to the synchronous rectifier power device.

[0037] Furthermore, in the process of generating the correction control signal based on the type and amount of the edge timing deviation, the deviation amount of the edge timing deviation is first compared with a preset correction threshold. If the deviation amount is less than or equal to the preset correction threshold, it is determined that no correction is needed and the initial state of the hardware correction circuit is maintained. If the deviation amount is greater than the preset correction threshold, the correction control signal is then generated.

[0038] If the actual driving signal has a composite edge timing deviation, multiple timing correction modules are enabled in series to perform cascaded timing correction on each individual deviation in the composite deviation in turn.

[0039] Compared to existing technologies, this invention and its preferred embodiment achieve adaptive closed-loop correction of timing deviations at the edges of synchronous rectification drive signals without modifying the original synchronous rectification control strategy. This solves the problems of poor system compatibility and long development cycles caused by modifications to the internal timing of the control strategy in existing technologies. By employing four modularly designed timing correction modules corresponding to four types of edge timing deviations, and in conjunction with bypass switch control, it can flexibly address the directional correction needs of single or compound edge timing deviations, improving the adaptability and versatility of the correction system. Through the coordinated design of the adjustable charging resistor and the basic path resistor in the RC delay unit, combined with the threshold detection mechanism of the logic gate output unit, high-precision matching and compensation of timing deviations are achieved. Simultaneously, the introduction of the basic path resistor effectively avoids loop disturbances during switch switching, improving the operational stability of the RC charging and discharging loop. By using a software control unit to preset correction thresholds and perform closed-loop verification, correction is triggered only when the deviation exceeds the threshold, avoiding unnecessary frequent adjustments while ensuring that the correction accuracy meets the preset requirements, thus forming a reliable adaptive correction mechanism. The overall solution achieves real-time compensation for timing deviations caused by the dispersion of power device parameters and long-term drift at the hardware level, and intelligent decision-making and closed-loop control at the software level, thus synergistically improving the operating efficiency and long-term reliability of the synchronous rectification system. Attached Figure Description

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 Control diagram for synchronous rectification strategy;

[0042] Figure 2 This is a circuit topology diagram of an LLC circuit according to an embodiment of the present invention;

[0043] Figure 3 This is a diagram showing the ideal synchronous rectification signal waveform of the LLC circuit topology in an embodiment of the present invention.

[0044] Figure 4 The diagram shows typical types of timing deviations of synchronous rectified signals according to embodiments of the present invention. In the diagram, (a) is a waveform diagram of synchronous rectified signal with rising edge leading, (b) is a waveform diagram of synchronous rectified signal with rising edge lagging, (c) is a waveform diagram of synchronous rectified signal with falling edge leading, and (d) is a waveform diagram of synchronous rectified signal with falling edge lagging.

[0045] Figure 5 The waveform diagram shows the low efficiency caused by the excessively small indentation of the synchronous rectification signal drive in an embodiment of the present invention.

[0046] Figure 6 This is a waveform diagram illustrating the low reliability caused by the timing delay of the synchronous rectification signal in an embodiment of the present invention.

[0047] Figure 7 A diagram showing the access architecture of the hardware-added correction circuit for the technical solution of this invention embodiment;

[0048] Figure 8 This is a block diagram of the synchronous rectification drive pre-correction circuit according to an embodiment of the present invention;

[0049] Figure 9 This is a circuit diagram of the synchronous rectification signal rising edge lead correction module according to an embodiment of the present invention;

[0050] Figure 10 This is a circuit diagram of the synchronous rectified signal rising edge lag correction module according to an embodiment of the present invention;

[0051] Figure 11 This is a circuit diagram of the synchronous rectification signal falling edge lead correction module according to an embodiment of the present invention;

[0052] Figure 12 This is a circuit diagram of the synchronous rectified signal falling edge hysteresis correction module according to an embodiment of the present invention;

[0053] Figure 13 The figure shows the circuit diagram of the precision adjustment unit for timing correction of synchronous rectified signal according to an embodiment of the present invention; in the figure, (a) is the circuit diagram of the precision adjustment unit adapted to the synchronous rectified signal lead correction circuit, and (b) is the circuit diagram of the precision adjustment unit adapted to the synchronous rectified signal lag correction circuit.

[0054] Figure 14 This is a flowchart illustrating the control strategy for adaptive timing correction of synchronous rectified signals according to an embodiment of the present invention.

[0055] Figure 15 This is a diagram illustrating the operating state of the synchronous rectification signal rising edge advance correction circuit according to an embodiment of the present invention.

[0056] Figure 16 The diagram shows the circuit and device selection parameters of the synchronous rectified signal rising edge lead correction module according to an embodiment of the present invention; in the diagram, (a) is the circuit diagram of the synchronous rectified signal rising edge lead correction module, and (b) is the circuit diagram of the accuracy adjustment unit of the corresponding correction module.

[0057] Figure 17 The figure shows the waveform of the correction process of the synchronous rectified signal rising edge lead correction circuit in an embodiment of the present invention; in the figure, (a) is the overall working waveform of the synchronous rectified signal rising edge lead correction circuit, and (b) is the waveform magnification of the corresponding correction process.

[0058] Figure 18 This is a diagram illustrating the effect of synchronous rectification signal rising edge lead correction in an embodiment of the present invention.

[0059] Figure 19This is a diagram illustrating the operating state of the synchronous rectified signal rising edge lag correction circuit according to an embodiment of the present invention.

[0060] Figure 20 The diagram shows the circuit and device selection parameters of the synchronous rectified signal rising edge lag correction module according to an embodiment of the present invention; in the diagram, (a) is the circuit diagram of the synchronous rectified signal rising edge lag correction module, and (b) is the circuit diagram of the accuracy adjustment unit of the corresponding correction module.

[0061] Figure 21 The figure shows the waveform of the correction process of the synchronous rectified signal rising edge lag correction circuit in an embodiment of the present invention; in the figure, (a) is the overall working waveform of the synchronous rectified signal rising edge lag correction circuit, and (b) is the waveform magnification of the corresponding correction process.

[0062] Figure 22 This is a diagram illustrating the effect of synchronous rectification signal rising edge lag correction in an embodiment of the present invention.

[0063] Figure 23 This is a diagram illustrating the operating state of the synchronous rectified signal falling edge advance correction circuit according to an embodiment of the present invention.

[0064] Figure 24 The diagram shows the circuit diagram of the synchronous rectified signal falling edge lead correction module and the waveform diagram of the correction process in an embodiment of the present invention. In the diagram, (a) is the circuit diagram of the synchronous rectified signal falling edge lead correction module, (b) is the overall working waveform diagram of the synchronous rectified signal falling edge lead correction circuit, and (c) is the waveform magnification diagram of the corresponding correction process.

[0065] Figure 25 This is a diagram illustrating the effect of synchronous rectification signal falling edge lead correction in an embodiment of the present invention.

[0066] Figure 26 This is a diagram illustrating the operating state of the synchronous rectified signal falling edge lag pre-correction circuit according to an embodiment of the present invention.

[0067] Figure 27 The diagram shows the circuit and device selection parameters of the synchronous rectified signal falling edge hysteresis correction module according to an embodiment of the present invention; in the diagram, (a) is the circuit diagram of the synchronous rectified signal falling edge hysteresis correction module, and (b) is the circuit diagram of the accuracy adjustment unit of the corresponding correction module.

[0068] Figure 28 The figure shows the waveform of the correction process of the synchronous rectified signal falling edge hysteresis correction circuit in an embodiment of the present invention; in the figure, (a) is the overall working waveform of the synchronous rectified signal falling edge hysteresis correction circuit, and (b) is the waveform magnification of the corresponding correction process.

[0069] Figure 29 This is a diagram illustrating the effect of correcting the falling edge hysteresis of the synchronous rectified signal in an embodiment of the present invention.

[0070] Figure 30 This is a diagram illustrating the operating state of the synchronous rectification signal rising edge lag and falling edge lead correction circuit according to an embodiment of the present invention.

[0071] Figure 31 This diagram illustrates the effect of correcting the composite type of rising edge lag and falling edge lead of the synchronous rectified signal in an embodiment of the present invention. Detailed Implementation

[0072] To make the features and advantages of the present invention more apparent and understandable, specific embodiments are described below in detail:

[0073] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0074] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0075] This invention addresses the technical shortcomings of existing synchronous rectification technology by providing a synchronous rectification signal timing adaptive correction device and method. It solves the dual impacts of inherent parameter dispersion of power devices and long-term operating parameter drift in existing technologies, and the problems of poor compatibility, limited adjustment accuracy, lack of full life cycle adaptability, and difficulty in mass production and later maintenance caused by relying on software modification of control strategies to correct timing. At the same time, it fills the gap in the industry for a mass-production-applicable, low-cost, high-precision, and highly adaptable online adaptive calibration method for synchronous rectification timing.

[0076] This invention, through a software control combined with hardware circuit correction architecture, achieves real-time adaptive correction of drive signal timing without altering the original system's synchronous control strategy. It automatically compensates for timing deviations caused by power device parameter tolerances and operational drift, ensuring the synchronous rectification system maintains optimal efficiency and reliability throughout its entire lifecycle. The invention's specific objectives are divided into core and extended objectives:

[0077] (a) Core Purpose

[0078] 1. Overcome the dual impact of inherent parameter dispersion of power devices and long-term operating parameter drift on synchronous rectification control, correct drive timing deviation in real time, reduce the deviation between theoretical design and actual operation of the system, and improve the control accuracy of synchronous rectification throughout its entire life cycle;

[0079] 2. Targeted and precise compensation is achieved for four typical timing deviations of synchronous rectification signals: leading / lagging rising edge and leading / lagging falling edge. The switching timing is optimized to reduce the conduction and switching losses of power devices, thereby significantly improving the overall energy conversion efficiency of the converter and maintaining stability.

[0080] 3. It fundamentally avoids risks such as timing misalignment, loop instability, and local runaway caused by parameter changes, prevents abnormal conduction and overheating damage of power devices, improves the operational stability and reliability of synchronous rectification systems, and extends the service life of products and power devices.

[0081] (II) Expansion Objectives

[0082] 1. Achieve independent and adjustable single-transistor drive timing for synchronous rectifier power devices. Through modular design of hardware correction circuits, improve the adaptability of the solution to devices with different parameters and operating conditions, and ensure optimal efficiency and reliability of a single product throughout its entire life cycle.

[0083] 2. Construct a generalized timing correction architecture that is compatible with LLC and its derivative topologies, phase-shifted full-bridge (dead time is required for the upper and lower arms, and the dead time refers to the interval between the power devices in the upper and lower arms to avoid being turned on at the same time), flyback, BOOST, BUCK (single-tube synchronous rectification), and other power conversion topologies. It can also be extended to other power electronic control applications that require timing correction of the control signal edges.

[0084] 3. A simple hardware architecture is built based on RC circuits and switching modules to achieve high-precision online adaptive parameter tuning with all core hardware domestically produced, without the need to add complex main control and computing chips. Flexible matching of timing calibration accuracy is achieved through hierarchical control of switches.

[0085] 4. Adapts to the needs of large-scale industrial production, eliminating the need for complex software programming and parameter burning for each product. By uniformly controlling the hardware switching actions through software, it solves the problem of inconsistent product performance caused by poor component consistency and improves the performance qualification rate of mass-produced products.

[0086] 5. By utilizing the hard delay correction characteristics of hardware circuits, real-time timing adjustment with fast response and wide switching frequency range adaptation is achieved, resulting in low control delay, good dynamic performance, and compatibility with MHz-level high-frequency synchronous rectification application requirements.

[0087] 6. Enables online, automatic, and non-disassembly-based correction of drive timing, eliminating the need for recalibrating and debugging the original control strategy, thus reducing the maintenance procedures and costs in the later stages of the system; at the same time, it maintains optimal power conversion efficiency throughout the entire life cycle, reducing energy consumption from the source and contributing to the energy conservation, carbon reduction, and industrialization development of power electronic equipment.

[0088] The implementation process of the present invention will be shown below through more specific embodiments:

[0089] This invention provides a synchronous rectification signal timing adaptive correction device and method, constructing a collaborative architecture of software decision control and hardware execution correction. Without altering the original synchronous rectification control strategy, the software performs timing deviation detection, judgment, and switching logic control, while the hardware circuit precisely corrects the edge timing of the synchronous rectification drive signal, solving the timing deviation problem caused by the inherent parameter dispersion of power devices and long-term operating parameter drift. This solution is applicable to the synchronous rectification control stage of various power conversion topologies such as LLC and its derivative topologies, flyback, phase-shifted full-bridge, BOOST, and BUCK. The following description uses an LLC resonant converter as an exemplary application scenario to fully illustrate the technical solution.

[0090] (I) Definition of application scenarios and core issues

[0091] Synchronous rectification is a core technology for improving the energy conversion efficiency of the secondary side of an LLC resonant converter. By replacing traditional rectifier diodes with MOSFETs, the conduction losses in the rectification stage can be significantly reduced. The efficiency improvement directly depends on the accuracy of the switching timing of the synchronous rectifier diodes. Figure 2 As shown, Q5, Q6, Q7, and Q8 are synchronous rectifier power devices on the secondary side of the LLC resonant converter, and their switching timing must be strictly matched to the LLC resonant operating characteristics. Figure 2 In the LLC resonant converter topology shown, two pairs of complementary conducting switches Q1 and Q2 (upper bridge arm) and Q3 and Q4 (lower bridge arm) are arranged on the primary side to form an LLC primary-side full-bridge inverter circuit; the primary side also includes a resonant capacitor C and a resonant inductor L. r The transformer T, integrated with the magnetizing inductor, has four synchronous rectifier power devices Q5, Q6, Q7, and Q8 on its secondary side, connected to the secondary winding of the transformer. After rectification, it outputs a DC voltage. OUT Input DC voltage IN Connecting to the primary-side full-bridge circuit, through the high-frequency complementary conduction of the primary-side switching transistors, combined with the resonant element L... r The C and T circuits enable resonant energy transfer. The switching sequence of the secondary synchronous rectifier diodes Q5 to Q8 must be strictly matched with the phase of the primary resonant cavity current and the secondary current to achieve efficient synchronous rectification.

[0092] Based on the above operating characteristics, the ideal synchronous rectified signal output by the LLC synchronous rectification control strategy is denoted as SR. ref Its waveform is as follows Figure 3 (Synchronous rectification ideal signal SR in LLC circuit topology) refAs shown in the diagram, this signal serves as the reference timing for the secondary-side MOSFET switch. In actual mass production and engineering applications, due to the inherent dispersion of parameters such as the power device's input junction capacitance, threshold voltage, and switching delay time, the synchronous rectification signal actually output by the control strategy and applied to the secondary-side power device is denoted as SR, which cannot be directly compared to SR. ref Even with a perfect match, a timing deviation Δt is unavoidable.

[0093] Analyzing the rising and falling edges of the SR signal, there are four typical timing deviation types: SR compared to SR ref Rising edge leading ( Figure 4 (a)), rising edge hysteresis ( Figure 4 (b) Falling edge leading ( Figure 4 (c) Falling edge hysteresis ( Figure 4 (d)).

[0094] This timing deviation Δt directly leads to two core issues: firstly, how... Figure 5 As shown, the deviation of lagging rising edge and leading falling edge will cause the SR drive to be too small, the conduction time of the secondary MOS transistor body diode to be too long, the conduction loss to increase significantly, and the converter conversion efficiency to fail to reach the theoretical optimal value; secondly, as Figure 6 As shown, if the timing deviation exceeds the reasonable range, the MOSFET will be abnormally turned on, causing the secondary side energy to flow back into the primary side, destroying the LLC resonant characteristics, leading to hard switching of the primary side main tube, severe overheating, or even permanent damage, which greatly reduces the reliability of the system.

[0095] (II) Device Architecture

[0096] The core improvement of this invention lies in the addition of a hardware correction circuit for the synchronous rectification signal. This device is connected in series between the output of the synchronous rectification control strategy and the synchronous rectification power device. The overall access architecture is as follows: Figure 7 As shown. Without altering the original LLC circuit's synchronous rectification control strategy, only the timing of the SR signal actually output to the synchronous rectifier diode before the strategy is corrected. The output SR signal is then time-compensated by the correction circuit. adj Matching synchronous rectification ideal timing signal SR ref This addresses the efficiency and reliability issues caused by timing deviations at their root.

[0097] This hardware correction circuit provides the physical execution platform for software decision-making. Its overall architecture is entirely subordinate to the software control strategy. The activation of the correction module and the selection of accuracy levels are determined by the switching control signals output by the software, forming a collaborative working mode where software decision-making is dominant and hardware circuit execution is paramount. The hardware correction circuit, as the core execution unit, adopts a modular design with cascaded connections, offering strong expansion flexibility and adaptability to multiple topologies and operating conditions. The overall topology structure is as follows: Figure 8 As shown.

[0098] Figure 8 It includes four independent timing correction modules and a precision adjustment unit integrated into each module. The core structure and working logic of each module are as follows.

[0099] 1. Timing Correction Module: Corresponding to Figure 4 The system employs four typical timing deviation types, each with its own rising edge lead correction module, rising edge lag correction module, falling edge lead correction module, and falling edge lag correction module. Each correction module is connected in parallel with a bypass switch (K1, K2, K3, and K4, all closed by default). Correction functions are activated as needed, minimizing the impact on the original circuit switching and ensuring system stability. When the switch is closed, the corresponding correction module is bypassed and does not participate in signal processing; when the switch is open, the corresponding correction module is activated. By controlling the on / off combinations of the four bypass switches, targeted correction of single or combined timing deviations can be achieved.

[0100] (1) Rising edge lead correction module: The internal circuit structure is as follows Figure 9 As shown, the core consists of an RC charging and discharging circuit, a discharge transistor Q, and an AND gate logic circuit. It utilizes the RC charging delay characteristic in conjunction with the AND gate threshold logic to achieve delay correction for the leading rising edge.

[0101] The other three correction modules are all based on this module and have been expanded in terms of functionality. The working principle of this module will be introduced in detail.

[0102] When SR is high, the discharge transistor Q is off, and SR charges capacitor C through the adjustable charging resistor R. When SR is low, the discharge transistor Q is closed, and capacitor C discharges through the discharge transistor Q. Since there is no resistance in the discharge circuit at this time, the discharge speed is very fast, preparing for the next switching cycle of SR. Additionally, the drive resistor R... DR It can also play a role in resisting high-frequency interference when driving the discharge tube Q.

[0103] Combination Figure 9 The rising edge lead correction circuit of SR works as follows: When SR is high, the discharge transistor Q is turned off, and SR charges capacitor C through the adjustable charging resistor R. The charging voltage on capacitor C is connected to pin 2 of the AND gate. When the charging voltage rises to the high-level threshold voltage V of the AND gate... IH Previously, Pin2 remained low, and the AND gate output remained low, achieving a delay cutoff of the leading rising edge of SR; when the charging voltage reached V... IHWhen SR is high, Pin2 goes high and performs an AND operation with Pin1's high SR. The AND gate outputs a high level, generating the corrected rising edge of the signal, thus accurately correcting the lead error of the SR rising edge. When SR is low, the AND gate outputs a low level. See the specific waveforms above. Figure 17 .

[0104] The essence of the circuit correcting the rising edge lead of SR is to use the charging voltage to raise the timing deviation Δt of the rising edge lead of SR to the high-level threshold voltage V of the AND gate. IH Correction: Charge C by adjusting the adjustable resistor R until the charging voltage reaches V. IH Previously, when pin 2 of the AND gate was low, the output was also low, thus delaying and truncating the leading rising edge of the SR, resulting in the corrected SR. adj .

[0105] (2) Rising edge hysteresis correction module: The internal circuit structure is as follows Figure 10 As shown, based on the rising edge lead correction circuit, NAND and OR gate logic circuits are added. The SR signal is inverted to generate a lead pulse signal to compensate for the timing deviation due to rising edge lag. Finally, an OR operation is performed with the SR signal to obtain the corrected SR. adj .

[0106] It should be noted that the logic inversion function in the correction circuit is not implemented using a NOT gate. Instead, it is achieved by shorting the two input terminals of a 2-input NAND gate to form an equivalent NOT gate. This engineering approach improves the circuit's reliability and anti-interference capability under high-frequency conditions, enhances the stability of the input signal, and reduces glitches and false triggers during high-frequency signal transmission. As a further preferred implementation, the equivalent NOT gate is connected as follows: the two signal input terminals of the 2-input NAND gate logic circuit are shorted and then connected to the input signal to be inverted. The output terminal of the NAND gate is then the inverted signal output terminal.

[0107] (3) Falling edge lead correction module: The internal circuit structure is as follows Figure 11 As shown, two NAND gate logic circuits are added to the rising edge lead correction circuit. Similarly, the RC charging and discharging characteristics are used to achieve precise control of the falling edge lead deviation, resulting in the corrected SR. adj .

[0108] (4) Falling edge hysteresis correction module: Internal circuit structure as follows Figure 12 As shown, two NAND gates and one OR gate are added to the rising edge lead correction circuit. Through logic combination, compensation for falling edge lag is achieved, resulting in the corrected SR. adj .

[0109] 2. Precision Adjustment Unit: This unit is integrated into the RC charging circuit of each timing correction module, and its core is a high-precision resistor adjustment array. This resistor adjustment array is the adjustable charging resistor R in the timing correction module (e.g., Figure 13 (The elliptical dashed frame annotation) Figure 13 The capacitor C in the original text is exactly the same as the capacitor C in the correction module. Additionally, Figure 13 V in DR The input drive voltage signal for the precision adjustment unit is either the voltage signal directly input to the SR or input to the precision adjustment unit via inversion.

[0110] This unit is implemented based on a 4-way switch (KA, KB, KC, KD). It consists of R5 connected in parallel with fixed resistors (R1~R4, with non-repeating resistance values) that are independently controlled by the multiple switches. By controlling the on / off combinations of KA~KD through software, 16 independent and non-repeating equivalent resistances can be formed, thereby flexibly changing the RC charging time and generating a timing compensation Δt that matches the timing deviation Δt. adj This enables high-precision timing correction at the level of hundreds of nanoseconds or even nanoseconds. The timing deviation Δt is the difference between the actual SR signal output to the synchronous rectifier before the strategy and the ideal timing signal SR of the synchronous rectifier. ref Timing deviation; timing compensation Δt adj This refers to timing compensation, where the correction circuit corrects the timing deviation Δt.

[0111] It should be noted that the number of switches is configurable and not limited to 4 channels. The number of switches and their matching fixed resistors can be flexibly adjusted according to the accuracy requirements of the actual engineering conditions. When the number of switches is n, 2 n The equivalent resistance change of independent circuits (such as a 6-way switch, to achieve 2) 6 =64 levels of adjustment), the more switches there are, the finer the accuracy levels of timing compensation, which can adapt to higher precision synchronous rectification timing correction requirements.

[0112] Figure 13 (a) Adapted to SR lead correction circuit (rising edge lead, falling edge lead), KA~KD are normally closed by default. At this time, the equivalent resistance of the adjustable charging resistor R is at its minimum value, and the corresponding lead correction amplitude is at its minimum level, so as to avoid the system abnormality caused by excessive lead correction amplitude in the early stage of correction. Figure 13(b) Adapted to SR hysteresis correction circuit (rising edge hysteresis, falling edge hysteresis). KA~KD are normally open by default. At this time, the equivalent resistance of the adjustable charging resistor R is at its maximum value, corresponding to the minimum hysteresis correction level. This also prevents the hysteresis correction level from being too large in the initial stage of correction, thus reducing the reliability of system operation. The above default level setting provides an initial safety threshold for the correction process, avoiding the problem of excessive timing correction caused by excessive compensation in the initial stage of correction from a hardware perspective, ensuring the stability and reliability of the synchronous rectification system during the correction process. In addition, resistor R5 is the basic charging path resistor for capacitor C. During the switching of KA~KD and the adjustment of the resistance array, it provides a continuous and stable charging path for capacitor C. The voltage stability of capacitor C can effectively avoid loop disturbances during the switching process, reduce signal interference, and improve the working stability and timing compensation accuracy of the RC charging and discharging circuit during the precision adjustment process. Its core mechanism is as follows: During the switching process of the multi-way switch of the precision adjustment unit, if all parallel branches are simultaneously disconnected at the moment of switch switching, the basic path resistor R5 can ensure that the charging circuit always remains in a conducting state, avoiding circuit disturbances such as sudden changes in capacitor voltage and oscillations caused by the opening of the charging circuit; at the same time, the fixed resistance value of R5 can avoid the step change in the total circuit resistance caused by the switching of parallel branches, so that the capacitor charging current remains continuous and stable, further ensuring the accuracy and stability of timing compensation.

[0113] The original synchronous rectification control strategy output SR signal is directly input to the input terminal of the hardware correction circuit. After being processed by the timing correction module and the accuracy adjustment unit, the corrected SR... adj The signal is directly applied to the LLC synchronous rectifier power devices (Q5~Q8) from the circuit output, completing the engineering implementation of timing correction. The logic gates, discharge tubes, and switching devices used in this device are all domestically produced components, which can improve supply chain security and engineering feasibility, while ensuring the reliability and accuracy stability of the circuit under high-frequency operating conditions.

[0114] (III) Control Methods

[0115] The control method of this invention, under steady-state operation conditions, achieves precise scheduling of the hardware correction circuit through software logic without changing the core logic of the original synchronous rectification control strategy. The control flow is as follows: Figure 14 As shown, the specific steps include:

[0116] 1. Deviation Detection Steps: After the LLC resonant converter enters steady-state operation, extract the rising and falling edges of the actual synchronous rectified signal SR and compare them with the ideal synchronous rectified signal SR. ref By comparison, the edge timing deviation Δt is calculated;

[0117] 2. Correction and Judgment Step: Compare the calculated timing deviation Δt with the preset correction threshold Δtth The comparison is performed to determine whether the correction process should be triggered. If Δt ≤ Δt th If it is determined that no correction is needed, the original hardware circuit state should be maintained; if Δt > Δt th The result indicates that correction is needed, and the subsequent correction steps will proceed.

[0118] 3. Correction type selection steps: Based on the type of timing deviation Δt (rising edge leading / lagging, falling edge leading / lagging), the software outputs a switch control signal to regulate the on / off state of bypass switches K1~K4, only activating the timing correction module that matches the deviation type, while the other modules remain in the bypass state, thus achieving directional correction;

[0119] 4. Precision Adjustment Steps: Based on the magnitude of the timing deviation Δt, the software outputs a precision control signal to adjust the on / off combination of KA~KD in the precision adjustment unit, selecting... Figure 13 The corresponding equivalent resistance setting causes the RC charging and discharging time to produce a timing compensation Δt that matches the Δt value. adj If timing compensation Δt adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th ≤Δt th (If a preset correction threshold is set), it is determined that the timing deviation has been accurately corrected.

[0120] This technical solution implements the core function of timing correction through hardware circuits and realizes intelligent scheduling of correction strategies through software logic. The two work together to solve the defects of existing software correction schemes such as poor compatibility, limited accuracy, and lack of full life cycle adaptability. It also realizes cross-topology universal and high-precision timing correction, ensuring that the synchronous rectification system maintains optimal efficiency and reliability throughout its entire life cycle.

[0121] The following test examples further demonstrate the effectiveness of the solution:

[0122] This embodiment uses an LLC resonant converter with a switching frequency of 145kHz as the application platform. In engineering practice, the correction threshold Δt is set at 1% of the switching period. th =69ns. This threshold is only set to verify the technical solution of the present invention and is for illustrative reference only. In practice, it can be set according to the engineering application conditions.

[0123] For four types of single timing deviations and one type of composite timing deviation, and in conjunction with the selection of domestically produced components, the correction effect of the "software decision-making-led, hardware circuit execution" collaborative architecture of this invention was verified: the original LLC synchronous rectification control strategy was not modified, the correction module was directionally activated only through the on / off combination of bypass switches (K1~K4), and the compensation amount was matched through the precision adjustment unit (KA~KD), and the corrected timing deviation was ≤Δt. thThe engineering requirements were met, and finally, the efficiency improvement after implementing the strategy was verified.

[0124] (I) Typical Single-Type Timing Deviation Correction Implementation Example

[0125] Example 1: SR rising edge lead deviation correction: This example is for Figure 4 (a) shows a typical type of rising edge lead in SR, verifying the hardware working logic, accuracy adjustment adaptability and correction effect of the rising edge lead correction module.

[0126] 1. Improved triggering and control strategy execution.

[0127] After the LLC converter enters steady-state operation, the software performs a deviation detection step to calculate the SR relative to SR. ref The rising edge lead time deviation is Δt = 500 ns, and Δt > Δt th =69ns), indicating that a correction process needs to be triggered. Based on the correction type, the software outputs switch control signals (default closed): closes K2, K3, and K4, opens K1, and only activates the rising edge lead correction module (e.g., ...). Figure 15 , 16 (a) As shown); simultaneously, the precision adjustment step is executed, controlling the on / off combination of KA~KD (default closed): KA and KB are closed, KC and KD are open, so that the equivalent resistance of the adjustable charging resistor R is 41.50Ω (as shown in (a)). Figure 16 (b) shows the requirement for a compensation amount of 500ns.

[0128] 2. Correcting circuit and component selection

[0129] The correction circuit used in this embodiment is an SR rising edge lead correction circuit, the specific circuit of which is as follows: Figure 16 As shown in (a); the selection and parameters of the core components are shown in Table 1. All components are domestically produced. The brands are only examples. Other domestic brands with equivalent performance can be used.

[0130] Precision adjustment unit such as Figure 16 As shown in (b), the resistance adjustment array within the elliptical dashed frame is the adjustable charging resistor R in 16(a); the resistance adjustment array and the states of KA~KD are shown in Table 2: when KA and KB are closed and KC and KD are open, the adjustable charging resistor R = R1 / / R2 / / R5 = 820 / / 390 / / 47 = 41.50Ω.

[0131] Table 1. Specific Models and Parameters of Corrected Circuit Components

[0132]

[0133] Table 2. Precision Adjustment Unit Resistor Array Parameters and On / Off States

[0134]

[0135] 3. Hardware Repair Process

[0136] The specific work process is as follows: Figure 17 As shown, when SR is high, the discharge transistor Q is turned off, and SR charges capacitor C through the 41.50Ω equivalent resistance of the precision adjustment unit. The charging voltage is connected to pin 2 of the AND gate. When the charging voltage rises to the high-level threshold voltage V of the AND gate... IH Before the voltage reaches 3.5V, Pin2 is at a low level, and the AND gate output remains low, thus delaying and trunculating the leading rising edge of SR. When the charging voltage reaches 3.5V, Pin2 becomes high, and it enters an AND operation with the high level of SR at Pin1. The AND gate outputs a high level, thereby generating a corrected rising edge and accurately correcting the leading edge deviation.

[0137] Figure 17 (a) (Vertical axis: 5V / division, horizontal axis: 2.5μs / division) verifies the working principle of SR rising edge lead correction. Δt2 and Δt3 represent the RC charging and discharging processes in the circuit, respectively. Δt1 is the inherent hardware delay of the falling edge. This delay is mainly caused by the inherent hardware delays of the discharge transistor Q, the AND gate, the circuit bypass switch K1, and the precision adjustment unit switches KC and KD. As shown in Table 1:

[0138] Δt1 = 3ns (discharge tube Q) + 4ns (AND gate) + 3ns (bypass switch K1) + 3ns (precision adjustment unit switch KC) + 3ns (precision adjustment unit switch KD) = 16ns (1)

[0139] Figure 17 (b) (Vertical axis: 5V / division, Horizontal axis: 500ns / division) Verify that the correction circuit is charged to the AND high-level threshold voltage V by RC. IH When the voltage is 3.5V, correction is performed. The waveform shows that this charging time is the timing compensation Δt of the rise-edge lead correction circuit. adj From Tables 1 and 2, the equivalent resistance R = 41.50Ω, the capacitance C = 10nF, and the charging voltage V... CC =5V, V IH =3.5V, then:

[0140] (2)

[0141] From (1) and (2), it can be seen that the timing deviation of the rising edge of SR can be corrected by the SR rising edge lead correction module circuit, and the timing compensation Δt is corrected. adj=499.65ns; Due to the inherent delay characteristics of the correction circuit hardware, the falling edge delay time Δt1=16ns is caused.

[0142] 4. Verification of Correction Effect

[0143] The correction effect of this embodiment is as follows: Figure 18 (Vertical axis: 5V / division, horizontal axis: 1μs / division) As shown.

[0144] pass Figure 18 SR in ref SR, SR adj Waveform comparison shows that the corrected SR adj Rising edge and ideal signal SR ref They are basically the same. In the waveform, except for the timing compensation Δt from the circuit correction... adj In addition, there is a falling edge delay caused by the correction circuit. This delay is due to the inherent hardware delay of the AND gate, which, according to the table, is 4ns. Therefore, the timing compensation Δt adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th :

[0145] Δt' th =|Δt-Δt adj -4|=|500-499.65-4|=3.65ns<Δt th =69ns (3)

[0146] Due to the inherent delay characteristics of the correction circuit hardware, SR is caused adj The falling edge delay time is:

[0147] Δt1=16ns<Δt th =69ns (4)

[0148] From equations (3) and (4), we can see that: SR adj The timing deviations of both the rising and falling edges meet the set correction threshold Δt. th As required, this embodiment achieves precise correction of the lead deviation of the rising edge of SR.

[0149] Example 2: SR rising edge hysteresis correction: This example is for... Figure 4 (b) shows a typical type of rising edge hysteresis in SR, verifying the hardware working logic, accuracy adjustment adaptability and correction effect of the rising edge hysteresis correction module.

[0150] 1. Improved triggering and control strategy execution.

[0151] Based on the correction type selection step, output switch control signals (default closed): close K1, K3, and K4, open K2, and only activate the rising edge hysteresis correction module (e.g., Figure 19 , 20 (a)); at the same time, the precision adjustment step is performed to adjust the on / off combination of KA~KD (default is off) so that the equivalent resistance of the adjustable charging resistor R matches the compensation requirement of 500ns.

[0152] 2. Correcting circuit and component selection

[0153] The correction circuit used in this embodiment is as follows: Figure 20 (a) Based on the original SR rising edge lead correction circuit (marked with dashed box), a NAND gate and an OR gate have been added; the selection and parameters of the new core components are shown in Table 3. All of them are domestically produced components. The brands are only examples. Other domestic brands with equivalent performance can be used.

[0154] Precision adjustment unit such as Figure 20 As shown in (b), the resistor adjustment array within the elliptical dashed frame is the adjustable charging resistor R in 20(a); the resistor adjustment array and the states of KA~KD are shown in Table 4: when KA is closed and KB, KC, and KD are open, the adjustable charging resistor R = R1 / / R5 = 8.2k / / 270 = 261.39Ω.

[0155] Table 3 Specific Models and Parameters of Corrected Circuit Components

[0156]

[0157] Table 4. Precision Adjustment Unit Resistor Array Parameters and On / Off States

[0158]

[0159] 3. Hardware Repair Process

[0160] The inverted value generates a lead pulse, which is then compensated using an OR logic. The specific correction process is as follows: Figure 21 As shown. Figure 21 In (a) (vertical axis: 5V / division, horizontal axis: 2.5μs / division), the SR signal is inverted by a NAND gate and then charged by an RC circuit to generate timing compensation Δt. adj Then, an OR operation is performed with the input SR waveform to obtain the corrected synchronous rectified waveform SR. adj . Figure 21 (b) (Vertical axis: 5V / division, Horizontal axis: 500ns / division) Verify that the correction circuit is charged to the AND high-level threshold voltage V by RC. IH Correction is made when the voltage is 3.5V, where Δt is... adj The timing compensation is generated by the circuit. Δt1 and Δt2 are the rising edge delay and falling edge delay caused by the hardware circuit, respectively.

[0161] Depend on Figure 21 (a) It can be seen that the timing compensation Δt adj With RC charging to the high-level threshold voltage V IH The sum of the times is the low-level pulse width of SR.

[0162] The low-level pulse width of SR is:

[0163] (5)

[0164] In equation (5): D = 0.47 (D is the driving duty cycle, the proportion of the high-level pulse width of the SR driving, the actual engineering value of 0.47 is taken to prevent the upper and lower arms from being common to the conductor and to leave a dead time), T is the switching period of the LLC resonant converter, which is inversely proportional to the switching frequency.

[0165] RC charging to high-level threshold voltage V IH The time is:

[0166] (6)

[0167] In equation (6): the adjustable equivalent resistance R = 261.39Ω, the capacitance C = 10nF, and the charging voltage V CC =5V, V IH =3.5V (data can be found in Tables 1 and 4).

[0168] Then the timing compensation Δt for rising edge lag correction adj for:

[0169] Δt adj =3655.17-3147.06=508.1ns (7)

[0170] Depend on Figure 21 (b) It can be seen that the SR output of the correction circuit adj The output has a certain signal delay on both the rising and falling edges. Specifically, the rising edge delay time Δt1 in the figure is caused by the inherent hardware delay of the discharge tube Q, AND gate, NAND gate, OR gate, circuit bypass switch K2, and precision adjustment unit switch KA; the falling edge delay time Δt2 is caused by the inherent hardware delay of AND gate, NAND gate, and OR gate.

[0171] The delay data for the above devices can be found in Tables 1 and 3. Therefore:

[0172] Δt1 = 3ns (discharge tube Q) + 4ns (AND gate) + 4ns (NAND gate) + 4ns (OR gate) + 3ns (bypass switch K2) + 3ns (precision adjustment unit switch KA) = 21ns (8)

[0173] Δt2 = 4ns (AND gate) + 4ns (NAND gate) + 4ns (OR gate) = 12ns (9)

[0174] From (7), (8), and (9), it can be seen that the timing deviation of the rising edge lag of SR can be corrected by the SR rising edge lag correction module circuit, and the timing compensation Δt is corrected. adj =508.1ns; Due to the inherent delay characteristics of the correction circuit hardware, the rising edge delay time Δt1=21ns and the falling edge delay time Δt2=12ns are caused.

[0175] 4. Verification of Correction Effect

[0176] The correction effect of this embodiment is as follows: Figure 22 (Vertical axis: 5V / division, horizontal axis: 1μs / division) As shown.

[0177] pass Figure 22 SR in ref SR, SR adj Waveform comparison shows that the corrected SR adj The rising edge and the ideal signal SR ref Basically the same: timing compensation Δt adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th :

[0178] Δt' th =|Δt adj -Δt-Δt1|=|508.1-500-21|=12.9ns<Δt th =69ns (10)

[0179] Because Δt adj >Δt and SR adj Rising edge timing precedes SR ref Therefore, when calculating the absolute value, it should be in accordance with (Δt) adj The calculation is performed using -Δt).

[0180] Revised SR adj The falling edge has a delay time due to the inherent delay characteristics of the correction circuit hardware.

[0181] Δt2=12ns<Δt th =69ns (11)

[0182] From equations (10) and (11), we can see that: SR adj The timing deviations of both the rising and falling edges meet the set correction threshold Δt. th As required, this embodiment achieves accurate correction of the lag deviation of the rising edge of SR.

[0183] Example 3: SR Falling Edge Lead Deviation Correction: This example is for... Figure 4 (c) shows a typical type of SR falling edge lead, verifying the hardware working logic, accuracy adjustment adaptability and correction effect of the falling edge lead correction module.

[0184] 1. Improved triggering and control strategy execution.

[0185] Based on the correction type selection step, output switch control signals (default closed): close K1, K2, and K4, open K3, and only activate the falling edge lead correction module (e.g., Figure 23 (As shown); at the same time, the precision adjustment step is performed to regulate the on / off combination of KA~KD (default is off) so that the equivalent resistance of the adjustable charging resistor R matches the compensation requirement of 500ns.

[0186] 2. Correcting circuit and component selection

[0187] The correction circuit used in this embodiment is as follows: Figure 24 (a) Two NAND gates were added to the original SR rising edge lead correction circuit (marked with dashed boxes). The number of components increased but the model remained the same. This circuit generates timing compensation Δt. adj The principle of the sequential type is exactly the same as that of the rising edge leading type, and the precision adjustment unit circuits of the two are identical. Figure 16 (b) The device parameters are consistent and are shown in Table 2.

[0188] 3. Hardware Repair Process

[0189] By using NAND gates for logic conversion, the rising edge correction principle is extended to the falling edge. The specific correction process is as follows: Figure 24 As shown. Figure 24 (b) (vertical axis: 5V / division, horizontal axis: 2.5μs / division), the SR signal is inverted by the NAND gate NAND1 and then charged by RC, resulting in a timing deviation Δt. adj After inverting NAND2, the SR with falling edge lead correction is obtained. adj . Figure 21 (c) (Y-axis: 5V / division, X-axis: 2.5μs / division) Similarly verify the falling edge lead correction process: RC charging to the AND high-level threshold voltage V IH Correction is performed at 3.5V.

[0190] Figure 24 (c) Verify that the correction circuit is charged to the AND high-level threshold voltage V by RC. IH Correction is performed when the voltage is 3.5V. The waveform shows that this charging time is the timing compensation Δt of the falling edge lead correction circuit. adjFrom Tables 1 and 2, the equivalent resistance R = 41.50Ω, the capacitance C = 10nF, and the charging voltage V... CC =5V, V IH =3.5V, then:

[0191] (12)

[0192] As shown in (12), the timing deviation of the falling edge of SR can be corrected by the SR falling edge lead correction module circuit, and the timing compensation Δt is corrected. adj =499.65ns.

[0193] 4. Verification of Correction Effect

[0194] The correction effect of this embodiment is as follows: Figure 25 (Vertical axis: 5V / division, horizontal axis: 1μs / division) As shown.

[0195] pass Figure 25 SR in ref SR, SR adj Waveform comparison shows that the corrected SR adj Rising edge and ideal signal SR ref The overall relationship is largely the same, except for a delay caused by the correction circuit. This delay is due to the inherent hardware delay characteristics of one AND gate and two NAND gates. Refer to Tables 1 and 3 for SR. adj Rising edge delay time = 4ns (AND gate) + 8ns (2 NAND gates) = 12ns < Δt th =69ns (13)

[0196] Also in SR adj The falling edge has a delay due to the inherent delay of the correction circuit hardware. This delay is caused by the discharge transistor Q, one AND gate, two NAND gates, the circuit bypass switch K3, and the precision adjustment unit switches KC and KD. Referring to Tables 1 and 3, SR... adj The falling edge delay time = 3ns (discharge tube Q) + 4ns (AND gate) + 3ns (bypass switch K3) + 3ns (precision adjustment unit switch KC) + 3ns (precision adjustment unit switch KD) + 8ns (2 AND gates) = 24ns (14)

[0197] SR adj Timing compensation Δt on falling edge adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th :

[0198] Δt' th =|Δt-Δt adj-24|=|500-499.65-24|=23.65ns<Δt th =69ns (15)

[0199] From (14) and (15), we can see that: SR adj The timing deviations of both the rising and falling edges meet the set correction threshold Δt. th As required, this embodiment achieves accurate correction of the SR falling edge lead deviation.

[0200] Example 4: SR Falling Edge Hysteresis Correction: This example is for... Figure 4 (d) shows a typical type of SR falling edge hysteresis, verifying the hardware working logic, accuracy adjustment adaptability and correction effect of the falling edge hysteresis correction module.

[0201] 1. Improved triggering and control strategy execution.

[0202] Based on the correction type selection step, the software outputs switch control signals (default closed): closes K1, K2, and K3, opens K4, and only activates the falling edge hysteresis correction module (e.g., ...). Figure 26 , 27 (a)); at the same time, the precision adjustment step is performed to adjust the on / off combination of KA~KD (default is off) so that the equivalent resistance of the adjustable charging resistor R matches the compensation requirement of 500ns.

[0203] 2. Correcting circuit and component selection

[0204] The correction circuit used in this embodiment is as follows: Figure 27 (a) Based on the original SR rising edge lead correction circuit (marked with dashed box), two NAND gates and one OR gate were added. The number of components increased, but the model remained the same; the precision adjustment unit is as follows: Figure 27 As shown in (b), the resistor adjustment array within the elliptical dashed frame is the adjustable charging resistor R in 27(a); the resistor adjustment array and the states of KA~KD are shown in Table 5: when KB and KD are closed and KA and KC are open, the adjustable charging resistor R = R2 / / R4 / / R5 = 4.7k / / 2.1k / / 270 = 227.65Ω.

[0205] Table 5. Precision Adjustment Unit Resistor Array Parameters and On / Off States

[0206]

[0207] 3. Hardware Repair Process

[0208] The falling edge lag compensation is achieved by using a NOT operator, an OR logic, and a second NOT. The specific correction process is as follows: Figure 28 As shown. Figure 28In (a) (vertical axis: 5V / division, horizontal axis: 2.5μs / division), the SR signal is inverted by a NAND gate and then charged by an RC gate to generate compensation for timing deviation Δt. adj By performing an OR operation with SR and then inverting it, we obtain the SR after the falling edge correction. adj . Figure 28 (b) (Vertical axis: 5V / division, Horizontal axis: 500ns / division) Verify that the correction circuit is charged to the AND high-level threshold voltage V by RC. IH Correction is performed at 3.5V.

[0209] Depend on Figure 28 (b) It can be seen that the timing compensation Δt adj With RC charging to the high-level threshold voltage V IH The sum of the times is the high-level pulse width of SR.

[0210] The high-level pulse width of SR is:

[0211] (16)

[0212] In equation (16): D = 0.47 (D is the driving duty cycle, the proportion of the high-level pulse width of the SR driving, the actual engineering value of 0.47 is taken to prevent the upper and lower arms from being common to the conductor and to leave a dead time), T is the switching period of the LLC resonant converter, which is inversely proportional to the switching frequency.

[0213] RC charging to high-level threshold voltage V IH The time is:

[0214] (17)

[0215] In equation (17): the adjustable equivalent resistance R = 227.65Ω, the capacitance C = 10nF, and the charging voltage V CC =5V, V IH =3.5V (data can be found in Table 1 and Table 5).

[0216] Then the timing compensation Δt for falling edge hysteresis correction adj for:

[0217] Δt adj =3241.38-2740.6=500.78ns (18)

[0218] As shown in (18), the timing deviation of the falling edge lag of SR can be corrected by the SR falling edge lag correction module circuit, and the timing compensation Δt is corrected. adj =500.78ns.

[0219] 4. Verification of Correction Effect

[0220] The correction effect of this embodiment is as follows: Figure 29 (Vertical axis: 5V / division, horizontal axis: 1μs / division) As shown.

[0221] Depend on Figure 29 It can be seen that the SR output of the correction circuit adj The output has a certain signal delay on both the rising and falling edges, which is caused by the inherent delay characteristics of the correction circuit. SR adj The rising edge delay is caused by the delay of one AND gate, two NAND gates, and one OR gate. adj Rising edge delay time = 4ns (1 AND gate) + 8ns (2 NAND gates) + 4ns (1 OR gate) = 16ns < Δt th =69ns (19)

[0222] SR adj The falling edge delay time is caused by the delays of the discharge tube Q, one AND gate, two NAND gates, one OR gate, circuit bypass switch K4, and precision adjustment unit switch KA. adj Falling edge delay time = 3ns (discharge tube Q) + 4ns (AND gate) + 8ns (2 NAND gates) + 4ns (OR gate) + 3ns (bypass switch K4) + 3ns (precision adjustment unit switch KA) = 25ns (20)

[0223] Therefore SR adj Timing compensation Δt on falling edge adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th :

[0224] Δt' th =|Δt adj -Δt-24|=|500.78-500-24|=23.22ns<Δt th =69ns (21)

[0225] Because Δt adj >Δt and SR adj Falling edge timing precedes SR ref Therefore, when calculating the absolute value, it should be in accordance with (Δt) adj The calculation is performed using -Δt).

[0226] From equations (19) and (21), we can see that: SR adj The timing deviations of both the rising and falling edges meet the set correction threshold Δt. th As required, this embodiment achieves accurate correction of the hysteresis deviation of the falling edge of SR.

[0227] (II) Example of composite type timing deviation correction

[0228] Example 5: Correction of composite deviation of SR "rising edge lag + falling edge lead". This example is for... Figure 5 In the example shown, the deviation of rising edge lag and falling edge lead will cause the SR drive to be too small (with an average deviation of 500ns), the conduction time of the secondary MOS body diode to be too long, the conduction loss to increase significantly, and the converter conversion efficiency to fail to reach the theoretical optimal value.

[0229] 1. Improved triggering and control strategy execution.

[0230] The software selects the corrective action based on the correction type and outputs switch control signals (default closed): closing K1 and K4, opening K2 and K3, and activating the rising edge lag correction module and the falling edge lead correction module (e.g., ...). Figure 30 (As shown); at the same time, the precision adjustment step is executed to regulate the on / off combination of KA~KD in these two modules, and to regulate the adjustable charging resistors of the rising edge lag and falling edge lead precision adjustment units, which are 41.50Ω and 261.39Ω respectively, each matching the 500ns compensation requirement.

[0231] 2. Correction Circuit and Correction Process

[0232] In this embodiment, after correcting the rising edge lag of the synchronous rectified signal SR, the signal is directly sent to the falling edge lead correction module for further correction. The corrected SR... adj It is sent to the synchronous rectifier power device. The circuit is essentially a cascaded implementation of a typical single-type rising edge lag correction module and a falling edge lead correction module in series. Therefore, its correction circuit, device parameters and correction process are completely consistent with the typical single type.

[0233] 3. Verification of Correction Effect

[0234] The correction effect of this embodiment is as follows: Figure 31 (Vertical axis: 5V / division, horizontal axis: 2μs / division). From... Figure 31 The waveform shows that: Figure 31 The waveforms at points A and B represent the actual synchronous rectified signal SR; the waveform at point C is an intermediate processed waveform with only the rising edge of SR lag correction applied; the waveforms at points D and E represent the SR obtained after applying both rising edge lag correction and falling edge lead correction. adj Waveform.

[0235] Figure 31 Δt adj1 Δt adj2 These are the intermediate processing waveforms at point C and SR, SR adjThe timing correction deviation is due to the fact that the correction circuit is exactly the same as that of a typical single type, therefore Δt adj1 =508.1ns, Δt adj2 =499.65ns; Δt1 and Δt2 are the inherent delay of the falling edge of the rising edge lag correction circuit and the inherent delay of the rising edge of the falling edge lead correction circuit, respectively, with values ​​of Δt1=12ns and Δt2=12ns; in addition, there are also inherent hardware delays in the circuit, namely the inherent delay of the rising edge of the rising edge lag correction circuit = 21ns and the inherent delay of the falling edge of the falling edge lead correction circuit = 24ns. The above data are the correction data for the corresponding typical single-type module.

[0236] Depend on Figure 31 SR in adj Waveform comparison shows that SR adj Rising edge timing compensation Δt adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th :

[0237] Δt' th =|Δt adj1 -Δt-Δt2-21ns|=|508.1-500-12-21|=24.9ns<Δt th =69ns(22)

[0238] SR adj Falling edge timing compensation Δt adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt'' th :

[0239] Δt'' th =|Δt-Δt adj2 -Δt1-24ns|=|500-499.65-12-21|=32.65ns<Δt th =69ns(23)

[0240] From (22) and (23), we can see that: SR adj The timing deviation corrections all meet the set correction threshold Δt. th As required, this embodiment achieves accurate correction of timing deviations in SR composite types.

[0241] (III) Efficiency Improvement Verification Examples

[0242] Example 6: This example is for Figure 2The LLC circuit resonant converter (switching frequency 145kHz, bus voltage 400V) uses CREEC3M0015065K SiCMOSFET as the synchronous rectification power device. Taking the single typical timing deviation scenario of "rising edge lag deviation" as an example, the efficiency improvement effect of the timing correction scheme of this invention on the synchronous rectification stage is quantitatively verified.

[0243] 1. Core parameters of synchronous rectifier power devices

[0244] According to the 2020-10-3 version datasheet of C3M0015065K, the unified dynamic / static testing standards are: synchronous rectification operating current I = 55.8A, and operating ambient temperature T. C =25℃, driving voltage V GS Voltage (drive low level voltage / drive high level voltage) = -4 / 15V, V R =400V, refers to the device test Q. rr The reverse voltage of the body diode at the specified time, and Figure 2 The bus voltage of the LLC resonant converter is 400V, and its specific parameters are shown in Table 6. The parameter values ​​in Table 6 are the basis for the quantitative calculation of efficiency improvement.

[0245] Table 6 Core parameters of the synchronous rectifier power device CREEC3M0015065K

[0246]

[0247] 2. Efficiency Improvement Quantitative Calculation

[0248] (1) Before correction: E: Total energy loss of diodes in the synchronous rectifier body during the synchronous rectifier tube in a single cycle during the Δt time period. loss-D

[0249] The deviation duration Δt = 500 ns, during which the internal diode performs rectification and freewheeling functions, while the internal MOSFET does not participate in rectification. The total energy loss of the diode per cycle is E. loss-D Forward conduction energy loss E loss-D-on With reverse recovery energy loss E loss-D-rr sum.

[0250] Energy loss E during forward conduction of the internal diode loss-D-on :

[0251] (twenty four)

[0252] The reverse recovery energy loss E of the internal diode loss-D-rr :

[0253] (25)

[0254] From equations (23) and (25), we can see that:

[0255] E loss-D =E loss-D-on +E loss-D-rr =145080+102000=247080nJ (26)

[0256] (2) Before correction: Total energy loss E of synchronous rectifier diode body MOS in a single cycle during non-Δt period loss-MOS

[0257] Because the proposed technical solution is a strategy to optimize synchronous rectification, the operating range outside the deviation time Δt is assumed to be synchronous rectification operation of the MOS transistor itself. Figure 4 As shown in (b). Therefore, E in the non-Δt time period. loss-MOS The total energy loss E during a single-cycle conduction in non-Δt time periods loss-MOS-on and the total energy loss E of a single-cycle switch loss-MOS-SW composition.

[0258] Before correction: Total energy loss E of the MOS single-cycle conduction during non-Δt periods loss-MOS-on :

[0259] (27)

[0260] In equation (27), the high-level pulse width TD = Δt time period + non-Δt time period, and TD = 3241.38ns can be found from equation (16).

[0261] Before correction: Total energy loss E of the synchronous rectifier diode body MOS in a single cycle during non-Δt periods loss-MOS :

[0262] E loss-MOS-SW =E ON +E OFF =240+360=600μJ=600000nJ (28)

[0263] From equations (27) and (28), it can be seen that the total energy loss E of the synchronous rectifier diode body MOS in a single cycle during the non-Δt period is... loss-MOS :

[0264] E loss-MOS =E loss-MOS-on +E loss-MOS-SW =150573+600000=750573nJ (29)

[0265] (3) Before correction: Total energy loss E of synchronous rectifier power devices in a single cycle loss

[0266] From equations (26) and (29), we can see that:

[0267] E loss =E loss-D +E loss-MOS =247080+750573=997653nJ (30)

[0268] (4) Corrected: Total energy loss E' of synchronous rectifier power device in a single cycle during the Δt period loss-Δt

[0269] The proposed technical solution is based on the premise of not changing the original synchronous rectification control strategy. The synchronous rectification power device only changes energy during the Δt period and does not change energy during non-Δt periods. Therefore, only the energy change before and after the correction during the Δt period is considered, which is to optimize the total energy loss of the synchronous rectification power device in a single cycle.

[0270] Data from Equation (10) on the rising edge hysteresis correction effect in Example 2: Timing compensation Δt adj The absolute value of the difference between the timing deviation Δt and the time deviation Δt is Δt' th Given that the diode conducts for 12.9 ns, the MOS conducts for 12.9 ns during the Δt period, and the MOS conducts for 500 - 12.9 = 487.1 ns.

[0271] Corrected: Energy loss E' during forward conduction of the diode in the body during time period Δt loss-D-on :

[0272] (31)

[0273] Corrected: Total energy loss E' of the MOS single-cycle conduction during the Δt period loss-MOS-on :

[0274] (32)

[0275] From equations (31) and (32), we can see that:

[0276] E' loss-Δt =E' loss-D-on +E' loss-MOS-on =3743+22750=26493nJ (33)

[0277] (5) Before and after correction: Optimization of total energy loss ΔE of synchronous rectifier power device per cycle loss

[0278] Combining the calculation results of equations (23) and (33), we can see that:

[0279] ΔE loss =E loss-D-on -E' loss-Δt =145080-26493=118587nJ (34)

[0280] (6) Corrected: Total energy improvement efficiency η of synchronous rectifier power devices in a single cycle Δ

[0281] The proposed technical solution does not change the original system's synchronous rectification control strategy, but optimizes the loss by adjusting ΔE. loss Compared with the total energy loss per cycle before correction E loss By comparing losses, the improved single-cycle total energy efficiency η of the corrected synchronous rectifier power device is obtained. Δ .

[0282] From equations (30) and (34), we can see that:

[0283] η Δ =ΔE loss / E loss =118587 / 997653≈12% (35)

[0284] This embodiment uses the "rising edge lag deviation" scenario and employs the C3M0015065K synchronous rectifier power device. Based on its core parameters and combined with the data from the aforementioned timing correction embodiment, the efficiency improvement of this technical solution is quantitatively analyzed from the perspective of single-cycle energy loss, and the efficiency improvement is approximately 12%.

[0285] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0286] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

[0287] This invention is not limited to the preferred embodiment described above. Anyone inspired by this invention can derive other forms of synchronous rectified signal timing adaptive correction device and method. All equivalent changes and modifications made within the scope of the claims of this invention shall fall within the scope of this invention.

Claims

1. A timing adaptive correction device for synchronous rectified signals, characterized in that: Connected in series between the output of the synchronous rectification control strategy and the synchronous rectification power device, it includes a software control unit and a hardware correction circuit; The software control unit is used to detect the edge timing deviation of the actual drive signal output by the synchronous rectification control strategy relative to the ideal synchronous rectification reference signal, determine the type and amount of the edge timing deviation, and generate a correction control signal. The input terminal of the hardware correction circuit receives the actual drive signal, the control terminal receives the correction control signal, and the output terminal outputs the corrected drive signal to the synchronous rectifier power device. The hardware correction circuit includes multiple timing correction modules, each corresponding to a different edge timing deviation type. Each timing correction module includes an RC delay unit and a logic gate output unit. The RC delay unit includes a charging resistor, a charging capacitor, and a base path resistor that provides a continuous charging path for the charging capacitor. The logic gate output unit is provided with a signal input terminal and a threshold detection terminal. The signal input terminal receives the actual driving signal or its derived logic signal, and the threshold detection terminal is connected to the common node of the charging resistor and the charging capacitor. The logic gate output unit is used to switch the output state when the voltage of the charging capacitor reaches its input threshold. The hardware correction circuit responds to the correction control signal, activates the timing correction module corresponding to the edge timing deviation type, and adjusts the resistance value of the charging resistor in the corresponding timing correction module so that the time for the voltage of the charging capacitor to charge from the initial state to the input threshold matches the deviation amount, thereby completing the timing correction of the actual drive signal.

2. The synchronous rectified signal timing adaptive correction device according to claim 1, characterized in that: The timing correction module includes four functionally independent units, which correspond to four edge timing deviation types of synchronous rectification drive signals: rising edge leading, rising edge lagging, falling edge leading, and falling edge lagging. The four timing correction modules adopt a modular design of being cascaded in series. Each timing correction module is connected in parallel with a bypass switch. When the bypass switch is closed, the corresponding timing correction module is bypassed and does not participate in signal processing. When the bypass switch is open, the corresponding timing correction module is put into operation. By controlling the on / off combination of each bypass switch, directional correction of single or compound edge timing deviations can be achieved.

3. The synchronous rectified signal timing adaptive correction device according to claim 1, characterized in that: The charging resistor of the RC delay unit adopts a resistor adjustment array architecture. The resistor adjustment array is composed of a basic path resistor and a fixed resistor independently controlled by a multiplexer connected in parallel. By controlling the on and off combinations of the multiplexer, multiple independent and non-repeating equivalent resistances are formed.

4. The synchronous rectified signal timing adaptive correction device according to claim 3, characterized in that: The timing correction module that adapts to timing deviations of rising edge lead and falling edge lead has a multi-way switch of its resistor adjustment array that is normally closed by default, and the equivalent resistance of the charging resistor is at its minimum value, corresponding to the minimum level of the lead correction. The timing correction module is adapted to timing deviations of rising edge lag and falling edge lag. Its resistor adjustment array multiplexer is normally open by default, the equivalent resistance of the charging resistor is at its maximum value, and the corresponding lag correction range is at its minimum level.

5. The synchronous rectified signal timing adaptive correction device according to claim 1, characterized in that: The RC delay unit also includes a discharge switch in parallel with the charging capacitor. The discharge switch is turned on when the synchronous rectification drive signal is low, so that the charging capacitor discharges quickly and prepares for timing correction in the next switching cycle. The basic path resistor is used to avoid loop disturbances during the switching process and improve the working stability of the RC charging and discharging circuit.

6. The synchronous rectified signal timing adaptive correction device according to claim 2, characterized in that: The timing correction module corresponding to the rising edge lead timing deviation is the basic correction module, and its logic gate output unit adopts AND gate logic circuit. The timing correction module for rising edge lag timing deviation adds NAND gate logic circuits and OR gate logic circuits to the basic correction module. The timing correction module for falling edge lead timing deviation adds two NAND gate logic circuits to the basic correction module. The timing correction module for falling edge lag timing deviation adds two NAND gate logic circuits and one OR gate logic circuit to the basic correction module. The logic inversion function in the timing correction module is implemented by shorting the two input terminals of the 2-input NAND gate logic circuit to form an equivalent NOT gate.

7. The synchronous rectified signal timing adaptive correction device according to claim 1, characterized in that: The software control unit has a preset correction threshold. The software control unit compares the detected edge timing deviation with the correction threshold, and generates a correction control signal only when the timing deviation is greater than the correction threshold. After adjusting the resistance value of the charging resistor in the corresponding timing correction module, the software control unit verifies whether the absolute value of the difference between the timing compensation amount and the timing deviation is less than or equal to the correction threshold. If it does not meet the requirement, the resistance value of the charging resistor is readjusted until the requirement is met, thus forming a closed-loop adaptive correction.

8. A synchronous rectified signal timing adaptive correction system, characterized in that, It includes a synchronous rectification control strategy module, a synchronous rectification power device, and a synchronous rectification signal timing adaptive correction device as described in any one of claims 1 to 7; The synchronous rectification signal timing adaptive correction device is connected in series between the output of the synchronous rectification control strategy module and the synchronous rectification power device. It is used to correct the timing of the drive signal output by the synchronous rectification control strategy module and then output it to the synchronous rectification power device.

9. A method for adaptive timing correction of synchronous rectified signals, characterized in that, Includes the following steps: The edge timing deviation of the actual drive signal output by the synchronous rectification control strategy relative to the ideal synchronous rectification reference signal is detected, and the type and amount of the edge timing deviation are determined. A correction control signal is generated based on the type and amount of the edge timing deviation; Based on the correction control signal, the timing correction module corresponding to the edge timing deviation type is activated, and the resistance value of the charging resistor in the corresponding timing correction module is adjusted so that the time for the voltage of the charging capacitor in the timing correction module to charge from the initial state to the input threshold of the logic gate output unit matches the deviation amount, thereby completing the timing correction of the actual drive signal. The corrected drive signal is output to the synchronous rectifier power device.

10. The synchronous rectified signal timing adaptive correction method according to claim 9, characterized in that, In the process of generating a correction control signal based on the type and amount of the edge timing deviation, the deviation amount of the edge timing deviation is first compared with a preset correction threshold. If the deviation amount is less than or equal to the preset correction threshold, it is determined that no correction is needed, and the initial state of the hardware correction circuit is maintained. If the deviation exceeds the preset correction threshold, a correction control signal will be generated. If the actual driving signal has a composite edge timing deviation, multiple timing correction modules are enabled in series to perform cascaded timing correction on each individual deviation in the composite deviation in turn.

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