A high power pin limiter

Abstract

The application provides a high-power PIN limiter, which adopts a three-stage limiting structure, and all the three-stage limiting structures adopt a diode string in reverse parallel connection; four groups of three diodes in series and in reverse parallel connection are adopted in the first stage, so that the high-power resistance of the limiter can be obviously improved, and the I layer thickness of the PIN tube in the first stage is the thickest, so that the limiter has higher resistance power. The microstrip line is combined with the PIN tube in reverse parallel connection, so that the L-band high-power limiter with excellent comprehensive performance is realized.

Description

Technical Field

[0001] This invention relates to the field of radio frequency microwave, specifically to a high-power PIN limiter. Background Technology

[0002] With the rapid development of microwave technology, the demand for high-power microwave devices in electronic systems such as radar, television broadcasting, and communications is increasing, leading to more prominent electromagnetic protection issues. The PIN limiter, as one of the core components for electromagnetic protection, is mainly used to prevent high-power microwave signals from damaging the receiver. When the input signal power is low, the PIN limiter hardly attenuates the signal; however, when the input power increases to a certain level, the limiter rapidly increases the attenuation, limiting the output signal amplitude within a certain range so that it does not rise further with increasing input power.

[0003] PIN limiters are widely used in radar receiver front-ends and various wireless communication systems. They are typically located between the antenna and subsequent devices to protect power-sensitive critical components such as low-noise amplifiers and mixers from damage caused by large signals. Simultaneously, they must possess good impedance matching characteristics to achieve low insertion loss and noise, ensuring that the RF front-end's reception performance for small signals is not affected.

[0004] PIN passive limiters primarily rely on the conductivity modulation effect of PIN diodes to achieve their limiting function. Their impedance varies with the input signal power: when the input power is below the limiting threshold, the microwave signal can reach the load with low loss through the transmission line; once the input power exceeds this threshold, the PIN diode quickly conducts, the impedance drops, causing circuit mismatch, and most of the incident signal is reflected back to the source, thus achieving the limiting purpose.

[0005] Traditional PIN passive limiters typically employ a single-transistor cascaded structure, with the two stages connected via a quarter-wavelength transmission line. The front-end usually uses a PIN diode with a thicker intrinsic I-layer to improve power handling capability; the rear-end uses a PIN diode with a thinner I-layer to improve response speed and sensitivity. This structure offers advantages such as simplicity, small size, fast response, and no need for an external power supply. However, traditional passive limiter circuits also have significant drawbacks: the inherent parasitic capacitance of the PIN diode severely limits the operating bandwidth of the limiter, making it difficult for traditional cascading methods to achieve a good balance between high power handling capability, low insertion loss, and other performance characteristics. Summary of the Invention

[0006] This invention proposes a high-power PIN limiter to address the problems mentioned in the background section. The technical solution provided by this invention is as follows:

[0007] A high-power PIN limiter comprises a first microstrip line L1, a second microstrip line L2, a third microstrip line L3, and a fourth microstrip line L4 connected in series to form a main radio frequency path. The first-stage limiting structure consists of four pairs of anti-parallel diode strings N1, N2, N3, and N4 connected between the first microstrip line L1 and the second microstrip line L2. The second-stage limiting structure consists of a pair of anti-parallel diode strings N5 connected between the second microstrip line L2 and the third microstrip line L3. The third-stage limiting structure consists of a pair of anti-parallel diode strings N6 connected between the third microstrip line L3 and the fourth microstrip line L4, wherein the number of diodes is N1=N2=N3=N4≥N5≥N6.

[0008] Preferably, the I-region of diodes N1, N2, N3, and N4 is the thickest.

[0009] Preferably, all of the diodes are elliptical junction PIN diodes.

[0010] Preferably, the die size of the second-stage limiting structure diode is the largest, followed by the die size of the first-stage limiting structure diode, and the die size of the third-stage limiting structure diode is the smallest.

[0011] Preferably, the size of the first-stage limiting diode is 40μm×15μm, the size of the second-stage limiting diode is 45μm×17μm, and the size of the third-stage limiting diode is 20μm×15μm.

[0012] Preferably, the third microstrip line L3 is the longest, followed by the second microstrip line L2, then the first microstrip line L1, and the fourth microstrip line L4 is the shortest.

[0013] Preferably, the diode strings N1, N2, N3 and N4 of the first-level limiting structure each include six diodes connected in series, the diode string N5 of the second-level limiting structure includes two diodes connected in series, and the diode string N6 of the third-level limiting structure includes two diodes connected in series.

[0014] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: The present invention adopts a three-stage limiting structure. The first-stage, second-stage, and third-stage limiting structures respectively adopt four pairs, one pair, and one pair of anti-parallel diode strings. The three-stage collaborative design of thick I-zone front-stage triggering, large-die mid-stage power handling, and small-die final-stage fine protection enables the limiter to achieve overall optimization in multiple key indicators such as peak power capacity, average power capacity, response speed, and insertion loss, reflecting a high degree of technical complexity and innovation. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0016] Figure 1 This is a structural diagram of a PIN limiter;

[0017] Figure 2 A schematic diagram of the simulation and testing of the PIN limiter;

[0018] Figure 3 A graph showing the limiting characteristics of a PIN limiter;

[0019] Figure 4 The figure shows the insertion loss test results for the PIN limiter.

[0020] Figure 5 The image shows the echo test results for the PIN limiter.

[0021] Figure 6 The figure shows the transient simulation results of the PIN limiter;

[0022] Figure 7 It is a PIN limiter back pattern. Detailed Implementation

[0023] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0024] Unless otherwise stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0025] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] It should be noted that similar symbols and letters in the following figures represent similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0029] This application discloses a high-power PIN limiter. Figure 1 This is a schematic diagram of a structural embodiment, including a first microstrip line L1, a second microstrip line L2, a third microstrip line L3, and a fourth microstrip line L4, a first-level limiting structure, a second-level limiting structure, and a third-level limiting structure. The first microstrip line L1, the second microstrip line L2, the third microstrip line L3, and the fourth microstrip line L4 are connected in series to form the main transmission path. The first-level limiting structure is connected between the first microstrip line L1 and the second microstrip line L2, the second-level limiting structure is connected between the second microstrip line L2 and the third microstrip line L3, and the third-level limiting structure is connected between the third microstrip line L3 and the fourth microstrip line L4.

[0030] The input port of the first microstrip line L1 is the signal input terminal of the entire limiter, and the output terminal is connected to the first-stage limiting structure. By changing the length and width of the first microstrip line L1, the data impedance can be adjusted, thereby adjusting the input return loss. The first microstrip line L1 is 394μm long and 30μm wide. The second microstrip line consists of three microstrip lines: the first segment is 20μm long and 30μm wide; the second segment is a tapered microstrip line, 50μm long, 30μm wide on the left and 20μm wide on the right; and the third segment is 362μm long and 20μm wide. The third microstrip line consists of seven segments. The first segment is 133 μm long and 20 μm wide; the second segment, perpendicular to the first, is 110 μm long and 20 μm wide; the third segment, perpendicular to the second, is 50 μm long and 20 μm wide; the fourth segment, perpendicular to the third, is 200 μm long and 20 μm wide; the fifth segment, perpendicular to the fourth, is 50 μm long and 20 μm wide; the sixth segment, perpendicular to the fifth, is 100 μm long and 20 μm wide; and the seventh segment, perpendicular to the sixth, is 100 μm long and 20 μm wide. The six corners are connected by 20 μm wide chamfered microstrip lines. The fourth microstrip line, L4, is 105 μm long and 20 μm wide.

[0031] The third microstrip line L3 is the longest, followed by the second microstrip line L2, then the first microstrip line L1, and the fourth microstrip line L4 is the shortest.

[0032] The first-stage limiting structure consists of four pairs of anti-parallel diode strings N1, N2, N3, and N4, used for primary front-end limiting; the second-stage limiting structure consists of one pair of anti-parallel diode strings N5, used for intermediate-stage limiting; and the third-stage limiting structure consists of one pair of anti-parallel diode strings N6, used for fine-tuning at the end. The number of diodes is N1=N2=N3=N4≥N5≥N6. These structures form a ladder of power processing capability. The closer to the input, the more diodes are connected in parallel and series, and the higher the pulse power that can be withstood, but the more obvious the junction capacitance effect becomes. The closer to the output, the simpler the structure, which aims to perform fast and fine-tuning of leaked low-power signals.

[0033] In practical implementation, the diode in the first-stage limiting structure has the thickest inlet region (I-region). A thicker I-region can withstand higher continuous wave power, protect subsequent circuits, disperse incident current, improve voltage handling capability, and increase heat dissipation area. A thicker I-region also means higher breakdown voltage and power capacity without increasing insertion loss, but the carrier transit time becomes longer, resulting in a slower response. This aligns with the characteristic that the first stage needs to handle high power, with absolute power capacity requirements outweighing speed requirements.

[0034] The diode uses an elliptical junction PIN diode. An elliptical junction PIN diode has a major axis and a minor axis. The major axis determines the effective current path width and heat conduction path of the PIN diode. Maintaining a sufficient major axis dimension ensures the necessary current handling capacity and power tolerance. The minor axis dimension is reduced to actively lower the junction capacitance. The elliptical junction can reduce the junction area while maintaining a certain current capacity, thereby reducing the junction capacitance. This is beneficial for improving response speed and reducing attenuation of high-frequency signal components.

[0035] The second-stage limiting diode has the largest die size. The second stage undertakes the main task of steady-state power dissipation and energy absorption. After the first stage performs initial "coarse limiting" and rapid triggering of the high-voltage pulse, the continuous low-power energy is carried by the second stage.

[0036] The die size of the first-stage limiting structure diode is secondary. The first stage withstands extremely high instantaneous pulse voltage or power, and its performance relies more on the thick I region to improve the breakdown voltage, rather than simply pursuing the largest die area.

[0037] The three-stage limiting diode has the smallest die size. The third stage focuses on high-speed, fine limiting. The smallest die size is designed to minimize junction capacitance, thereby minimizing the impact on signal transmission, i.e., low insertion loss and improving the response speed to residual fast edge signals.

[0038] Figure 2 The diagram shows the simulation and testing structure of a PIN limiter. The limiter was simulated in ADS2021 software for limiting level, insertion loss, return loss, and transient response. The results are as follows. Figure 3 , 4 As shown in Figures 5 and 6, the threshold value of the limiter is related to the forward voltage of the PIN diode, the operating frequency band, and the intrinsic layer width. The limiting level of a single diode is typically around 10 dBm. Here, four pairs of diodes are used in series to control the limiting level to around 14 dBm. Figure 3 As shown, large signals are limited without affecting the loss of small signals.

[0039] Larger diodes allow for greater current per unit area, resulting in more complete conduction and more pronounced limiting characteristics. However, this also introduces new insertion loss issues. To balance the relationship between insertion loss and conduction, after multiple simulations and optimizations, the dimensions of the first-stage limiting diode were determined to be 40μm × 15μm, the second-stage limiting diode to be 45μm × 17μm, and the third-stage limiting diode to be 20μm × 15μm.

[0040] The overall final size of the limiter is approximately 1.55mm × 1.2mm. Small-signal insertion loss is less than -0.21dB, return loss is below -15dB, power withstand capability reaches 80dBm, and the limiting level is less than 14dBm. Due to the thinner final-stage PIN diode and the addition of multiple parallel PIN diodes, the limiter exhibits a signal spike leakage time of only 7ns under pulse signal excitation conditions, and the peak voltage of the spike leakage is not significant. The layout is as follows... Figure 7 As shown, a three-stage limiting structure is adopted. The first-stage, second-stage, and third-stage limiting structures use four pairs, one pair, and one pair of diode strings connected in reverse parallel, respectively. The three-stage collaborative design of thick I-zone front-stage triggering, large-die mid-stage power handling, and small-die final-stage fine protection enables the limiter to achieve overall optimization in multiple key indicators such as peak power capacity, average power capacity, response speed, and insertion loss, reflecting a high degree of technical complexity and innovation.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-power PIN limiter, characterized in that, The first microstrip line L1, the second microstrip line L2, the third microstrip line L3, and the fourth microstrip line L4 are connected in series to form the main RF path. The first-level limiting structure consists of diode strings N1, N2, N3, and N4, with each diode string having the same number of diodes, connected between the first microstrip line L1 and the second microstrip line L2. The second-level limiting structure is diode string N5, with fewer diodes than any of the diode strings in the first-level limiting structure, connected between the second microstrip line L2 and the third microstrip line L3. The third-level limiting structure is diode string N6, with no more diodes than the number of diodes in the second-level limiting structure, connected between the third microstrip line L3 and the fourth microstrip line L4. The diodes in each diode string are connected in reverse parallel between the main path and ground.

2. A high-power PIN limiter according to claim 1, characterized in that, The I-region of the first-stage limiting diode is the thickest.

3. A high-power PIN limiter according to claim 2, characterized in that, All diodes are elliptical junction PIN diodes.

4. A high-power PIN limiter according to claim 3, characterized in that, The die size of the two-stage limiting diode is the largest, followed by the single-stage limiting diode, and the die size of the three-stage limiting diode is the smallest.

5. A high-power PIN limiter according to claim 4, characterized in that, The size of the first-stage limiting diode is 40μm×15μm, the size of the second-stage limiting diode is 45μm×17μm, and the size of the third-stage limiting diode is 20μm×15μm.

6. A high-power PIN limiter according to claim 1, characterized in that, The third microstrip line L3 is the longest, followed by the second microstrip line L2, then the first microstrip line L1, and the fourth microstrip line L4 is the shortest.

7. A high-power PIN limiter according to any one of claims 1-6, characterized in that, The diode strings N1, N2, N3, and N4 of the first-level limiting structure each include six diodes connected in series. The diode string N5 of the second-level limiting structure includes two diodes connected in series. The diode string N6 of the third-level limiting structure includes two diodes connected in series.

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