Method, device and equipment for reducing glitch signal in chip circuit and storage medium

Abstract

The application relates to the technical field of integrated circuits, and provides a method, a device, equipment and a storage medium for reducing a glitch signal in a chip circuit, the method comprising the following steps: analyzing the chip circuit to obtain circuit signals; wherein the circuit signals comprise a flip rate and a fan-out coefficient; based on the flip rate and the fan-out coefficient, identifying and screening a target glitch signal to be optimized from the circuit signals; according to the arrival time of the target glitch signal, selecting a matching target clock signal from at least two kinds of preset control clock signals with different duty cycles; and implanting a clock operation unit controlled by the target clock signal on the path of the target glitch signal to reduce the target glitch signal. The application introduces control clock signals with different duty cycles, and intelligently selects according to the arrival time of the target glitch signal, thereby enhancing the flexibility of the implantation position, and expanding the optimization space and application range of the glitch signal reduction.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to methods, apparatus, devices and storage media for reducing glitches in chip circuits. Background Technology

[0002] Modern digital integrated circuits contain numerous sequential and combinational logic units, which perform functional operations on multiple signals. When the input signals of combinational logic travel along different paths, their arrival times vary. During these operations, brief pulse signals, known as glitch signals, are generated. Glitches produce unnecessary switching, wasting power. Statistics show that power consumption caused by glitch signals typically exceeds 20% of the total chip power consumption, and in some designs, it can even reach 40%. Therefore, effectively reducing glitch signals is crucial.

[0003] Currently, two main methods are used to suppress glitches. The first is buffer insertion, which involves inserting a buffer along the path where the glitch occurs, using its own delay characteristics to filter out narrow glitches. However, the main drawback of this method is that the inserted buffer introduces additional path delay, which has a significant negative impact on the overall timing convergence of the circuit. Its application is limited, especially on timing-critical paths, and its effectiveness is limited.

[0004] The second type is clocking control, which uses logical operations between the signal and the clock to clamp the signal to a fixed level for half a clock cycle, thereby eliminating all glitches within that cycle. This method eliminates a wide range of glitches, but its drawback is that it has extremely strict requirements on the placement of the clock operation unit. Not only does it also introduce timing delays, but improper placement can easily lead to functional errors, posing a high risk to design and verification. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for reducing glitches in chip circuits, in order to solve the technical problem that existing glitches reduction methods are difficult to balance between power consumption, performance, and design reliability, and have a significant impact on timing performance and are unreliable.

[0006] This application provides a method for reducing glitches in a chip circuit, comprising: analyzing the chip circuit to obtain various circuit signals; wherein each circuit signal includes a toggle rate and a fan-out coefficient; identifying and filtering target glitches to be optimized from the various circuit signals based on the toggle rate and fan-out coefficient; selecting a matching target clock signal from at least two preset control clock signals with different duty cycles according to the arrival time of the target glitches; and embedding a clock operation unit controlled by the target clock signal along the path of the target glitches to reduce the target glitches.

[0007] According to the method for reducing glitches in a chip circuit provided in this application, the target glitches to be optimized are identified and screened from each circuit signal based on the flip-flop rate and fan-out coefficient. The method includes: calculating the product of the flip-flop rate and fan-out coefficient in each circuit signal to obtain a priority index; and determining the circuit signals with priority indices higher than a preset threshold as target glitches.

[0008] According to the method for reducing glitches in a chip circuit provided in this application, a matching target clock signal is selected from at least two preset control clock signals with different duty cycles based on the arrival time of the target glitches. The method includes: when the arrival time of the target glitches is in the first half of the clock cycle, selecting a control clock signal with a smaller duty cycle as the target clock signal; when the arrival time of the target glitches is in the second half of the clock cycle, selecting a control clock signal with a larger duty cycle as the target clock signal.

[0009] According to the method for reducing glitches in a chip circuit provided in this application, the method of implanting a clock operation unit controlled by a target clock signal includes: finding an existing buffer on the path of the target glitches and replacing the buffer with a clock operation unit.

[0010] According to the method for reducing glitches in a chip circuit provided in this application, the method of embedding a clock operation unit controlled by a target clock signal includes: if there is no buffer on the path of the target glitches, inserting multiple buffers to filter out the target glitches, and replacing one of the multiple buffers with a clock operation unit.

[0011] According to the method for reducing glitches in a chip circuit provided in this application, after embedding a clock operation unit controlled by a target clock signal on the path of the target glitches to reduce the target glitches, the method further includes: performing timing analysis on the new chip circuit to obtain timing analysis results; if a violation occurs in the timing analysis results, the clock operation unit that caused the violation will be removed from the chip circuit.

[0012] According to the method for reducing glitches in a chip circuit provided in this application, the chip circuit is analyzed to obtain the signals of each circuit, including: obtaining the chip circuit in the input file; performing timing analysis and power consumption analysis on the chip circuit to determine the toggle rate, fan-out coefficient and arrival time of each circuit signal on the timing path.

[0013] This application also provides a device for reducing glitches in a chip circuit, comprising: a circuit analysis module for analyzing the chip circuit and acquiring various circuit signals, wherein each circuit signal includes a toggle rate and a fan-out coefficient; a glitch location module for identifying and filtering target glitches to be optimized from the various circuit signals based on the toggle rate and fan-out coefficient; a duty cycle adjustment module for selecting a matching target clock signal from at least two preset control clock signals with different duty cycles according to the arrival time of the target glitches; and a unit implantation module for implanting a clock operation unit controlled by the target clock signal along the path of the target glitches to reduce the target glitches.

[0014] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a method for reducing glitches in the chip circuit as described above.

[0015] This application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a method for reducing glitches in a chip circuit as described above.

[0016] This application provides a method, apparatus, device, and storage medium for reducing glitches in chip circuits. The method includes: analyzing the chip circuit to obtain various circuit signals, wherein each circuit signal includes a toggle rate and a fan-out coefficient; identifying and filtering target glitches to be optimized from the various circuit signals based on the toggle rate and fan-out coefficient; selecting a matching target clock signal from at least two preset control clock signals with different duty cycles according to the arrival time of the target glitches; and embedding a clock operation unit controlled by the target clock signal along the path of the target glitches to reduce the target glitches. Through this method, this application introduces control clock signals with different duty cycles and intelligently selects them according to the arrival time of the target glitches, enhancing the flexibility of the embedding location, breaking the limitations of timing path insertion, expanding the optimization space and application scope of glitches reduction, and thus improving the reliability of the design. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the flowcharts illustrating the method for reducing glitches in a chip circuit provided in this application embodiment.

[0019] Figure 2 This is a schematic diagram of a chip circuit with a different logic depth than the two-way signals from the door panel provided in this application embodiment.

[0020] Figure 3 Based on Figure 2 The diagram shows a glitch signal generated by the output of the AND gate in the circuit shown.

[0021] Figure 4 This is a circuit diagram illustrating the generation and propagation of glitch signals provided in an embodiment of this application.

[0022] Figure 5 The embodiments provided in this application are based on Figure 4 The timing diagram of the glitch signal propagation in the circuit shown.

[0023] Figure 6 This is a schematic diagram of a circuit for reduction through timing control provided in an embodiment of this application.

[0024] Figure 7 The embodiments provided in this application are based on Figure 6 The timing diagram of the glitch signal propagation in the circuit shown.

[0025] Figure 8 This is a circuit diagram illustrating the effect of high fan-out coefficient glitches on signal propagation, as provided in an embodiment of this application.

[0026] Figure 9 The embodiments provided in this application are based on Figure 8 The circuit diagram shown is a schematic diagram of the circuit after the clock operation unit is installed.

[0027] Figure 10 This is a circuit diagram showing that the source of the glitch signal provided in this application is classified into different categories under different timing paths.

[0028] Figure 11 The embodiments provided in this application are based on Figure 10 The circuit shown is a schematic diagram of a circuit that eliminates glitches in clock signals of different types using different duty cycles.

[0029] Figure 12 This is the second flowchart illustrating the method for reducing glitches in a chip circuit provided in this application embodiment.

[0030] Figure 13 This is a schematic diagram of the structure of the glitch signal reduction device in the chip circuit provided in the embodiments of this application.

[0031] Figure 14 This is a schematic diagram of the physical structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0034] This application provides a method for reducing glitches in chip circuits. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is one of the flowcharts illustrating a method for reducing glitches in a chip circuit according to an embodiment of this application. In this embodiment, the method for reducing glitches in a chip circuit may include steps S110 to S140, and the specific steps are as follows: S110: Analyze the chip circuit and obtain the signals of each circuit; the circuit signals include the toggle ratio and fan-out coefficient.

[0035] By analyzing the chip circuitry, the signals of each circuit can be obtained. Each circuit signal can include the toggle rate and the fanout coefficient.

[0036] The flip-flop ratio reflects how frequently the circuit signal changes per unit time. The more frequently the signal flips, the greater the possibility of glitches and the more dynamic power consumption it will consume. The fan-out ratio reflects the circuit signal's ability to drive multiple loads. The larger the fan-out ratio, the more easily the circuit signal will affect downstream circuits during transmission.

[0037] Alternatively, circuit simulation tools can be used to analyze the chip circuit. Circuit simulation tools can simulate the circuit's operation based on information such as the circuit's topology, component parameters, and input signals, and calculate the relevant characteristics of each signal to obtain circuit signals including the flip-flop rate and fan-out coefficient.

[0038] S120: Based on the flip-flop rate and fan-out coefficient, identify and filter the target glitch signal to be optimized from the signals of each circuit.

[0039] Please refer to Figures 2-3 , Figure 2 This is a schematic diagram of a chip circuit with a different logic depth than the two incoming signals of the door, provided in an embodiment of this application. Figure 3 Based on Figure 2 The diagram shows a glitch signal generated by the output of the AND gate in the circuit shown.

[0040] refer to Figure 2 The chip circuit includes an AND gate Y1 and an OR gate H1. The first input signal n0 of the AND gate Y1 comes directly from the outside with a logic depth of 0; the second input signal n1 of the AND gate Y1 first passes through the OR gate H1 with a logic depth of 1. Due to the inherent propagation delay of the OR gate H1, the n1 signal will inevitably arrive at the AND gate Y1 later than the n0 signal, thus forming a time window during input switching.

[0041] refer to Figure 3 In an ideal zero-delay model, the n2 signal output by AND gate Y1 should have no transient jumps. However, under actual process conditions, when the arrival times of signals n0 and n1 are different, a glitch signal is generated, such as... Figure 3 As shown in the dashed ellipse.

[0042] Processing glitches inevitably incurs additional overhead; therefore, this embodiment also provides an effective filtering mechanism. By setting thresholds for the toggle rate and fan-out coefficient, signals that significantly impact power consumption can be filtered out as target glitches.

[0043] For example, if the toggle rate of a circuit signal exceeds a preset toggle rate threshold, it indicates that the signal changes frequently and has a high probability of generating glitches. Simultaneously, if the fan-out coefficient of the circuit signal also exceeds a fan-out coefficient threshold, it means that the signal drives a large load, and the impact range of the glitches will be larger. Therefore, this circuit signal will be identified as the target glitches signal to be optimized.

[0044] This screening mechanism in this embodiment avoids processing all detected glitch, improving optimization efficiency and reducing unnecessary area and power consumption overhead.

[0045] S130: Select a matching target clock signal from at least two preset control clock signals with different duty cycles, based on the arrival time of the target glitch signal.

[0046] Different target glitch signals appear at different locations on the timing path, i.e., their arrival times are different. Related methods generally use a clock signal with a fixed duty cycle as the control signal, which cannot be flexibly adjusted according to the specific arrival time of the glitch.

[0047] This embodiment pre-sets various control clock signals with different duty cycles. The duty cycle refers to the ratio of the high-level duration of the clock signal to the entire cycle time. By selecting a matching control clock signal based on the arrival time of the target glitch signal, adaptive control of glitch signals with different timing characteristics can be achieved.

[0048] For example, for glitch signals that appear in the first half of the timing path, a control clock signal with a smaller duty cycle can be selected, so that the glitch can be filtered in advance without affecting the normal signal transmission; for glitch signals that appear in the second half of the timing path, a control clock signal with a larger duty cycle can be selected to expand the filtering window and eliminate the glitch more effectively.

[0049] S140: A clock operation unit controlled by the target clock signal is implanted along the path of the target glitch signal to reduce the target glitch signal.

[0050] This embodiment reduces the target glitch signal by embedding a clock operation unit. A clock operation unit is a circuit element that processes an input signal according to a clock signal. The clock operation unit, controlled by the target clock signal, is embedded in the path of the target glitch signal. When the target clock signal is active, the clock operation unit samples and processes the target glitch signal.

[0051] Since the target clock signal is selected based on the arrival time and characteristics of the target glitch signal, the clock operation unit can filter and shape the glitch signal at the appropriate time, eliminating or suppressing it to an acceptable range. This avoids unnecessary charging and discharging of downstream logic units due to glitch signals, thereby reducing dynamic power consumption and improving circuit stability and reliability.

[0052] The present application provides a method for reducing glitches in chip circuits, which comprehensively considers signal characteristics and timing information, and eliminates glitches through intelligent screening and adaptive control. First, the toggle rate and fan-out coefficient of each signal in the chip circuit are analyzed to screen out target glitches that have a significant impact on the total power consumption of the circuit, avoiding blindly processing all glitches and improving optimization efficiency. Then, based on the arrival time of the target glitches, a matching target clock signal is selected from preset control clock signals with different duty cycles. This adaptive selection mechanism breaks the limitations of traditional methods in terms of insertion location and can be flexibly adjusted according to the specific timing characteristics of the glitches. Finally, a clock operation unit controlled by the target clock signal is inserted into the path of the target glitches, using the synchronization effect of the clock signal to filter and shape the target glitches, thereby effectively reducing glitches, lowering dynamic power consumption, and improving circuit performance and reliability.

[0053] The glitch signal reduction method in the chip circuit provided in this application introduces control clock signals with different duty cycles and intelligently selects them according to the arrival time of the target glitch signal. This enhances the flexibility of the implantation location, breaks the insertion limitation of the timing path, expands the optimization space and application scope of glitch signal reduction, and thus improves the reliability of the design.

[0054] In some embodiments, the step of identifying and filtering the target glitch signal to be optimized from each circuit signal based on the toggle rate and fan-out coefficient may specifically include: Calculate the product of the flip rate and fan-out coefficient in each circuit signal to obtain the priority index; identify the circuit signals with priority indices higher than a preset threshold as target glitch signals.

[0055] In this embodiment, the priority index is obtained by multiplying the flip-flop rate by the fan-out coefficient, which can reflect the severity of signal glitches and the impact of glitches on circuit power consumption and performance.

[0056] For example, a signal with a high toggle rate but a small fan-out coefficient may have a high probability of generating glitches, but its impact on the entire circuit may be relatively small due to its limited range of influence. On the other hand, a signal with a moderate toggle rate but a large fan-out coefficient may generate glitches that affect multiple downstream logic units, thus having a greater impact on the circuit.

[0057] Therefore, by calculating the product of the flip rate and the fan-out coefficient, this embodiment can take both factors into account and more accurately assess the potential harm of each signal generating spikes, thereby providing a quantitative indicator for subsequent screening.

[0058] In this embodiment, the preset threshold is a critical value pre-set based on factors such as the specific design requirements of the circuit, power consumption targets, and performance indicators. When the priority index of a circuit signal is higher than this preset threshold, it indicates that the signal is more likely to generate glitches, and the glitches have a more serious impact on the circuit. Therefore, it is identified as the target glitch signal to be optimized.

[0059] The specific value of the preset threshold can be set according to the needs of the actual scenario. For example, in a low-power chip circuit design, to reduce dynamic power consumption, the preset threshold may be set relatively low, thus filtering out more signals that may cause severe glitches for optimization. In a chip circuit design with high performance requirements, the preset threshold may be appropriately increased to process only those glitches that have a significant impact on circuit performance, balancing the cost and effectiveness of optimization. In this way, glitches that have a significant impact on the circuit can be processed in a targeted manner, avoiding unnecessary processing of all signals and improving the efficiency and accuracy of optimization.

[0060] In the above embodiments, by calculating priority indicators and comparing them with preset thresholds, the target glitches that have a significant impact on the total power consumption of the circuit can be accurately screened out. Only these key signals are processed, avoiding blind processing of all signals, thereby greatly improving the efficiency of optimization; and avoiding the implantation of clock operation units in unnecessary signal paths, thereby reducing additional circuit area and power consumption overhead.

[0061] Optionally, the step of identifying circuit signals with priority indicators higher than a preset threshold as target glitch signals may further include: The initial target glitch signal is determined from the signals of each circuit based on the flip rate; The priority index is obtained by calculating the product of the flip rate and the fan-out coefficient in each initial target glitch signal; The initial target glitch signal with a priority index higher than a preset threshold is determined as the target glitch signal.

[0062] In this embodiment, a two-stage screening mechanism is added. First, a preliminary screening is performed based on the flip rate, and then a secondary screening is performed by combining the fan-out coefficient to calculate the priority index. By first narrowing down the scope and then making a precise evaluation, the accuracy of the screening is ensured and the screening efficiency is improved.

[0063] For example, within one cycle of a clock signal, if the toggle rate of the circuit signal is greater than 1 for single-edge triggering, or greater than 2 for double-edge triggering, then the circuit signal is determined to be the initial target glitch signal.

[0064] In some embodiments, the step of selecting a matching target clock signal from at least two preset control clock signals with different duty cycles based on the arrival time of the target glitch signal may specifically include: When the arrival time of the target glitch signal is in the first half of the clock cycle, the control clock signal with a smaller duty cycle is selected as the target clock signal; when the arrival time of the target glitch signal is in the second half of the clock cycle, the control clock signal with a larger duty cycle is selected as the target clock signal.

[0065] Control clock signals with different duty cycles have different timing characteristics and will produce different effects when processing glitch signals. In this embodiment, at least two control clock signals with different duty cycles are preset, which provides multiple possibilities for matching and selecting based on the arrival time of the target glitch signal.

[0066] The arrival position of the target glitch signal within the clock cycle plays a crucial role in selecting an appropriate control clock signal to process the glitch signal.

[0067] For example, when the target glitch signal arrives in the first half of the clock cycle, the circuit may have just completed the previous stage of operation and is in a relatively sensitive and unstable state. A control clock signal with a shorter duty cycle has a shorter high-level duration, enabling a rapid response the instant the glitch appears, suppressing or filtering it with a shorter control time. Simultaneously, because the high-level duration is short, it does not excessively interfere with the transmission of subsequent normal signals, avoiding the circuit remaining in a control state when normal signals arrive, thus preventing disruption to the normal logic of the circuit.

[0068] For example, if the target glitch signal arrives in the latter half of the clock cycle, the circuit may have already completed an operation cycle, and the presence of the glitch may affect the final output. A control clock signal with a large duty cycle has a longer high-level duration, providing sufficient time to adequately process the glitch. A longer control time ensures that the glitch is completely eliminated or suppressed to an acceptable level, guaranteeing the accuracy and stability of the circuit output.

[0069] Optionally, a dedicated monitoring circuit or logic module can be used to track the arrival time of the target glitch signal within the clock cycle in real time and accurately determine whether it is located in the first half or the second half of the clock cycle; based on the monitored arrival time, a matching target clock signal can be selected from at least two control clock signals with different duty cycles according to a preset selection rule.

[0070] It should be noted that when processing control clock signals, the selection rule for control clock signals with smaller duty cycles is as follows, depending on the number of duty cycles: When there are two different duty cycles for the control clock signal, selecting the control clock signal with the smaller duty cycle means selecting the control clock signal with the smallest duty cycle value; when there are three or more different duty cycles for the control clock signal, selecting the control clock signal with the smaller duty cycle means not selecting the control clock signal with the largest duty cycle value.

[0071] Similarly, when processing control clock signals, the selection rule for control clock signals with larger duty cycles is as follows, depending on the number of duty cycles: When there are two different duty cycles in the control clock signal, selecting the control clock signal with the larger duty cycle means selecting the control clock signal with the largest duty cycle value; when there are three or more different duty cycles in the control clock signal, selecting the control clock signal with the larger duty cycle means not selecting the control clock signal with the smallest duty cycle value.

[0072] In some embodiments, the implanted clock operation unit controlled by the target clock signal may include at least one of the following: ① Locate an existing buffer on the path of the target glitch signal and replace the buffer with a clock operation unit; ② If there is no buffer on the path of the target glitch signal, multiple buffers are inserted to filter out the target glitch signal, and one of the multiple buffers is replaced with a clock operation unit.

[0073] This embodiment introduces two processing methods for implanting clock operation units: First, search for an existing buffer in the transmission path of the target glitch signal; if found, replace the buffer with a clock operation unit. Second, if no buffer is found in the transmission path of the target glitch signal, insert multiple buffers to initially filter out the target glitch signal, and then select one of these buffers to replace it with a clock operation unit. The two methods are described in detail below: ① Replace the existing buffer At least one buffer is already located on the transmission path of the target glitch signal. Under the specific control of the target clock signal, the clock operation unit processes the passing target glitch signal, such as shaping and filtering the glitch signal according to the high and low level changes of the target clock signal, to remove abnormal pulses and make the signal more in line with the normal logic requirements of the circuit.

[0074] Replacing existing buffers utilizes existing circuit element locations, eliminating the need for additional wiring and component installation space, thus reducing hardware costs and design complexity.

[0075] ②Insert the buffer first, then replace it. If there is no buffer on the target glitch signal path, multiple buffers are inserted first. Buffers themselves have signal delay and filtering characteristics; multiple buffers connected in series can initially smooth and filter out the target glitch signal, reducing its amplitude and width. Then, one of the buffers is replaced with a clock operation unit, using the target clock signal to further refine the initially processed glitch signal. Through more precise control logic, residual glitches are further eliminated, ensuring the stability and accuracy of the final output signal.

[0076] Both methods minimize large-scale modifications to the existing circuitry. Replacing an existing buffer involves replacing only one component, having minimal impact on other circuit sections. Furthermore, it allows the clock operation unit to operate directly at critical points in the glitch signal transmission path, promptly processing the glitch and preventing its further propagation that could affect subsequent circuits, thus improving the timeliness and effectiveness of glitch handling. Inserting the buffer first and then replacing it only involves a moderate extension of the existing path. These minor modifications allow the new glitch handling scheme to be better compatible with the existing circuitry. Combining the initial filtering by the buffer with the precise processing by the clock operation unit enables more comprehensive and in-depth processing of glitch signals. Compared to a single processing method, this approach more effectively eliminates glitches, improving signal quality and circuit reliability.

[0077] In some embodiments, for paths with tight timing margins, a buffer can be found on the second half of the cycle path where the glitch signal appears and replaced with a clock operation unit; for paths with loose timing margins and no buffers on the second half of the cycle path, multiple buffers can be inserted first to filter out the glitch signal, and then the buffers on the second half of the cycle path can be replaced with clock operation units.

[0078] Timing margin refers to the difference between the actual propagation time of a signal from the origin to the receiver in a circuit and the maximum allowable propagation time required by the design. A tight timing margin means that the signal propagation time is close to or has exceeded the maximum allowable time, which may lead to timing violations and affect the normal operation of the circuit. A loose timing margin indicates that there is sufficient time leeway for signal propagation, allowing for appropriate signal processing without affecting the circuit timing.

[0079] The propagation path of a glitch signal in a circuit can be divided into the first half-cycle and the second half-cycle. The clock operation unit is controlled by the target clock signal and can perform filtering, shaping, and other processing on the glitch signal.

[0080] When timing margins are tight in a circuit path, it's crucial to minimize any additional impact on signal propagation time. To address this, a buffer can be located in the latter half of the cycle where the glitch signal occurs, and replaced with a clock operation unit. Since buffers inherently introduce signal delay, replacing them with a clock operation unit, while adding glitch handling capabilities, allows the operation to occur in the already timing-critical latter half of the cycle. Furthermore, utilizing the buffer's existing location avoids interference with critical timing in the first half of the cycle. This approach maintains the original timing relationships to the greatest extent possible while handling glitches, ensuring the circuit functions correctly even under tight timing conditions. Moreover, this method fully utilizes existing buffer locations, reducing additional wiring and component installation, thus lowering costs and design complexity.

[0081] When the timing margin of the path is not tight, there is more time for glitch handling. If there is no buffer in the latter half of the cycle, multiple buffers can be inserted first to initially filter out glitch signals. The delay and filtering characteristics of the buffers can smooth and suppress glitch signals to a certain extent. Then, one of the buffers is replaced with a clock operation unit to achieve more precise glitch handling. This method of initial buffer processing followed by precise control by the clock operation unit not only effectively eliminates glitch and improves signal quality without affecting circuit timing, but also reuses the initial filtering function of the buffers, avoiding the use of a large number of dedicated glitch handling circuits, thereby reducing hardware costs and design complexity.

[0082] Both of these approaches make the best use of existing circuit structures and components, and perform different processing based on different timing margins. This achieves an effective balance between timing optimization and glitches handling, while also utilizing existing circuit structures and components, thereby reducing costs and complexity.

[0083] In related circuit design, methods for reducing glitches mainly fall into the following two categories: (1) Timing of input signals for balanced combinational logic gates These methods aim to minimize the arrival time differences of logic gate input signals. For example, clock skew can be used to optimize the arrival time of different clock signals by rationally planning the phase relationship between them; and gate sizing can be used to change the physical size of the logic gate to adjust its delay characteristics, thereby making the arrival times of the logic gate input signals more similar.

[0084] (2) Insert a circuit in the glitch signal path to block propagation. This includes, but is not limited to, latch / buffer insertion, gate-level freezing, and clocking control.

[0085] For example, in buffer insertion, this method involves inserting a buffer at the location where the glitch occurs. When the glitch width is less than a certain percentage of the buffer cell delay, these narrow glitches will be filtered out due to the capacitive nature of the buffer itself. Taking a certain process as an example, inserting a buffer with a cell delay of 15 ps can filter out narrow glitch widths of less than 10 ps. However, inserting a buffer introduces additional timing delay, which has a significant negative impact on the timing convergence of the circuit, thus limiting its effectiveness in reducing glitch signals.

[0086] For example, in clock control, this method performs an AND / OR operation on the signal and the clock signal, forcibly clamping the signal value to 0 or 1 for the first half of the clock cycle, thereby eliminating glitches within that cycle. This method requires the introduction of a clock operation unit, such as a NAND gate, which can eliminate glitches within half a clock cycle. For instance, in a circuit operating at 1GHz using a certain process, the clock-controlled NAND gate has a delay of approximately 8ps, yet it can eliminate glitches within a range of 500ps (i.e., 1 / 2 clock cycle). However, its drawback is also significant: the clock operation unit must be precisely placed in the latter half of the timing path. Doing so not only introduces additional timing delays, but incorrect placement can also lead to circuit malfunctions.

[0087] Based on this, the present application provides a method for reducing glitches in a chip circuit. For paths with tight timing margins, a buffer is found in the second half of the cycle of the path where the glitches occur and replaced with a clock operation unit. For paths with ample timing margins and no buffer in the second half of the cycle, multiple buffers are inserted to filter out the glitches, and the buffer in the second half of the cycle is replaced with a clock operation unit.

[0088] However, inserting either a buffer or a clock operation unit controlled by a clock introduces additional overhead. To address this, this embodiment proposes a corresponding strategy: firstly, identifying cells with large glitches and large fanouts, and assessing the range that glitches can cover by reducing these locations; secondly, adding a checker process to perform timing checks on the path after inserting the clock operation unit to ensure the correctness of the circuit timing.

[0089] In an exemplary gate-level simulation process, it can be observed that the distribution range of the glitches is mostly concentrated within half a clock cycle, and mainly close to the first half of the cycle, indicating a slight delay.

[0090] Please see Figures 4-5 , Figure 4 This is a circuit diagram illustrating the generation and propagation of glitch signals provided in an embodiment of this application. Figure 5 The embodiments provided in this application are based on Figure 4 The timing diagram of the glitch signal propagation in the circuit shown.

[0091] Five combinational logic units are connected between two flip-flops (FF). Flip-flops are the basic storage units in digital circuits. Their core function is to capture and stably store a binary data (0 or 1) at a specific moment until the next specific moment arrives.

[0092] S0 is the output node of the first flip-flop, S1 is the output node of combinational logic 1, S2 is the output node of the second combinational logic 2, S3 is the output node of combinational logic 3, S4 is the output node of combinational logic 4, and S5 is the output node of combinational logic 5. Combinational logic 3 is the main source of glitches, and the glitches it generates propagate to downstream combinational logic 4 and combinational logic 5. During propagation, the glitches typically worsen gradually; for example, the length of the glitches window in S5 is greater than the length of the glitches window in S3. Therefore, there are relatively low glitches before combinational logic 3, which can be considered a normal power consumption state; and there are higher glitches after combinational logic 3, i.e., an abnormal power consumption state.

[0093] Please see Figures 6-7 , Figure 6 This is a schematic diagram of a circuit for reduction via timing control provided in an embodiment of this application. Figure 7 The embodiments provided in this application are based on Figure 6 The timing diagram of the glitch signal propagation in the circuit shown.

[0094] Based on the observation that glitches mostly occur within half a clock cycle, the clock control strategy of this application clamps the glitches to logic values ​​"0" or "1" by performing specific logical operations between the signal with a higher frequency of glitches and the clock signal. Under the assumption that the probability of the signal taking the value "0" and "1" is 50%, the number of toggle operations of the signal within half a cycle can be effectively reduced to an average of about 0.5 times, thereby significantly reducing the impact of glitches.

[0095] like Figure 6 As shown, an OR gate is used as the clock operation unit, corresponding to the cases where the OR gate is inserted into the first and second half of the timing path, respectively. It is worth noting that this strategy only introduces a single cell delay (approximately 10 ps) generated by the OR gate into the timing path, which is effective in handling glitches on the order of half a clock cycle (Tck / 2) under a specific process technology. Under this process technology, the time cycle is approximately 500 ps, ​​and the clock frequency is 1 GHz. Therefore, compared to ordinary buffer insertion techniques that can only filter out glitches in the range of approximately 7-8 ps under this process technology, the strategy in this embodiment significantly improves the glitch filtering effect.

[0096] This embodiment also provides clock control scenarios for the first and second half of the OR gate insertion timing path, respectively.

[0097] Assume the arrival time of the signal at the insertion position is Tarrival, and the signal flip time caused by the glitch removal operation is Tck / 2+dor, where dor is the unit delay generated by the OR gate, which is usually much smaller than half a clock cycle Tck / 2.

[0098] When the OR gate insertion position is in the first half of the timing path, Figure 6 Taking the insertion after combinational logic 3 as an example, after introducing a clock control strategy through an OR gate, the actual signal arrival time of node s3 becomes max(Tarrival,Tck / 2+dor)=Tck / 2+dor. Although this strategy can completely eliminate glitches at node s3, it inevitably introduces an additional signal delay τ=Tck / 2+dor-Tarrival. This additional delay has a certain impact on timing.

[0099] When the OR gate insertion position is in the second half of the timing path, Figure 6 Taking the insertion after the S4 timing sequence as an example, after introducing the clock control strategy, the actual signal arrival time of the S4 node is max(Tarrival,Tck / 2+dor)=Tarrival. This shows that although the strategy can only partially eliminate glitches at the S4 node, it does not introduce additional signal delay.

[0100] Where s'3 and s'4 represent the output nodes after the OR gate, respectively. CK and CKS both represent clock signals.

[0101] Based on the above embodiments, the embodiments of this application are further optimized and improved to solve the following problems: 1. Find a suitable position in the second half of the timing path to insert the clock operation unit, thereby better optimizing the circuit signal timing and improving system performance.

[0102] 2. Find a suitable position in the first half of the timing path to insert the clock operation unit without introducing additional delay, so as to ensure the efficiency and accuracy of signal processing.

[0103] 3. A strategy to minimize the number of clock operation units inserted while achieving the same glitch signal reduction effect.

[0104] The higher the fan-out factor of a glitching signal, the greater its impact on downstream circuits. Please refer to [link / reference]. Figures 8-9 , Figure 8 This is a circuit diagram illustrating the effect of high fan-out coefficient glitches on signal propagation, provided in an embodiment of this application. Figure 9 The embodiments provided in this application are based on Figure 8 The circuit diagram shown is a schematic diagram of the circuit after the clock operation unit is installed.

[0105] It can be seen that among the three timing paths, the fan-out coefficient of the glitch signal generated by combinational logic 3 is relatively large, thus affecting the other two timing paths as well. Figure 8 As shown.

[0106] This application provides a method for reducing glitches. After implanting a clock operation unit with selectable duty cycle, multiple timing paths can be optimized, with the following effect: Figure 9 As shown.

[0107] To better illustrate this implementation plan, the following details are provided: Step 1: Adjust the clock signal duty cycle.

[0108] In this embodiment, the clock signal used for clock control is adjusted from a conventional signal to a clock cycle signal with a different duty cycle.

[0109] Step 2: Design data input and analysis.

[0110] Input the netlist, standard parasitic parameter file (SPEF), design constraint file (SDC), and waveform file of the circuit to be designed. Use professional analysis tools to perform a comprehensive timing and power analysis of the design. During the analysis, focus on extracting key parameters for all signals (nets), including toggle rate, fanout, and delay (Tdelay) in the timing path.

[0111] Step 3: Determine the burr signal.

[0112] The signal's flip-flop rate is used to determine whether it is a glitch signal. For single-edge triggered signals, a flip-flop rate greater than 1 within one clock cycle is considered a glitch signal; for dual-edge triggered signals, a flip-flop rate greater than 2 within one clock cycle is considered a glitch signal. Furthermore, a higher flip-flop rate indicates a more severe glitch problem. Additionally, a higher fan-out factor means a greater impact of the glitch on downstream circuitry.

[0113] Step 4: Signal sorting and filtering.

[0114] Taking into account both the signal's toggle rate and fan-out coefficient, signals with high values ​​for both are quantitatively evaluated. For example, a priority index m=toggle_rate is used. Fanout performs calculations and sorts the signals from high to low based on the calculation results.

[0115] Set a reasonable threshold, and filter out signals that exceed this threshold, adding them to the set S_glitch. The signals in this set are the target glitch signals that need to be processed.

[0116] Step 5: Select the clock signal duty cycle.

[0117] Obtain the arrival time (Tarrival) of each signal in the set S_glitch in each timing path. Based on the location of these arrival times, select a clock signal (CKS) with an appropriate duty cycle for each signal, such that the duration T1 of the selected clock signal within one clock cycle satisfies a preset condition, i.e., T1 <Tarrival。

[0118] Optionally, considering engineering implementation, and for ease of operation and control, the duty cycle of CKS can be divided into three cases: 25%, 50%, and 75%. Understandably, those skilled in the art can also make more detailed divisions according to actual needs to achieve precise control of different signal glitches.

[0119] Please see Figures 10-11 , Figure 10 This is a circuit diagram illustrating how the source of the glitch signal, provided in an embodiment of this application, falls into different categories under different timing paths. Figure 11 The embodiments provided in this application are based on Figure 10 The circuit shown is a schematic diagram of a circuit that eliminates glitches in clock signals of different types using different duty cycles.

[0120] like Figure 10 As shown, the clock period T is divided into two segments: the first T / 2 segment and the last T / 2 segment. The source of the glitch signal is classified differently under different timing paths; it may be the first T / 2 segment or the last T / 2 segment.

[0121] like Figure 11 As shown, different duty cycles of clock signals can be used to eliminate glitches for different types of glitches. The clock operation unit (such as...) Figure 11 The OR gate shown can be used to change the duty cycle. For example, if the glitch signal is in the first T / 2 segment, the high-level width of the clock can be shortened, which reduces the duty cycle; if the glitch signal is in the last T / 2 segment, the high-level width can be extended, which increases the duty cycle.

[0122] The method provided in the embodiments of this application, by comprehensively considering the signal flip rate and fan-out coefficient, accurately locates the source of the glitches that have the greatest impact, effectively reducing the number of clock operation units used and reducing the area overhead during operation.

[0123] To address the limitation that clock control methods can only be inserted in the latter half of the timing path, this application employs a clock signal with a variable duty cycle. This improvement expands the insertion position of the clock operation unit, allowing it to be inserted in the first half of the timing path without introducing additional delay when reducing glitches; it can also be inserted in the latter half of the timing path, expanding the range of glitches that can be reduced. For example, when the duty cycle is 75%, glitches within 75% of the clock cycle range can be eliminated.

[0124] Regarding the use of clock operation units, embodiments of this application propose replacing buffers with clock operation units at the source of glitches, rather than simply inserting them. The clock operation unit can be a simple logic unit with a delay approximately equal to that of the buffer, thus not introducing additional timing overhead.

[0125] This application also establishes a complete glitch signal elimination process. After the insertion or replacement of clock operation units is completed, the timing is checked again, and clock operation units that have an adverse effect on the timing are iteratively removed, thereby ensuring that the logic function of the circuit is correct before and after glitch signal elimination.

[0126] Simulation results show that the method in this application is highly effective, significantly reducing the flip rate of glitches in typical circuits from an average of 5.5 times to 1.5 times, improving circuit stability and reliability, and saving power consumption.

[0127] In some embodiments, the step of analyzing the chip circuit and obtaining the signals of each circuit may specifically include: Obtain the chip circuit from the input file; perform timing and power consumption analysis on the chip circuit to determine the toggle rate, fan-out coefficient, and arrival time of each circuit signal on the timing path.

[0128] In this embodiment, the input file can be a specific format file generated during the chip design process. The input file can describe the logic structure of the chip circuit, the connection relationship of components, and the signal flow, etc.

[0129] Timing analysis is used to determine the time required for a circuit signal to travel from one component to another within a chip circuit, and whether the circuit signal can reach its destination within a specified clock cycle. Power consumption analysis is used to evaluate the energy consumption of a chip circuit during operation.

[0130] For example, Static Timing Analysis (STA) is a method that uses analysis and calculation to verify that a digital circuit can meet timing requirements under all conditions.

[0131] In a timing path, each signal has a specific arrival time. Specifically, timing analysis tools can calculate the time required for a signal to travel from its source to its destination based on the circuit's delay model. By determining the signal arrival time, it's possible to check whether the setup and hold time requirements are met.

[0132] In some embodiments, the steps following the reduction of the target glitch signal, which involve embedding a clock operation unit controlled by a target clock signal along the path of the target glitch signal, may further include: A timing analysis is performed on the new chip circuit to obtain the timing analysis results; if a violation is found in the timing analysis results, the clock operation unit that caused the violation will be removed from the chip circuit.

[0133] After eliminating glitches by embedding clock operation units in the target glitch signal path, timing analysis can be performed on the new chip circuit. Timing analysis can clarify the actual operation of the chip circuit to verify whether the propagation time of circuit signals between various components and paths meets the design requirements.

[0134] Furthermore, based on the chip circuit layout, component parameters, and clock signal information, the signal transmission process can be simulated to calculate timing parameters such as delay time, setup time, and hold time for each path, thereby obtaining timing analysis results. Then, by comparing the timing analysis results with pre-set timing constraints, it can be determined whether there are timing violations in the circuit.

[0135] If timing analysis results show violations, it indicates that the implantation of the clock operation unit has a negative impact on the timing of the chip circuit, causing the transmission time of some signals to not meet the design requirements.

[0136] Furthermore, if a timing violation is identified and it can be clearly caused by a specific clock operation unit, that clock operation unit can be removed from the chip circuit. Removal eliminates this potential timing malfunction and restores the original timing relationship of the chip circuit.

[0137] Optionally, after removing the clock operation unit, timing analysis can be performed again to confirm whether the timing violation has been eliminated. If the problem persists, it may be necessary to further investigate other possible causes or consider using other methods to handle glitches.

[0138] Please see Figure 12 , Figure 12 This is the second flowchart illustrating the method for reducing glitches in a chip circuit provided in this application embodiment.

[0139] Timing and power consumption analyses are performed on the chip circuitry to obtain the signals of each circuit. Then, based on the analysis results, change commands are issued, such as Engineering Change Orders (ECOs), to insert or replace clock operation units at candidate locations according to the arrival time of the target glitch signal. After the change is completed, a timing check is performed to determine whether the newly inserted or replaced unit causes a timing violation. If a violation is detected, the clock operation unit on the violation path is removed, the original state of the path is restored, and the timing check is restarted. If no violation is detected, the process ends, and the current clock operation unit configuration can be retained.

[0140] ECO is a method that allows for the modification of the netlist in the later stages of chip design without re-performing the entire synthesis and placement process. This modification can fix bugs, optimize timing, improve performance, or reduce power consumption.

[0141] In summary, the embodiments of this application, through timing analysis and handling of timing violations, ensure that the chip circuit operates stably according to design requirements under various operating conditions. Timely detection and resolution of timing issues improve the reliability and stability of the chip, preventing numerous problems from arising in subsequent production and testing phases.

[0142] This application also provides a glitch signal reduction device in a chip circuit. The glitch signal reduction device in a chip circuit provided in this application will be described below. The glitch signal reduction device in a chip circuit described below can be referred to in correspondence with the glitch signal reduction method in a chip circuit described above.

[0143] Please see Figure 13 , Figure 13 This is a schematic diagram of the structure of the glitch signal reduction device in the chip circuit provided in this application embodiment. In this embodiment, the glitch signal reduction device in the chip circuit may include a circuit analysis module 1310, a glitch positioning module 1320, a duty cycle adjustment module 1330, and a unit implantation module 1340.

[0144] The circuit analysis module 1310 is used to analyze the chip circuit and obtain the signals of each circuit; the circuit signals include the toggle ratio and the fan-out coefficient.

[0145] The burr positioning module 1320 is used to identify and filter the target burr signal to be optimized from various circuit signals based on the flip rate and fan-out coefficient.

[0146] The duty cycle adjustment module 1330 is used to select a matching target clock signal from at least two preset control clock signals with different duty cycles based on the arrival time of the target glitch signal.

[0147] The unit implantation module 1340 is used to implant a clock operation unit controlled by the target clock signal in the path of the target glitch signal to reduce the target glitch signal.

[0148] In some embodiments, the burr positioning module 1320 can be specifically used for: Calculate the product of the flip rate and fan-out coefficient in each circuit signal to obtain the priority index; identify the circuit signals with priority indices higher than a preset threshold as target glitch signals.

[0149] In some embodiments, the duty cycle adjustment module 1330 can be specifically used for: When the arrival time of the target glitch signal is in the first half of the clock cycle, the control clock signal with a smaller duty cycle is selected as the target clock signal; when the arrival time of the target glitch signal is in the second half of the clock cycle, the control clock signal with a larger duty cycle is selected as the target clock signal.

[0150] In some embodiments, the unit implantation module 1340 is specifically used for: Locate an existing buffer on the path of the target glitch signal and replace the buffer with a clock operation unit.

[0151] In some embodiments, the unit implantation module 1340 is specifically used for: If no buffer exists on the path of the target glitch signal, multiple buffers are inserted to filter out the target glitch signal, and one of the multiple buffers is replaced with a clock operation unit.

[0152] In some embodiments, the glitch signal reduction device in the chip circuit may further include an inspection module, which may specifically be used for: A timing analysis is performed on the new chip circuit to obtain the timing analysis results; if a violation is found in the timing analysis results, the clock operation unit that caused the violation will be removed from the chip circuit.

[0153] In some embodiments, the circuit analysis module 1310 may specifically be used for: Obtain the chip circuit from the input file; perform timing and power consumption analysis on the chip circuit to determine the toggle rate, fan-out coefficient, and arrival time of each circuit signal on the timing path.

[0154] On the other hand, this application also provides an electronic device, please refer to... Figure 14 , Figure 14 This is a schematic diagram of the physical structure of the electronic device provided in the embodiments of this application, such as... Figure 14 As shown, the electronic device may include a memory 1420, a processor 1410, and a computer program stored in the memory 1420 and executable on the processor 1410. When the processor 1410 executes the program, it can implement a method for reducing glitches in the chip circuitry. This method may include: The chip circuit is analyzed to obtain the signals of each circuit, including the toggle rate and fan-out coefficient. Based on the toggle rate and fan-out coefficient, the target glitch signal to be optimized is identified and screened from the circuit signals. According to the arrival time of the target glitch signal, a matching target clock signal is selected from at least two preset control clock signals with different duty cycles. A clock operation unit controlled by the target clock signal is implanted on the path of the target glitch signal to reduce the target glitch signal.

[0155] Optionally, the electronic device may further include a communication bus 1430 and a communication interface 1440, wherein the processor 1410, the communication interface 1440, and the memory 1420 communicate with each other through the communication bus 1430. The processor 1410 can call the computer program in the memory 1420 to execute the glitch signal reduction method in the chip circuit provided by the above methods.

[0156] Furthermore, the logical instructions in the aforementioned memory 1420 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0157] In another aspect, this application also provides a non-transitory computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the method for reducing glitches in the chip circuit provided by the above methods. The steps and principles of the method have been described in detail in the above methods and will not be repeated here.

[0158] Non-transitory computer-readable storage media can be any available medium or data storage device that can be accessed by a processor, including but not limited to magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MOs), etc.), optical storage (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs)).

[0159] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0160] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for reducing glitches in a chip circuit, characterized in that, include: Analyze the chip circuitry to obtain the signals from each circuit. The circuit signals mentioned above include the toggle ratio and the fan-out coefficient; Based on the aforementioned flip-flop rate and fan-out coefficient, the target glitch signals to be optimized are identified and filtered from the signals of each circuit. Based on the arrival time of the target glitch signal, a matching target clock signal is selected from at least two preset control clock signals with different duty cycles. A clock operation unit controlled by the target clock signal is implanted along the path of the target glitch signal to reduce the target glitch signal.

2. The method for reducing glitches in a chip circuit according to claim 1, characterized in that, The step of identifying and filtering the target glitch signal to be optimized from the circuit signals based on the flip-flop rate and fan-out coefficient includes: The priority index is obtained by calculating the product of the flip rate and the fan-out coefficient in each circuit signal; Circuit signals whose priority index is higher than a preset threshold are identified as the target glitch signals.

3. The method for reducing glitches in a chip circuit according to claim 1, characterized in that, The step of selecting a matching target clock signal from at least two preset control clock signals with different duty cycles based on the arrival time of the target glitch signal includes: When the arrival time of the target glitch signal is in the first half of the clock cycle, the control clock signal with a smaller duty cycle is selected as the target clock signal. When the arrival time of the target glitch signal is in the second half of the clock cycle, the control clock signal with a large duty cycle is selected as the target clock signal.

4. The method for reducing glitches in a chip circuit according to claim 1, characterized in that, The implanted clock operation unit controlled by the target clock signal includes: Locate an existing buffer on the path of the target glitch signal and replace the buffer with the clock operation unit.

5. The method for reducing glitches in a chip circuit according to claim 1, characterized in that, The implanted clock operation unit controlled by the target clock signal includes: If no buffer exists on the path of the target glitch signal, multiple buffers are inserted to filter out the target glitch signal, and one of the multiple buffers is replaced by the clock operation unit.

6. The method for reducing glitches in a chip circuit according to any one of claims 1 to 5, characterized in that, After embedding a clock operation unit controlled by the target clock signal along the path of the target glitch signal to reduce the target glitch signal, the method further includes: Perform timing analysis on the new chip circuit and obtain the timing analysis results; If a violation is found in the timing analysis results, the clock operation unit that caused the violation will be removed from the chip circuit.

7. The method for reducing glitches in a chip circuit according to any one of claims 1 to 5, characterized in that, The analysis of the chip circuit and acquisition of signals from each circuit include: Obtain the chip circuit from the input file; Timing and power consumption analyses are performed on the chip circuit to determine the switching rate, fan-out coefficient, and arrival time of each circuit signal on the timing path.

8. A device for reducing glitches in a chip circuit, characterized in that, include: The circuit analysis module is used to analyze the chip circuit and obtain the signals of each circuit. The circuit signals mentioned above include the toggle ratio and the fan-out coefficient; A burr positioning module is used to identify and filter out the target burr signal to be optimized from the circuit signals based on the flip rate and fan-out coefficient. The duty cycle adjustment module is used to select a matching target clock signal from at least two preset control clock signals with different duty cycles based on the arrival time of the target glitch signal. The unit implantation module is used to implant a clock operation unit controlled by the target clock signal along the path of the target glitch signal in order to reduce the target glitch signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the method for reducing glitches in the chip circuit as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method for reducing glitches in the chip circuit as described in any one of claims 1 to 7.

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