Analog-to-digital converter and method for controlling an analog-to-digital converter

Abstract

The present disclosure relates to an analog-to-digital converter and a method for controlling the analog-to-digital converter. The analog-to-digital converter outputs a conversion value acquired by performing analog-to-digital conversion on an input signal. A nonvolatile memory stores a plurality of correction values. A correction circuit selects, as a selection correction value, a correction value corresponding to a state that affects an offset in the conversion value of the analog-to-digital converter from among the plurality of correction values in response to the state, and outputs an output value in which the offset in the conversion value is corrected based on the selection correction value.

Description

Cross-references to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-210898, filed on December 4, 2024 (including the specification, drawings and abstract), is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor devices, methods, and procedures for correcting the conversion values ​​of analog-to-digital converters, which are applicable to, for example, semiconductor devices having non-volatile memory. Background Technology

[0003] Microcomputers integrated into semiconductor devices are equipped with analog-to-digital converters (hereinafter also referred to as A / D converters). It is known that A / D converters introduce offsets into the conversion results caused by factors such as operating frequency and ambient temperature. While it is conceivable to define semiconductor device specifications based on usage conditions, the complexity of this approach makes it impractical. Consequently, situations may arise where the use of a semiconductor device needs to be determined by assuming worst-case scenarios caused by the usage conditions. In such cases, the inherent performance of the semiconductor device may be limited.

[0004] In this regard, a method is provided in which the offset of an A / D converter mounted on a semiconductor device is measured, and the measured offset is added to or subtracted from the output of the A / D converter to correct the output of the A / D converter. In such a method, the measured offset of the A / D converter is stored in a register mounted on the semiconductor device. Then, depending on the operating conditions of the semiconductor device, the offset read from the register is added to or subtracted from the output of the A / D converter to correct the output of the A / D converter.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2014-209390

[0007] Patent document 1 also discloses a method in which the settings of a processing unit are switched based on a non-volatile memory mounted on a semiconductor device. Summary of the Invention

[0008] However, the general method described above corrects for the output offset of the A / D converter caused by the connections between the semiconductor device and other devices. Therefore, the measurement of the offset and the determination of the correction value are performed by the user of the semiconductor device. Consequently, there may be situations where the general method cannot be applied when determining the specifications of the semiconductor device before it is provided to the user.

[0009] Other issues and novel features will become clear from the description in this specification and the accompanying drawings.

[0010] According to one embodiment, a semiconductor device is provided, comprising: an analog-to-digital converter configured to output a converted value obtained by performing analog-to-digital conversion on an input signal; a non-volatile memory configured to store a plurality of correction values; and a correction circuit configured to, in response to a state affecting an offset in the converted value of the analog-to-digital converter, select a correction value corresponding to the state as a selected correction value from the plurality of correction values, and output an output value wherein the offset in the converted value is corrected based on the selected correction value.

[0011] According to one embodiment, a method for correcting the conversion value of an analog-to-digital converter is provided. The method includes the steps of: outputting the conversion value obtained by performing analog-to-digital conversion on an input signal; selecting a correction value corresponding to a state from a plurality of correction values ​​stored in a non-volatile memory in response to a state affecting an offset in the conversion value; and outputting an output value in which the offset in the conversion value is corrected based on the selected correction value.

[0012] According to one embodiment, a program is provided, the program being configured to cause a computer to perform: a process of selecting a correction value corresponding to the state from a plurality of correction values ​​stored in non-volatile memory in response to a state affecting an offset in a converted value obtained by performing analog-to-digital conversion on an input signal using an analog-to-digital converter; and a process of outputting an output value in which the offset in the converted value is corrected based on the selected correction value.

[0013] According to one embodiment, a semiconductor device configured to automatically correct the conversion values ​​of an analog-to-digital converter (ADC) can be provided, along with a method and procedure for correcting the conversion values ​​of the ADC. Attached Figure Description

[0014] Figure 1 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the first embodiment.

[0015] Figure 2 This is a sequence diagram illustrating the operation of a semiconductor device according to a first embodiment.

[0016] Figure 3 This is a block diagram showing in more detail the configuration of the semiconductor device according to the first embodiment.

[0017] Figure 4 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the second embodiment.

[0018] Figure 5 This is a block diagram schematically illustrating the configuration of a semiconductor device according to a third embodiment.

[0019] Figure 6 This is a block diagram that schematically illustrates an example configuration of the main parts of an A / D converter.

[0020] Figure 7 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the fourth embodiment.

[0021] Figure 8 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the fifth embodiment.

[0022] Figure 9 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the sixth embodiment.

[0023] Figure 10 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the seventh embodiment.

[0024] Figure 11 This is a diagram illustrating an example configuration of a computer used to implement semiconductor devices. Detailed Implementation

[0025] The following is a description of the embodiments with reference to the accompanying drawings. In each of the drawings, the same elements are represented by the same reference numerals, and redundant descriptions are omitted as appropriate.

[0026] First Embodiment

[0027] Figure 1 This is a block diagram schematically illustrating the configuration of a semiconductor device according to a first embodiment. The semiconductor device 100 includes an analog-to-digital converter 1, a non-volatile memory 11, and a correction circuit 21. Hereinafter, for simplicity, the analog-to-digital converter will also be referred to as an A / D converter.

[0028] The configuration of semiconductor device 100 will now be described with reference to the operating procedure. Figure 2 This is a sequence diagram illustrating the operation of a semiconductor device according to a first embodiment.

[0029] Step S1

[0030] A / D converter 1 converts the input analog signal IN into a converted value DS as a digital value. A / D converter 1 outputs the converted value DS to the correction circuit 21.

[0031] The non-volatile memory 11 stores multiple correction values ​​for correcting the offset in the conversion value DS of the A / D converter 1. The multiple correction values ​​stored in the non-volatile memory 11 are preset correction values ​​to correspond to the operating state of the semiconductor device 100.

[0032] Step S2

[0033] The correction circuit 21 receives multiple correction values ​​from the non-volatile memory 11. Furthermore, the correction circuit 21 receives status information INF indicating the operating state of the semiconductor device 100. Figure 1 For simplicity, multiple correction values ​​are represented by the reference symbol CV. The correction circuit 21 selects a correction value CVS from the multiple correction values ​​CV that corresponds to the operating conditions of the semiconductor device 100 indicated by the status information INF. Then, the correction circuit 21 uses the selected correction value CVS to correct the conversion value DS of the A / D converter 1 and outputs the corrected output value OUT. In the following text, the correction value selected by the correction circuit will also be referred to as the selected correction value.

[0034] The configuration and operation of the semiconductor device 100 will now be described with reference to specific examples. In this embodiment, an example is described of correcting the offset in the conversion value DS of the A / D converter 1 based on the operating frequency of the circuitry mounted on the semiconductor device 100 and the A / D converter 1.

[0035] Figure 3 This is a block diagram showing in more detail the configuration of the semiconductor device according to the first embodiment. The semiconductor device 100 is provided with a clock generation circuit 110. The clock generation circuit 110 outputs a clock signal ADCLK, specifying the A / D conversion operating frequency of the A / D converter 1, to the A / D converter 1. Furthermore, the clock generation circuit 110 outputs a reference clock signal PCLK. In addition to at least the A / D converter 1, circuitry mounted on the semiconductor device 100 operates in response to the reference clock signal PCLK output by the clock generation circuit 110. Note that in Figure 3 In this example, clock generation circuit 110 generates both clock signal ADCLK and reference clock signal PCLK, but this is merely an example. For instance, clock signal ADCLK and reference clock signal PCLK could be generated by different clock signal generation components provided in semiconductor device 100.

[0036] In semiconductor device 100, A / D converter 1 performs A / D conversion in response to a clock signal ADCLK different from the reference clock signal PCLK. The converted value DS of A / D converter 1 includes an offset caused by various factors. It is known that the offset in the converted value DS occurs based on, for example, a combination of the reference clock and the A / D conversion frequency. In such a case, the offset in the converted value DS varies according to the change in the combination of the reference clock and the A / D conversion frequency. Note that although the combination of the reference clock and the A / D conversion frequency is given as an example of factors that cause an offset in the converted value DS, the factors that cause an offset are not limited to these.

[0037] Therefore, the semiconductor device 100 according to this embodiment is based on the frequency f of the clock signal ADCLK, which is the A / D conversion operation frequency.AD and the frequency f of the reference clock signal PCLK P Both are used to correct the offset in the converted value DS.

[0038] Non-volatile memory 11 stores the frequency f corresponding to the clock signal ADCLK. AD and the frequency f of the reference clock signal PCLK P Multiple correction values ​​CV. In the following text, for the sake of simplicity, the frequency f of the clock signal ADCLK is... AD and the frequency f of the reference clock signal PCLK P This will also be referred to as the operating frequency of the semiconductor device 100. Furthermore, the frequency f of the clock signal ADCLK... AD This will also be referred to as the conversion operation frequency of A / D converter 1.

[0039] The correction circuit 21 includes an operational circuit 20, a selection signal generation circuit 21A, and a selector 21B.

[0040] The selection signal generation circuit 21A receives the clock signal ADCLK and the reference clock signal PCLK. Note that the clock signal ADCLK and the reference clock signal PCLK correspond to the aforementioned status information INF. The selection signal generation circuit 21A generates a selection signal SEL to control the operation of the selector 21B based on the frequencies of the clock signal ADCLK and the reference clock signal PCLK. The selection signal generation circuit 21A can determine the frequency f of the clock signal ADCLK based on the multiplication and division settings of the clock generation circuit 110. AD and the frequency f of the reference clock signal PCLK P However, in the selection signal generation circuit 21A, the frequency f used to determine the clock signal ADCLK is... AD and the frequency f of the reference clock signal PCLK P The method described is merely an example. The signal generation circuit 21A can use various frequency determination methods to determine the frequency f of the clock signal ADCLK. AD and the frequency f of the reference clock signal PCLK P The selection signal generation circuit 21A outputs the generated selection signal SEL to the selector 21B.

[0041] Selector 21B selects a correction value from a plurality of correction values ​​stored in non-volatile memory 11 that corresponds to the combination of frequencies of clock signal ADCLK and reference clock signal PCLK indicated by selection signal SEL. For example, when the frequency of clock signal ADCLK is 8MHz and the frequency of reference clock signal PCLK is 24MHz, selector 21B selects a correction value CV (8MHz, 24MHz) corresponding to the combination of frequencies of clock signal ADCLK and reference clock signal PCLK, and outputs this value as the selected correction value CVS to arithmetic circuit 20.

[0042] The arithmetic circuit 20 corrects the conversion value DS based on the correction value CVS selected from the selector 21B. The arithmetic circuit 20 can be configured as, for example, an adder / subtractor circuit. In such a case, the selector 21B adds the selected correction value CVS to the conversion value DS or subtracts the selected correction value CVS from the conversion value DS to correct the conversion value DS. The arithmetic circuit 20 then outputs the value obtained through correction as the output value OUT.

[0043] Therefore, according to semiconductor device 100, the offset in the converted value of the A / D converter can be automatically corrected by an appropriate correction value corresponding to the conversion operating frequency of the A / D converter and the frequency of the reference clock signal of semiconductor device 100. Thus, regardless of the conversion operating frequency of the A / D converter and the frequency of the reference clock signal, semiconductor device 100 can obtain the desired output value as the A / D conversion result of the A / D converter for the input signal.

[0044] The selection of the correction value can be performed, for example, during the startup of the semiconductor device 100. Selecting the correction value after startup but before the start of operation of the A / D converter allows for proper correction of the offset in the output value from the start of the A / D converter's operation.

[0045] Furthermore, the selection of a correction value can be performed during the operation of the semiconductor device 100. For example, the expected frequency combination of the clock signal ADCLK and the reference clock signal PCLK may change after the semiconductor device 100 starts operating (such as when the user changes the frequency setting). In such a case, the selection signal generation circuit 21A detects the change in the frequency combination of the clock signal ADCLK and the reference clock signal PCLK and reflects the detection result to the selection signal SEL. As a result, the selector 21B can select a correction value corresponding to the changed frequency combination of the clock signal ADCLK and the reference clock signal PCLK in response to the selection signal SEL. Therefore, according to the semiconductor device 100, the offset in the conversion value of the A / D converter can be appropriately corrected in response to the latest operating state.

[0046] As described above, the correction of the offset in the converted value of the A / D converter in semiconductor device 100 is performed automatically, and the user of semiconductor device 100 does not need to pay special attention to it. Therefore, unlike the general method described above, the user of the semiconductor device does not need to perform the task of determining the correction value of the offset. Therefore, the user can more easily introduce semiconductor device 100 and can reduce the amount of work required to introduce the device.

[0047] Therefore, the maximum performance of semiconductor device 100 can be presented to the user as a specification of semiconductor device 100 based on its operating state. As a result, unlike the general approach, the specifications of semiconductor device 100 can be determined based on the performance that semiconductor device 100 can inherently achieve, without limiting the specifications presented to the user.

[0048] Furthermore, the non-volatile memory 11 of the semiconductor device 100 can utilize optional memory typically provided in semiconductor devices, and can store various additional data. Therefore, the semiconductor device 100 according to the first embodiment can be implemented without adding any special hardware configuration to a general semiconductor device. As a result, by utilizing existing semiconductor devices, the semiconductor device according to the embodiment can be easily implemented at low cost.

[0049] Second Embodiment

[0050] In the first embodiment, a semiconductor device for correcting the offset in the conversion value DS based on the operating frequency of the semiconductor device has been described. However, the factors causing the offset in the conversion value DS are not limited to the operating frequency of the semiconductor device. For example, it is conceivable that the offset in the conversion value DS can change with the temperature of the semiconductor device. Therefore, in the second embodiment, a semiconductor device for correcting the offset in the conversion value of an A / D converter based on the ambient temperature has been described.

[0051] Figure 4 This is a block diagram schematically illustrating the configuration of a semiconductor device according to a second embodiment. The semiconductor device 200 according to the second embodiment has a configuration in which the non-volatile memory 11 and the correction circuit 21 of the semiconductor device 100 are replaced by a non-volatile memory 12 and a correction circuit 22, respectively.

[0052] Furthermore, the difference between semiconductor device 200 and semiconductor device 100 is that the input of the selection signal generation circuit 22A is replaced by a temperature sensor 210 and a reference voltage source 220 from the clock generation circuit 110. Note that in Figure 4 For simplicity, the clock generation circuit 110 has been omitted.

[0053] Temperature sensor 210 measures the temperature of semiconductor device 200 at a predetermined location. Then, temperature sensor 210 outputs a temperature signal ST, indicating the measured ambient temperature TMP, to calibration circuit 22. The temperature signal ST is, for example, a voltage signal representing temperature.

[0054] Reference voltage source 220 outputs a reference voltage REF, indicating a reference temperature for comparison with temperature signal ST, to correction circuit 22.

[0055] The non-volatile memory 12 stores multiple correction values ​​corresponding to temperature TMP. Figure 4 For example, a correction value CV (TL to TH) is set for each temperature range in a 10-degree increment from the lower limit temperature to the upper limit temperature TH.

[0056] The correction circuit 22 has a selection signal generation circuit 22A and a selector 22B that correspond to the selection signal generation circuit 21A and selector 21B of the correction circuit 21, respectively. Note that the arithmetic circuit 20 in the correction circuit 22 is the same as the arithmetic circuit 20 in the correction circuit 21.

[0057] The selection signal generation circuit 22A compares the temperature signal ST and the reference voltage REF, and detects the temperature TMP indicated by the temperature signal ST. Note that the temperature signal ST and the reference voltage REF correspond to the aforementioned state information INF. Based on the detected temperature TMP, the selection signal generation circuit 22A outputs a selection signal SEL to the selector 22B, indicating the correction value to be selected from a plurality of correction values ​​output by the non-volatile memory 12.

[0058] Selector 22B selects from a plurality of correction values ​​stored in non-volatile memory 12 the correction value corresponding to the temperature TMP indicated by the selection signal SEL. For example, when the temperature TMP is 28°C, the correction value CV (20°C to 30°C) corresponding to the temperature range 20°C ≤ T < 30°C is selected as the correction value CVS and output to the arithmetic circuit 20.

[0059] The operation of the operational circuit 20 in the correction circuit 22 is the same as that in the correction circuit 21, and therefore its description is omitted.

[0060] Therefore, according to semiconductor device 200, the offset in the converted value of the A / D converter can be automatically corrected by an appropriate correction value corresponding to the ambient temperature. Thus, semiconductor device 200 can obtain the desired output value OUT after correction as the A / D conversion result of the A / D converter for the input signal, regardless of the ambient temperature.

[0061] Other advantages of semiconductor device 200 are the same as those of semiconductor device 100, and therefore, their redundant description is omitted.

[0062] Third Embodiment

[0063] In the above embodiments, a semiconductor device for correcting offsets in the conversion value DS based on the operating frequency of the semiconductor device or the ambient temperature has been described. However, the factors causing offsets in the conversion value DS are not limited to the operating frequency of the semiconductor device or the ambient temperature. For example, it is conceivable that the offset in the conversion value DS can vary depending on the input signal IN. Therefore, in the third embodiment, a semiconductor device for correcting offsets that vary depending on the input signal IN is described. Note that the conversion value DS varies depending on the input signal IN and the reference voltage of the A / D converter 1. However, the case where the reference voltage of the A / D converter 1 is a predetermined constant voltage is described.

[0064] Figure 5 This is a block diagram schematically illustrating the configuration of a semiconductor device according to a third embodiment. The semiconductor device 300 according to the third embodiment has a configuration in which the non-volatile memory 11 and correction circuit 21 of the semiconductor device 100 are replaced by a non-volatile memory 13 and a correction circuit 23, respectively. Furthermore, the semiconductor device 300 differs from the semiconductor device 100 in that the input from the clock generation circuit 110 to the selection signal generation circuit 23A has been removed. Note that in... Figure 5 For simplicity, the clock generation circuit 110 has been omitted.

[0065] A / D converter 1 outputs the converted value DS, which constitutes the converted code after performing A / D conversion, to both the arithmetic circuit 20 and the correction circuit 23. Here, for distinction, the converted value output from A / D converter 1 to the arithmetic circuit 20 is called the converted value DS_REF. Note that the converted value DS_REF corresponds to the status information INF mentioned above.

[0066] At this time, A / D converter 1 can output the conversion code to correction circuit 23 before outputting the conversion value DS to arithmetic circuit 20. Figure 6 This is a block diagram that schematically illustrates an example configuration of the main parts of an A / D converter. Figure 6An example is shown in which A / D converter 1 is configured as a successive approximation A / D converter and converts the input signal IN into an N-bit conversion code. In this case, the A / D conversion of the input signal IN is performed sequentially, one bit at a time, from the most significant bit (MSB) BIT[N-1] to the least significant bit (LSB) BIT[0]. At this time, the conversion result of each bit is held in latch circuits L_N-1 to L_0. After all bits have been converted, A / D converter 1 outputs the converted value DS from output circuits OC_N-1 to OC_0 to the arithmetic circuit 20 according to the conversion of the output enable signals EN provided to the output circuits OC_N-1 to OC_0.

[0067] On this point, Figure 6 The A / D converter 1 shown sequentially outputs the conversion result of each bit held in the latch circuits L_N-1 to L_0 to the correction circuit 23, regardless of the output enable signal EN. In this case, the conversion value DS_REF can be notified to the correction circuit 23 before the arithmetic circuit 20 receives the conversion value DS from the A / D converter 1. As a result, before the arithmetic circuit 20 corrects the conversion value DS, the correction circuit 23 can provide the arithmetic circuit 20 with a selected correction value CVS corresponding to the conversion value DS_REF.

[0068] Non-volatile memory 13 stores multiple correction values ​​corresponding to the conversion value DS_REF. For example, in Figure 5 In this context, a correction value CV (MIN to MAX) is set for each range in increments of 1000, where the range of the conversion value DS_REF is from the lower limit MIN to the upper limit MAX.

[0069] The correction circuit 23 has a selection signal generation circuit 23A and a selector 23B that correspond to the selection signal generation circuit 21A and selector 21B of the correction circuit 21, respectively. Note that the arithmetic circuit 20 in the correction circuit 23 is the same as the arithmetic circuit 20 in the correction circuit 21.

[0070] Based on the conversion value DS_REF, the selection signal generation circuit 23A outputs a selection signal SEL to the selector 23B, indicating the correction value to be selected from a plurality of correction values ​​output by the non-volatile memory 12.

[0071] Selector 23B selects a correction value corresponding to the conversion value DS_REF indicated by the selection signal SEL from a plurality of correction values ​​stored in non-volatile memory 13. For example, when the conversion code is 5265, the correction value CV (5000 to 5999) is selected as the selection correction value CVS and output to the arithmetic circuit 20.

[0072] The operation of the arithmetic circuit 20 in the correction circuit 23 is the same as that of the arithmetic circuit 20 in the correction circuit 21, and therefore its description is omitted.

[0073] In this embodiment, for the sake of simplicity, the case where the reference voltage of A / D converter 1 is a predetermined constant voltage has been described, but this is merely an example. Generally, the reference voltage of the A / D converter is variable, and its value varies depending on the user. That is, even if the input signal IN is constant, the conversion code used to correct the offset can differ depending on the reference voltage. Therefore, instead of using the conversion value DS_REF, the reference voltage of A / D converter 1 can be input to the selection signal generation circuit 23A to allow the selection signal generation circuit 23A to determine the reference voltage. Thus, the selection signal generation circuit 23A can output a selection signal SEL corresponding to A / D converter 1. Furthermore, by storing the correction value CV corresponding to the reference voltage in the non-volatile memory 13, the selector 21B can select the correction value CV corresponding to the reference voltage. To determine the reference voltage of A / D converter 1, if a holding component, such as a register, exists in the semiconductor device 300 that holds information indicating the reference voltage of A / D converter 1, then the information indicating the reference voltage of A / D converter 1 can be input to the selection signal generation circuit 23A from the holding component.

[0074] By combining these, according to semiconductor device 300, the offset in the converted value of the A / D converter can be automatically corrected by an appropriate correction value corresponding to the offset that varies in response to the input signal IN. Therefore, semiconductor device 300 can appropriately correct the offset that varies according to the input signal IN to obtain the desired output value OUT.

[0075] Other advantages of semiconductor device 300 are the same as those of the semiconductor device according to the above embodiments, and therefore redundant descriptions thereof are omitted.

[0076] Fourth embodiment

[0077] In the above embodiments, one type of parameter—the operating frequency of the semiconductor device, the ambient temperature, and the conversion value output by the A / D converter—is used as the operating state of the semiconductor device to select a correction value. However, depending on the application of the semiconductor device, there may be situations where it is desirable to select a correction value by simultaneously referencing multiple parameters to more accurately correct the conversion value. Therefore, in the fourth embodiment, a semiconductor device is described that selects a correction value by referring to two types of information indicating independent operating states.

[0078] Figure 7This is a block diagram schematically illustrating the configuration of a semiconductor device according to the fourth embodiment. The semiconductor device 400 corrects the conversion value DS by means of information indicating two types of independent operating states using two types of correction values ​​corresponding to the two types of operating states respectively.

[0079] Semiconductor device 400 has a configuration in which non-volatile memory 11 and correction circuit 21 of semiconductor device 100 are replaced by non-volatile memory 14 and correction circuit 24, respectively.

[0080] Furthermore, the difference between semiconductor device 400 and semiconductor device 100 is that semiconductor device 400 also provides the same temperature sensor 210 and reference voltage source 220 as semiconductor device 200.

[0081] The non-volatile memory 14 has at least a memory region 14A and a memory region 14B, wherein the memory region 14A is used to store a correction value set corresponding to the operating frequency in the first embodiment, and the memory region 14B is used to store a correction value set corresponding to the temperature in the second embodiment.

[0082] The correction circuit 24 includes a selection signal generation circuit 24A, a selector 24B, a selection signal generation circuit 24C, and a selector 24D. Note that the operational circuit 20 in the correction circuit 24 is the same as the operational circuit 20 in the correction circuit 21.

[0083] The selection signal generation circuit 24A and selector 24B are the same as the selection signal generation circuit 21A and selector 21B according to the first embodiment, and therefore their redundant description is omitted. Note that in Figure 7 For the sake of distinction, the selection signal output from the selection signal generation circuit 24A to the selector 24B is called the selection signal SEL1. Additionally, the selection correction value selected by the selector 24B is called the selection correction value CVS1.

[0084] The selection signal generation circuit 24C and selector 24D are the same as the selection signal generation circuit 22A and selector 22B according to the second embodiment, and therefore their redundant description is omitted. Note that in Figure 7 In this context, for the sake of distinction, the selection signal output from the selection signal generation circuit 24C to the selector 24D is called the selection signal SEL2. Additionally, the selection correction value selected by the selector 24D is called the selection correction value CVS2.

[0085] In this embodiment, the clock signal ADCLK, the reference clock signal PCLK, the temperature signal ST, and the reference voltage REF correspond to the aforementioned state information INF.

[0086] Therefore, according to the semiconductor device 400, a selection correction value CVS1 corresponding to the operating frequency of the semiconductor device 400 and a selection correction value CVS2 corresponding to the ambient temperature can be selected from a plurality of correction values ​​stored in the non-volatile memory 14. Then, the arithmetic circuit 20 can correct the conversion value DS of the A / D converter 1 by combining the selection correction value CVS1 corresponding to the operating frequency of the semiconductor device 400 and the selection correction value CVS2 corresponding to the ambient temperature, thereby appropriately correcting the offset in the conversion value DS.

[0087] Other advantages of semiconductor device 400 are the same as those of the semiconductor device according to the above embodiments, and therefore redundant descriptions thereof are omitted.

[0088] Fifth embodiment

[0089] In the fourth embodiment, an example has been described in which the offset corresponding to the operating frequency of the semiconductor device and the offset corresponding to the ambient temperature are independent of each other. However, in real semiconductor devices, the effects of operating frequency and ambient temperature on the offset are inseparable and may not be independent of each other. In such cases, as in the fourth embodiment, it is inappropriate to set correction values ​​separately for the operating frequency and ambient temperature.

[0090] Therefore, in this embodiment, a semiconductor device is described that selects a single correction value by referring to information indicating two types of operating states that are not independent of each other. Figure 8 This is a block diagram schematically illustrating the configuration of a semiconductor device according to the fifth embodiment.

[0091] According to the fifth embodiment, the semiconductor device 500 has a configuration in which the non-volatile memory 14 and the correction circuit 24 of the semiconductor device 400 are replaced by a non-volatile memory 15 and a correction circuit 25, respectively.

[0092] The non-volatile memory 15 stores multiple preset correction values ​​to correspond to the frequency f of the clock signal ADCLK. AD The frequency f of the reference clock signal PCLK P The combination of temperature (TMP). In Figure 8 In the context, the frequency f corresponding to the clock signal ADCLK is... AD [MHz], the frequency f of the reference clock signal PCLK P The correction values ​​for [MHz] and temperature TMP are expressed as C(f AD f P ,TL to TH).

[0093] The correction circuit 25 includes a selection signal generation circuit 25A and a selector 25B. Note that the operational circuit 20 in the correction circuit 25 is the same as the operational circuit 20 in the correction circuit 21.

[0094] The signal generation circuit 25A selects the clock signal ADCLK, the reference clock signal PCLK, the temperature signal ST, and the reference voltage REF. Then, the signal generation circuit 25A selects the frequency f based on the clock signal ADCLK. AD The frequency f of the reference clock signal PCLK P The temperature TMP is used to generate a selection signal SEL to control the operation of selector 25B. The selection signal generation circuit 25A outputs the generated selection signal SEL to selector 25B.

[0095] Selector 25B selects a frequency f corresponding to the clock signal ADCLK from a plurality of correction values ​​stored in nonvolatile memory 15. AD The frequency f of the reference clock signal PCLK P The correction value is a combination of the temperature TMP indicated by the selection signal SEL. Here, we assume an example where the frequency of the clock signal ADCLK is 8MHz, the frequency of the reference clock signal PCLK is 24MHz, and the temperature TMP is 28°C. In such a case, selector 25B outputs the correction value C (8MHz, 24MHz, 20°C to 30°C) corresponding to these values ​​as the selection correction value CVS to the arithmetic circuit 20.

[0096] In this embodiment, the clock signal ADCLK, the reference clock signal PCLK, the temperature signal ST, and the reference voltage REF correspond to the aforementioned state information INF.

[0097] The operation of the arithmetic circuit 20 in the correction circuit 25 is the same as that of the arithmetic circuit 20 in the correction circuit 24, and therefore its redundant description is omitted.

[0098] Therefore, according to the semiconductor device 400, a single selected correction value CVS corresponding to the operating frequency of the semiconductor device 400 and the ambient temperature can be selected from a plurality of correction values ​​stored in the non-volatile memory 15. Thus, even when the effects of the operating frequency and the effects of temperature relative to the offset are not independent of each other, the semiconductor device 500 can appropriately correct the offset in the conversion value DS.

[0099] Other advantages of semiconductor device 500 are the same as those of the semiconductor device according to the above embodiments, and therefore redundant descriptions thereof are omitted.

[0100] Sixth Embodiment

[0101] In the above embodiments, a semiconductor device for selecting a correction value to correct an offset in the conversion value has been described based on the operating state. However, there may be cases where the offset of the conversion value of the A / D converter 1 mounted on the semiconductor device depends on a combination of the semiconductor device and an external device connected to the semiconductor device. Therefore, in this embodiment, a semiconductor device for selecting a correction value based on the connected external device is described.

[0102] Figure 9 This is a block diagram schematically illustrating the configuration of a semiconductor device according to a sixth embodiment. In this embodiment, semiconductor device 600 is connected to external devices 601 and 602. External devices 601 and 602 are each provided with operation enable signals EN1 and EN2 indicating activation / deactivation, and are activated in a complementary manner. Furthermore, operation enable signals EN1 and EN2 are input to enable signal terminals T1 and T2 disposed in semiconductor device 600. In this embodiment, the offset in the expected conversion value DS varies depending on which of external devices 601 and 602 is activated.

[0103] Semiconductor device 600 has a configuration in which non-volatile memory 11 and correction circuit 21 of semiconductor device 100 are replaced by non-volatile memory 16 and correction circuit 26, respectively.

[0104] The non-volatile memory 16 has at least memory region 16A and memory region 16B. Memory region 16A stores a set of correction values ​​ST1 used when external device 601 is activated. Memory region 16B stores a set of correction values ​​ST2 when external device 602 is activated.

[0105] The correction value corresponding to each of the external devices described above can be prepared by, for example, a user of a semiconductor device using various methods such as actual measurement or simulation, depending on the external device used with the semiconductor device. In this case, as mentioned above, since the optional memory provided in the semiconductor device can be used as the non-volatile memory of this embodiment, the user can easily store the prepared correction value in the non-volatile memory.

[0106] The correction circuit 26 includes a selection signal generation circuit 26A and a selector 26B. Note that the operational circuit 20 in the correction circuit 26 is the same as the operational circuit 20 in the correction circuit 21.

[0107] The selection signal generation circuit 26A receives operation enable signals EN1 and EN2 via enable signal terminals T1 and T2. Then, the selection signal generation circuit 26A generates a selection signal SEL indicating the correction value to be selected by the selector 26B based on which of the external devices 601 and 602 is activated. The selection signal generation circuit 26A outputs the generated selection signal SEL to the selector 26B.

[0108] Selector 26B selects from a plurality of correction values ​​stored in memory regions 16A and 16B the correction value corresponding to the external device indicated by the selection signal SEL. Here, we assume an example where external device 601 is activated. In such a case, selector 26B outputs the correction value corresponding to external device 601 and stored in memory region 16A to arithmetic circuit 20.

[0109] In this embodiment, the operation enable signals EN1 and EN2 are included in the aforementioned status information INF.

[0110] The operation of the arithmetic circuit 20 in the correction circuit 26 is the same as that of the arithmetic circuit 20 in the correction circuit 21, and therefore its description is omitted.

[0111] Therefore, according to semiconductor device 600, even if the offset in the conversion value DS is affected by the operation of external devices of the semiconductor device, an appropriate correction value can be selected to properly correct the offset. As a result, as in the semiconductor device according to the above embodiment, the offset in the conversion value of the A / D converter can be automatically corrected. Therefore, semiconductor device 600 can appropriately correct the offset in the conversion value DS to obtain the desired output value OUT.

[0112] Other advantages of semiconductor device 600 are the same as those of the semiconductor device according to the above embodiments, and therefore redundant descriptions thereof are omitted.

[0113] Seventh Embodiment

[0114] In the above embodiments, a semiconductor device for correcting offsets in the converted values ​​of the mounted A / D converter 1 has been described. However, by combining the selection signal generation circuit and selector of the above-described correction circuit with a non-volatile memory, it is possible to correct offsets in the converted values ​​and adjust the operation of the hard macro mounted on the semiconductor device according to the operating state of the semiconductor device. Therefore, in this embodiment, a semiconductor device capable of adjusting the operation of the mounted hard macro is described.

[0115] Figure 10This is a block diagram schematically illustrating the configuration of a semiconductor device according to the seventh embodiment. The semiconductor device 700 has a configuration in which the non-volatile memory 12 and correction circuit 22 of the semiconductor device 200 are replaced by a non-volatile memory 17 and a correction circuit 27, respectively. Furthermore, the semiconductor device 700 is provided with a register 710 that holds the value of the power supply voltage VCC supplied to the semiconductor device 700. Additionally, the semiconductor device 700 is provided with a hard macro 70 that performs various processes and includes variable elements.

[0116] Non-volatile memory 17 stores multiple fine-tuning values ​​TRM_1 to TRM_M to be provided to the hard macro, corresponding to the ambient temperature.

[0117] The correction circuit 27 has a selection signal generation circuit 27A and a selector 27B.

[0118] The selection signal generation circuit 27A receives a temperature signal ST and a reference voltage REF from the temperature sensor 210 and the reference voltage source 220, respectively. The selection signal generation circuit 27A compares the temperature signal ST and the reference voltage REF, and detects the temperature TMP indicated by the temperature signal ST. Furthermore, the selection signal generation circuit 27A receives a power supply voltage signal SV indicating the power supply voltage output from the register 710. Note that to determine the power supply voltage, it can be configured such that a power supply voltage is input to the selection signal generation circuit 27A. Determining the power supply voltage in the selection signal generation circuit 27A in this manner is merely an example. The selection signal generation circuit 27A can use various other methods to determine the power supply voltage. The selection signal generation circuit 27A outputs a selection signal SEL to the selector 27B, indicating the selection from a plurality of fine-tuning values ​​stored in the non-volatile memory 17 to correspond to the temperature TMP and the fine-tuning value of the power supply voltage indicated by the power supply voltage signal SV.

[0119] Selector 27B selects a fine-tuning value indicated by the selection signal SEL from a plurality of fine-tuning values ​​stored in non-volatile memory 17. The selected fine-tuning value TRM is then output to hard macro 70.

[0120] The hard macro 70 performs fine-tuning, for example, of internal variable elements, based on the fine-tuning value TMR received from selector 27B.

[0121] As described above, according to the semiconductor device 700, hardware such as hard macros set in the semiconductor device 700 can be adjusted in response to the operating state of the semiconductor device.

[0122] Other embodiments

[0123] The present disclosure has been described above with reference to embodiments. However, the present disclosure is not limited to the foregoing embodiments, and various modifications can be made to the configuration and details of the present disclosure within the scope of the disclosure as will be understood by those skilled in the art. Note that each embodiment may be appropriately combined with other embodiments.

[0124] In the fourth and fifth embodiments, examples have been described in which the correction value is selected based on a combination of the semiconductor device's operating frequency and ambient temperature. However, the combination of operating states used to select the correction value is not limited to this. For example, in the embodiments described above, in addition to the combinations described above, the semiconductor device may select the correction value based on a combination of some or all of the types of operating states described above, which at least include the operating frequency, ambient temperature, and the converted value after A / D conversion.

[0125] In the above embodiments, the semiconductor device according to this disclosure has been primarily described as a hardware configuration, but is not limited thereto. The semiconductor device according to this disclosure can be implemented by executing a computer program on a computer to perform desired processes. These processes can be implemented by executing a program on a computer including at least one processor (e.g., a microprocessor, CPU, GPU, MPU, DSP (digital signal processor)). Specifically, one or more programs including a set of instructions for causing the computer to execute algorithms related to transmitting or receiving signal processing can be created and supplied to the computer.

[0126] Computer programs can be stored on any type of non-transitory computer-readable medium for feeding to a computer. Non-transitory computer-readable media include a wide variety of tangible storage media. By way of example, and not limitation, non-transitory computer-readable media include magnetic storage media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (read-only memory), CD-Rs, CD-RWs, semiconductor memories (e.g., mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs), flash ROMs, and RAMs (random access memory). Furthermore, the program can be supplied to a computer via a wide variety of transient computer-readable media. By way of example, and not limitation, transient computer-readable media include electrical or optical signals and electromagnetic waves. Transient computer-readable media can supply programs to a computer via wired communication paths such as electrical wires and optical fibers, or via wireless communication paths.

[0127] A configuration example of a computer for implementing a semiconductor device according to the above embodiments will now be described. Figure 11This diagram illustrates an example configuration of a computer used to implement a semiconductor device. The semiconductor device can be implemented by a computer 9000, such as a dedicated computer or a personal computer (PC). However, the computer does not need to be physically single, and there can be multiple computers when performing distributed processing. Figure 11 As shown, the computer 9000 has, for example, a processor 9001, a ROM (read-only memory) 9002, a RAM (random access memory) 9003, a storage device 9004, a communication interface 9005, and a user interface 9006.

[0128] The processor 9001, ROM 9002, RAM 9003, storage device 9004, communication interface 9005, and user interface 9006 are interconnected via bus 9007 for mutual communication. Note that the OS software and other components necessary for operating the computer are omitted in this description, but may be appropriately implemented in the computer 9000.

[0129] ROM is constructed from, for example, non-volatile semiconductor memory devices. ROM 9002 stores information such as various programs used in computer 9000.

[0130] Storage device 9004 is composed of various storage devices, such as hard disks or solid-state drives. Furthermore, storage device 9004 is not limited to storage devices installed in computer 9000, but can also be an external storage device. External storage devices may include various communication components, such as cloud storage devices connected to computer 9000 via a network. Storage device 9004 stores information such as various programs and data used by computer 9000.

[0131] RAM 9003 is composed of volatile semiconductor memory devices. Program and data information used by processor 9001 is appropriately loaded into RAM 9003 from one or both of ROM 9002 and storage device 9004.

[0132] The processor 9001 may be composed of, for example, a CPU (Central Processing Unit). In addition to a CPU, the processor 9001 may also be equipped with a GPU (Graphics Processing Unit). GPUs are suitable for performing standardized processing in parallel, and when used in applications such as processing neural networks, they can improve processing speed compared to CPUs. The processor 9001 appropriately performs various processing operations based on various programs stored in ROM 9002 or various programs and data stored in RAM 9003. Furthermore, the processor 9001 can appropriately store data generated during processing in RAM 9003 or storage device 9004.

[0133] The communication interface 9005 is an interface that connects the computer 9000 to a communication network such as the Internet or intranet via various wired or wireless communication components. Therefore, the computer 9000 can communicate with other devices, systems, and sensors connected to the communication network.

[0134] User interface 9006 includes: a display that provides information recognizable by a user using a component such as a display device; and a voice output unit that outputs voice. Furthermore, user interface 9006 includes an input unit that allows the user to input information into computer 9000 by operating a keyboard, mouse, touchpad, etc. Additionally, user interface 9006 may include devices such as sensors that acquire information useful to the user.

[0135] Here, Computer 9000 has been described as a single device, but this is merely an example. Computer 9000 can consist of multiple physically separate devices. Some devices may be portable, while others may be stationary.

[0136] Each figure in the accompanying drawings is merely an example for illustrating one or more embodiments. Each figure in the drawings is not necessarily associated with only one specific embodiment, but may also be associated with one or more other embodiments. As those skilled in the art will understand, various features or steps described with reference to any of the figures in the accompanying drawings may be combined with features or steps shown in one or more other figures to create embodiments that are not explicitly illustrated or described. Not all features or steps shown in any of the figures used to describe exemplary embodiments are necessarily required, and some features or steps may be omitted. The order of steps described in any of the figures in the accompanying drawings may be appropriately changed.

Claims

1. A semiconductor device, comprising: An analog-to-digital converter is configured to output a converted value, which is obtained by performing an analog-to-digital conversion on an input signal; Non-volatile memory, configured to store multiple correction values; as well as A correction circuit is configured to, in response to a state affecting an offset in the conversion value of the analog-to-digital converter, select a correction value corresponding to the state from a plurality of correction values ​​as a selected correction value, and output an output value in which the offset in the conversion value is corrected based on the selected correction value.

2. The semiconductor device according to claim 1, The correction circuit includes: A selection signal generator is configured to receive information indicating the state and generate a selection signal based on the information, the selection signal indicating the correction value to be selected from the plurality of correction values; The selector is configured to output the correction value indicated by the selection signal from the non-volatile memory as the selection correction value; as well as An arithmetic circuit is configured to output the output value, in which the offset in the converted value is corrected based on the selected correction value.

3. The semiconductor device according to claim 1, The non-volatile memory is configured to store the plurality of correction values, each corresponding to a frequency of a clock signal used to control the operation of the semiconductor device. The correction circuit is configured to select a correction value corresponding to the frequency of the clock signal as the selected correction value.

4. The semiconductor device according to claim 3, The non-volatile memory is configured to store the plurality of correction values, each corresponding to a combination of the frequency of a first clock signal for controlling the operation of the semiconductor device and the frequency of a second clock signal for controlling the analog-to-digital conversion operation of the analog-to-digital converter. The correction circuit is configured to select a correction value corresponding to the combination of the frequency of the first clock signal and the frequency of the second clock signal as the selected correction value.

5. The semiconductor device according to claim 1, The non-volatile memory is configured to store the plurality of correction values, each corresponding to the temperature of the semiconductor device. The correction circuit is configured to select a correction value corresponding to the temperature as the selected correction value.

6. The semiconductor device according to claim 1, The non-volatile memory is configured to store the plurality of correction values, each corresponding to the input signal of the analog-to-digital converter. The correction circuit is configured to select a correction value corresponding to the input signal of the analog-to-digital converter as the selected correction value.

7. The semiconductor device according to claim 1, The plurality of correction values ​​includes some or all of the following: a first set of correction values ​​corresponding to a combination of the frequency of a first clock signal used to control the operation of the semiconductor device and the frequency of a second clock signal used to control the analog-to-digital conversion operation of the analog-to-digital converter; a second set of correction values ​​corresponding to the temperature of the semiconductor device; and a third set of correction values ​​corresponding to the conversion value of the analog-to-digital converter. The correction circuit is configured to select one, two, or three correction values ​​from some or all of the first set to the third set, which are combinations of the frequency corresponding to the analog-to-digital converter, the temperature, and the conversion value, as the selected correction values.

8. The semiconductor device according to claim 1, Each of the plurality of correction values ​​corresponds to some or all of the following: a combination of the frequency of a first clock signal used to control the operation of the semiconductor device and the frequency of a second clock signal used to control the analog-to-digital conversion operation of the analog-to-digital converter; the temperature of the semiconductor device; and the conversion value of the analog-to-digital converter. The correction circuit is configured to select a chosen correction value from a plurality of correction values ​​based on a combination of the frequency of the analog-to-digital converter, the temperature, and some or all of the conversion value.

9. The semiconductor device according to claim 1, The plurality of correction values ​​includes a set of correction values ​​corresponding to a plurality of external devices, and The correction circuit is configured to select the selected correction value from the plurality of correction value sets, corresponding to a single external device among the plurality of external devices.

10. A method for correcting the conversion value of an analog-to-digital converter, comprising the following steps: The output is the converted value obtained by performing analog-to-digital conversion on the input signal; In response to a state affecting the offset in the conversion value, a correction value corresponding to the state is selected from a plurality of correction values ​​stored in non-volatile memory; as well as Output an output value, in which the offset in the converted value is corrected based on the selected correction value.

11. A program configured to cause a computer to execute: The process of selecting a correction value corresponding to a state from a plurality of correction values ​​stored in non-volatile memory, in response to a state affecting the offset in the converted value obtained by performing analog-to-digital conversion on the input signal using an analog-to-digital converter; and The process of outputting the following output value: In the output value, the offset in the transformed value is corrected based on the selected correction value.

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