Current sampling circuit, analog-to-digital converter front-end sampling device and electronic equipment

Abstract

The present disclosure relates to the technical field of integrated circuits, and particularly relates to a current sampling circuit, an analog-to-digital converter front-end sampling device and an electronic device. The circuit comprises: an input conversion module, the input conversion module comprising a current buffer of a common-gate structure, the current buffer being configured to convert a received input voltage signal into a current signal; and a sampling module connected to the input conversion module, configured to perform current integration sampling on the current signal and output a sampled voltage signal. The input conversion module of the embodiment of the present disclosure comprises a current buffer of a common-gate structure, the current buffer being configured to convert a received input voltage signal into a current signal, which can improve the linearity of voltage-to-current conversion, so that the sampling module performs current integration sampling on the current signal with high linearity, completes current integration sampling with high linearity, and has low power consumption, and the implementation is easy to integrate.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a current sampling circuit, an analog-to-digital converter front-end sampling device, and electronic equipment. Background Technology

[0002] A sample-and-hold front-end (SHU) circuit is a circuit that samples a continuous analog signal and outputs a stable sampled voltage during the "hold" phase. It is typically a key front-end module of an ADC (Analog-to-Digital Converter) to facilitate accurate digitization by the subsequent ADC stage. Therefore, the sampling circuit can convert continuous-time signals to discrete-time signals and is usually implemented using integrated circuits (chips).

[0003] The main performance indicators of a sampling circuit are fourfold: speed (sampling rate), input bandwidth, accuracy (linearity, signal-to-noise ratio), power consumption, and cost (chip area).

[0004] The sampling circuit of this invention belongs to the ultra-high-speed (sampling rate higher than 10GS / s) and ultra-wideband (input bandwidth higher than 10GHz) category. The main applications of this type of sampling circuit include wideband oscilloscopes, wired communication, wireless communication, and electronic warfare. Commonly used ultra-high-speed and ultra-wideband sampling circuits can generally be divided into voltage domain sampling circuits and current domain sampling circuits. Since the input analog signal is generally a voltage signal, the voltage domain sampling circuit can directly acquire the input voltage signal. Based on the natural MOS switching devices provided by CMOS technology, it can achieve high-precision, low-power sampling, and is currently the most widely used sampling circuit. Figure 1 As shown. However, the sampling circuit based on MOS switches requires a full-swing drive clock and suffers from parasitic resistance and capacitance inherent in the MOS transistor, which leads to severe performance degradation during ultra-high-speed and ultra-wideband sampling.

[0005] A switched emitter follower (SEF) is a voltage-domain sampling circuit commonly used in designs based on high-speed BiCMOS technology, such as... Figure 2 As shown. Since SEF performs sampling based on current-mode switching and directly switches the emitter follower itself, the driving clock swing can be smaller, and the parasitic resistance and capacitance of the sampling switch itself are also minimized, making it suitable for ultra-high-speed, ultra-wideband sampling circuits.

[0006] However, SEF suffers from severe sampling accuracy degradation when sampling high-frequency input signals due to the severe feedthrough effect and off-time modulation. Furthermore, since the voltage domain sampling circuit directly samples the instantaneous voltage signal, sampling clock jitter noise directly degrades the output signal-to-noise ratio of the sampling result, especially for high-frequency input signals.

[0007] To overcome the problem of voltage domain sampling circuit performance being significantly affected by clock jitter, current domain sampling circuits were initially proposed based on CMOS technology. Current domain sampling circuits first convert the input voltage into current using a transconductance amplifier, and then integrate and sample the signal current, such as... Figure 3 As shown, this sampling is equivalent to sampling within a time window, so its actual sampled value is the average value of the input signal within that sampling window, significantly reducing the sensitivity to noise introduced by the jitter of the sampling clock itself. However, the process of converting the input voltage into current and then integrating it introduces many parasitic nodes, making it difficult to achieve ultra-wideband sampling. Simultaneously, transconductance amplifiers struggle to achieve high-linearity voltage-to-current conversion, thus the sampling accuracy of this type of sampling circuit is often limited by its linearity. Although ultra-high-speed, ultra-wideband current-domain sampling circuits can be realized in recent years based on high-speed BiCMOS technology, their sampling accuracy is still limited by linearity performance. However, in practical product applications, the sampling circuit must be integrated with the back-end CMOS process ADC, and using BiCMOS technology to design the front-end sampling circuit incurs significant additional packaging and integration overhead.

[0008] Traditional current-domain sampling circuit structures implemented using CMOS technology, such as Figure 4 As shown.

[0009] The current-domain sampling circuit first converts the input voltage signal into a current signal. In high-speed circuit design, traditional solutions typically use a single-transistor common-source transconductance amplifier. However, considering that a large input voltage swing can cause severe nonlinear degradation, a common-source amplifier circuit with source negative feedback is used. A low-impedance path is created by switching on the integrating window, conducting the input signal current to the integrating capacitor to complete the sampling.

[0010] Due to the Miller multiplication effect, common-source amplifiers exhibit significant parasitic load capacitance at their input ports, severely degrading the signal bandwidth at the input node. Furthermore, the signal current, after generation, must pass through a series MOS switch before reaching the integrating capacitor, further attenuating the signal current, especially as the input signal frequency increases. Therefore, traditional current-domain sampling circuits implemented using CMOS technology suffer from severe attenuation at high frequencies, severely limiting signal bandwidth and making ultra-wideband sampling difficult. Simultaneously, although source-negative feedback common-source transconductance amplifiers can mitigate the nonlinear degradation caused by gate-source voltage modulation, the source voltage of this structure follows the input gate signal, while the drain voltage is out of phase with the input signal. This results in severe nonlinear degradation due to drain-source voltage modulation, as explained below. Figure 5 As shown. The nonlinear voltage-to-current conversion of this structure severely affects the sampling accuracy of the current domain sampling circuit.

[0011] In recent years, some works have overcome the input bandwidth limitation problem of current-domain sampling circuits based on CMOS technology by using high-speed SiGe HBT devices provided by high-speed SiGe BiCMOS technology, such as... Figure 6 As shown. Although the bandwidth issue was resolved by leveraging the advantages of SiGe technology, the same linearity degradation problem still exists in this type of circuit. Furthermore, due to the high operating voltage (>3V) of SiGe HBT devices, despite the same drive load and drive current, this type of sampling circuit requires a high-voltage power supply, resulting in significantly higher power consumption than current-domain sampling circuits based on CMOS technology.

[0012] Furthermore, since the sampling front-end circuit has a relatively small number of transistors and low integration density, it can be implemented using SiGe HBT technology. However, because the back-end ADC and other modules contain more complex and large-scale digital circuits, they need to be implemented based on advanced CMOS technology to significantly improve the performance of these digital circuits. Therefore, interconnection and integration between SiGe chips and CMOS chips are required. The additional high-speed sampling and holding analog signal transmission between chips requires high-bandwidth, high-linearity drive circuits, which significantly increases the power consumption and design complexity of SiGe chips. At the same time, because HBT transistors operate at higher voltages, even with the same circuit structure, they have higher power consumption compared to CMOS circuit implementations. Therefore, the power consumption of currently reported SiGe-based current-domain high-speed sampling circuit chips exceeding 100GS / s all exceed 1W.

[0013] In summary, current-domain high-speed sample-and-hold circuits in related technologies struggle to achieve a balance in terms of input bandwidth, linearity, power consumption, and integration. For ease of comparison, the advantages and disadvantages of current-domain high-speed sample-and-hold circuits in related technologies are summarized in Table 1.

[0014] Table 1

[0015] Summary of the Invention

[0016] In view of this, the present disclosure proposes a current sampling circuit, the circuit comprising:

[0017] An input conversion module, the input conversion module including a common-gate current buffer, the current buffer being used to convert a received input voltage signal into a current signal;

[0018] The sampling module, connected to the input conversion module, is used to perform current integration sampling on the current signal and output a sampled voltage signal.

[0019] In one possible implementation, the current buffer includes a first input resistor, a second input resistor, a first switching transistor, and a second switching transistor, wherein,

[0020] The first terminal of the first input resistor and the first terminal of the second input resistor are used to receive input voltage signals.

[0021] The second terminal of the first input resistor is connected to the source of the first switching transistor, and the second terminal of the second input resistor is connected to the source of the second switching transistor.

[0022] The gate of the first switching transistor is connected to the gate of the second switching transistor.

[0023] The drains of the first and second switching transistors are connected to the input terminal of the sampling module.

[0024] In one possible implementation, the input conversion module further includes a coupling input unit and a coupling output unit.

[0025] The input voltage signal is input to the current buffer through the coupling input unit.

[0026] The current signal is output to the sampling module through the coupling output unit.

[0027] The coupling output unit is further configured to receive a common-gate bias voltage signal and input it to the gate of the first conversion transistor and the gate of the second conversion transistor.

[0028] In one possible implementation, the coupling input unit includes a first input transformer, a second input transformer, a first input transistor, and a second input transistor, wherein,

[0029] The first terminal of the primary winding of the first input transformer is used to receive the positive voltage signal of the input voltage signal.

[0030] The first terminal of the primary winding of the second input transformer is used to receive the negative voltage signal of the input voltage signal.

[0031] The second end of the primary winding of the first input transformer is connected to the first end of the first input resistor.

[0032] The second end of the primary winding of the second input transformer is connected to the first end of the second input resistor.

[0033] The first terminal of the secondary winding of the first input transformer and the first terminal of the secondary winding of the second input transformer are both used to receive the first bias voltage.

[0034] The second end of the secondary winding of the second input transformer is connected to the gate of the second input transistor.

[0035] The drain of the first input transistor is connected to the source of the first switching transistor and the second terminal of the first input resistor.

[0036] The drain of the second input transistor is connected to the source of the second switching transistor and the second terminal of the second input resistor.

[0037] The source of both the first input transistor and the source of the second input transistor are grounded.

[0038] In one possible implementation, the coupling input unit further includes a first electrostatic discharge diode and a second electrostatic discharge diode, wherein...

[0039] The first electrostatic discharge diode is connected to the drain of the first input transistor, the second terminal of the first input resistor, and the source of the first switching transistor.

[0040] The second electrostatic discharge diode is connected to the drain of the second input transistor, the second terminal of the second input resistor, and the source of the second switching transistor.

[0041] The input voltage signal is fed into the coupling input unit through the pads.

[0042] In one possible implementation, the coupling output unit includes a first output transformer and a second output transformer, wherein,

[0043] The first end of the primary winding of the first output transformer and the first end of the primary winding of the second output transformer are connected to receive the common gate bias voltage signal.

[0044] The second end of the primary winding of the first output transformer and the second end of the primary winding of the second output transformer are respectively connected to the gate of the first conversion transistor and the gate of the second conversion transistor.

[0045] The first terminal of the secondary winding of the first output transformer is connected to the drain of the first conversion transistor, and the second terminal of the secondary winding of the first output transformer is used to output the positive signal of the current signal.

[0046] The first end of the secondary winding of the second output transformer is connected to the drain of the second conversion transistor, and the second end of the secondary winding of the second output transformer is used to output the negative signal of the current signal.

[0047] In one possible implementation, the input conversion module further includes an auxiliary common-source unit.

[0048] The auxiliary common-source unit includes a first auxiliary capacitor, a second auxiliary capacitor, a first auxiliary transistor, a second auxiliary transistor, a first auxiliary resistor, and a second auxiliary resistor, wherein...

[0049] The first terminal of the first auxiliary capacitor is connected to the source of the second switching transistor and the second terminal of the second input resistor.

[0050] The second terminal of the first auxiliary capacitor is connected to the gate of the first auxiliary transistor to receive the second bias voltage through the first auxiliary resistor.

[0051] The drain of the first auxiliary transistor is connected to the drain of the first switching transistor.

[0052] The first terminal of the second auxiliary capacitor is connected to the source of the first switching transistor and the second terminal of the first input resistor.

[0053] The second terminal of the second auxiliary capacitor is connected to the gate of the second auxiliary transistor to receive the second bias voltage through the second auxiliary resistor.

[0054] The drain of the second auxiliary transistor is connected to the drain of the second switching transistor.

[0055] The source of the second auxiliary transistor and the source of the first auxiliary transistor are both grounded.

[0056] In one possible implementation, the sampling module includes multiple sampling units, each sampling unit including a first sampling capacitor, a second sampling capacitor, a first sampling transistor, a second sampling transistor, a first CML transistor, and a second CML transistor, wherein...

[0057] The source of the first CML transistor and the source of the second CML transistor are used to receive the current signal.

[0058] The gate of the first CML transistor is connected to the gate of the second CML transistor.

[0059] The drain of the first CML transistor, the first terminal of the first sampling capacitor, and the drain of the first sampling transistor are connected together to form the first output terminal of the sampling module.

[0060] The drain of the second CML transistor is connected to the first terminal of the second sampling capacitor and the drain of the second sampling transistor, serving as the second output terminal of the sampling module. The first output terminal and the second output terminal are used to output the sampled voltage signal.

[0061] The gate of the first sampling transistor is connected to the gate of the second sampling transistor.

[0062] The source of both the first sampling transistor and the source of the second sampling transistor are used to receive the power supply voltage.

[0063] The second terminal of the first sampling capacitor and the second sampling capacitor are both grounded.

[0064] In one possible implementation, the sampling module further includes a first reset transistor and a second reset transistor, wherein,

[0065] The gates of the first reset transistor and the second reset transistor are both connected to the gates of the first sampling transistor and the second sampling transistor, respectively.

[0066] The source of the first reset transistor and the drain of the second reset transistor are both connected to the second output terminal.

[0067] The source of the second reset transistor and the drain of the first reset transistor are both connected to the first output terminal.

[0068] In one possible implementation, the current sampling circuit further includes a driving module, which includes at least one driving unit, wherein any driving unit includes a first driving capacitor, a first driving transistor, a second driving capacitor, a second driving transistor, a first driving resistor, and a second driving resistor, wherein...

[0069] The first terminal of the first driving capacitor and the first terminal of the second driving capacitor are used to receive the sampled voltage signal.

[0070] The second terminal of the first driving capacitor is connected to the first terminal of the first driving resistor and the gate of the first driving transistor. The second terminal of the first driving resistor is used to receive the first bias voltage.

[0071] The second terminal of the second driving capacitor is connected to the first terminal of the second driving resistor and the gate of the second driving transistor. The second terminal of the second driving resistor is used to receive the second bias voltage.

[0072] The source of the first driving transistor and the drain of the second driving transistor are connected together to serve as the output terminal of the driving module, which is used to output a driving signal.

[0073] The drain of the first driving transistor is grounded, and the source of the second driving transistor is connected to the power supply voltage.

[0074] According to one aspect of this disclosure, a front-end sampling device for an analog-to-digital converter is provided, the sampling device comprising:

[0075] The first-stage sampling component includes the aforementioned current sampling circuit;

[0076] The second-level sampling component is connected to the first-level sampling component, and the second-level sampling component includes a multi-channel bootstrap sampling circuit;

[0077] A third-level sampling component is connected to the second-level sampling component, and the third-level sampling component includes an extraction sampler;

[0078] A clock generation unit is connected to the first-level sampling component, the second-level sampling component, and the third-level sampling component. It is used to provide clock signals to each level of the sampling component. The falling edge of the clock signal of the second-level sampling component is aligned with the end time of the hold phase of the clock signal of the first-level sampling component, and the falling edge of the clock signal of the third-level sampling component is aligned with the end time of the hold phase after sampling in the clock signal of the second-level sampling component.

[0079] In one possible implementation, the third-level sampling component includes a push-pull buffer, a downsampling circuit unit, and a driving circuit connected in sequence.

[0080] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the current sampling circuit, or the current sampling circuit described above.

[0081] The input conversion module of this embodiment includes a common-gate current buffer. The current buffer converts the received input voltage signal into a current signal, which can improve the linearity of voltage-to-current conversion. This allows the sampling module to use the high-linearity current signal for current integration sampling, achieving high-linearity current integration sampling with low power consumption and easy integration.

[0082] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0083] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0084] Figure 1 A schematic diagram of a voltage domain sampling circuit based on a MOS switch is shown.

[0085] Figure 2 A schematic diagram of a voltage domain sampling circuit based on SEF is shown;

[0086] Figure 3 A schematic diagram of a current domain sampling circuit in the related art is shown;

[0087] Figure 4 A schematic diagram of a current-domain sampling circuit structure based on CMOS technology is shown in the related technology;

[0088] Figure 5 A schematic diagram illustrating the principle of linearity degradation in a current-domain sampling circuit based on CMOS technology is shown in the relevant technology.

[0089] Figure 6 A schematic diagram of a current-domain sampling circuit based on SiGe BiCMOS technology is shown in the relevant technology.

[0090] Figure 7 A schematic diagram of a current sampling circuit according to an embodiment of the present disclosure is shown;

[0091] Figure 8 A schematic diagram of a common gate structure according to an embodiment of the present disclosure is shown;

[0092] Figure 9 A schematic diagram of a transformer magnetic coupling peaking broadening structure according to an embodiment of the present disclosure is shown;

[0093] Figure 10 A schematic diagram of a current sampling circuit according to an embodiment of the present disclosure is shown;

[0094] Figure 11A schematic diagram of a current sampling circuit according to an embodiment of the present disclosure is shown;

[0095] Figure 12a A schematic diagram of a drive unit 310 according to an embodiment of the present disclosure is shown;

[0096] Figure 12b A schematic diagram of the sampling circuit's operating cycle is shown.

[0097] Figure 13 A schematic diagram of an analog-to-digital converter front-end sampling device according to an embodiment of the present disclosure is shown;

[0098] Figure 14 A schematic diagram of an analog-to-digital converter front-end sampling device according to an embodiment of the present disclosure is shown;

[0099] Figure 15 It shows Figure 14 The timing diagram of the front-end sampling device of the analog-to-digital converter is shown. Detailed Implementation

[0100] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0101] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0102] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0103] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are used only to distinguish one element / operation from another. Therefore, without departing from the teachings of the conception of embodiments of this disclosure, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0104] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0105] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0106] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0107] Please see Figure 7 , Figure 7 A schematic diagram of a current sampling circuit according to an embodiment of the present disclosure is shown.

[0108] like Figure 7 As shown, the circuit includes:

[0109] The input conversion module 10 includes a common-gate current buffer, which is used to convert the received input voltage signal into a current signal.

[0110] The sampling module 20 is connected to the input conversion module 10 and is used to perform current integration sampling on the current signal and output a sampled voltage signal.

[0111] The input conversion module 10 of this embodiment includes a common-gate current buffer. The common-gate current buffer converts the received input voltage signal into a current signal, which can improve the linearity of the voltage-to-current conversion. This allows the sampling module 20 to use the high-linearity current signal for current integration sampling, achieving high-linearity current integration sampling with low power consumption and easy integration.

[0112] The present invention does not limit the specific implementation of the input conversion module 10 and the sampling module 20. Those skilled in the art can sample appropriate technical solutions to implement them, as long as the corresponding functions can be achieved.

[0113] The embodiments disclosed herein do not limit the specific implementation of the common-gate current buffer. Those skilled in the art can adopt a suitable circuit structure to implement it according to actual conditions and needs.

[0114] Please see Figure 8 , Figure 8 A schematic diagram of a common gate structure according to an embodiment of the present disclosure is shown.

[0115] like Figure 8 As shown in the right figure, when a large-swing voltage signal is input, since the common-gate input point is a low-impedance node, most of the input signal voltage will be applied to the passive resistor and converted into a current signal input to the common gate through the passive resistor device. Since the passive device is inherently linear, the current signal converted by the passive resistor is also inherently linear.

[0116] like Figure 8 As shown in the left figure, in the related technology, the common-source amplifier based on the source negative feedback structure can also absorb a large input swing and improve the nonlinearity introduced by the VGS change by means of the source resistance negative feedback. However, since its source voltage changes with the input signal almost at full swing, and the drain will have an inverse change of the input signal, there will be very serious nonlinearity caused by VDS modulation in the transconductor.

[0117] like Figure 8 As shown in the right figure, the embodiments of this disclosure propose a common-gate hybrid structure. Since most of the input swing is directly absorbed at the input through the resistor, the source of the common-gate input transistor only sees a small swing change, which is different from that of the common-source transistor. In addition, the source and drain signals of the common-gate transistor are in phase. Therefore, when the source and drain node impedances of the common-gate input transistor are close, the common-gate structure proposed in the embodiments of this disclosure can achieve the elimination of VDS modulation and achieve higher linearity.

[0118] Furthermore, in the embodiments of this disclosure, a transformer magnetic coupling peaking broadening structure can be further set in the current sampling circuit to offset the high-frequency loss caused by parasitic capacitance in the path and improve the bandwidth expansion capability. The principle is first explained by example.

[0119] Please see Figure 9 , Figure 9 A schematic diagram of a transformer magnetic coupling peaking broadening structure according to an embodiment of the present disclosure is shown.

[0120] This embodiment of the disclosure uses a transformer magnetic coupling peaking broadening structure to offset parasitic capacitance losses on the direct transmission path of the input signal, and also uses a bypass inductor to connect to the gate-source capacitance C of the common-gate transistor. GS and the gate-drain capacitance C of the bias transistor GD To create a negative resistance of appropriate strength to compensate for the high-frequency losses of the transistor.

[0121] Figure 9In the circuit, the MOSFET with its source grounded is the bias transistor (acting as a current source to determine the bias current of this branch), while the MOSFET above it is a common-gate transistor. Due to the magnetic field coupling between the main and secondary coil inductances of the transformer, the voltage signal on the inductor through the signal path will be coupled to the gates of the bias transistor and the common-gate transistor, forming a certain strength of negative resistance (positive feedback). Since the signal coupling of the inductor gradually increases with frequency (until the self-resonant frequency of the circuit), the negative resistance effect is mainly manifested at high frequencies.

[0122] The embodiments disclosed herein can use the main and auxiliary coils of two sets of transformers to achieve the function of the discrete inductors mentioned above. The structure that originally required four sets of discrete inductors in a single-ended circuit can be completed by using the transformer, which only requires the area of ​​two sets of discrete inductors, reducing the area overhead by half. At the same time, the high-frequency magnetic coupling effect of the transformer further provides a passive voltage gain path for high-frequency input signals, thereby expanding the high-frequency bandwidth.

[0123] like Figure 9 As shown, the two coils below form one set of transformers, and the two coils above form another set of transformers.

[0124] Among them, V IN It is the input signal; V b2 This is the bias voltage signal applied to the gate of the bias transistor in this circuit (used to define the bias current of this circuit); V g This refers to the gate bias voltage of the common-gate transistor. It needs to be placed within a suitable voltage range to ensure that the common-gate transistor and the bias transistor below it operate in the saturation region.

[0125] For example, instead of a transformer, four inductor coils can be used. This method also has a certain bandwidth expansion effect because the parasitic capacitance on the signal path will resonate with the inductor, and the inductor on the bias path will form a high-frequency positive feedback path with the parasitic capacitance, both of which will help increase the bandwidth.

[0126] However, if a transformer is not constructed (i.e., the four inductor coils are independent and have no magnetic field coupling), then four inductors need to be placed independently, occupying the area of ​​four inductor blocks (in actual chips, the area required by inductors is enormous; the area of ​​one coil may be larger than the total area of ​​all other MOS circuits). But if a transformer is formed, the main and auxiliary coils can usually be nested in pairs, ultimately occupying only the area of ​​two independent inductors. Therefore, the area overhead in the physical implementation of the chip can be reduced by half.

[0127] At the same time, the transformer itself provides additional magnetic field coupling between the main and auxiliary coils compared to four independent inductors, further strengthening the high-frequency positive feedback (negative resistance) of the circuit, thus further improving the bandwidth expansion capability.

[0128] Therefore, using only four independent inductors would result in a loss of area advantage and would not be as good as using a transformer in terms of high-frequency bandwidth expansion.

[0129] Of course, the specific circuit implementation of the common gate structure and the specific implementation circuit of transformer magnetic coupling peaking broadening are not limited in the embodiments disclosed herein. Those skilled in the art can refer to relevant technologies to implement them according to actual conditions and needs. The preferred embodiments are described below by way of example.

[0130] Please see Figure 10 , Figure 10 A schematic diagram of a current sampling circuit according to an embodiment of the present disclosure is shown.

[0131] In one possible implementation, such as Figure 10 As shown, the current buffer may include a first input resistor R. in1 Second input resistor R in2 First switching transistor Q c1 Second switching transistor Q c2 ,in,

[0132] The first input resistor R in1 The first terminal and the second input resistor R in2 The first terminal is used to receive the input voltage signal (V). ip V in ),

[0133] The first input resistor R in1 The second terminal is connected to the first switching transistor Q. c1 The source, the second input resistor R in2 The second terminal is connected to the second switching transistor Q. c2 The source pole,

[0134] The first switching transistor Q c1 The gate of the second switching transistor Q is connected. c2 The gate,

[0135] The first switching transistor Q c1 The drain of the second switching transistor Q c2 The drain is connected to the input terminal of the sampling module 20.

[0136] Among them, the first switching transistor Q c1 Second switching transistor Q c2 It can be an NMOS transistor, or other types of transistors. This disclosure does not limit the embodiments, and those skilled in the art can set it according to the actual situation and needs.

[0137] For example, the first input resistance Rin1 Second input resistor R in2 It can be a variable resistor

[0138] This disclosure embodiment is illustrated by, as follows Figure 10 The first input resistor R shown in1 Second input resistor R in2 First switching transistor Q c1 Second switching transistor Q c2 The connection method implemented in this embodiment realizes a common gate hybrid structure with differential input mode, which has been exemplarily described. Of course, in other embodiments, the common gate hybrid structure may also include other devices and be implemented in other ways. In this regard, the embodiments disclosed herein do not limit the scope of the invention.

[0139] In one possible implementation, such as Figure 10 As shown, the input conversion module 10 may further include a coupling input unit 110 and a coupling output unit 120.

[0140] The input voltage signal is input to the current buffer through the coupling input unit 110.

[0141] The current signal is output to the sampling module 20 through the coupling output unit 120.

[0142] The coupling output unit 120 is further configured to receive a common-gate bias voltage signal (Vg) and input it to the first switching transistor Q. c1 The gate of the second switching transistor Q c2 The gate.

[0143] In this embodiment, both the coupling input unit 110 and the coupling output unit 120 can offset the high-frequency loss caused by parasitic capacitance in the path and improve the bandwidth expansion capability. Of course, the coupling input unit 110 and the coupling output unit 120 can be implemented using a separate inductor or a transformer. In this embodiment, a transformer structure is preferred to implement the coupling input unit 110 and the coupling output unit 120. Compared with the solution implemented using a separate inductor, the area overhead can be reduced by half, and additional magnetic field coupling of the main and secondary coils can be provided to further enhance the high-frequency positive feedback (negative resistance) strength of the circuit. Therefore, the bandwidth expansion capability can be further improved.

[0144] In one possible implementation, such as Figure 10 As shown, the coupling input unit 110 may include a first input transformer TF1, a second input transformer TF2, and a first input transistor Q. in1 The second input transistor Q in2 ,in,

[0145] The primary winding (L) of the first input transformer TF1 i The first terminal is used to receive the positive voltage signal (V) of the input voltage signal. ip ),

[0146] The primary winding (L) of the second input transformer TF2 i The first terminal is used to receive the negative voltage signal (V) of the input voltage signal. in ),

[0147] The second end of the primary winding of the first input transformer TF1 is connected to the first input resistor R. in1 The first end,

[0148] The second end of the primary winding of the second input transformer TF2 is connected to the second input resistor R. in2 The first end,

[0149] The secondary winding (L) of the first input transformer TF1 b The first terminal of the input transformer TF2 and the first terminal of the secondary winding of the second input transformer TF2 are both used to receive the first bias voltage (Vb2).

[0150] The secondary winding (L) of the second input transformer TF2 b The second terminal of the transistor is connected to the second input transistor Q. in2 The gate,

[0151] The first input transistor Q in1 The drain of the transistor is connected to the first switching transistor Q. c1 The source and the first input resistor R in1 The second end,

[0152] The second input transistor Q in2 The drain of the transistor is connected to the second switching transistor Q. c2 The source and the second input resistor R in2 The second end,

[0153] The first input transistor Q in1 The source and the second input transistor Q in2 The source electrodes are all grounded.

[0154] This disclosure embodiment relates to the first input transistor Q. in1 The second input transistor Q in2 The type of transistor is not limited; those skilled in the art can set it according to actual conditions and needs. For example, the first input transistor Q... in1 The second input transistor Q in2 It can be an NMOS transistor.

[0155] The embodiments disclosed herein do not limit the transformation ratio of the first input transformer TF1 and the second input transformer TF2, which can be set by those skilled in the art according to actual conditions and needs.

[0156] In one possible implementation, such as Figure 10 As shown, the coupling input unit 110 may further include a first electrostatic discharge diode C. ESD1 Second electrostatic discharge diode C ESD2 ,in

[0157] The first electrostatic discharge diode C ESD1 Connected to the first input transistor Q in1 The drain of the first input resistor R in1 The second terminal and the first switching transistor Q c1 The source pole,

[0158] The second electrostatic discharge diode C ESD2 Connected to the second input transistor Q in2 The drain of the second input resistor R in2 The second terminal and the second switching transistor Q c2 The source pole,

[0159] The input voltage signal is transmitted through the pad (C). pad The signal is fed into the coupling input unit 110.

[0160] In one possible implementation, such as Figure 10 As shown, the coupling output unit 120 may include a first output transformer TF3 and a second output transformer TF4, wherein,

[0161] The primary winding (L) of the first output transformer TF3 g The first terminal of the second output transformer TF4 and the primary winding (L) g The first terminal of the signal is connected to the common gate bias voltage signal (Vg).

[0162] The primary winding (L) of the first output transformer TF3 g The second terminal of the second output transformer TF4 and the primary winding (L) g The second terminal of the transistor is connected to the first switching transistor Q. c1 The gate of the second switching transistor Q c2 The gate,

[0163] The secondary winding (L) of the first output transformer TF3 d The first terminal of the transistor is connected to the first switching transistor Q. c1The drain of the first output transformer TF3, the secondary winding (L) d The second terminal is used to output the positive signal of the current signal.

[0164] The secondary winding (L) of the second output transformer TF4 d The first terminal of the transistor is connected to the second switching transistor Q. c2 The drain of the second output transformer TF4, the secondary winding (L) d The second terminal is used to output the negative signal of the current signal.

[0165] In this embodiment of the disclosure, although the conversion gain of the common-gate hybrid structure is limited by input impedance matching, an auxiliary common-source stage can be introduced from the low-impedance node of the common-gate input transistor's source to compensate for the low-frequency gain. Since the node swing is sufficiently small and the VGS modulation effect is weak, the common-source transistor does not require a source negative feedback resistor, thus ensuring sufficient VDS margin. Therefore, the auxiliary common-source stage will not degrade the linearity of the original circuit.

[0166] The following example illustrates the common-source circuit structure.

[0167] In one possible implementation, such as Figure 10 As shown, the input conversion module 10 may further include an auxiliary common-source unit 130.

[0168] The auxiliary common-source unit 130 includes a first auxiliary capacitor Cf1, a second auxiliary capacitor Cf2, a first auxiliary transistor Qf1, a second auxiliary transistor Qf2, a first auxiliary resistor Rf1, and a second auxiliary resistor Rf2, wherein,

[0169] The first terminal of the first auxiliary capacitor Cf1 is connected to the source of the second switching transistor Qc2 and the second terminal of the second input resistor Rin2.

[0170] The second terminal of the first auxiliary capacitor Cf1 is connected to the gate of the first auxiliary transistor Qf1 to receive the second bias voltage Vb1 through the first auxiliary resistor Rf1.

[0171] The drain of the first auxiliary transistor Qf1 is connected to the drain of the first switching transistor Qc1.

[0172] The first terminal of the second auxiliary capacitor Cf2 is connected to the source of the first switching transistor Qc1 and the second terminal of the first input resistor Rin1.

[0173] The second terminal of the second auxiliary capacitor Cf2 is connected to the gate of the second auxiliary transistor Qf2 to receive the second bias voltage Vb1 through the second auxiliary resistor Rf2.

[0174] The drain of the second auxiliary transistor Qf2 is connected to the drain of the second switching transistor Qc2.

[0175] The source of the second auxiliary transistor Qf2 and the source of the first auxiliary transistor Qf1 are both grounded.

[0176] The embodiments disclosed herein do not limit the specific transistor types of the first auxiliary transistor Qf1 and the second auxiliary transistor Qf2. Those skilled in the art can set them according to actual conditions and needs. For example, the first auxiliary transistor Qf1 and the second auxiliary transistor Qf2 can be NMOS transistors.

[0177] In one possible implementation, such as Figure 10 As shown, the sampling module 20 may include multiple sampling units 140, and each sampling unit 140 may include a first sampling capacitor C. S1 Second sampling capacitor C S2 The first sampling transistor Q cy1 The second sampling transistor Q cy2 The first CML transistor Q cml1 and the second CML transistor Q cml2 ,in,

[0178] The first CML transistor Q cml1 The source of the second CML transistor Q cml2 The source is used to receive the current signal.

[0179] The first CML transistor Q cml1 The gate of is connected to the gate of the second CML transistor.

[0180] The first CML transistor Q cml1 The drain of the first sampling capacitor C S1 The first terminal and the first sampling transistor Q cy1 The drain of the sample module 20 is connected to the first output terminal of the sampling module 20.

[0181] The second CML transistor Q cml2 The drain of the second sampling capacitor C S2 The first terminal and the second sampling transistor Q cy2 The drain of the first output terminal is connected to the second output terminal of the sampling module 20. The first output terminal and the second output terminal are used to output the sampled voltage signal.

[0182] The first sampling transistor Q cy1 The gate of the second sampling transistor Q is connected. cy2 The gate,

[0183] The first sampling transistor Q cy1 The source of the second sampling transistor Q cy2 The sources are all used to receive the power supply voltage.

[0184] The first sampling capacitor C S1 The second terminal, the second sampling capacitor C S2 The second end of each is grounded.

[0185] This disclosure embodiment relates to the first sampling transistor Q. cy1 The second sampling transistor Q cy2 The first CML transistor Q cml1 and the second CML transistor Q cml2 The specific transistor type is not limited; those skilled in the art can set it according to the actual situation and needs. For example, the first sampling transistor Q... cy1 The second sampling transistor Q cy2 It can be a PMOS transistor, the first CML transistor Q cml1 and the second CML transistor Q cml2 It is an NMOS transistor.

[0186] The sampling units 140 can be arranged in an interleaved manner, and the first CML transistor Q of the interleaved sampling units cml1 The source of the second CML transistor Q cml2 The sources of each sample unit 140 receive the current signal, and the first output terminals of each sample unit 140 are connected together, as are the second output terminals of each sample unit 140.

[0187] In one possible implementation, such as Figure 10 As shown, the sampling module 20 may further include a first reset transistor Q. fy1 The second reset transistor Q fy2 ,in,

[0188] The first reset transistor Q fy1 The gate of the second reset transistor Q fy2 The gates of all are connected to the first sampling transistor Q. cy1 The gate of the second sampling transistor Q cy2 The gate,

[0189] The first reset transistor Q fy1 The source of the second reset transistor Q fy2 The drains of all three terminals are connected to the second output terminal.

[0190] The second reset transistor Q fy2 The source of and the first reset transistor Q fy1The drains of all terminals are connected to the first output terminal.

[0191] For example, the first CML transistor Q cml1 and the second CML transistor Q cml2 The gate terminal receives the gate control signal and the first reset transistor Q. fy1 The second reset transistor Q fy2 The first sampling transistor Q cy1 The second sampling transistor Q cy2 The gate control signals are 90° out of phase.

[0192] This disclosure describes an embodiment of the first reset transistor Q. fy1 The second reset transistor Q fy2 The specific transistor type is not limited; those skilled in the art can set it according to actual conditions and needs. For example, the first reset transistor Q... fy1 The second reset transistor Q fy2 It can be a PMOS transistor.

[0193] The following is about Figure 10 The circuit structure of the current sampling circuit shown is described in its entirety.

[0194] For example, such as Figure 10 As shown, the high-frequency differential input analog voltage signals (Vip and Vin) are respectively drawn from the primary winding (L) of the first input transformer TF1. i The first end of the second input transformer TF2 and the primary winding (L) i Feed into the first end of the feed.

[0195] In order to complete current integration sampling, the input voltage signal needs to be converted from voltage to current.

[0196] This disclosure relies on the embodiments of the present disclosure. Figure 10 The common-gate current buffer, marked by the blue shading, completes the voltage-to-current conversion.

[0197] First, for ease of understanding, consider analyzing the signal flow at low frequencies (ignoring...). Figure 10 (inductance and transformer), input voltage signal (V) ip and V in After feeding in, because the input impedance of the common-gate amplifier is low, the two input resistors (R) in1 R in2 It will withstand a large input voltage swing, completing a linear voltage-to-current conversion. From a formula perspective, Figure 10In a common-gate current buffer, the low-frequency input impedance is approximately Rin + 1 / gm. If Rin >> 1 / gm (where gm is the transconductance of the common-gate amplifier and 1 / gm is the input impedance of the common-gate amplifier), then it can be approximated as... Figure 10 The low-frequency input impedance of the structure is only Rin (the resistance value of the input resistor), while the two input resistors (R... in1 R in2 As a passive resistor, it exhibits excellent voltage-to-current linearity. Therefore, after passing through two input resistors (R... in1 R in2 With a common gate transistor and a common gate transistor, the input voltage signal is linearly converted into an input current signal.

[0198] For example, when the input frequency increases, the parasitic capacitance of each node in the circuit will shunt the input signal current, so the integral gain of the circuit will have a large high-frequency attenuation at high frequencies. The embodiments of this disclosure solve this problem through the aforementioned transformer magnetic coupling bandwidth extension scheme, i.e., a series of optimization methods.

[0199] For example, to implement current integration sampling, after completing the signal voltage-to-current conversion, the input signal current needs to be integrated on the sampling capacitor within a certain time window (i.e., the current continuously excites the capacitor). The final integrated voltage on the capacitor is the final sampled voltage. This is the operation of current integration sampling.

[0200] The current integral control timing used in this embodiment feeds the current signal sequentially into multiple (e.g., 4 channels, i.e., including 4 sampling units 140) interleaved CML (Current Mode Logic) switches.

[0201] For example, four CML switches (purple shaded in the figure) are turned on sequentially at a speed of fs / 4 and a phase interval of 1 / fs. Current integration sampling is completed through four fs / 4 switches with different initial phases, which is equivalent to achieving an fs sampling rate.

[0202] Related technologies employ heterojunction bipolar transistor (HBT) technology to implement similar control logic. However, only n-type bipolar junction transistors (BJTs) can be used for resetting the integrating capacitor. Therefore, the control signal for the reset switch needs to be raised to an additional common-mode level (usually based on AC coupling at high frequencies), which inevitably introduces additional insertion loss and increases power consumption. At the same time, the size of the reset transistor will be very large, making it difficult to control the parasitic capacitance of the output node, which will affect the integration gain (the integration gain is inversely proportional to the size of the output capacitor).

[0203] Of course, the embodiments of this disclosure can use P-type transistors based on CMOS technology, and a differential reset switch can also be introduced to reduce the output parasitic capacitance.

[0204] The integral sampling switch structure proposed in this disclosure uses an NMOS transistor as the CML switch (the first CML transistor Q). cml1 and the second CML transistor Q cml2 The high-speed switch control channel switching is completed, and the reset transistor is implemented using a PMOS.

[0205] In related technologies, the current-domain overlapping sampling circuit proposed based on SiGe HBT technology only uses a single-ended reset structure. To ensure the reset effect, the size of the reset transistor will be very large, significantly increasing the additional parasitic contribution of the integrating sampling capacitance and causing a serious deterioration in the integrating sampling gain.

[0206] This disclosed embodiment additionally incorporates a differential reset structure (first reset transistor Q). fy1 The second reset transistor Q fy2 ).

[0207] The current-domain high-speed sample-and-hold circuit of this disclosure has four main advantages over existing methods:

[0208] 1. Compared with existing voltage domain high-speed sample-and-hold circuits, it improves sampling accuracy (signal-to-noise ratio, linearity).

[0209] 2. Compared with existing current-domain high-speed sample-and-hold circuits based on CMOS technology, it improves sampling linearity and sampling bandwidth.

[0210] 3. Compared with existing current-domain high-speed sample-and-hold circuits based on SiGe BiCMOS technology, it improves sampling linearity and reduces system power consumption and back-end integration complexity.

[0211] 4. Combining the characteristics of current domain integral sampling, an automatic gated shutdown Hold Buffer mechanism was implemented, which improved the energy efficiency of the sampling circuit system.

[0212] At the application level, the embodiments disclosed herein can be used as a single-channel sampling circuit in wireless communication receivers as a front-end direct sampling / undersampling circuit; they can also be used as a multi-channel interleaved sampling circuit in high-speed real-time oscilloscope front-end sampling circuits and high-speed wired communication receiver front-end sampling circuits. They primarily serve back-end ultra-high-speed (sampling rate higher than 10GS / s) and medium-to-low precision (6-8 bit quantization accuracy) ADC products.

[0213] Of course, the present disclosure does not limit the specific application scenarios of the current sampling circuit. Those skilled in the art can apply it to suitable scenarios according to actual conditions and needs.

[0214] The advantages of the current sampling circuit in this disclosure will solve the problems of deteriorated sampling circuit accuracy, limited input bandwidth, and high system overhead in these products under high sampling rates and high-frequency signal inputs. The control transistor can significantly reduce the size of the reset transistor while achieving the same reset effect, avoiding severe degradation of the integral sampling gain.

[0215] The current sampling circuit in this embodiment has a low-impedance input and can be directly used as the input termination stage of the ADC front end without the need for an additional input buffer and termination circuit. Furthermore, to optimize input bandwidth and broadband matching performance, the electrostatic discharge (ESD) protection diode is placed at the low-impedance source node of the common gate stage, separated from the pad (C). pad This minimizes parasitic effects and achieves ultra-high input bandwidth and wideband impedance matching performance.

[0216] Please see Figure 11 , Figure 11 A schematic diagram of a current sampling circuit according to an embodiment of the present disclosure is shown.

[0217] In one possible implementation, such as Figure 11 As shown, the current sampling circuit may further include a driving module 30, which may include at least one driving unit 310.

[0218] Since the sample-and-hold circuit itself has no driving capability, after the current domain sampling is completed, the driving module 30 is needed to pass the sampled and held signal to the subsequent circuit.

[0219] The specific implementation of the driving module 30 in this embodiment is not limited. For example, it may include a hold buffer as the driving unit 310. Of course, the specific circuit structure of the hold buffer is not limited in this embodiment. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0220] The preferred implementation of the driving unit 310 in the present disclosure will be described below by way of example.

[0221] Please see Figure 12a , Figure 12a A schematic diagram of a drive unit 310 according to an embodiment of the present disclosure is shown.

[0222] Any driving unit 310 may include a first driving capacitor C i1 First driving transistor Qi1 Second driving capacitor C i2 Second driving transistor Q i2 First driving resistor R i1 Second driving resistor R i2 ,in,

[0223] The first driving capacitor C i1 The first terminal and the second driving capacitor C i2 The first terminal is used to receive the sampled voltage signal (V ip V in ),

[0224] The first driving capacitor C i1 The second end is connected to the first driving resistor R i1 The first terminal and the first driving transistor Q i1 The gate, the first driving resistor R i1 The second terminal is used to receive the first bias voltage (V b2 ),

[0225] The second driving capacitor C i2 The second end is connected to the second driving resistor R i2 The first terminal and the second driving transistor Q i2 The gate, the second driving resistor R i2 The second terminal is used to receive the second bias voltage (V b1 ),

[0226] The first driving transistor Q i1 The source and the second driving transistor Q i2 The drain of the circuit is connected to serve as the output terminal of the driving module 30, and the output terminal of the driving module 30 is used to output a driving signal (V). op ),

[0227] The first driving transistor Q i1 The drain of the second driving transistor Q is grounded. i2 The source is connected to the power supply voltage.

[0228] For example, the first driving transistor Q i1 Second driving transistor Q i2 Both can be PMOS transistors.

[0229] This disclosure proposes an embodiment for the high-efficiency buffer current sampling circuit's sampling module 20 after integration and sampling-holding, which uses the following method to achieve the desired output result. Figure 12aThe driving unit 310 is implemented using a hybrid structure of a PMOS source follower-common source amplifier. The circuit structure of the driving unit 310 can achieve automatic gating on and off by means of the change in the common-mode voltage output by the current domain sampling switch.

[0230] For example, the workflow of the current sampling circuit may include "Reset (RST) - Integrate (INTE) - Hold (HOLD)" to complete one cycle of sampling and holding. The working timing of the current sampling circuit is described below as an example.

[0231] Please see Figure 12b , Figure 12b A schematic diagram of the sampling circuit's operating cycle is shown.

[0232] For example, such as Figure 12b As shown, the first sampling unit CH1 will be used as an example for introduction.

[0233] When the sampling circuit is in the reset ("RST1" and "RST2") phase, Figure 10 The differential output result of the sampling circuit shown (V) op1 V on1 The input common-mode voltage V of the drive module 30 is 0. i,cm Through the first driving transistor Q i1 Second driving transistor Q i2 When the device is reset to VDD, the |VGS| of the input transistor of the drive unit will decrease, turning off the drive unit and thus reducing static power consumption.

[0234] Figure 12a In the middle, V i,cm for Figure 10 The common-mode voltage of the output differential nodes Vop and Von (i.e., the output voltage signal when the input differential signal is 0, or the average voltage of the two differential ports). Figure 12a V in in and V ip Corresponding to Figure 10 V op and V on .

[0235] In the integral (“INTE”) phase, V i,CM As the current integral proceeds, |VGS| will continuously decrease, while |VGS| will continuously increase until it reaches its maximum when the phase is held (“HOLD”). The drive unit is biased in the strong inversion region, which can achieve fast and high linearity drive of the subsequent circuit.

[0236] The proposed driving unit, combined with a current-domain sample-and-hold circuit, can automatically achieve gated shutdown. Traditional gated shutdown techniques require the addition of a switching transistor to dynamically shut down the circuit. However, for ultra-high-speed sampling switches, the current-domain sampling rate often exceeds 10 GS / s, and the additional overhead from the gate clock and switching transistors would be enormous.

[0237] The common-mode voltage output by the current sampling circuit used in this embodiment has dynamic gating characteristics, eliminating the need for any additional control clock and switching transistors. This significantly improves the energy efficiency of the current domain sampling circuit driving the subsequent circuit.

[0238] The current domain sampling circuit of this disclosure replaces the traditional source negative feedback structure with a common gate hybrid structure to achieve high linear voltage-current conversion. At the same time, it ensures sufficient input bandwidth by means of transformer coupling peaking broadening technology, and improves the energy efficiency of the sampling circuit by means of a holding voltage buffer circuit with automatic gate turn-off function.

[0239] Furthermore, the embodiments disclosed herein can be implemented based on CMOS technology, and therefore can be well integrated with the back-end CMOS ADC.

[0240] The advantages of the embodiments disclosed herein compared to existing current domain sampling circuits are summarized in Table 2.

[0241]

[0242] Please see Figure 13 , Figure 13 A schematic diagram of an analog-to-digital converter front-end sampling device according to an embodiment of the present disclosure is shown.

[0243] like Figure 13 As shown, the sampling device includes:

[0244] The first-stage sampling component 300 includes the aforementioned current sampling circuit;

[0245] The second-level sampling component 400 is connected to the first-level sampling component 300, and the second-level sampling component 400 includes a multi-channel bootstrap sampling circuit.

[0246] A third-level sampling component 500 is connected to the second-level sampling component 400, and the third-level sampling component 500 includes an extraction sampler;

[0247] A clock generation unit 600 is connected to the first-stage sampling component 300, the second-stage sampling component 400, and the third-stage sampling component 500. It is used to provide clock signals to each sampling component. The falling edge of the clock signal of the second-stage sampling component 400 is aligned with the end time of the hold phase of the clock signal of the first-stage sampling component 300, and the falling edge of the clock signal of the third-stage sampling component 500 is aligned with the end time of the hold phase after sampling in the clock signal of the second-stage sampling component 400.

[0248] The embodiments disclosed herein do not limit the specific implementation of the sampling components and clock generation units at each level. Those skilled in the art can adopt appropriate technical solutions according to actual conditions and needs.

[0249] The following is an example.

[0250] Please see Figure 14 , Figure 14 A schematic diagram of an analog-to-digital converter front-end sampling device according to an embodiment of the present disclosure is shown.

[0251] Based on the aforementioned current-domain high-speed sample-and-hold circuit design techniques, a 128GS / s ADC front-end sampling circuit was implemented.

[0252] like Figure 13 and Figure 14 As shown, this case uses a 3-level interleaved sampling structure:

[0253] The first-stage sampling component 300 includes the current sampling circuit (including a voltage-to-current conversion circuit, an integral sampling circuit, and a drive unit Hold Buffer).

[0254] In one possible implementation, the second-level sampling component 400 includes multiple bootstrap sampling circuits, and the third-level sampling component 500 includes a push-pull buffer, a downsampling circuit unit, and a driving circuit connected in sequence. The embodiments of this disclosure do not limit the specific implementation of the bootstrap sampling circuit, the push-pull buffer, the downsampling circuit unit, and the driving circuit. Those skilled in the art can refer to relevant technologies to implement them according to actual conditions and needs.

[0255] For example, such as Figure 14 As shown, the input signal is first converted from a voltage signal to a current signal through a wideband, high-linearity common-gate hybrid structure, and then transmitted to a four-channel 32GS / s interleaved current-mode integral sampling switch to complete the first stage of sampling.

[0256] This case study requires achieving a sampling rate of 128 GS / s, which is achieved through four interleaved 32 GS / s sub-samplers with a phase spacing of 1 / 128 GHz (the inputs and outputs of the sub-samplers are connected together). Each sub-sampler is based on current integral sampling. Since the input signals are primarily voltage signals, a wideband, high-linearity common-gate hybrid structure is used to convert the voltage signals into current signals. The current signals are then routed to the four sampling capacitors via four 32 GHz CML (Current Mode Logic) switches, achieving 128 GS / s current integral sampling.

[0257] After the first-stage sampling component 300 completes sampling, it is buffered by the drive unit (HoldBuffer) with automatic gating shutdown function and passed to the second-stage 32-channel interleaved 4GS / s sampling circuit.

[0258] Since the second-stage sampling component 400 captures the hold signal of the first-stage sampling component 300, the input bandwidth pressure is significantly reduced, and it is also less sensitive to clock jitter and skew. Therefore, a bootstrap switching sampling circuit is used to reduce power consumption.

[0259] The bootstrap switching circuit is a classic high-linearity voltage signal sampling circuit (conventional technology), similar to... Figure 1 For specific technical principles, please refer to relevant technologies (such as AM Abo and PR Gray, "A 1.5-V, 10-bit, 14.3-MS / s CMOS pipeline analog-to-digital converter," in IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999, doi: 10.1109 / 4.760369). The linearity of the sampling circuit is improved by using a switched-capacitor bootstrap gating system on the gate voltage of the switching MOSFET. The advantages are low power consumption and circuit simplicity. The disadvantages are limited signal bandwidth and difficulty in achieving a high sampling rate. Here, as a second-stage sample-and-hold circuit, a sampling rate of only 4GS / s is acceptable for capturing the held signal (approximately considered a DC signal) after the previous stage sampling.

[0260] The clock generation circuit of this embodiment can inject an externally input 32GHz differential clock (32GHz CLK) into the on-chip quadrature VCO (voltage-controlled oscillator) to generate the 4-phase 32GHz sampling clock signal required for the first stage of integration sampling.

[0261] For the architecture proposed in this disclosure, the generation and distribution requirements of the 32-phase 4GHz sampling clock of the second-stage sampling component 400 are reduced, and the design complexity and pressure are decreased. Therefore, by passing the 4-phase 32GHz clock signal through a first-stage CML divider (current-mode divider), and a second-stage CML divider... 2 The MOS divider generates the 32-phase 4GHz clock signal required by the second-stage sampling component 400.

[0262] Among them, the current-mode frequency divider and C described here 2 A MOS frequency divider is a frequency divider structure based on D flip-flops, except that the digital logic implementation takes the form of current-mode logic (CML) and complementary clock dynamic logic (CML). 2 (MOS). The frequency divider structure based on D flip-flops is a conventional technique in clock and digital circuits and will not be elaborated upon here. Those skilled in the art can configure it according to actual conditions and needs. Because the clock frequency in this case is relatively high, conventional CMOS logic D flip-flops are difficult to achieve such a high operating frequency. Therefore, in the design of frequency dividers for high-frequency clocks, CML and C... 2 MOS is used to replace static CMOS logic in implementing D flip-flops. The fundamental structure of the frequency divider remains unchanged; it is a very classic frequency divider circuit structure. Only the implementation of the digital logic has been altered to achieve higher speeds.

[0263] Finally, to facilitate the output and testing of the sample-and-hold results, a 125MS / s decimation sampler (used for outputting off-chip tests) was designed for the third-stage sampling component 500 to further reduce the output speed of the sample-and-hold results. The timing diagram of the overall three-stage sampling circuit is shown below. Figure 14 As shown, a device such as the one described above is thus implemented based on the aforementioned current sampling circuit. Figure 14 The 128GS / s ADC current domain front-end sample-and-hold circuit shown is illustrated.

[0264] Since this structure is a fairly conventional sample-and-hold circuit, it will only be briefly described and will not be elaborated upon here. Those skilled in the art can refer to relevant technologies to implement its specific methods according to their actual needs and circumstances. The 125MS / s decimation downsampling circuit is shown in the yellow shaded area in the figure.

[0265] The extractor consists of a first-stage push-pull source follower, a 125MS / s bootstrap switching sampling circuit, and a common-source drive circuit with a 50-ohm load resistor.

[0266] Since the operating frequency of this low-speed sample-and-hold circuit is 1 / 32 of that of the previous sample-and-hold circuit, it is equivalent to decimating the sampling result of the previous stage by 32 times (directly outputting a 4GS / s sample-and-hold result is difficult to accurately capture and test with external instruments, so it is decimated by 32 times to reduce the speed signal before testing).

[0267] Please see Figure 15 , Figure 15 It shows Figure 14 The timing diagram of the front-end sampling device of the analog-to-digital converter is shown.

[0268] like Figure 15 As shown, CK10-CK13 are the four 32GS / s sampling control clocks of the first-stage sampling component 300.

[0269] For example, such as Figure 15 As shown, two adjacent phases of the CK10-CK13 four-phase 32GHz clock are used sequentially as the control clock for each sampler of the first-stage sampling component 300, as follows: Figure 15 As shown in the left half, each sampler of CH1-CH4 uses the clock overlap of CK10-CK13 to achieve the "Reset 1 (RST1) - Reset 2 (RST2) - Integrate (INTE) - Hold (HOLD)" phase required for each integration sampling. The specific principle of this clock control timing can be found in related technologies (such as S. Niu et al., "A 200–256-GS / s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme," in IEEE Journal of Solid-State Circuits, vol. 60, no. 1, pp. 244-259, Jan. 2025, doi: 10.1109 / JSSC.2024.3416528).

[0270] The 32-channel 4GS / s bootstrap sampling circuit of the second-stage sampling component 400 is divided into 4 groups of 8 channels each, and each group is driven by the 4-channel 32GS / s sampling circuit of the first stage. Since the second-stage 4GS / s sampling circuit needs to sample the results held after sampling by the previous 32GS / s stage, the falling edge of the clock signal of the second-stage sampling component 400 needs to be aligned with the end of the holding phase of the clock signal of the first-stage sampling component 300, i.e., the sampling clock CK20-CK2 of the second-stage 4GS / s sampling circuit. 31The falling edge (sampling instant) is aligned with the end time of the HOLD phase of the preceding 32GS / s sampler. The clock edge alignment requirements are shown by the red and green arrows in Figure 12.

[0271] To avoid crosstalk between the eight 4GS / s samplers in each group in the second stage due to overlapping sampling pulses, each group of eight 4GS / s samplers is further divided into two subgroups, with four samplers in each subgroup. Two drive units are used to drive these two subgroups of 4GS / s samplers respectively to avoid crosstalk caused by overlapping sampling pulses.

[0272] Since the third-stage 125MS / s sampling circuit is only used for the final test output extraction, only one third-stage sampling circuit is designed, cascaded after the 4GS / s sampler controlled by CK20, for sampling the hold phase signal of the 4GS / s sampler. Therefore, the falling edge of the clock signal of the third-stage sampling component 500 needs to be aligned with the end time of the sampled hold phase in the clock signal of the second-stage sampling component 400, i.e., its sampling pulse CK Decimator The falling edge (the instant of the third-level sampling) is aligned with the rising edge of CK20 (the end of the hold phase after the second-level sampling), and the 4GS / s sample-hold result is extracted at a rate of 125MS / s.

[0273] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the current sampling circuit, or the current sampling circuit described above.

[0274] This disclosure does not limit the specific implementation of the electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include terminal devices and servers. The terminal device may be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or vehicle-mounted device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.

[0275] The advantages and effects of this application compared to existing technologies should be explained from both technical and application perspectives.

[0276] The current-domain high-speed sample-and-hold circuit of this disclosure has four main advantages over existing methods:

[0277] Compared with existing voltage-domain high-speed sample-and-hold circuits, it improves sampling accuracy (signal-to-noise ratio, linearity).

[0278] Compared with existing current-domain high-speed sample-and-hold circuits based on CMOS technology, it improves sampling linearity and sampling bandwidth.

[0279] Compared with existing current-domain high-speed sample-and-hold circuits based on SiGe BiCMOS technology, this improves sampling linearity and reduces system power consumption and back-end integration complexity.

[0280] By combining the characteristics of current domain integral sampling, an automatic gated shutdown drive unit mechanism was implemented, which improved the energy efficiency of the sampling circuit system.

[0281] At the application level, the embodiments disclosed herein can be used as a single-channel sampling circuit in wireless communication receivers as a front-end direct sampling / undersampling circuit; they can also be used as a multi-channel interleaved sampling circuit in high-speed real-time oscilloscope front-end sampling circuits and high-speed wired communication receiver front-end sampling circuits. They primarily serve back-end ultra-high-speed (sampling rate higher than 10GS / s) and medium-to-low precision (6-8 bit quantization accuracy) ADC products.

[0282] The advantages of the embodiments disclosed herein will solve the problems of deteriorated sampling circuit accuracy, limited input bandwidth, and high system overhead in these products under high sampling rates and high frequency signal inputs.

[0283] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A current sampling circuit, characterized in that, The circuit includes: An input conversion module, the input conversion module including a common-gate current buffer, the current buffer being used to convert a received input voltage signal into a current signal; The sampling module, connected to the input conversion module, is used to perform current integration sampling on the current signal and output a sampled voltage signal.

2. The current sampling circuit according to claim 1, characterized in that, The current buffer includes a first input resistor, a second input resistor, a first conversion transistor, and a second conversion transistor, wherein, The first terminal of the first input resistor and the first terminal of the second input resistor are used to receive input voltage signals. The second terminal of the first input resistor is connected to the source of the first switching transistor, and the second terminal of the second input resistor is connected to the source of the second switching transistor. The gate of the first switching transistor is connected to the gate of the second switching transistor. The drains of the first and second switching transistors are connected to the input terminal of the sampling module.

3. The current sampling circuit according to claim 2, characterized in that, The input conversion module further includes a coupled input unit and a coupled output unit. The input voltage signal is input to the current buffer through the coupling input unit. The current signal is output to the sampling module through the coupling output unit. The coupling output unit is further configured to receive a common-gate bias voltage signal and input it to the gate of the first conversion transistor and the gate of the second conversion transistor.

4. The current sampling circuit according to claim 3, characterized in that, The coupling input unit includes a first input transformer, a second input transformer, a first input transistor, and a second input transistor, wherein, The first terminal of the primary winding of the first input transformer is used to receive the positive voltage signal of the input voltage signal. The first terminal of the primary winding of the second input transformer is used to receive the negative voltage signal of the input voltage signal. The second end of the primary winding of the first input transformer is connected to the first end of the first input resistor. The second end of the primary winding of the second input transformer is connected to the first end of the second input resistor. The first terminal of the secondary winding of the first input transformer and the first terminal of the secondary winding of the second input transformer are both used to receive the first bias voltage. The second end of the secondary winding of the second input transformer is connected to the gate of the second input transistor. The drain of the first input transistor is connected to the source of the first switching transistor and the second terminal of the first input resistor. The drain of the second input transistor is connected to the source of the second switching transistor and the second terminal of the second input resistor. The source of both the first input transistor and the source of the second input transistor are grounded.

5. The current sampling circuit according to claim 4, characterized in that, The coupling input unit further includes a first electrostatic discharge diode and a second electrostatic discharge diode, wherein... The first electrostatic discharge diode is connected to the drain of the first input transistor, the second terminal of the first input resistor, and the source of the first switching transistor. The second electrostatic discharge diode is connected to the drain of the second input transistor, the second terminal of the second input resistor, and the source of the second switching transistor. The input voltage signal is fed into the coupling input unit through the pads.

6. The current sampling circuit according to claim 3, characterized in that, The coupling output unit includes a first output transformer and a second output transformer, wherein, The first end of the primary winding of the first output transformer and the first end of the primary winding of the second output transformer are connected to receive the common gate bias voltage signal. The second end of the primary winding of the first output transformer and the second end of the primary winding of the second output transformer are respectively connected to the gate of the first conversion transistor and the gate of the second conversion transistor. The first terminal of the secondary winding of the first output transformer is connected to the drain of the first conversion transistor, and the second terminal of the secondary winding of the first output transformer is used to output the positive signal of the current signal. The first end of the secondary winding of the second output transformer is connected to the drain of the second conversion transistor, and the second end of the secondary winding of the second output transformer is used to output the negative signal of the current signal.

7. The current sampling circuit according to claim 3, characterized in that, The input conversion module also includes an auxiliary common-source unit. The auxiliary common-source unit includes a first auxiliary capacitor, a second auxiliary capacitor, a first auxiliary transistor, a second auxiliary transistor, a first auxiliary resistor, and a second auxiliary resistor, wherein... The first terminal of the first auxiliary capacitor is connected to the source of the second switching transistor and the second terminal of the second input resistor. The second terminal of the first auxiliary capacitor is connected to the gate of the first auxiliary transistor to receive the second bias voltage through the first auxiliary resistor. The drain of the first auxiliary transistor is connected to the drain of the first switching transistor. The first terminal of the first auxiliary capacitor is connected to the source of the first switching transistor and the second terminal of the second input resistor. The second terminal of the second auxiliary capacitor is connected to the gate of the second auxiliary transistor to receive the second bias voltage through the second auxiliary resistor. The drain of the second auxiliary transistor is connected to the drain of the second switching transistor. The source of the second auxiliary transistor and the source of the first auxiliary transistor are both grounded.

8. The current sampling circuit according to claim 1, characterized in that, The sampling module includes multiple sampling units, each sampling unit including a first sampling capacitor, a second sampling capacitor, a first sampling transistor, a second sampling transistor, a first CML transistor, and a second CML transistor, wherein... The source of the first CML transistor and the source of the second CML transistor are used to receive the current signal. The gate of the first CML transistor is connected to the gate of the second CML transistor. The drain of the first CML transistor, the first terminal of the first sampling capacitor, and the drain of the first sampling transistor are connected together to form the first output terminal of the sampling module. The drain of the second CML transistor is connected to the first terminal of the second sampling capacitor and the drain of the second sampling transistor, serving as the second output terminal of the sampling module. The first output terminal and the second output terminal are used to output the sampled voltage signal. The gate of the first sampling transistor is connected to the gate of the second sampling transistor. The source of both the first sampling transistor and the source of the second sampling transistor are used to receive the power supply voltage. The second terminal of the first sampling capacitor and the second sampling capacitor are both grounded.

9. The current sampling circuit according to claim 8, characterized in that, The sampling module further includes a first reset transistor and a second reset transistor, wherein, The gates of the first reset transistor and the second reset transistor are both connected to the gates of the first sampling transistor and the second sampling transistor, respectively. The source of the first reset transistor and the drain of the second reset transistor are both connected to the second output terminal. The source of the second reset transistor and the drain of the first reset transistor are both connected to the first output terminal.

10. The current sampling circuit according to any one of claims 1-9, characterized in that, The current sampling circuit further includes a driving module, which includes at least one driving unit. Each driving unit includes a first driving capacitor, a first driving transistor, a second driving capacitor, a second driving transistor, a first driving resistor, and a second driving resistor. The first terminal of the first driving capacitor and the first terminal of the second driving capacitor are used to receive the sampled voltage signal. The second terminal of the first driving capacitor is connected to the first terminal of the first driving resistor and the gate of the first driving transistor. The second terminal of the first driving resistor is used to receive the first bias voltage. The second terminal of the second driving capacitor is connected to the first terminal of the second driving resistor and the gate of the second driving transistor. The second terminal of the second driving resistor is used to receive the second bias voltage. The source of the first driving transistor and the drain of the second driving transistor are connected together to serve as the output terminal of the driving module, which is used to output a driving signal. The drain of the first driving transistor is grounded, and the source of the second driving transistor is connected to the power supply voltage.

11. A front-end sampling device for an analog-to-digital converter, characterized in that, The sampling device includes: The first-stage sampling component includes the current sampling circuit as described in any one of claims 1-10; The second-level sampling component is connected to the first-level sampling component, and the second-level sampling component includes a multi-channel bootstrap sampling circuit; A third-level sampling component is connected to the second-level sampling component, and the third-level sampling component includes an extraction sampler; A clock generation unit is connected to the first-level sampling component, the second-level sampling component, and the third-level sampling component. It is used to provide clock signals to each level of the sampling component. The falling edge of the clock signal of the second-level sampling component is aligned with the end time of the hold phase of the clock signal of the first-level sampling component, and the falling edge of the clock signal of the third-level sampling component is aligned with the end time of the hold phase after sampling in the clock signal of the second-level sampling component.

12. The analog-to-digital converter front-end sampling device according to claim 11, characterized in that, The third-level sampling component includes a push-pull buffer, a downsampling circuit unit, and a driving circuit connected in sequence.

13. An electronic device, characterized in that, The electronic device includes a current sampling circuit as described in any one of claims 1-10, or a current sampling circuit as described in claim 11 or 12.

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