A quantum circuit scheduling method and related apparatus

Abstract

The application discloses a quantum circuit scheduling method and related device, and belongs to the technical field of quantum computing. The method comprises the following steps: obtaining the topology structure of a target quantum circuit as a first topology structure, wherein the target quantum circuit is a quantum logic circuit which initiates a scheduling request but has not been scheduled in the current batch of scheduling; determining a target physical bit group allocated to the target quantum circuit based on the first topology structure and a first mapping relationship, wherein the first mapping relationship is a mapping relationship between each second topology structure in a topology set and an available physical bit group, and the topology set is composed of all possible second topology structures determined by the physical bit layout of a quantum computing platform; when there are still quantum logic circuits which have not been scheduled and available physical bit groups in the current batch of scheduling, selecting one of the quantum logic circuits which have not been scheduled as a target quantum circuit, and returning to execute the step of obtaining the topology structure of the target quantum circuit as the first topology structure; when there is no available physical bit group, or when there is an available physical bit group but all quantum logic circuits which initiate a scheduling request have been scheduled, executing the target quantum circuit which has been allocated the target physical bit group in parallel. The application improves the service efficiency and throughput of the quantum computing platform.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, specifically a quantum circuit scheduling method and related apparatus. Background Technology

[0002] Quantum computing has matured from a purely theoretical computational model, capable of outperforming traditional computers on certain specific problems. Currently, numerous companies offer free or paid access to their quantum hardware devices. This access is mostly provided through quantum computing platforms. As the demand for quantum computing continues to grow, users often experience long waiting times, with their jobs only able to proceed after all previously submitted jobs have been completed. Therefore, there is an urgent need to improve the service efficiency and throughput of quantum computing platforms to enhance the user experience.

[0003] Improving service efficiency and throughput requires efficiently scheduling quantum logic circuits on a single quantum computing platform, scheduling as many quantum logic circuits as possible at once. However, using existing technology to call the maximum number of quantum circuits possible at once is a process of determining the optimal combination so that the mapping between quantum logic circuits and physical bits satisfies global optimum. The optimization process consumes a lot of time resources, which weakens the service efficiency and throughput advantages brought by parallel execution of quantum logic circuits. Summary of the Invention

[0004] The purpose of this application is to provide a quantum circuit scheduling method and related apparatus, which aims to improve the service efficiency and throughput of quantum computing platforms.

[0005] One embodiment of this application provides a quantum circuit scheduling method, the method comprising:

[0006] Obtain the topology of the target quantum circuit as the first topology, wherein the target quantum circuit is a quantum logic circuit that initiated a scheduling request but did not attempt to schedule in this batch of scheduling;

[0007] Based on the first topology, using the first mapping relationship, the target physical bit group allocated to the target quantum circuit is determined, wherein the first mapping relationship is the mapping relationship between each second topology in the topology set and the available physical bit group, and the topology set consists of all possible second topologies determined by the physical bit layout of the quantum computing platform;

[0008] If there are still unscheduled quantum logic lines and available physical bit groups in this batch of scheduling, select one of the unscheduled quantum logic lines as the target quantum line, return to the execution step of obtaining the topology of the target quantum line as the first topology;

[0009] When no available physical bit set exists, or when an available physical bit set exists but all quantum logic circuits that initiated scheduling requests in this batch of scheduling attempt to schedule, the target quantum circuit with the allocated target physical bit set is executed in parallel.

[0010] Optionally, determining the target physical bit group allocated to the target quantum circuit based on the first topology and utilizing the first mapping relationship includes:

[0011] From the topology set, determine a second topology that is identical to the first topology, and use it as the target topology.

[0012] Using the first mapping relationship, determine all physical bit groups corresponding to the target topology;

[0013] Select one of the determined physical bit groups as the target physical bit group.

[0014] Optionally, a hashing method can be used to determine the physical bit group corresponding to the target topology.

[0015] Optionally, the method further includes:

[0016] Set the physical bit group containing any physical bit from the target physical bit group to unavailable.

[0017] Optionally, setting a physical bit group containing any physical bit from the target physical bit group from the available physical bit groups to unavailable includes:

[0018] Using the second mapping relationship, the second topological structure corresponding to each physical bit in the target physical bit group is obtained as the third topological structure, wherein the second mapping relationship is the mapping relationship between physical bits and the second topological structure in the quantum computing platform;

[0019] Based on the first mapping relationship, all available physical bit groups corresponding to all third topologies are determined, and all determined available physical bit groups are set to unavailable.

[0020] Optionally, both the first mapping relationship and the second mapping relationship are obtained in advance based on the physical bit layout and the relationship between the physical bits of the quantum computing platform.

[0021] Optionally, both the first mapping relationship and the second mapping relationship are stored using a persistent method.

[0022] Another embodiment of this application provides a quantum circuit scheduling device, the device comprising:

[0023] The module is used to obtain the topology of the target quantum circuit as the first topology, wherein the target quantum circuit is a quantum logic circuit that initiated a scheduling request but did not attempt to schedule in this batch of scheduling;

[0024] The determining module is used to determine the target physical bit group allocated to the target quantum circuit based on the first topology and using a first mapping relationship, wherein the first mapping relationship is the mapping relationship between each second topology in the topology set and the available physical bit group, and the topology set consists of all possible second topologies determined by the physical bit layout of the quantum computing platform;

[0025] The selection module is used to select one quantum logic circuit as the target quantum circuit from the unscheduled quantum logic circuits and the available physical bit groups in the current batch scheduling, and then return to the execution acquisition module.

[0026] The execution module is used to execute the target quantum circuit with the allocated target physical bit group in parallel when no available physical bit group exists, or when an available physical bit group exists but all quantum logic circuits that initiated scheduling requests in this batch of scheduling have attempted to schedule.

[0027] Another embodiment of this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the quantum circuit scheduling method described in any of the above embodiments.

[0028] Another embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit scheduling method in any of the above embodiments.

[0029] Compared to existing technologies, this application first determines the quantum logic circuits to be scheduled and their physical qubit mapping relationships through a first mapping relationship. This allows the quantum logic circuits to select available topologies, i.e., available physical qubit groups, rather than the globally optimal topology. This reduces the significant time cost caused by canceling global enumeration and comparison. Furthermore, the quantum logic circuits received by the quantum computing platform are uncertain, and the corresponding topologies are also uncertain. Therefore, the second topology is dynamic and unenumerable, and searching for the globally optimal combination would waste a lot of time. In the embodiments of this application, after determining the quantum logic circuits to be scheduled and their physical qubit mapping relationships, the process is repeated to allow the quantum computing platform to schedule as many quantum logic circuits as possible simultaneously. Compared to the serial calling of quantum logic circuits, this improves service efficiency and throughput. Compared to searching for the globally optimal solution, it reduces the cost of time resources. The service efficiency and throughput advantages brought by parallel execution of quantum logic circuits are more obvious, reducing user waiting time and improving user experience. Attached Figure Description

[0030] Figure 1 A network block diagram of a quantum computing platform provided in an embodiment of this application;

[0031] Figure 2 A flowchart of a quantum circuit scheduling method provided in this application embodiment;

[0032] Figure 3 A schematic diagram of the physical bit layout of a quantum computing platform provided in an embodiment of this application;

[0033] Figure 4 A schematic diagram of all possible second topologies corresponding to the physical bit layout of a quantum computing platform provided in an embodiment of this application;

[0034] Figure 5 A schematic diagram of a first mapping relationship presented in table form for embodiments of this application;

[0035] Figure 6 A schematic diagram of a third mapping relationship presented in tabular form for embodiments of this application;

[0036] Figure 7 A schematic diagram illustrating another first mapping relationship presented in tabular form for embodiments of this application;

[0037] Figure 8 A schematic diagram of another third mapping relationship presented in tabular form for the embodiments of this application;

[0038] Figure 9 This is a schematic diagram of the structure of a quantum circuit scheduling device provided in an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0040] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0041] Figure 1 This is a network block diagram of a quantum computing platform provided in an embodiment of this application. The quantum computing platform may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0042] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum computing platform, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0043] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0044] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled according to the quantum circuit scheduling method provided in the embodiments of this application.

[0045] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0046] It should be noted that a true quantum computing platform has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0047] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0048] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0049] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0050] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0051] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0052] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0053] See Figure 2 , Figure 2 A quantum circuit scheduling method provided in this application includes the following steps:

[0054] S201: Obtain the topology of the target quantum circuit as the first topology, wherein the target quantum circuit is a quantum logic circuit that initiated a scheduling request but did not attempt to schedule in this batch of scheduling.

[0055] It should be noted that the quantum circuits mentioned in this application embodiment refer to quantum logic circuits, which are circuits formed by quantum logic bits. The target quantum circuit can be randomly selected from quantum logic circuits that have initiated scheduling requests but have not yet attempted scheduling in the current batch scheduling, or it can be the quantum logic circuit with the highest priority among these quantum logic circuits, or the quantum logic circuit that first requested scheduling among these quantum logic circuits. Of course, other methods can also be used to determine the target quantum circuit. "Current batch scheduling" refers to the current batch scheduling. In this application embodiment, it is desirable to schedule as many quantum circuits as possible at once. "Current batch scheduling" can be all quantum circuits that have initiated scheduling requests but have not yet executed, or it can be a subset of quantum circuits that have initiated scheduling requests but have not yet executed. The sum of the number of qubits occupied by the selected subset of quantum circuits can be less than the number of physical bits of the quantum computing platform. Attempting scheduling is performed according to the method provided in this application embodiment, using the first mapping relationship. If the target physical bit group allocated to the quantum circuit is not determined, then the quantum circuit is considered a quantum circuit that has been attempted to be scheduled.

[0056] S202: Based on the first topology, using the first mapping relationship, determine the target physical bit group to be allocated to the target quantum circuit, wherein the first mapping relationship is the mapping relationship between each second topology in the topology set and the available physical bit group, and the topology set consists of all possible second topologies determined by the physical bit layout of the quantum computing platform.

[0057] A physical bit set can contain all the physical bits in a quantum computing platform, or it can contain only one physical bit, depending on the corresponding second topology. An available physical bit set refers to a set of physical bits that have not been assigned to the target quantum circuit. For example, taking a quantum computing platform with 4 physical bits as an example, one possible physical bit layout for this platform is as follows: Figure 3 As shown. All possible second topologies corresponding to this physical bit layout are as follows: Figure 4 As shown, there are five second topological structures. Based on the physical bit layout and the second topological structure, the physical bit group corresponding to the second topological structure can be determined, and the first mapping relationship can be obtained. Because the layout of physical bits in a quantum computing platform is stably bound to the platform model and is fixed, its topological structure and the topological structure of its subgraphs are fixed, finite, and enumerable. Based on this, the first mapping relationship obtained is also fixed. That is, the first mapping relationship can be obtained in advance based on the physical bit layout and the relationship between physical bits of the quantum computing platform. Then, the first mapping relationship can be pre-stored in the quantum computing platform using a persistent method, which can quickly determine the target physical bit group.

[0058] The first mapping relationship can be stored in the form of a table. Continuing the example above, when all physical bits are available, the first mapping relationship can be as follows: Figure 5 As shown, id refers to the physical bit group. Different second topologies correspond to different physical bit groups, and the number of physical bit groups may also be different.

[0059] In practical applications, the second topological structure in the stored first mapping relationship can be represented by a real number. However, in general programming implementations, the topological structure is rarely directly used as a function parameter or compared with other topological structures. A one-to-one third mapping relationship F can be established, where F maps a second topological structure to a real number g. This means that the real number g can uniquely identify the second topological structure. The first mapping relationship can be implemented using hashes with real numbers as keys, such as associative containers in C++ or dictionaries in Python.

[0060] There are many ways to achieve the third mapping relationship, as long as the above constraints are met. For example, matrix factorization or deep learning-based methods can be used. Taking a deep learning-based implementation as an example, the learning model needs to map the input topology to real numbers, where each real number represents the same topological result. The input is the second topology, which can be represented by a graph in data structures. The learning model can be a neural network model, using graph neural networks or graph attention networks to extract the feature parts of the graph. Then, a fully connected layer maps the extracted graph features to the output scores of neurons that match the total number of categories. SoftMax or similar methods are used to convert the scores into predicted probabilities. Finally, the item with the highest predicted probability is selected as the classification result, which corresponds to a real number.

[0061] In this embodiment, a data structure can be used to represent the first and second topological structures. The data structure can be a real number, a complex number, a string, a class from object-oriented programming, a special encoding for the topological structure, etc. The second topological structure is a graph structure, used as an element in the domain of the mapping relationship. During programming, it requires special implementation to uniquely identify the topological structure and facilitate storage. Other requirements can then be met on top of this. Representing the second topological structure with numbers is simple, requires little memory, and is easy to perform arithmetic calculations; representing the topological structure with strings is more flexible; using special encoding can meet specific purposes; representing the second topological structure with classes is more complete but more complex, requiring more time and space resources.

[0062] It should be noted that if the target physical bit group is not determined using the first mapping relationship, then S203 or S204 will be executed depending on the situation.

[0063] In this embodiment, the calculation and storage of the topology of physical bits in the quantum computing platform only needs to be performed once. By using hashing to determine the physical bit group corresponding to the target topology, the processing speed can be greatly accelerated.

[0064] S203: If there are still unscheduled quantum logic lines and available physical bit groups in this batch of scheduling, select one of the unscheduled quantum logic lines as the target quantum line and return to execute S201.

[0065] This application requires that the quantum computing platform execute as many quantum logic circuits as possible in parallel at a time, and continue to allocate when there are quantum logic circuits that have not yet been attempted to be scheduled and available physical bit groups.

[0066] S204: When there is no available physical bit group, or when there is an available physical bit group but all quantum logic lines that initiated scheduling requests in this batch of scheduling have attempted to schedule, the target quantum line with the allocated target physical bit group is executed in parallel.

[0067] In this embodiment, the quantum logic circuits are selected based on available topologies, i.e., available physical qubit groups, rather than the globally optimal topology. This reduces the significant time cost associated with canceling global enumeration and comparison. The quantum logic circuits received by the quantum computing platform are uncertain, and their corresponding topologies are also uncertain. Therefore, the second topology is dynamic and unenumerable, and searching for the globally optimal combination would waste a lot of time. In this embodiment, the quantum logic circuits to be scheduled and their physical qubit mappings are quickly determined through a first mapping relationship. Then, a cyclical determination is performed, allowing the quantum computing platform to schedule as many quantum logic circuits as possible simultaneously. Compared to serial calling of quantum logic circuits, this improves service efficiency and throughput. Compared to searching for the globally optimal solution, it reduces the cost of time resources, making the service efficiency and throughput advantages brought by parallel execution of quantum logic circuits more significant, reducing user waiting time and improving user experience.

[0068] In some embodiments of this application, determining the target physical bit group allocated to the target quantum circuit based on the first topology and utilizing the first mapping relationship includes:

[0069] From the topology set, determine a second topology that is identical to the first topology, and use it as the target topology.

[0070] Using the first mapping relationship, determine all physical bit groups corresponding to the target topology;

[0071] Select one of the determined physical bit groups as the target physical bit group.

[0072] In this embodiment, the topology set can be queried to determine whether there is a second topology set that is the same as the first topology set. If both the first and second topology sets are represented by real numbers, it can be determined that there is a real number in the topology set that is the same as the first topology set. If it exists, the second topology set corresponding to the real number is taken as the target topology set, and one of the available physical bit sets corresponding to the target topology set is selected as the target physical bit set. If it does not exist, the next quantum logic circuit is scheduled, and the information can be fed back to the user to indicate that the quantum computing platform does not support the operation of this quantum logic circuit at this time.

[0073] In some embodiments of this application, the method may further include:

[0074] Set the physical bit group containing any physical bit from the target physical bit group to unavailable.

[0075] When a physical bit group is assigned to a target quantum logic circuit, it means that the physical bits in that physical bit group are currently occupied. However, physical bits may exist in multiple physical bit groups within the target physical bit group. To reduce the time added by repeatedly determining available physical bit groups during subsequent allocation processes, all associated physical bit groups of the already assigned physical bit group are set to unavailable. A mapping relationship between the second topology and the unavailable physical quantum bit groups can be established as a third mapping relationship. In practical applications, HGQ is used to map a second topology Graph to a set Q = {Q0, Q1, ...}, Qi = {qk, qk+1, ...}, where each qk corresponds to a physical bit of the quantum platform. Formalized as: Q = HGQ(Graph). Specifically, for unsupported Graphs, the resulting Q is an empty set. The first mapping is defined as HGQ1, where Q' = HGQ1(Graph) represents obtaining all currently available physical qubit sets Q' corresponding to the first topological structure Graph. The third mapping is defined as HGQ2, where Q” = HGQ2(Graph) represents obtaining all currently unavailable physical qubit sets Q” corresponding to the second topological structure Graph. Clearly, for Q = HGQ(Graph), there is a union of Q = Q' and Q”, while the intersection of Q' and Q” is an empty set. There are still multiple implementation schemes for HGQ1 and HGQ2. Figure 3 and Figure 4 On this basis, Figure 5 and Figure 6 Examples of implementation schemes for HGQ1 and HGQ2 are given in tabular form. When all physical bits q1 in the quantum computing platform become unavailable, HGQ1 and HGQ2 can be implemented as follows: Figure 7 and Figure 8As shown. When the allocation of physical qubits changes, the records in the tables of HGQ1 and HGQ2 will change. Clearly, a change in the allocation of any number of physical qubits can be obtained by changing the allocation of a single physical qubit. For example, when the allocations of q1, q2, and q3 change, the result is equivalent to changing the allocations of q1, q2, and q3 sequentially.

[0076] It should be noted that when the corresponding quantum logic circuit finishes execution, the physical bits it occupies need to be released, and a physical bit group containing the occupied physical bits needs to be determined. For a determined physical bit group, if all physical bits in the physical bit group are in an unoccupied state, then the physical bit group is set to available and can be moved from HGQ2 to HGQ1. In the embodiments of this application, when all target quantum circuits with allocated target physical bit groups have finished execution, all physical bit groups are set to available state. Alternatively, when target quantum circuits with allocated target physical bit groups are executed in parallel, all physical bit groups are set to available state to allocate target physical bit groups for the next batch of quantum circuits. When all currently executing quantum circuits have finished execution, the next batch of target quantum circuits with allocated target physical bit groups is executed directly. Of course, there are other mechanisms to determine whether to modify the state of physical bit groups, as long as they can improve the computational efficiency of the quantum computing platform without causing errors in the execution results.

[0077] In some possible implementations of this application, setting a physical bit group containing any physical bit from the target physical bit group as unavailable may include:

[0078] Using the second mapping relationship, the second topological structure corresponding to each physical bit in the target physical bit group is obtained as the third topological structure, wherein the second mapping relationship is the mapping relationship between physical bits and the second topological structure in the quantum computing platform;

[0079] Based on the first mapping relationship, all available physical bit groups corresponding to all third topologies are determined, and all determined available physical bit groups are set to unavailable.

[0080] The second mapping relationship is obtained in advance based on the physical bit layout and the relationship between physical bits of the quantum computing platform. The second mapping relationship is the mapping relationship between physical bits and the second topology. One physical bit may exist in multiple second topologies. Because the structure of the second topology is fixed, the second mapping relationship is also fixed and stable, and can be pre-stored using persistent methods.

[0081] Once the third topology is determined, using the first mapping relationship, all available physical bit groups associated with the currently allocated physical bit groups can be identified, and these physical bit groups are set to unavailable. Specifically, an unselected physical bit is selected from the target physical bit group. Using the second mapping relationship, the second topology corresponding to the selected physical bit is determined. An unprocessed second topology is selected from the determined second topology, and all physical bit groups corresponding to the selected second topology are set to unavailable. Specifically, taking HGQ1 and HGQ2 as examples, the determined physical bit group is moved from HGQ1 to HGQ2, and then the process of selecting an unprocessed second topology from the determined second topology is repeated until there are no unprocessed second topologies in the determined second topology. Then, the process of selecting an unselected physical bit from the target physical bit group is repeated until there are no unselected physical bits in the target physical bit group.

[0082] See Figure 9 , Figure 9 A quantum circuit scheduling device provided in this application embodiment may include:

[0083] The module 901 is used to obtain the topology of the target quantum circuit as the first topology, wherein the target quantum circuit is a quantum logic circuit that initiated a scheduling request but did not attempt to schedule in this batch of scheduling;

[0084] The determining module 902 is used to determine the target physical bit group allocated to the target quantum circuit based on the first topology and using the first mapping relationship, wherein the first mapping relationship is the mapping relationship between each second topology in the topology set and the available physical bit group, and the topology set consists of all possible second topologies determined by the physical bit layout of the quantum computing platform;

[0085] The selection module 903 is used to select one quantum logic line from the unscheduled quantum logic lines as the target quantum line when there are still unscheduled quantum logic lines and available physical bit groups in the current batch scheduling, and then return to the execution acquisition module 901.

[0086] Execution module 904 is used to execute the target quantum circuit with the allocated target physical bit group in parallel when there is no available physical bit group, or when there is an available physical bit group but all quantum logic circuits that initiated scheduling requests in this batch of scheduling have attempted to schedule.

[0087] The specific functions and effects of the aforementioned quantum circuit scheduling device can be explained by referring to other embodiments of this application, and will not be repeated here. Each module in the quantum circuit scheduling device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0088] Please see Figure 10 This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit scheduling method in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 10 The computer device can be a classical computer or a quantum computer.

[0089] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit scheduling method in any of the above embodiments.

[0090] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the quantum circuit scheduling method in any of the above embodiments.

[0091] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0092] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0093] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0094] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0095] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0096] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0099] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0100] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0101] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0102] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A quantum circuit scheduling method, characterized in that, The method includes: Obtain the topology of the target quantum circuit as the first topology, wherein the target quantum circuit is a quantum logic circuit that initiated a scheduling request but did not attempt to schedule in this batch of scheduling; Based on the first topology, using the first mapping relationship, the target physical bit group allocated to the target quantum circuit is determined, wherein the first mapping relationship is the mapping relationship between each second topology in the topology set and the available physical bit group, and the topology set consists of all possible second topologies determined by the physical bit layout of the quantum computing platform; If there are still unscheduled quantum logic lines and available physical bit groups in this batch of scheduling, select one of the unscheduled quantum logic lines as the target quantum line, return to the execution step of obtaining the topology of the target quantum line as the first topology; When no available physical bit set exists, or when an available physical bit set exists but all quantum logic circuits that initiated scheduling requests in this batch of scheduling attempt to schedule, the target quantum circuit with the allocated target physical bit set is executed in parallel.

2. The method as described in claim 1, characterized in that, The step of determining the target physical bit group allocated to the target quantum circuit based on the first topology and using the first mapping relationship includes: From the topology set, determine a second topology that is identical to the first topology, and use it as the target topology. Using the first mapping relationship, determine all physical bit groups corresponding to the target topology; Select one of the determined physical bit groups as the target physical bit group.

3. The method as described in claim 2, characterized in that, The physical bit group corresponding to the target topology is determined by hashing.

4. The method as described in claim 1, characterized in that, The method further includes: Set the physical bit group containing any physical bit from the target physical bit group to unavailable.

5. The method as described in claim 4, characterized in that, Setting a physical bit group containing any physical bit from the target physical bit group from the available physical bit groups to unavailable includes: Using the second mapping relationship, the second topological structure corresponding to each physical bit in the target physical bit group is obtained as the third topological structure, wherein the second mapping relationship is the mapping relationship between physical bits and the second topological structure in the quantum computing platform; Based on the first mapping relationship, all available physical bit groups corresponding to all third topologies are determined, and all determined available physical bit groups are set to unavailable.

6. The method as described in claim 5, characterized in that, Both the first mapping relationship and the second mapping relationship are obtained in advance based on the physical bit layout and the relationship between the physical bits of the quantum computing platform.

7. The method as described in claim 6, characterized in that, Both the first mapping relationship and the second mapping relationship are stored using persistent methods.

8. A quantum circuit scheduling device, characterized in that, The device includes: The module is used to obtain the topology of the target quantum circuit as the first topology, wherein the target quantum circuit is a quantum logic circuit that initiated a scheduling request but did not attempt to schedule in this batch of scheduling; The determining module is used to determine the target physical bit group allocated to the target quantum circuit based on the first topology and using a first mapping relationship, wherein the first mapping relationship is the mapping relationship between each second topology in the topology set and the available physical bit group, and the topology set consists of all possible second topologies determined by the physical bit layout of the quantum computing platform; The selection module is used to select one quantum logic circuit as the target quantum circuit from the unscheduled quantum logic circuits and the available physical bit groups in the current batch scheduling, and then return to the execution acquisition module. The execution module is used to execute the target quantum circuit with the allocated target physical bit group in parallel when no available physical bit group exists, or when an available physical bit group exists but all quantum logic circuits that initiated scheduling requests in this batch of scheduling have attempted to schedule.

9. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the quantum circuit scheduling method of any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit scheduling method of any one of claims 1-7.

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