Adaptive power reduction readout for overflow pixel sensors

Abstract

The present disclosure relates to adaptive power reduction readout of overflow pixel sensors. Systems, devices, and methods for adaptively performing and / or skipping one or more multi-gain pixel readout operations based on one or more pixel values and one or more thresholds are described. An image sensor can include a readout circuit having an adaptive readout control circuit. The adaptive readout control circuit can be configured to controllably disable one or more multi-gain readout operations based on a comparison of a pixel value to a threshold. The readout circuit can compare a first threshold to a reset value resulting from a high conversion gain readout operation and a second threshold to an image value resulting from the high conversion gain readout operation. The adaptive readout control circuit can be configured to responsively disable one or more of the high conversion gain readout operation, a mid conversion gain readout operation, and / or a low conversion gain readout operation. The image sensor can determine a corresponding final pixel.

Description

Background Technology

[0001] This patent application relates generally to image sensors, and more specifically, to adapting pixel readout according to the illumination intensity of the imaging scene.

[0002] Image sensors with overflow pixels are designed to handle high-intensity light conditions and reduce the risk of image saturation or clipping. By processing excess light more effectively, overflow pixels expand the dynamic range of the image sensor and enhance its ability to capture a wider range of light intensities. Such image sensors are advantageous for high dynamic range (HDR) imaging. Overflow pixel image sensors can be used in many applications, such as advanced driver assistance systems (ADAS), autonomous vehicles, surveillance systems, and industrial inspection.

[0003] An overflow pixel may include a photodiode (PD) and one or more storage structures configured to convert incident photons into electrical charge, and the storage structures adapted to store excess charge generated in a high-illumination environment. The overflow pixel may be adapted to provide multiple gain readouts, such as providing one or more pixel values ​​with one or more gains to cover the entire pixel signal range. For example, an exemplary overflow pixel might require six readouts, including three reset-level readouts and three corresponding image-level readouts, where the gain of each pair of reset and signal readouts is different. The multiple values ​​read from the pixel by the corresponding readout circuitry can then be recombinated, for example, by linearization, to provide a single output HDR value. Recombination can be performed by downstream processing circuitry such as an HDR pipeline circuit.

[0004] Multiple pixel readout operations increase power consumption. In compact cameras, this increased power can raise the temperature of the sensor and other camera electronics, leading to degraded camera performance, such as reduced low-light performance, decreased dynamic range, and increased transition noise, to name a few examples. The increased power consumption further makes camera designs more expensive, and in some cases, may require active cooling.

[0005] Therefore, there is a need to provide improved systems, devices, and methods for overflow pixel sensors to reduce power consumption. Attached Figure Description

[0006] Figure 1 This is a block diagram of an exemplary image sensor according to various implementation schemes.

[0007] Figure 2 These are circuit diagrams of exemplary pixels according to various implementation schemes.

[0008] Figure 3 Timing diagrams for manipulating pixels are illustrated representatively according to various implementation schemes.

[0009] Figure 4 This is a schematic diagram of an exemplary readout circuit according to various implementation schemes.

[0010] Figure 5 This is a flowchart illustrating exemplary adaptive readout methods according to various implementation schemes.

[0011] Figure 6A Representative examples illustrate charge distribution in pixels under specular conditions according to various implementation schemes.

[0012] Figure 6B Representative examples illustrate readout operations performed outside of highlight conditions according to various implementation schemes.

[0013] Figure 7A Charge distribution in pixels under low-light conditions is illustrated in various implementation schemes.

[0014] Figure 7B Representative examples illustrate readout operations performed outside of low-light conditions according to various implementation schemes.

[0015] Figure 8A Charge distribution in pixels under medium light conditions is illustrated representatively according to various implementation schemes.

[0016] Figure 8B Representative examples illustrate readout operations performed under non-light conditions according to various implementation schemes. Summary of the Invention

[0017] Various implementation schemes involve systems, devices, and methods for adaptively controlling the multi-gain readout operation of image sensors.

[0018] In various embodiments, a method for multi-gain readout of a pixel of an image sensor may include: obtaining a high conversion gain (HCG) reset value from the pixel; comparing the HCG reset value with a first threshold; disabling HCG image value readout operation (RO) and medium conversion gain (MCG) RO in response to the HCG reset value being less than the first threshold; and obtaining an HCG image value from the pixel in response to the HCG reset value being greater than or equal to the first threshold; comparing the HCG image value with a second threshold; disabling low conversion gain (LCG) RO in response to the HCG image value being less than the second threshold; and disabling MCG RO and LCG RO in response to the HCG image value being greater than or equal to the second threshold.

[0019] In various embodiments, the image sensor may include a pixel having an output terminal and configured to provide a pixel value at the output terminal; and a readout circuit coupled to the output terminal of the pixel, wherein the readout circuit includes: a memory and a plurality of readout components, the memory being configured to provide a first threshold, wherein the plurality of readout components includes a sample-and-hold circuit, a comparator, and an adaptive readout control circuit, the sample-and-hold circuit being configured to store a sampled value corresponding to the pixel value, the comparator being coupled to the memory and the sample-and-hold circuit and configured to compare the sampled value with the first threshold and responsively output a first comparison result, and the adaptive readout control circuit being coupled to the comparator and configured to controllably disconnect at least one of the plurality of readout components from the supply voltage in response to the comparison result.

[0020] In various embodiments, an adaptive readout control circuit configured to be coupled to the readout circuitry of an image sensor may include a first input, a second input, and an output. The first input is configured to receive a digital value corresponding to a pixel value from the readout circuitry, the second input is configured to receive a first threshold, and the output is configured to be coupled to the readout circuitry. The adaptive readout control circuitry is configured to: compare the digital value with the first threshold, and controllably disable the readout circuitry via the output and based on the comparison during one or more pixel readout operations (RO).

[0021] These and other examples are described in more detail below. Detailed Implementation

[0022] The following detailed description is intended to provide several examples illustrating the broader concepts set forth herein, but is not intended to limit the invention or its application and use. Furthermore, one is not expected to be bound by any theory presented in the foregoing background or the following detailed description.

[0023] According to various embodiments, overflow pixel sensor devices and methods are provided that are beneficial for reducing power consumption, improving performance, and reducing camera system costs. Exemplary image sensor devices and methods can logically analyze sequential readout analog-to-digital conversions of pixel signal values ​​to determine whether to shut down certain readout circuits for part or all of the remaining readout time.

[0024] According to various embodiments, exemplary image sensor devices and methods can reduce readout power by about one-third to about two-thirds, depending on the brightness mixing of the imaging scene. In some cases, readout power may include about half the power used by the image sensor. For example, a typical eight-megapixel automotive HDR image sensor performs multi-gain overflow HDR pixel readout and consumes about 650mW of power. An image sensor performing multi-gain overflow HDR pixel readout according to the embodiments described herein consumes about 300mW to 400mW of power. The reduced power consumption leads to improved performance and facilitates cheaper camera designs, such as enabling the use of plastic housings.

[0025] Figure 1 A block diagram of an exemplary image sensor 100 is illustrated. In some embodiments, the configuration of the image sensor, the arrangement of the various components therein, and the operation of the various components may be similar to those described with reference to U.S. Patent No. 11,722,794, which is incorporated herein by reference. However, the embodiments described herein can be applied to other configurations of image sensors, pixel arrays, pixels, etc. In some embodiments, the image sensor 100 may be implemented as a semiconductor device on a single substrate, a stacked substrate, a system-on-a-chip, etc.

[0026] In some embodiments, the image sensor 100 may include a pixel array 110 having a plurality of image sensor pixels 120. The pixels 120 may be arranged in any suitable manner. For example, the pixels 120 may be arranged in groups, such as in a stacked sensor arrangement. In some embodiments, the pixels 120 may be arranged in rows and columns. The image sensor 100 may also include control and processing circuitry 130, which may be referred to herein as control circuitry 130.

[0027] Control circuitry 130 can be coupled to row control circuitry 140 and column readout and control circuitry 150, which may be referred to herein as readout circuitry 150. Control circuitry 130 can perform timing control on row control circuitry 140. Based on timing control, row control circuitry 140 can provide corresponding row control signals to each row pixel 120 via one or more conduction row control paths 145, such as reset signals, row selection signals, charge transfer signals, double-conversion gain signals, readout signals, and / or any other suitable pixel control signals.

[0028] In some embodiments, the image sensor 100 may include conductive column lines 155 coupled to each column of pixels 120 in the pixel array 110. Column lines 155 may be used to read signals from pixels 120 and to supply bias current and / or bias voltage to pixels 120. In some embodiments, pixel readout operation may include selecting and controlling pixel rows in the pixel array 120 using row control circuitry 140, and reading pixel values ​​generated by pixels 120 in the selected rows using column lines 155. Pixel values ​​may be analog values, such as analog voltage or analog current.

[0029] The readout circuit 150 controls the operation (including readout) of pixel 120 and receives pixel values ​​from column lines 155. The readout circuit 150 may include memory circuitry for permanently or non-permanently storing calibration signals such as reset level signals and reference level signals, and / or pixel signals read from pixel array 120. The readout circuit 150 may include amplifier circuitry, analog-to-digital converter (ADC) circuitry, bias circuitry, control circuitry, and / or other circuitry coupled to the pixel columns of pixel array 110.

[0030] An amplifier circuit amplifies the pixel value read from pixel 120, and an ADC circuit converts the analog pixel value into a digital pixel value. A readout circuit 150 provides the digital pixel value to the control circuit 130 and / or other storage and processing circuitry of the image sensor 100 for further processing. Additional processing may include converting the digital pixel value into image data, performing HDR processing by appropriately combining multiple exposures and / or readouts with different gains, etc.

[0031] One or more of the control circuit 130, the row control circuit 140, and / or the readout circuit 150 may include associated storage circuitry configured to store instructions, such as firmware or software, executable by the processing units of the respective control circuits 130, 140, and 150. The associated storage circuitry may include, for example, a non-transitory computer-readable medium. The stored instructions, when executed by the respective processing units, can implement one or more processes described herein, such as one or more timing diagrams for controlling one or more pixels 120, one or more process flowcharts for adaptively performing pixel readout, etc.

[0032] Figure 2This is a circuit diagram of an exemplary pixel 120 according to various embodiments. Pixel 120 may include a photosensitive device, such as a photodiode 220 having a first terminal coupled to a voltage terminal 210 that receives a reference voltage, such as a ground voltage. The photodiode 220 may generate a charge, such as electrons, in response to receiving incident light, such as photons. The photodiode 220 may have a second terminal at which the generated charge is stored. The amount of charge generated by the photodiode 220 may depend on the exposure duration (also known as the integration time) and on the intensity of the incident light. For example, the photodiode 220 may be exposed to high light levels, medium light levels, low light levels, etc. Each pixel 120 of the pixel array 110 may be exposed to different light levels in a given imaging scene.

[0033] In some embodiments, charge transfer transistor 225 may couple photodiode 220 to floating diffusion region 230. Transfer transistor 225 may receive a control signal 'transfer' at its control terminal (e.g., at its gate terminal). When the 'transfer' control signal is partially or fully active, transfer transistor 225 may conduct charge from photodiode 220 to floating diffusion region 230, respectively, partially or fully.

[0034] In some implementations, pixel 120 may be configured to operate in multiple conversion gain modes, such as a low conversion gain (low gain) mode, a medium conversion gain (medium gain) mode, and / or a high conversion gain (high gain) mode. For example, pixel 120 may include a charge storage structure such as capacitor 250, for example, a low-gain capacitor C arranged to have capacitance. lg Capacitor 250 may have a first terminal coupled to voltage terminal 255 and a second terminal serving as a charge storage terminal. Voltage terminal 255 may provide a voltage reference signal, such as ground voltage or another supply voltage 'Vrst'. In some embodiments, the voltage reference signal at voltage terminal 255 may be a variable voltage signal, for example, having a first voltage across a first time period and a second voltage across a second time period.

[0035] Capacitor 250 can be coupled to floating diffusion region 230 via gain transistor 240. Gain transistor 240 can receive a control signal 'gain_ctrl' at its control terminal. When the 'gain_ctrl' control signal is active, gain transistor 240 can conduct stored charge from capacitor 250 to floating diffusion region 230 or vice versa. When floating diffusion region 230 is coupled to capacitor 250 via gain transistor 240, the charge storage capacity of floating diffusion region 230 is effectively expanded. In some embodiments, when both transfer transistor 225 and gain transistor 240 are activated, a portion of the charge generated by photodiode 220 can be transferred from photodiode 220 to capacitor 250.

[0036] In some embodiments, pixel 120 may include a reset transistor 245 arranged to reset pixel 120 to, for example, a reset voltage level. The reset transistor 245 may, for example, couple voltage terminal 255 to floating diffusion region 230 via gain transistor 240. The reset transistor 245 may receive a control signal 'reset' at its control terminal and may conduct charge to / from voltage terminal 255 when the 'reset' control signal is active.

[0037] For example, when both reset transistor 245 and gain transistor 240 are activated, the floating diffusion region 230 can be reset to the reset voltage level based on the supply voltage at voltage terminal 255. In some embodiments, reset transistor 245 can couple the terminals of capacitor 250 to voltage terminal 255, such that capacitor 250 can be reset to the reset voltage level when reset transistor 245 is activated. In some embodiments, when reset transistor 245, gain transistor 240, and transfer transistor 225 are activated, photodiode 220 can be reset to its fixed voltage level.

[0038] Pixel 120 may include an output terminal. In some embodiments, pixel 120 may include a source follower transistor 260 and a pixel or row select transistor 270 forming an output circuit portion of pixel 120. The source follower transistor 260 may couple a voltage terminal 275 to the select transistor 270, and a control terminal of the source follower transistor 260 may be coupled to a floating diffusion region 230. The voltage terminal 275 may provide a voltage reference signal, such as an analog level supply voltage 'Vaa'. The select transistor 270 may couple the source follower transistor 260 to a column line 155 of the pixel array 110. The select transistor 270 may receive a control signal 'select' at its control terminal. In some embodiments, column line 155 may be associated with one or more columns of pixels, and the 'select' signal may be activated to read pixel signals from pixels in a specific row.

[0039] When the control signal 'select' is active, a corresponding pixel output signal, proportional to the amount of charge at the floating diffusion region 230, is transmitted to column line 155 via source follower transistor 260 and select transistor 270. When the floating diffusion region 230 stores the charge generated by photodiode 220 in response to incident light, the corresponding pixel output signal may be referred to as an image signal or image level signal. When the floating diffusion region 230 stores a reset voltage level, the corresponding pixel output signal may be referred to as a reset signal or reset level signal. The pixel output signal can be provided to readout circuit 150, and then to control circuit 130 and / or other processing circuits as needed.

[0040] In some implementations, such as for HDR applications, pixel 120 can be adapted and controlled to generate more than one set of image and reset signals for each integration time period. Multiple image and reset signals can be read out in two or more operations using different gains. For example, pixel 120 can be adapted and controlled to perform low conversion gain (LCG) readout, medium or intermediate conversion gain (MCG) readout, and high conversion gain (HCG) readout. See still Figure 2 In some embodiments, pixel 120 may include a conversion gain device such as conversion gain device 235. Conversion gain device 235 may be referred to as dual conversion gain or intermediate (or intermediate) conversion gain (MCG) device 235. In some embodiments, both capacitor 250 and MCG device 235 may be configured to be selectively connected individually or in combination to floating diffusion region 230 to modify the capacitance of floating diffusion region 230.

[0041] In some implementations, the MCG device 235 may be a two-terminal device, such as a capacitor, a modified metal-oxide-semiconductor (MOS) transistor, or other devices suitable for selectively modifying the capacitance of the floating diffusion region 230. For example, the MCG device 235 may include a gate structure receiving a control signal 'MCG' and a semiconductor substrate separated by an insulator such as a gate insulator. A second terminal of the MCG device 235 may be electrically connected to the floating diffusion region 230 and to the semiconductor substrate. When the MCG device 235 is activated, for example when the control signal 'MCG' is active, the MCG device 235 may provide additional capacitance to the floating diffusion region 230.

[0042] Capacitor 250 can be configured to support LCG mode readout operation of pixel 120, and MCG device 235 can be configured to support MCG mode readout operation of pixel 120. In some exemplary embodiments, the capacitance of MCG device 235 may be more than 0.25 times, more than 0.5 times, more than 0.75 times, more than 1 times, more than 2 times, less than 6 times, less than 5 times, less than 4 times, less than 3 times, and / or less than 2 times, or generally any suitable multiple of the capacitance of floating diffusion region 230. For example, the capacitance of MCG device 235 may be about three to about five times the capacitance of floating diffusion region 230. In some exemplary embodiments, the capacitance of capacitor 250 may be more than 3, 6, 10, 20, 30, 50, 100, 200, less than 150, less than 100, less than 80, less than 70, and / or less than 50, or generally any suitable multiple of the capacitance of floating diffusion region 230. For example, the capacitance of capacitor 250 may be about 70 to about 80 times the capacitance of floating diffusion region 230. It should be understood that any suitable capacitance value may be used, depending on the design choice, desired characteristics, etc.

[0043] In some implementations, pixel 120 can be configured to generate pixel signals, such as image signals, using various combinations of the floating diffusion region 230, MCG device 235, and capacitor 250. For example, pixel 120 can generate pixel signals such as by using LCG readout when capacitor 250 is connected to floating diffusion region 230, by using MCG readout when MCG device 235 is connected to floating diffusion region 230, and by using HCG readout when both capacitor 250 and MCG device 235 are disconnected from floating diffusion region 230.

[0044] Figure 3This is an exemplary timing diagram for operating one or more pixels 120 to perform multi-gain readouts, such as LCG readout, MCG readout, and HCG readout. In some embodiments, control signals such as 'select', 'transfer', 'reset', 'gain_ctrl', and 'MCG' described above can be used to control the operation of pixel 120. For example, control circuitry such as row control circuitry 140 and readout circuitry 150 can be configured to provide one or more of these control signals to corresponding components of pixel 120 and / or other circuitry such as readout circuitry 150 via respective row control paths 145 and / or other control paths. In some embodiments, the control circuitry can provide the control signal 'SH' to corresponding readout circuitry 150 components such as sample-and-hold circuitry, sample switches, and / or other related circuitry. As a non-limiting example, the sampled pixel signal values ​​read from pixel 120 can be stored for further processing, such as analog-to-digital conversion, on the falling edge of the 'SH' signal.

[0045] The control circuitry can operate pixel 120 during the shutter time period, integration time period, and readout time period. During the shutter time period, the control circuitry can fully activate the control signals 'select', 'transfer', 'reset', and 'gain_ctrl' to reset components of pixel 120, such as the floating diffuser region 230, photodiode 220, capacitor 250, and MCG device 235, to a reset voltage level. In some embodiments, the reset voltage level can be a supply voltage 'Vrst' provided at voltage terminal 255. After photodiode 40 has been reset to the reset voltage level, for example, after the 'transfer' signal is deactivated (falling edge) during the shutter time period, the integration time period can begin.

[0046] During the integration period, pixel 120 may begin to generate and accumulate charge in response to incident light. Pixel 120 may be configured to separate the generated charge into an overflow portion or an overflow charge and a remaining portion stored at photodiode 220. In some embodiments, a 'transfer' signal portion 300 may be activated to set a barrier for photodiode 220. The barrier may set or limit the overflow portion of charge from photodiode 220, and set or limit the remaining portion of charge from photodiode 220. In some embodiments, a 'gain_ctrl' signal portion 302 may also be activated to set a barrier in a similar manner. By maintaining both transistors 240 and 225 in an activated state during the integration period, pixel 120 allows an excess of overflow charge from photodiode 220 to flow to floating diffusion region 230 and further to capacitor 250.

[0047] In some implementations, the control circuitry may also activate a portion of the 'reset' signal 304 during the integration time period. Activating the 'reset' signal along with portions of the 'transfer' and 'gain_ctrl' signals can create an anti-halo path for the photodiode 220. For example, charge exceeding the storage capacity of the floating diffusion region 230 and capacitor 250, which could cause pixel 120 to oversaturate, can flow through transistors 225, 240, and 245 to voltage terminal 255. The voltage level used to activate each portion of the 'reset', 'transfer', and 'gain_ctrl' signals can be set to any appropriate level, depending on the control signals and the desired reset, overflow, and / or anti-halo effect.

[0048] The readout period may occur after the integration period. In some embodiments, the readout period may include, for example, performing multi-gain readout of pixel 120 using LCG, MCG, and / or HCG readout. The terms readout and readout operation are used interchangeably herein. Furthermore, HCG readout may be referred to as E1, MCG readout as E2, and LCG readout as E3. In some embodiments, each of the LCG readout operation (RO), MCG readout operation, and HCG readout operation may be configured to provide an actual pixel value based on the corresponding gain (low, medium, and high), indicating the actual amount of charge generated by pixel 120 in response to incident light. For example, LCG, MCG, and HCG RO may be configured to provide a pixel value that does not include charge generated by noise and / or other sources.

[0049] Each of LCG, MCG, and HCG RO may include obtaining one or more pixel signal values, such as from a reset signal and an image signal. The readout of the reset signal may be referred to as a sample-and-hold (SHR) of the reset signal, and the readout of the image signal may be referred to as a sample-and-hold (SHS) of the image signal. Therefore, the readout period may include performing one or more of the following readout operations: an HCG readout operation including HCG(E1)SHR readout and HCG(E1)SHS readout, an MCG readout operation including MCG(E2)SHR readout and MCG(E2)SHS readout, and / or an LCG readout operation including LCG(E3)SHR readout and LCG(E3)SHS readout. In some embodiments, each of the paired E1 readouts, E2 readouts, and / or E3 readouts (e.g., E1 SHR and SHS) may facilitate double sampling or correlated double sampling determination of the actual pixel value of the corresponding gain readout, for example, by subtracting the SHR readout value from the corresponding SHS readout value.

[0050] At the end of the integration period, or equivalently at the beginning of the readout period, the control circuit can fully activate both the 'gain_ctrl' 306 signal and the 'MCG' 308 signal to redistribute the overflow charge between capacitor 250, floating diffusion region 230, and MCG device 235. The charge redistribution can be based on the charge storage capacity of each corresponding device. The 'select' signal can be activated and can remain active throughout the readout period.

[0051] In some implementations, an HCG SHR readout can then be performed. For example, after charge redistribution, because the storage capacity of capacitor 250 and MCG device 235 is much larger than the storage capacity of floating diffusion region 230, minimal charge remains in floating diffusion region 230. This charge redistribution (leaving minimal charge in floating diffusion region 230) can be effectively used as a reset operation for floating diffusion region 230. For example, charge redistribution can set floating diffusion region 230 to (or substantially set to) a reset voltage level. Subsequently, the control circuitry can activate the 'SH' signal 310 while completely deactivating the control signals 'gain_ctrl' and 'MCG'. The 'SH' signal can activate the sampling circuitry in readout circuitry 150 to sample and store the HCG reset level signal based on the voltage level at floating diffusion region 230.

[0052] The control circuit can then perform HCG image signal readout (HCG SHS). To perform HCG SHS readout, the control circuit can activate the 'transfer' signal 316-1 and the 'MCG' signal 312-1 to perform a charge transfer operation to transfer the remaining photodiode charge to the floating diffusion region 230. Subsequently, the control circuit can deactivate the 'MCG' signal and the 'transfer' signal, and perform HCG readout on the image signal associated with the remaining photodiode charge by activating the 'SH' signal 320. The HCG readout of the reset level signal and the image level signal can be a correlated double-sample readout. For example, the actual HCG pixel signal without reset noise can be obtained by subtracting the reset level signal from the image level signal. In various embodiments, this subtraction can be performed by the readout circuitry of the image sensor 100, downstream processing circuitry, or any other suitable circuitry.

[0053] In some implementations, an MCG readout operation can be performed after an HCG readout operation. For example, the control circuitry can then perform an MCG SHS readout. To perform the MCG SHS readout, the control circuitry can activate the 'transfer' signal 316-2 and the 'MCG' signal 312-2 to ensure that all remaining photodiode charge is transferred to the floating diffusion region 230. Subsequently, the control circuitry can keep the control signal 'MCG' active and perform MCG readout on the image signal (MCG SHS) associated with the remaining photodiode charge by activating the 'SH' signal 318 based on activating 316-1 and 316-2. The control circuitry can keep the 'MCG' signal active 312-2 throughout the entire MCG SHS readout operation and SHR readout operation.

[0054] The control circuit can then perform an MCG SHR readout by first activating the 'gain_ctrl' signal 307 to effectively equalize the voltage level of the floating diffusion region 230 using capacitor 250. In some cases, because capacitor 250 can store overflow charge, this reset operation may not require supplying a reset level to the floating diffusion region 230 equal to the supply voltage level Vrst supplied by voltage terminal 255. However, this approach achieves satisfactory performance because the reset level voltage in this reset operation is a small fraction of the image level signal and has minimal impact on the gain of the MCG image signal.

[0055] Following this reset operation, the control circuit enables the 'SH' signal 314 while the 'MCG' signal remains active 312-2 to perform MCG readout on the reset level signal (MCG SHR). The MCG SHS readout can be correlated with the MCG SHR readout as a double-sample readout, but the noise in the MCG SHS and MCG SHR readouts can be independent of each other. The actual MCG pixel value can be obtained by subtracting the MCG SHR readout value from the MCG SHS readout value.

[0056] After performing HCG and MCG readout operations on the remaining photodiode charge, the control circuit can control pixel 120 to perform LCG SHS readout on the overflow charge along with the photodiode charge (OVF+PD). The overflow charge plus the photodiode charge can be the charge generated by the entire photodiode. In some embodiments, the control circuit can enable the 'gain_ctrl' signal 322 and keep the 'gain_ctrl' signal active 322 during the LCG readout operation. When the 'gain_ctrl' signal is active, charge sharing can be formed between the floating diffusion region 230 and the capacitor 250. In this low conversion gain configuration, the capacitor 250 can effectively increase the storage capacity of the floating diffusion region 230 multiple times.

[0057] The control circuit can activate the 'transfer' signal 324 to transfer any remaining photodiode charge to the floating diffusion region 230 and the capacitor 250 connected to the floating diffusion region 230. The control circuit can deactivate the 'MCG' signal. After transferring any remaining photodiode charge, all the charge generated by the photodiode, including overflow charge and total photodiode charge, can be shared between the floating diffusion region 230 and the capacitor 250. The control circuit can then activate the 'SH' signal 326 while activating the 'gain_ctrl' signal 322 to perform LCG readout on the image level signal (LCG SHS). Therefore, the LCG SHS readout can be associated with the total charge generated by the photodiode.

[0058] In some implementations, a low conversion gain configuration can also be used to read out the corresponding LCG reset level signal (LCG SHR). For example, since the 'gain_ctrl' signal 322 is still active, the control circuit can activate the 'reset' signal 328 to reset the capacitor 250 and the floating diffusion region 230 to the reset level voltage provided by the voltage terminal 255. The control circuit can then activate the 'SH' signal 330 while the 'gain_ctrl' signal 322 is activated to perform LCG SHR readout based on the combined reset level voltage at the floating diffusion region 230 and the capacitor 250. The LCG SHS readout can be correlated with the LCG SHR readout as a double-sample readout, but the noise in the LCG SHS and LCG SHR readouts can be uncorrelated. The actual LCG pixel value can be obtained by subtracting the LCG SHR readout value from the LCG SHS readout value.

[0059] Figure 3 The timing diagram shown is merely illustrative and can be modified as appropriate. For example, it can be modified if needed. Figure 3 The timing diagram is modified so that an LCG readout operation can be performed on the overflow charge (e.g., excluding the remaining photodiode charge) before performing HCG and MCG operations on the remaining photodiode charge.

[0060] Figure 4 This is a schematic diagram showing an exemplary readout circuit 150 coupled to the output of pixel 120, which is configured, for example, to read pixel values ​​based on the charge at the floating diffusion region 230 via a selection transistor 270 and a source follower transistor 260. For ease of reference, Figure 4The remaining portion of pixel 120 is not reproduced. As described above, pixel values ​​can be supplied from pixel 120 to column line 155. Column line 155 can be coupled to current source 405, which may be referred to herein as Vln circuit 405. Current source 405 can provide a reference current to the column line and can facilitate accurate measurement of voltage or voltage changes on column line 155 caused by reading pixel values.

[0061] In some embodiments, the image sensor 100 may use a per-column implementation of the readout circuitry 150, wherein each of the plurality of columns 155 has its own corresponding readout circuitry 150. In some embodiments, the image sensor 100 may be configured to use region-by-region readout, for example, in the case of using an image sensor with a stacked substrate, and the readout circuitry 150 may be adapted to perform region-by-region readout. In some embodiments, the image sensor 100 may be configured to use per-pixel readout, for example, in the case of using an image sensor with a stacked substrate, and the readout circuitry 150 may be configured to perform readout for each individual pixel.

[0062] The readout circuit 150 may include any suitable components, processor, software, etc., adapted to process pixel values ​​read from pixel 120. In some embodiments, the readout circuit 150 may be configured to adaptively perform and / or skip one or more reset signal readouts or image signal readouts, such as one or more of HCG SHR readout, HCG SHS readout, MCG SHR readout, MCG SHS readout, LCG SHR readout, and / or LCG SHS readout. In some embodiments, the readout circuit 150 may be configured to perform and / or skip various readouts based on one or more pixel values ​​read from pixel 120 and one or more thresholds. In some embodiments, a reference may be used... Figure 4 One or more of the described components, processors, software, functions, etc., may be appropriately incorporated into other control circuitry, such as into control circuitry 130 and / or other downstream processing circuitry.

[0063] In some implementations, the readout circuit 150 may include multiple readout components, such as a column amplifier 410, a sample-and-hold circuit 415, and an analog-to-digital converter (ADC) circuit 420. The column amplifier 410 may provide gain to the voltage level on column line 155, wherein the voltage level is generated, for example, due to the readout pixel value. The sample-and-hold circuit 415 may be coupled to the output of the column amplifier 410 and may be configured to store the sampling result (also referred to as the sampled value) at the output of the column amplifier 410, for example, upon activation of a 'SH' control signal. The sampling result may be stored in a capacitor or other suitable memory structure of the sample-and-hold circuit 415. The ADC circuit 420 may be coupled to the sample-and-hold circuit 415 and may convert the sampled value stored by the sample-and-hold circuit 415 from an analog value to a digital value. The ADC circuit 420 may be referred to as ADC 420 and may include any suitable ADC circuit, such as a ramp ADC, a successive approximation register (SAR) ADC, etc.

[0064] In some embodiments, the readout component of the readout circuit 150 may further include a comparator 425 and a memory 430. The comparator 425 may include any suitable circuitry, device, etc., for comparing two or more values. The comparator 425 may be appropriately configured to output a comparison result indication, such as logic '1' or '0' or other suitable analog or digital value, if the first input of the comparator 425 is equal to, greater than, greater than or equal to, less than, less than or equal to, not equal to (etc.) the second input of the comparator 425. The comparator 425 may be configured to compare a readout pixel value (or its representation) with one or more thresholds and / or other values.

[0065] In some embodiments, comparator 425 may include a digital comparator configured to compare two or more digital values. For example, comparator 425 may be adapted to receive the output of ADC 420 at one input (e.g., its first input). Comparator 425 may be further adapted to receive the output of memory 430, which may include digital values, at another input (e.g., its second input). In some other embodiments, comparator 425 may include an analog comparator coupled to the output of sample-and-hold circuit 415 and configured to compare two analog values, such as amplified pixel values, and one or more analog thresholds provided by memory 430 prior to AD conversion. Other suitable analog and mixed-signal implementations may be used as needed.

[0066] In some implementations using digital comparator 425, comparator 425 can advantageously use a subgroup of bits derived from the entire bit width of ADC 420 and still provide sufficient granularity for accurate comparisons, while reducing and / or minimizing the circuitry required for comparisons. For example, comparator 425 can be adapted to use the four most significant bits (MSB) of the output of ADC 420. Other examples may suitably use different numbers of bits and / or a subgroup of bits derived from the output of ADC 420. The output of memory 430 can be configured to match the number of bits, scaling, etc., based on the subgroup of bits used by comparator 425.

[0067] Memory 430 may be configured to store one or more thresholds that can be used by comparator 425 for comparison with pixel values ​​read by readout circuitry 150. For example, in an embodiment where comparator 425 receives pixel values ​​converted by an analog-to-digital converter, one or more stored thresholds (which may also be referred to as thresholds) may be digital values ​​and may be or include the same number of bits as the number of bits received by comparator 425 from ADC 420. Memory 430 may be any suitable storage device, such as random access memory, volatile memory, non-volatile memory such as a one-time programmable fuse, reprogrammable memory, etc. In some embodiments, one or more thresholds may correspond to pixel values ​​such as reset level values ​​and / or image level values, which can be used to make a decision regarding whether to perform or skip one or more of the reset level readout and / or image level readout.

[0068] In some embodiments, memory 430 may include or otherwise store a lookup table (LUT). The LUT may be configured to store one or more thresholds corresponding to one or more pixel values. For example, the LUT may store a first threshold (reset level threshold) corresponding to a reset level and a second threshold (image level threshold) corresponding to an image level. In some embodiments, one or more thresholds may depend on one or more factors, such as the length of the integration period (referred to as integration time) (Tint), temperature (Tp), and / or other desired operating conditions. The LUT may be configured to store multiple values ​​of one or more thresholds, wherein each stored value corresponds to a specific combination of factors. For example, the LUT may store a pair of first and second thresholds for each of multiple values ​​of integration time, temperature, etc.

[0069] In some implementations, one or more thresholds or other values ​​may be retrieved from memory 430 based on one or more factors. For example, memory 430 may output thresholds for the integration time, temperature, and / or other factors at which the nearest (or other relevant) pixel 120 is operating. Integration time may be received by memory 430 from appropriate control circuitry such as row control circuitry 140, control circuitry 130, etc. Temperature may be received and / or estimated based on one or more temperature sensors present in image sensor 100 (e.g., in and / or around pixel array 110).

[0070] In some embodiments, memory 430 may include circuitry configured to determine a threshold by approximating it based on a stored threshold and relevant operating factors. For example, the LUT may not include thresholds for every possible combination of integration time, temperature, etc. If memory 430 receives a set or more factors not perfectly represented in the LUT, the circuitry may approximate the threshold using a linear approximation, a quadratic approximation, or other suitable algorithm based on two or more values ​​in LUTs with similar operating factors. In some embodiments, memory 430 may approximate the threshold by using a linear approximation for integration time, a quadratic approximation for temperature, etc.

[0071] In some implementations, one or more thresholds may be generated by an algorithm based on one or more factors such as integration time and temperature. In such implementations, memory 430 may be replaced and / or supplemented by appropriate threshold generation circuitry, such as hardware configured to execute a set of stored software or firmware instructions, or other suitable circuitry, to perform threshold generation.

[0072] The readout component of the readout circuit 150 may further include readout timing logic circuitry 440, which may also be referred to as adaptive readout control circuitry 440. Adaptive readout control circuitry 440 may be configured to receive a comparison result from comparator 425, indicating the relationship between the output of ADC 420 corresponding to a pixel value and one or more thresholds provided by memory 430. In various embodiments, adaptive readout control circuitry 440 may include comparator 425 and / or memory 430. Adaptive readout control circuitry 440 may also be configured to receive one or more readout timing signals 435. Readout timing signals 435 may indicate which type of readout is being performed, such as HCG SHR readout, HCG SHS readout, MCG SHR readout, MCG SHS readout, LCG SHR readout, or LCG SHS readout, which readout is being or recently sampled by sample-and-hold circuitry 415, converted by ADC 420, compared by comparator 425, etc. In some implementations, the readout timing signal 435 may be provided by appropriate control circuits such as line control circuit 140, control circuit 130, etc.

[0073] In some implementations, the readout circuit 150 may be configured to adaptively control one or more readout components and / or associated components of the readout circuit 150 to allow one or more subsequent readout operations to be performed or skipped, for example, based on the output of comparator 425 and the readout timing signal 435. Exemplary details regarding adaptive control are discussed in more detail below with reference to an adaptive readout method. The adaptive readout method may be implemented by the readout circuit 150 and may be referred to as an adaptive readout process.

[0074] In some implementations, the readout circuit 150 can adaptively control one or more components by disconnecting one or more components from one or more supply voltages used to operate those components. For example, see still... Figure 4 The column amplifier 410, sample-and-hold circuit 415, and / or ADC 420 may receive power from the analog-level supply voltage (Vaa), for example, by being electrically connected to voltage terminal 275. The ADC 420, comparator 425, and / or adaptive readout control circuit 440 may receive power from the digital-level supply voltage (Vdd), for example, by being electrically connected to voltage terminal 465. Column line 155 may receive current from current source 405.

[0075] The readout circuit 150 may include a Vaa cut-off switch 455 configured to controllably connect and disconnect a corresponding component from voltage terminal 275. The readout circuit 150 may include a Vdd cut-off switch 450 configured to controllably connect and disconnect a corresponding component from voltage terminal 465. The readout circuit 150 may include a current source cut-off switch 460 configured to controllably connect and disconnect column line 155 from current source 405. In some embodiments, the adaptive readout control circuit 440 may control or otherwise influence the 'SH' control signal, for example, by selectively disabling control signals for skipped readout operations.

[0076] The output of the adaptive readout control circuit 440 can provide a power control signal 470, which is configured to control the cut-off switches 450, 455, and 460 according to the adaptive readout method described below. The power control signal 470 may be directly or indirectly electrically coupled to the cut-off switches. In some embodiments, the Vaa cut-off switch 455, the Vdd cut-off switch 450, and the current source cut-off switch 460 may include any suitable control element, such as a metal-oxide-semiconductor transistor that receives the power control signal 470 at its gate input, has a source or drain terminal coupled to voltage terminal 465, voltage terminal 275, or current source 405, respectively, and has a drain or source terminal coupled to a voltage supply, current supply, or similar terminal of the corresponding component.

[0077] The various states of the power control signal 470 can be appropriately selected according to the adaptive readout method to properly control the various components of the readout circuit 150, control circuit 130, etc. For example, if the cut-off switches 450, 455, and 460 are N-type MOS (NMOS) transistors, the power control signal 470 can be activated high to turn on each of the cut-off switches 450, 455, and 460, making these switches conduct, and can be activated low to turn off each of the cut-off switches 450, 455, and 460 to disconnect the corresponding components from the voltage source and / or current source.

[0078] In some implementations, the adaptive readout control circuit 440 can operate continuously and receive ungated power input, such that it is never disconnected from its corresponding voltage supply. For example, the adaptive readout control circuit 440 can be directly coupled to voltage terminal 465 without the intermediate cut-off switch 450. In some such implementations, the power control signal 470 provided by the adaptive readout control circuit 440 can be provided directly and / or indirectly to Vdd cut-off switch 450, Vaa cut-off switch 455, and / or current source cut-off switch 460.

[0079] The power control signal 470 may also be provided to a downstream image processing pipeline (not shown), such as an HDR pipeline. The downstream image processing pipeline may include any suitable circuitry, software, firmware, etc., configured to receive one or more reset-level and image-level readouts of pixel 120 and accordingly reconstruct or otherwise determine the output image value of the pixel. For example, the downstream image processing pipeline may receive readout timing signal 435 and the output of ADC 420 during a corresponding readout operation and may be configured to perform HDR processing on one or more pixel values ​​read from pixel 120 accordingly.

[0080] In some implementations, the downstream image processing pipeline can be configured to adaptively perform processing on one or more pixel values ​​using the power control signal 470. For example, the downstream image processing pipeline can be configured to exclude one or more pixel values ​​from the HDR image value calculation results when the power control signal 470 indicates that a corresponding readout operation is not performed. To achieve this, the power control signal 470 may be referred to as an on / off flag.

[0081] In some embodiments, the adaptive readout control circuit 440 may also be configured to disconnect its corresponding voltage supply when skipping one or more readout operations. For example, the adaptive readout control circuit 440 may be coupled to voltage terminal 465 via Vdd disconnect switch 450, as described above. In some such embodiments, the power control signal 470 provided by the adaptive readout control circuit 440 may be indirectly provided to Vdd disconnect switch 450, Vaa disconnect switch 455, and / or current source disconnect switch 460.

[0082] For example, the readout circuit 150 may include a latch 445, and a power control signal 470 may be provided to the input of the latch 445 via an adaptive readout control circuit 440. The latch 445 may be directly coupled to and powered by a voltage terminal 465. The latch 445 may, for example, provide a latched or otherwise stored form of the power control signal 470 to a Vdd cut-off switch 450, a Vaa cut-off switch 455, and / or a current source cut-off switch 460 at its output. For example, if the adaptive readout control circuit 440 is powered down (disconnected from the corresponding voltage supply) due to performing its adaptive readout process, the state of the latched power control signal 475 may be maintained by the latch 445, and the corresponding components may remain disconnected from the corresponding power supplies 465, 275 even when the adaptive readout control circuit 440 is powered down. In some such embodiments, an on / off flag may be provided by the latch 445 to a downstream image processing pipeline.

[0083] In some implementations, latch 445 may include an input configured to receive an 'Enable' signal. When the 'Enable' signal is active, latch 445 may be configured to force the on / off switches 450, 455, 460 to enable readout by appropriately controlling the latched power control signal 470 (e.g., overriding the state of power control signal 475). In some implementations, the 'Enable' signal may also be latched by latch 445, for example, to maintain its state in the event that the 'Enable' signal is deactivated. In some implementations, the 'Enable' signal may be activated by a pulse at the beginning of each pixel readout cycle (e.g., at the end of the integration period). In some implementations, where only LCG readout is required, for example in analysis as described below... Figure 5 Following the described early readout operation, the 'Enable' signal can be activated via a pulse.

[0084] Figure 5 This is an example of adaptively performing reference. Figure 3 A flowchart of an exemplary adaptive readout method 500 for the various readout operations described herein. The adaptive readout method 500 may be executed by readout circuitry 150, for example implemented in adaptive readout control circuitry 440, and / or by associated circuitry such as comparator 425, memory 430, etc. Adaptively executing the various readout operations may include selectively executing and not executing various combinations of HCG SHR readout operations, HCG SHS readout operations, MCG SHR readout operations, MCG SHS readout operations, LCG SHR readout operations, and / or LCG SHS readout operations. Figure 6B , Figure 7B and Figure 8B A representative example is the operation based on the adaptive readout method 500. Figure 3 The timing diagram shows various combinations of read operations that are performed and not performed. Not performing read operations can be referred to as disabling read operations.

[0085] In some embodiments, disabling or not performing one or more readout operations (RO) may include disconnecting corresponding circuitry in readout circuitry 150, control circuitry 130, etc., from one or more voltage and / or current supplies to reduce the power consumption of image sensor 100. In some embodiments, not performing one or more readout operations may include adaptive readout control circuitry 440 controlling the disconnection of corresponding circuitry. In some embodiments, it may be based on... Figure 3 The adaptive performance of the readout operation is determined by one or more reset-level readouts and / or image-level readouts. The adaptive readout method 500 will be described with reference to the states of various pixel 120 components under different lighting conditions, for example... Figure 6A , Figure 7A and Figure 8A exemplified.

[0086] Figure 6A , Figure 7A and Figure 8A This is a schematic diagram of charge-based potential diagrams for various pixel 120 elements during various readout operations, where the lower limit of the diagram represents, for example, the reset voltage level provided by voltage terminal 255, while the upper limit represents, for example, the maximum amount of charge that causes the voltage potential of the pixel 120 element to be approximately 0V. Various pixel 120 transistors, such as transfer transistor 225 and gain transistor 240, act as barriers to charge movement within the pixel 120. Various storage nodes of the pixel 120 (e.g., photodiode 220, floating diffusion region 230, and capacitor 250) act as “buckets” that can be filled with charge. Charge can flow from one storage node to another, depending on, for example, the amount of charge, the size of the storage node, and the potential of the barrier.

[0087] More specifically, Figure 6A The following is a representative example illustrating the state of noise and generated charge after an HCGSHR readout operation is performed in response to a pixel capturing a highlight portion of an image scene. Figure 7A The diagram illustrates, representatively, the state of noise and generated charge after an HCG SHS readout operation in response to a pixel capturing a low-light portion of an image scene, and... Figure 8A The state of noise and generated charge after an HCG SHS readout operation is performed in response to a pixel capturing the mid-light portion of an image scene is typically illustrated.

[0088] See Figure 6A As described above, prior to performing the HCG SHR readout at step 505, the pixel 120 component is reset to a reset voltage level during the shutter time period. As a non-limiting example, the reset voltage level Vrst from voltage terminal 255 may be approximately 2.8V or any other suitable voltage level. Since the photodiode 220 generates charge during the subsequent integration period in response to the incident photon, the floating diffusion region 230 and / or capacitor 250 may accumulate charge in the form of noise 620.

[0089] Noise 620 (also referred to as parasitic charge) may be caused, for example, by dark current or other undesirable effects. The amount of accumulated noise 620 may correspond to the temperature of pixel 120 and / or the corresponding component (represented by the variable Tp), the length of the integration time period (also referred to as the integration time and represented by the variable Tint), and / or other factors. In some embodiments, the generated and accumulated charge may reduce the potential of photodiode 220, floating diffusion region 230, capacitor 250, etc., from a reset value Vrst to a common voltage reference, such as ground, for example, 0V.

[0090] As described above, the gain transistor 240 and transfer transistor 225 can be partially activated by partially activating the 'gain_ctrl' signal and the 'transfer' signal during the integration period, allowing excess charge generated by photodiode 220 due to high-light conditions to overflow from photodiode 220 to the floating diffusion region 230 and further to capacitor 250. The charge overflowing from photodiode 220 forms an overflow charge portion 610, and the remaining portion of the generated charge is located at photodiode 220 as a residual charge portion 600. In some embodiments, as described above, the 'gain_ctrl' signal can be fully activated 306 to redistribute the overflow charge at the end of the integration period, which is achieved by... Figure 6A The downward arrow below 'gain_ctrl' is an example. Therefore, in some embodiments, during highlight conditions, the total charge at the floating diffusion region 230 may include a combination of both the overflow charge portion 610 and the noise 620.

[0091] See you again Figure 5 At step 505, after the integration period, the control circuit may perform as described above (reference). Figure 3 The described HCG reset level readout (HCG SHR) may, for example, include performing an analog-to-digital (AD) conversion on the reset level read from pixel 120. In some embodiments, the AD conversion may be performed by a readout circuit 150, such as an ADC 420. In other embodiments, the threshold checking process steps described below with reference to the adaptive readout method 500 may be performed appropriately based on the analog pixel value without AD conversion or before AD conversion.

[0092] At step 510, the readout circuit 150 compares the HCG SHR reset level signal with the reset level threshold. Figure 5 This is exemplified as ThresholdR. In some embodiments, the reset level threshold can be selected based on the operating conditions of the image sensor 100, such that it exceeds the range of the noise 620 expected at the floating diffusion region 230. For example, the reset level threshold can be a predetermined reset level threshold and / or can be dynamically set based on one or more parameters such as temperature Tp, integration time Tint, etc. In some embodiments, this comparison can be performed by comparator 425 based on the value received from ADC 420 and a corresponding threshold from memory 430. As described above, the threshold can be retrieved from memory 430 according to one or more operating conditions such as Tp, Tint, etc.

[0093] like Figure 6A , Figure 7A and Figure 8AAs illustrated, this document describes the threshold with reference to the voltage and charge levels at the floating diffusion region 230. However, it should be understood that the threshold can be selected based on the corresponding value of the pixel read on column line 155 or modified by column amplifier 410, sample-and-hold circuit 415, ADC 420, etc. For example, the value of the pixel read on column line 155 can be amplified by column amplifier 410 and converted into a digital representation by ADC 420, and the corresponding threshold (reset level, image level) can be a digital value whose level is amplified compared to the digital value present on the floating diffusion region 230.

[0094] In some implementations, for example at the reset voltage level (e.g., 2.8V), due to... Figure 6A In cases where the accumulated and / or generated charge is greater than the image level, a reset level threshold can be selected to correspond to the voltage level on the floating diffusion region 230, which is less than or equal to the reset voltage level minus the expected noise 620. It should also be appreciated that the adaptive readout method 500 can be appropriately adjusted, for example, by selecting different thresholds, changing the sign of the threshold comparison result, etc., so that the pixel circuitry operates at lower reset voltage levels and higher image voltage levels and / or reset voltage levels.

[0095] For example, since there is no overflow charge portion 610 on the floating diffusion region 230, the voltage level of the floating diffusion region 230 can be expected to be equal to or greater than the reset level threshold. If noise is present at the floating diffusion region 230 in the absence of overflow charge portion 610, the voltage level of the floating diffusion region 230 can be between the reset level threshold and the reset voltage level. If some overflow charge portion 610 is present on the floating diffusion region 230, the voltage level of the floating diffusion region 230 can be less than the reset level threshold. In such an example, the voltage level of the floating diffusion region 230 can be equal to the reset voltage level minus the noise 620 minus the overflow charge portion 610.

[0096] If the comparison performed at step 510 indicates that the HCG SHR reset level signal is less than the reset level threshold, it can be assumed that this particular pixel 120 is affected by high-light conditions, causing charge to overflow from the photodiode 220 to the floating diffusion region 230, and correspondingly reducing the voltage level at the floating diffusion region 230 by a greater margin than the voltage level reduction caused solely by noise 620. In this case, the HCG (low-light) readout operation and the MCG (medium-light) readout operation may have a negligible or no effect on the final pixel value to be determined by the downstream processing circuit for this particular pixel 120, and the readout circuit 150 may skip (not perform) the corresponding readout.

[0097] See Figure 5 and Figure 6BIf, at step 510, it is determined that the HCG SHR reset level signal is less than the reset level threshold ThresholdR, then at step 515, the readout circuit 150 may responsively disconnect one or more corresponding components of the readout circuit 150 during subsequent HCG SHS, MCG SHR, and MCG SHS readout operations. For example, in some embodiments, at step 515, the adaptive readout control circuit 440 may control the power control signal 470 to disconnect the Vdd cutoff switch 450, the Vaa cutoff switch 455, and / or the current source cutoff switch 460. At step 515, the readout circuit 150 may disconnect the adaptive readout control circuit 440 from its corresponding voltage supply.

[0098] At the end of step 515, the readout circuit 150 can activate the corresponding components to enable subsequent LCGSHS and LCG SHR readout operations. For example, the adaptive readout control circuit 440 or associated circuitry can control the power control signal 470 to activate the Vdd cutoff switch 450, Vaa cutoff switch 455, and / or current source cutoff switch 460 to enable the corresponding readout circuit 150 components. In some embodiments, an 'Enable' signal can be used to reset or otherwise control the latch 445 to provide a latched power control signal 475 that enables the corresponding components.

[0099] At step 520, the readout circuit 150 can perform an LCG SHS readout operation, and at step 525, it can perform an LCG SHR readout operation, for example, as referenced above. Figure 3 As described. For example, steps 520 and 525 may include amplifying the values ​​on column line 155 using column amplifier 410, sampling the corresponding values ​​using sample-and-hold circuit 415, and performing AD conversion using ADC 420.

[0100] At step 530, the downstream processing circuitry can determine and output the final pixel value based on the LCG(E3) readout from steps 520 and 525, without considering the HCG SHS readout operation at step 505. More generally, the downstream processing circuitry can be configured to consider various combinations of missing HCG readout values, MCG readout values, and / or LCG readout values, as indicated by the power control signal 470, when determining the final pixel value of pixel 120.

[0101] In some implementations, the output of the ADC 420 used for the LCG SHS 520 and LCG SHR 525 readout operations can be provided to downstream processing circuitry for determining the final pixel value at step 530. For example, the downstream processing circuitry can determine the final pixel value by determining the pixel value based on the LCG readouts 520 and 525 and gaining, amplifying, or otherwise multiplying the determined pixel value by an HCG-to-LCG factor. The HCG-to-LCG factor can be based on the ratio of the capacitance of capacitor 250 to the capacitance of the floating diffusion region 230. For example, if the capacitance of capacitor 250 is approximately 70 times the capacitance of the floating diffusion region 230, the gain used for the E3 readout can be approximately 70.

[0102] Therefore, pixels 120 that capture the highlight portion of the image scene only require three AD conversions, and the readout circuit 150 can be shut down for the remaining portion of HCG RO and for MCG RO (e.g., from the end of HCG SHR readout to the start of LCG SHS readout). Thus, through steps 505, 510, 515, 520, 525, and 530, the readout circuit 150 performs HCG SHR readout, LCG SHR readout, and LCG SHS readout only under highlight conditions, achieving a reduction in readout power consumption of approximately 50% compared to performing full group HCG row readout, MCG row readout, and LCG row readout.

[0103] Returning to step 510, if the comparison result indicates that the HCG SHR reset level signal is not less than the reset level threshold, it can be assumed that this particular pixel 120 is not affected by the bright light condition, because the voltage level at the floating diffusion region 230 is not lower than the voltage level caused only by the noise 620. Such a comparison result at step 510 indicates that no charge overflows from the photodiode 220 to the floating diffusion region 230, and therefore pixel 120 is not affected by the bright light condition. The adaptive readout method 500 can then determine, based on further determination of whether pixel 120 is affected by the low-light or medium-light condition, whether to skip the LCG readout operation or perform one or more of the HCG and MCG readout operations.

[0104] If the comparison performed at step 510 determines that the HCG SHR reset level signal is not less than the reset level threshold, then at step 535, for example, the adaptive readout method 500 executed by the adaptive readout control circuit 440 may cause or otherwise enable the readout circuit 150 to perform an HCG SHS readout operation, for example, as referenced above. Figure 3 As described. In some implementations, the HCG SHS readout operation may include performing AD conversion on the image level read from pixel 120, as well as other readout operations such as magnification, sampling, etc.

[0105] At step 540, the readout circuit 150 compares the HCG SHS image level signal with an image level threshold. Figure 5 The example is ThresholdS. See briefly... Figure 7A In some embodiments, the image level threshold may be selected based on the operating conditions of the image sensor 100, along with the amount of charge generated during HCG SHS readout by activating the 'transfer' control signal, transferred from the photodiode 220 to the floating diffusion region 230, such that it exceeds the range of the noise 620 expected at the floating diffusion region 230. The image level threshold may be a predetermined image level threshold and / or may be dynamically set based on operating conditions such as Tp, Tint, etc. In some embodiments, this comparison may be performed by a comparator 425 based on a value received from the ADC 420 and a corresponding threshold from the memory 430. As described above, the threshold may be retrieved from the memory 430 according to one or more operating conditions such as Tp, Tint, etc.

[0106] For example, under low-light or medium-light conditions, the residual charge portion 600 at photodiode 220 may include all the charge generated by photodiode 220, with no or substantially no overflow charge portion 610 generated. The image level threshold may be based on the amount of charge generated at photodiode 220, corresponding to the transition between low-light and medium-light conditions. In some embodiments, the image level threshold may be selected based on operating conditions (Tp, Tint, etc.) as equal to the expected noise 620 plus the maximum amount of charge generated at photodiode 220 in response to low-light conditions. For example, the full charge capacity of photodiode 220 may only be achieved under medium-light conditions.

[0107] Return to Figure 5 If the comparison performed at step 540 indicates that the HCG SHR reset level signal is not less than the image level threshold ThresholdS, it can be assumed that this particular pixel 120 is affected by low-light conditions, under which the photodiode 220 cannot generate enough charge, along with noise 620, to reduce the initial reset level of the floating diffusion region 230 below the image level threshold. In this case, the HCG (low light) readout operation may be able to adequately resolve the final pixel value, and the MCG (medium light) and LCG (high light) readout operations may have a negligible or no effect on the final pixel value. Therefore, the readout circuit 150 may skip (not perform) the corresponding MCG and LCG readouts.

[0108] See Figure 5 and Figure 7BIf, at step 540, it is determined that the HCG SHS image level signal is not less than the image level threshold ThresholdS, then at step 545, the readout circuit 150 may responsively disconnect one or more corresponding components of the readout circuit 150 during subsequent MCG SHS readout operations, MCG SHR readout operations, LCG SHS readout operations, and LCG SHR readout operations. For example, in some embodiments, at step 545, the adaptive readout control circuit 440 may control the power control signal 470 to disconnect the Vdd cutoff switch 450, the Vaa cutoff switch 455, and / or the current source cutoff switch 460 during the corresponding readout operation.

[0109] At step 545, the readout circuit 150 may also disconnect the adaptive readout control circuit 440 from its corresponding voltage supply during the respective subsequent readout operation. In some embodiments, at the end of step 545, the adaptive readout control circuit 440 or associated circuitry may control the power control signal 470 to turn on the Vdd cutoff switch 450, Vaa cutoff switch 455, and / or current source cutoff switch 460 to enable the corresponding readout circuit 150 components for the next set of HCG, MCG, and LCG readouts after the next integration period. In some embodiments, at the end of step 545, the adaptive readout control circuit 440 or associated circuitry may control the 'Enable' signal to achieve the same purpose.

[0110] At step 550, the downstream processing circuitry can determine and output the final pixel value of pixel 120 based on the HCG(E1) readouts from steps 505 and 535. In some embodiments, the output of ADC 420 used for HCG SHR readout operation 505 and HCG SHS readout operation 535 can be provided to the downstream processing circuitry for determining the final pixel value at step 550. In some embodiments, the downstream processing circuitry can output the final pixel value without any additional gain or amplification.

[0111] Therefore, pixels 120 capturing the low-light portion of the image scene only require two AD conversions, and the readout circuit 150 can be shut down for the remainder of the MCG row readout and LCG row readout operations. Thus, through steps 505, 510, 535, 540, 545, and 550, the readout circuit 150 performs HCG SHR and HCG SHS readout operations only under low-light conditions, achieving a reduction in readout power consumption of approximately 66% compared to performing the entire set of HCG row readout, MCG row readout, and LCG row readout operations.

[0112] Returning to step 540, if the comparison result indicates that the HCG SHS image level signal is less than the image level threshold ThresholdS, it can be assumed that this particular pixel 120 is affected by mid-light conditions, under which the photodiode 220 can generate sufficient charge, along with noise 620, to reduce the initial reset level of the floating diffusion region 230 below the image level threshold. In this case, the HCG (low light) readout operation and the MCG (mid light) readout operation can adequately distinguish the final pixel value, and the LCG (high light) readout operation may have a negligible or no effect on the final pixel value. Therefore, the readout circuit 150 can skip (not perform) the corresponding LCG readout.

[0113] See Figure 5 and Figure 8B If it is determined at step 540 that the HCG SHS image level signal is less than the image level threshold ThresholdS, then at step 555, the readout circuit 150 can perform an MCG SHS readout operation, and at step 560, it can perform an MCG SHR readout operation, for example, as described above. Figure 3 As described. For example, steps 555 and 560 may include amplifying the value on column line 155 using column amplifier 410, sampling the corresponding value using sample-and-hold circuit 415, and performing AD conversion using ADC 420.

[0114] At step 565, after the HCG and MCG readout operations have been performed, the readout circuit 150 may disconnect one or more corresponding components during subsequent LCG SHS and LCG SHR readout operations. For example, in some embodiments, at step 565, the adaptive readout control circuit 440 may control the power control signal 470 to disconnect the Vdd cutoff switch 450, the Vaa cutoff switch 455, and / or the current source cutoff switch 460. At step 565, the readout circuit 150 may disconnect the adaptive readout control circuit 440 from its corresponding voltage supply.

[0115] In some embodiments, at the end of step 565, the adaptive readout control circuit 440 or associated circuitry controls the power control signal 470 to turn on the Vdd cutoff switch 450, Vaa cutoff switch 455, and / or current source cutoff switch 460 to enable the corresponding readout circuit 150 components for performing the next set of HCG, MCG, and LCG readouts after the next integration period. In some embodiments, at the end of step 565, the adaptive readout control circuit 440 or associated circuitry controls the 'Enable' signal to achieve the same purpose.

[0116] In some implementations, the output of ADC 420 for HCG SHR readout operation 505, HCG SHS readout operation 535, MCGSHS readout operation 555, and MCG SHR readout operation 560 may be provided to downstream processing circuitry for determining the final pixel value at step 570. For example, the downstream processing circuitry may determine and output the final pixel value of pixel 120 based on the HCG(E1) readout operations of steps 505 and 535 and the MCG(E2) readout operations of steps 555 and 560.

[0117] In some implementations, the downstream processing circuitry can amplify the indicated pixel value derived from the MCG (E2) readout operation by multiplying it by an HCG-to-MCG factor. The HCG-to-MCG factor can be based on the ratio of the capacitance of the MCG device 235 to the capacitance of the floating diffusion region 230. For example, if the capacitance of the MCG device 235 is approximately five times the capacitance of the floating diffusion region 230, the gain for the E2 readout can be approximately 5.

[0118] Downstream processing circuitry can determine the final pixel value based on a mixture of the amplified MCG (E2) readout value and the unamplified pixel value derived from the indicated HCG (E1) readout operation. In some embodiments, the mixture of the E1 readout value and the (amplified) E2 readout value can be based on the relative intensities of the indicated MCG and LCG values. For example, as the light level exposed to pixel 120 increases from a transition zone between low and medium light levels to a level just before overflow (e.g., at the full-well capacity of photodiode 220), the HCG SHS readout value will further decrease from the image level threshold ThresholdS. The HCG SHS readout value and / or the corresponding value determined by the readout circuitry 150 can thus indicate the relative intensity of the light exposed to pixel 120, and therefore the relative weights of the amplified E2 readout and the unamplified E1 readout in the mixture of the final pixel value. For example, as the HCG SHS readout value is further reduced from the image level threshold, the downstream processing circuitry can increase the relative weight of the indicated value derived from the MCG readout compared to the HCG readout in the final pixel value blend.

[0119] Therefore, pixels 120 capturing the mid-light portion of the image scene only require four AD conversions, and the readout circuit 150 can be shut down for the remainder of the LCG row readout operation. Thus, through steps 505, 510, 535, 540, 555, 560, 565, and 570, the readout circuit 150 performs HCG SHR readout, HCG SHS readout, MCG SHS readout, and MCG SHR readout operations only under mid-light conditions, achieving a reduction in readout power consumption of approximately 33% compared to performing the entire group of HCG row readout, MCG row readout, and LCG row readout operations.

[0120] The adaptive readout method 500 can be appropriately adapted to pixels, readout circuits, image sensors, etc., wherein the readout operations are arranged in a different order than that described herein. For example, the order of E1 readout operations, E2 readout operations, and E3 readout operations can be rearranged in various ways. Figure 5 The flowchart.

[0121] Therefore, the adaptive readout method 500 performs logical analysis on the first SHR pixel output to make a branch decision to shut down the readout circuit during medium gain readout, wherein low gain readout is woken up and continued, further logical analysis is performed on the first SHS pixel output to make a branch decision to shut down the readout circuit during medium-low gain readout or during medium gain readout continuation, and to shut down the readout circuit during low gain readout.

[0122] Therefore, various embodiments provide systems, devices, and methods that can adaptively perform and / or skip one or more multi-gain readout operations based on values ​​provided by pixels and depending on the amount of incident light exposed to the pixels. Image sensor 100 may include readout circuitry 150 having adaptive readout control circuitry 440 configured to compare pixel values ​​with thresholds and responsively disable one or more subsequent readout operations. Various embodiments may include adapting reset thresholds and image thresholds based on sensor temperature, integration time, etc.

[0123] Advantageously, the image sensors according to the various embodiments described herein can perform only, or substantially only, the necessary readout operations to determine accurate final pixel values ​​under given illumination conditions, while minimizing the amount of power used for readout operations. The various embodiments can reduce readout power by 33% to 66%, depending on the incident light level. Energy savings can be achieved while minimizing the impact on manufacturing costs. In contrast, existing methods involve performing all readout operations regardless of the light level.

[0124] The reference processing flow and various components and functions shown and described in the image sensor can be distributed in any manner across various components of the image sensor 100 and / or external systems, and different implementations can organize the processing of various features and information in any number of different ways. Several of the various features and systems described herein can be implemented in software and / or firmware residing in a non-transitory data storage device for execution by one or more processors to perform the various automated processes described herein. For example, the adaptive readout control circuitry 440 and / or the adaptive readout method 500 can be implemented using processors, transistor logic units, field-programmable gate arrays (FPGAs), state machines, etc.

[0125] The pixel arrangement of 120 in this article is merely illustrative. Typically, any desired pixel circuitry can be combined with... Figure 4 The illustrated readout circuitry is used in conjunction with this. Pixel circuitry may include anti-halo transistors, one or more multi-gain transistors, and / or memory nodes, etc. Figure 4 The readout circuit can be used in image sensors that operate with a rolling shutter (where each row of pixels captures an image sequentially) or a global shutter (where each pixel in the image sensor captures an image simultaneously).

[0126] It should be recognized that the various circuits described herein may alternatively or otherwise be implemented as computer instructions (software, firmware, etc.) configured to cause a processor to perform the functions of the described circuits. It should also be recognized that the computer instructions and / or automation processes described herein may alternatively or otherwise be implemented as hardware circuits capable of operating to perform the functions of the described computer instructions.

[0127] The general concepts set forth herein are applicable to any number of alternative but equivalent embodiments. The term “exemplary” is used herein to denote an example, illustration, or description that may have any number of alternatives. Any specific embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other specific embodiments, nor is it intended as a model that must be replicated in other specific embodiments. While several exemplary embodiments have been presented in the foregoing detailed description, it should be understood that numerous alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, various changes may be made to the function and arrangement of the described elements without departing from the scope of the claims and their legal equivalents.

Claims

1. A multi-gain readout method for pixels of an image sensor, the method comprising: Obtain the high conversion gain (HCG) reset value from the pixel; The HCG reset value is compared with a first threshold. In response to the HCG reset value being less than the first threshold, disable HCG image value readout operation (RO) and intermediate conversion gain (MCG) RO; and In response to the HCG reset value being greater than or equal to the first threshold: Obtain HCG image values ​​from the pixels; The HCG image value is compared with a second threshold. Low conversion gain (LCG) RO is disabled in response to the HCG image value being less than the second threshold; and The MCG RO and LCG RO are disabled in response to the HCG image value being greater than or equal to the second threshold.

2. The method according to claim 1, wherein: Disabling the MCG RO includes disabling the MCG image value RO and the MCG reset value RO; and Disabling the LCG RO includes disabling the LCG image value RO and the LCG reset value RO.

3. The method according to claim 2, wherein, The image sensor includes a readout circuit, which comprises an analog-to-digital converter, a sample-and-hold circuit, and an amplifier, wherein: Disabling readout operation includes disconnecting the analog-to-digital converter, the sample-and-hold circuit, or the amplifier from the supply voltage during the readout operation.

4. The method according to claim 1, wherein, The image sensor includes a readout circuit, the readout circuit includes a comparator, and wherein: The readout circuit is used to obtain the HCG reset value and the HCG image value from the pixel; The comparator is used to compare the HCG reset value with the first threshold; and The comparator is used to compare the HCG image value with the second threshold.

5. The method according to claim 4, wherein, The readout circuit further includes a memory coupled to the comparator, wherein: Comparing the HCG reset value with the first threshold includes obtaining the first threshold from the memory; and Comparing the HCG image value with the second threshold includes obtaining the second threshold from the memory.

6. The method according to claim 1, further comprising: The first threshold is selected based on the temperature of the image sensor and the length of the integration period. as well as The second threshold is selected based on the temperature of the image sensor and the length of the integration period.

7. The method according to claim 1, further comprising: In response to the HCG reset value being less than the first threshold, a final pixel value is provided based on the LCG RO; In response to the HCG image value being less than the second threshold, the final pixel value is provided based on the HCG reset value, the HCG image value, and the MCGRO; and The final pixel value is provided based on the HCG reset value and the HCG image value in response to the HCG image value being greater than or equal to the second threshold.

8. An image sensor, the image sensor comprising: A pixel having an output terminal and configured to provide a pixel value at the output terminal; and A readout circuit, coupled to the output terminal of the pixel, wherein the readout circuit includes: Memory, the memory being configured to provide a first threshold; and Multiple readout components, wherein the multiple readout components include: A sample-and-hold circuit, configured to store sampled values ​​corresponding to the pixel values; A comparator, coupled to the memory and the sample-and-hold circuitry and configured to compare the sampled value with the first threshold and responsively output a first comparison result; and An adaptive readout control circuit, coupled to the comparator and configured to controllably disconnect at least one of the plurality of readout components from the supply voltage in response to the comparison result.

9. The image sensor according to claim 8, wherein, The plurality of readout components also include: An amplifier, coupled to the output of the pixel and configured to amplify the pixel value, wherein the sample-and-hold circuit is coupled to the output of the amplifier; and An analog-to-digital converter (ADC), coupled to the sample-and-hold circuit and configured to convert the sampled value into a digital value, wherein: The comparator is coupled to the output of the ADC; and Comparing the sampled value with the first threshold includes comparing the digital value with the first threshold.

10. The image sensor according to claim 9, wherein: The image sensor includes column lines and a current source; The column lines are coupled to the current source, the amplifier, and the output terminal of the pixel; and The adaptive readout control circuit is also configured to controllably disconnect the column line from the current source in response to the comparison result.

11. The image sensor according to claim 8, wherein: The pixel includes an overflow pixel configured to provide a plurality of pixel values ​​in response to multiple corresponding readout operations (RO), wherein the plurality of pixel values ​​include a high conversion gain (HCG) reset value, an HCG image value, a medium conversion gain (MCG) reset value, an MCG image value, a low conversion gain (LCG) reset value, and an LCG image value. The memory is configured to provide a second threshold to the comparator, wherein: The first threshold corresponds to the HCG reset value RO; The second threshold corresponds to the HCG image value RO; and The comparator is configured to compare the sampled value with the second threshold and responsively output a second comparison result; and The adaptive readout control circuit is configured to disconnect at least one of the readout components from the supply voltage during at least one readout operation in the readout operation based on the first comparison result or the second comparison result.

12. The image sensor according to claim 11, wherein, The adaptive readout control circuit is configured as follows: In response to the first comparison result indicating that the HCG reset value is less than the first threshold, at least one of the readout components is disconnected from the supply voltage during the HCG image value RO, MCG image value RO, and MCG reset value RO. In response to the first comparison result indicating that the HCG reset value is greater than or equal to the first threshold and the second comparison result indicating that the HCG image value is less than the second threshold, at least one of the readout components is disconnected from the supply voltage during the period of LCG image value RO and LCG reset value RO; as well as In response to the first comparison result indicating that the HCG reset value is greater than or equal to the first threshold and the second comparison result indicating that the HCG image value is greater than or equal to the second threshold, at least one of the readout components is disconnected from the supply voltage during the MCG image value RO, the MCG reset value RO, the LCG image value RO, and the LCG reset value RO.

13. The image sensor according to claim 12, wherein, The image sensor is configured as follows: In response to the first comparison result indicating that the HCG reset value is less than the first threshold, a final pixel value is provided based on the LCG image value and the LCG reset value; In response to a first comparison result indicating that the HCG reset value is greater than or equal to the first threshold and a second comparison result indicating that the HCG image value is less than the second threshold, the final pixel value is provided based on the HCG reset value, the HCG image value, the MCG image value, and the MCG reset value. as well as The final pixel value is provided based on the HCG reset value and the HCG image value in response to the first comparison result indicating that the HCG reset value is greater than or equal to the first threshold and the second comparison result indicating that the HCG image value is greater than or equal to the second threshold.

14. The image sensor according to claim 11, wherein, The memory is configured to provide the first threshold and the second threshold based on the temperature of the image sensor or the length of the integration time of the pixel.

15. The image sensor according to claim 8, wherein: The image sensor includes a voltage terminal configured to provide the supply voltage; as well as The readout circuit includes a cut-off switch coupled between the voltage terminal and at least one of the plurality of readout components, wherein controllably disconnecting at least one of the plurality of readout components from the supply voltage includes controlling the cut-off switch.

16. An adaptive readout control circuit, the adaptive readout control circuit being configured to be coupled to a readout circuit of an image sensor, the adaptive readout control circuit comprising: A first input terminal is configured to receive a digital value corresponding to a pixel value from the readout circuit. The second input terminal is configured to receive the first threshold. and The output terminal is configured to be coupled to the readout circuit, wherein the adaptive readout control circuit is configured to: Compare the numerical value with the first threshold; as well as The readout circuitry can be controlled to be disabled via the output and based on the comparison during one or more pixel readout operations (RO).

17. The adaptive readout control circuit according to claim 16, wherein: The second input is further configured to receive a second threshold, wherein the first threshold corresponds to a reset value and the second threshold corresponds to an image value; and The adaptive readout control circuit is configured as follows: Compare the numerical value with the second threshold; and The readout circuit can be controlled to be disabled based on the comparison with the first threshold or the comparison with the second threshold.

18. The adaptive readout control circuit according to claim 17, wherein: The readout operation includes high conversion gain (HCG) reset value RO, HCG image value RO, medium conversion gain (MCG) image value RO, MCG reset value RO, low conversion gain (LCG) image value RO, and LCG reset value RO; Comparing the digital value with the first threshold includes comparing the first digital value corresponding to the HCG reset value with the first threshold. Comparing the digital value with the second threshold includes comparing a second digital value corresponding to the HCG image value with the second threshold. as well as Disabling the readout circuit includes: In response to the first digital value being less than the first threshold, the HCG image value RO, the MCG image value RO, and the MCG reset value RO are disabled; and In response to the first digital value being greater than or equal to the first threshold: In response to the second digital value being less than the second threshold, the LCG image value RO and the LCG reset value RO are disabled; and The MCG image value RO, the MCG reset value RO, and the LCG image value RO are disabled in response to the second digital value being greater than or equal to the second threshold.

19. The adaptive readout control circuit according to claim 16, wherein: The readout circuit includes a column amplifier, an analog-to-digital converter (ADC), and a sample-and-hold circuit; and Disabling the readout circuitry includes disconnecting the column amplifier, the ADC, or the sample-and-hold circuit from the voltage supply.

20. The adaptive readout control circuit according to claim 19, wherein: The image sensor includes a pixel having an output terminal and column lines, wherein the column lines are coupled to the output terminal of the pixel; The column lines are coupled to the current source and the readout circuit; and Disabling the readout circuitry includes disconnecting the column lines from the current source.

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