A selective poly-silicon passivated contact cell with anti-breaker pattern and method of fabrication

Abstract

The application discloses a selective polysilicon passivated contact cell with a breakable grid pattern and a preparation method. The cell comprises an N-type silicon wafer substrate 1, metal contact areas and non-metal contact areas arranged at intervals on the back surface of the N-type silicon wafer substrate 1; the non-metal contact area is provided with a recess structure recessed into the substrate, and a heavily doped area 7 extending into the substrate is arranged in the middle of the recess structure; the total area of the recess structure accounts for 90% to 95% of the back surface area of the substrate, and the area of the heavily doped area 7 accounts for 1% to 2% of the back surface area of the substrate. In the application, a part of the heavily doped area is arranged in the middle of the area where the doped polysilicon is removed, and the heavily doped area is located on the substrate, which is equivalent to shortening the carrier transmission path and improving the lateral transmission capacity of the back surface carriers. When the breakable grid occurs, the current can be transmitted through the heavily doped area, the resistance loss is reduced, the filling factor of the selective Poly structure is improved, and the cell efficiency is ensured.

Description

Technical Field

[0001] This invention belongs to the field of solar cells, specifically relating to a selective polycrystalline silicon passivated contact cell with an anti-breakage grid pattern and its preparation method. Background Technology

[0002] In recent years, with the successful industrialization of passivated emitter and field-conducting (PERC) technologies, the efficiency improvement of mass-produced P-type batteries has approached its bottleneck, and N-type batteries, which have higher minority carrier lifetime and lower degradation, have gradually attracted industry attention. Among them, TOPCon batteries, or passivated contact batteries, are gradually becoming the mainstream development trend of N-type batteries. Their structure involves preparing an ultrathin silicon oxide layer and a highly doped polycrystalline silicon layer (Poly-Si) on the silicon surface. The passivation effect of silicon oxide and the field passivation effect of the polycrystalline silicon layer can significantly reduce the minority carrier recombination rate on the silicon surface. However, the heavy doping of the polycrystalline silicon layer on the back side results in a large light absorption coefficient for long-wavelength light. This type of absorption is called free carrier absorption (FCA), which does not contribute to the photocurrent. Moreover, the higher the doping concentration of the polycrystalline silicon layer, the more severe the FCA absorption, the worse the spectral response of long-wavelength light, the lower the quantum efficiency, and the greater the loss of battery conversion efficiency.

[0003] To address the parasitic absorption of long-wavelength light in TOPCon cells, the mainstream industry solution is to replace the entire tunneling oxide / doped polysilicon layer structure on the back of the cell with a patterned selective tunneling oxide / doped polysilicon layer. This reduces parasitic absorption of long-wavelength light by decreasing the area of ​​the doped polysilicon. This structure is achieved by removing the Poly-Si layer outside the grid contact area using laser ablation and cleaning processes. However, this selective tunneling oxide / doped polysilicon layer structure also weakens the lateral transport capability of charge carriers on the back side, reducing the cell's fill factor, which is detrimental to improving TOPCon cell efficiency. Furthermore, in actual mass production, the screen printing slurry often suffers from poor slurry penetration, localized screen clogging, and uneven squeegee, leading to frequent breaks in the fine grid printing. These grid line discontinuities result in longer current transmission paths and increased resistance in the selective Poly-Si structure, further reducing the fill factor of the selective Poly structure cell and causing even lower efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a selective Poly-Si passivated contact cell structure with an anti-breakage grid pattern, based on existing technologies. This invention involves setting a partially heavily doped region in the middle of the undoped polycrystalline silicon region. This heavily doped region is located on the substrate and functions similarly to an anti-breakage grid, effectively shortening the carrier transport path and improving the lateral transport capability of carriers on the back side. Furthermore, in the event of a grid breakage, current can be transmitted through the heavily doped region, reducing resistance loss, improving the fill factor of the selective Poly structure, and ensuring cell efficiency.

[0005] The objective of this invention can be achieved through the following measures: A selective polycrystalline silicon passivated contact cell with an anti-breakage grid pattern includes an N-type silicon wafer substrate 1, and spaced-apart metal contact regions and non-metal contact regions on the back side of the N-type silicon wafer substrate 1. The non-metallic contact area has a recessed structure that is recessed into the substrate, and a heavily doped region 7 extending into the substrate is provided in the middle of the recessed structure; the total area of ​​the recessed structure accounts for 90% to 95% of the back surface area of ​​the substrate, and the area of ​​the heavily doped region 7 accounts for 1% to 2% of the back surface area of ​​the substrate.

[0006] In the selective polycrystalline silicon passivated contact cell with anti-breakage grid pattern of the present invention, preferably, the metal contact area is provided with a tunneling oxide layer 3 and a phosphorus-doped polycrystalline silicon layer 5 sequentially from the back side of the substrate outward.

[0007] In this invention, the cell contains one or more heavily doped regions 7 within a recessed structure, and the height difference between the bottom surface of the recessed structure and the back surface of the substrate is 2~5μm. Each heavily doped region 7 in this invention serves as a single anti-breakage gate; therefore, the number of anti-breakage gates in the cell is ≥1.

[0008] In this invention, the heavily doped region 7 is formed by the diffusion of phosphorus atoms into the silicon substrate, and its doping concentration is 0.1~1.0E+20 cm⁻¹. -3 The phosphorus atoms can originate from the tunneling oxide layer and phosphorus-doped polysilicon layer during the preparation process, or from other pathways. The thickness of the heavily doped region 7 is 1~4 μm.

[0009] The tunneling oxide layer 3 in this invention is made of silicon dioxide (SiO2). x The thickness of the tunneling oxide layer 3 is 0.5~2.5 nm, preferably 1.0~1.5 nm.

[0010] In this invention, the phosphorus doping concentration of the phosphorus atoms in the phosphorus-doped polycrystalline silicon layer 5 is 2.0~8.0E+20 cm-3, the sheet resistance is 40~150 Ω / sq, and the thickness of the phosphorus-doped polycrystalline silicon layer 5 is 60~200 nm.

[0011] In a preferred embodiment, the width W1 of the tunneling oxide layer 3 and the phosphorus-doped polysilicon layer 5 in the metal contact region is 45 to 95 µm, and the width W2 of the non-metallic contact region between two adjacent phosphorus-doped polysilicon layers (5) is 830 to 870 µm.

[0012] The present invention may further provide a boron-doped emitter 2 and a front surface passivation antireflection film 10 sequentially on the front side of the N-type silicon wafer substrate 1, and a back surface passivation antireflection film 9 on the surface of the phosphorus-doped polysilicon layer 5 and the recessed structure (and the heavily doped region 7) on the back side of the N-type silicon wafer substrate 1.

[0013] This invention discloses a method for fabricating a selective polycrystalline silicon passivated contact solar cell with an anti-breakage grid pattern, comprising the following steps S1, S2, S3, S4, and S5: S1. Tunnel oxide layer and intrinsic polysilicon layer are grown on the back surface: Take an N-type silicon substrate 1 with a boron-doped emitter on the front and a smooth back, and grow a tunnel oxide layer and an intrinsic polysilicon layer on the entire back surface. S2, Phosphorus diffusion: Phosphorus diffusion is performed on the back side of the N-type silicon wafer to form a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer; S3, Laser doping: Laser is used to pattern and heavily dope the back surface of the silicon wafer, removing the local tunneling oxide layer, phosphorus-doped polysilicon layer and phosphorus-silicon glass layer, and diffusing phosphorus atoms in the phosphorus-silicon glass layer and phosphorus-doped polysilicon layer in the corresponding area into the silicon wafer substrate by 3~6 μm to form a heavily doped region. S4. Laser film opening: Laser is used to open the phosphosilicate glass layer, removing the phosphosilicate glass layer around the heavily doped region, leaving the non-metallic contact area, while the phosphosilicate glass layer is still retained in the metallic contact area. S5. Wet chemical etching: Wet chemical etching is performed on the non-metallic contact area on the back surface of the silicon wafer to remove the tunneling oxide layer and phosphorus-doped polysilicon layer in this area, and 2~5μm is etched into the silicon substrate to form a recessed structure and heavily doped region 7; then the phosphorus silicon glass layer in the metal contact area is removed.

[0014] This invention also discloses another method for preparing a selective polycrystalline silicon passivated contact cell with an anti-breakage grid pattern, comprising the following steps S11, S22, S3, S4, and S5: S11. Tunnel oxide layer and intrinsic polysilicon layer grown on the back surface: Take an N-type silicon substrate 1 with a boron-doped emitter on the front and a smooth back, and grow a tunnel oxide layer and an in-situ phosphorus-doped polysilicon layer on the entire back surface. S22, Annealing and thermal crystallization treatment: The N-type silicon wafer is subjected to high-temperature annealing treatment, and after annealing, a doped polycrystalline silicon layer and a phosphosilicate glass layer are formed. S3, Laser doping: Laser is used to pattern and heavily dope the back surface of the silicon wafer, removing the local tunneling oxide layer, phosphorus-doped polysilicon layer and phosphorus-silicon glass layer, and diffusing phosphorus atoms in the phosphorus-silicon glass layer and phosphorus-doped polysilicon layer in the corresponding area into the silicon wafer substrate by 3~6 μm to form a heavily doped region. S4. Laser film opening: Laser is used to open the phosphosilicate glass layer, removing the phosphosilicate glass layer around the heavily doped region, leaving the non-metallic contact area, while the phosphosilicate glass layer is still retained in the metallic contact area. S5. Wet chemical etching: Wet chemical etching is performed on the non-metallic contact area on the back surface of the silicon wafer to remove the tunneling oxide layer and phosphorus-doped polysilicon layer in this area, and 2~5μm is etched into the silicon substrate to form a recessed structure and heavily doped region 7; then the phosphorus silicon glass layer in the metal contact area is removed.

[0015] In various preparation methods of the present invention, the following steps S6 and S7 may be further included: S6. Deposit passivation antireflection film: Deposit a surface passivation antireflection film on the back side of the silicon wafer and deposit a front surface passivation antireflection film on the front side of the silicon wafer; S7. Metal Electrode Printing and Sintering: Metallization patterns are printed on the front and back sides of the silicon wafer and then sintered to prepare metal electrodes.

[0016] In step S1, preferably, an ultrathin tunneling oxide layer and an intrinsic polycrystalline silicon layer are grown on the entire back surface of a silicon wafer in a low-pressure chemical vapor deposition apparatus. The material of the tunneling oxide layer is silicon dioxide, and the thickness of the tunneling oxide layer is 0.5~2.5 nm. The deposition temperature of the intrinsic polycrystalline silicon is 610~620 °C, and the thickness of the intrinsic polycrystalline silicon is 60~200 nm.

[0017] In step S2, preferably, phosphorus diffusion is performed on the back side of the N-type silicon wafer. The phosphorus source for diffusion is phosphorus oxychloride, the peak diffusion temperature is 800~900 °C, and the phosphorus diffusion time is 25~30 min. After the phosphorus diffusion is completed, a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer are formed. The phosphorus doping concentration of phosphorus atoms in the phosphorus-doped polycrystalline silicon layer is 2.0~8.0E+20 cm-3, the sheet resistance is 40~150 Ω / sq, and the thickness of the phosphorus-silicon glass layer is 25~30 nm.

[0018] In step S3, preferably, a laser is used to pattern and heavily dope the back surface of the silicon wafer, pushing phosphorus atoms from the localized phosphorus-silicon glass and phosphorus-doped polycrystalline silicon layer into the silicon substrate. The phosphorus atoms diffuse into the silicon substrate by 3-6 μm, forming a heavily doped region; the phosphorus doping concentration in the heavily doped region is 0.1-1.0E+20 cm⁻¹. -3The area of ​​the heavily doped region accounts for 1% to 2% of the back surface area of ​​the silicon wafer. The laser spot is a square spot with a length and width of 100 to 500 µm. The wavelength of the laser is 600 to 1100 nm and is at least one of nanosecond lasers. In the unit cell, the number of heavily doped regions is ≥1.

[0019] In step S4, preferably, the laser spot is a square spot with a length and width of 100~500 µm, the laser wavelength is 350~540 nm, and it is at least one of picosecond lasers.

[0020] In step S5, preferably, a mixed solution of wet additive + KOH & NaOH + water is used to etch the silicon wafer. The reaction temperature of the solution is 60±10℃, the reaction time is 5~8 min, and the etching depth of the silicon wafer is 2~5μm. After etching, the wafer is rinsed with pure water and then placed in a tank containing HF solution to remove the remaining PSG protective layer. After wet chemical etching, the area of ​​the unremoved phosphorus-doped polysilicon layer accounts for 5%~10% of the back surface area of ​​the battery, the width W1 of the unremoved phosphorus-doped polysilicon layer is 45~95 µm, the total area of ​​the etched area accounts for 90%~95% of the back surface area of ​​the silicon wafer, and the width W2 between two adjacent phosphorus-doped polysilicon layers (5) is 830~870 µm.

[0021] In step S11, preferably, the material of the tunneling oxide layer is silicon dioxide, and the thickness of the tunneling oxide layer is 0.5~2.5 nm; the deposition temperature of the in-situ phosphorus-doped polycrystalline silicon layer is 500~650ºC, and its thickness is 80~200 nm.

[0022] In step S12, preferably, the annealing temperature is 800~950 ºC and the annealing time is 30~90 min; the doping concentration of phosphorus atoms in the doped polycrystalline silicon layer is 2.0~8.0E+20 cm-3 and the sheet resistance is 40~150 Ω / sq; the thickness of the phosphorus silicon glass layer is 25~30 nm.

[0023] This invention employs a laser to perform two laser treatments on the back of a TOPCon cell, forming a selective polycrystalline silicon passivated contact cell structure with an anti-breakage grid pattern. The first laser doping treatment localizes the phosphorus-silicon glass layer, pushing the abundant phosphorus atoms in the phosphorus-silicon glass layer and the phosphorus-doped polycrystalline silicon layer (Poly-Si) into the silicon substrate, resulting in a locally distributed heavily doped phosphorus layer on the back of the silicon wafer. Furthermore, the heavily doped region exists on the silicon substrate and is located within the removed tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer (SiO2). x The / Poly-Si) region. After the second laser film-opening process, the phosphorus-silicon glass protective layer on the back side was partially removed. In the subsequent wet etching, the SiO₂ without the phosphorus-silicon glass protective layer was exposed. x / Poly-Si is removed, and SiO2 with a phosphorus-silicon glass protective layer is formed. x / Poly-Si was not removed. The heavily doped region of this invention is located on the substrate, which allows current to be effectively transported through the heavily doped region in the event of a gate breakage, shortening the carrier transport path and improving the lateral transport capability of carriers on the back side; moreover, in the event of a gate breakage, the anti-gate breakage structure reduces the dependence of carrier transport on the fine gate lines, which can significantly improve the lateral transport of the back side current and avoid a significant reduction in the fill factor.

[0024] The selective polycrystalline silicon passivated contact battery disclosed in this invention has the following beneficial effects: 1) In this invention, the TOPCon battery adopts a selective Poly passivated contact battery structure with an anti-breakage grid pattern on the back. The metal contact area on the back of the battery adopts a passivation structure locally composed of a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer, while the SiO2 / Poly in the non-metal contact area is locally removed. This structure can effectively reduce parasitic absorption of long-wavelength light. 2) The selective poly structure of the anti-breakage grid pattern sets the locally heavily doped region in the middle of the removed doped polysilicon region. The locally heavily doped layer balances the loss of carrier lateral transport and carrier recombination, which helps to improve the efficiency of the battery. 3) The locally heavily doped region is located in the silicon substrate, rather than on the heavily doped polycrystalline silicon layer. The introduction of the locally heavily doped region will not cause additional optical loss to the back side and will not reduce the efficiency of the back side of the battery. 4) In the event of grid breakage during mass production, the improved lateral current transport on the back side reduces the dependence of charge carriers on grid line transport, which can effectively avoid a significant reduction in the fill factor and enhance the process stability of the battery. Attached Figure Description

[0025] Figure 1 This is a schematic diagram showing the result of step 1) in Embodiments 1-2 of the present invention; Figure 2 This is a schematic diagram showing the result of step 2) in Embodiments 1-2 of the present invention; Figure 3 This is a schematic diagram showing the result of step 3) in Embodiments 1-2 of the present invention; Figure 4 This is a schematic diagram showing the result of step 4) in Embodiments 1-2 of the present invention; Figure 5 This is a schematic diagram showing the result of step 5) in Embodiments 1-2 of the present invention; Figure 6 This is a schematic diagram of the planar result of step 6) in Embodiment 1 of the present invention; Figure 7 This is the present invention. Figure 6Schematic diagram of the cross-section at position AA; Figure 8 This is a schematic diagram of the planar result of step 7) in Embodiment 1 of the present invention; Figure 9 This is the present invention. Figure 8 Schematic diagram of the cross-section at the location of BB in the middle; Figure 10 This is a schematic diagram showing the result of step 8) in Embodiment 1 of the present invention; Figure 11 This is a schematic diagram showing the result of step 9) in Embodiment 1 of the present invention; Figure 12 This is a schematic diagram of the planar result of step 10) in Embodiment 1 of the present invention; Figure 13 This is the present invention. Figure 12 Schematic diagram of the cross-section at the CC position; Figure 14 This is the present invention. Figure 12 Schematic diagram of the cross-section at the DD position in the middle; Figure 15 This is a schematic diagram showing the result of step 10) in Embodiment 2 of the present invention; Figure 16 This is a schematic diagram showing the result of step 9) in Comparative Example 1 of the present invention; In this diagram, 1 is a silicon substrate, 2 is a boron-doped emitter, 3 is a tunneling oxide layer, 4 is an intrinsic amorphous silicon layer, 5 is a phosphorus-doped polycrystalline silicon layer, 6 is a phosphorus-silicon glass layer, 7 is a heavily doped region, 8 is a region where the polycrystalline silicon has been dedoped, 9 is a back surface passivation antireflection film, 10 is a front surface passivation antireflection film, 111 is a front metal main gate line, 112 is a back metal main gate line, 121 is a front metal fine gate line, and 122 is a back metal fine gate line. Detailed Implementation

[0026] The present invention can be better understood from the following embodiments. However, those skilled in the art will readily understand that the descriptions in the embodiments are for illustrative purposes only and should not, and will not, limit the invention as detailed in the claims.

[0027] TOPCon battery, Tunnel Oxide Passivated Contact solar cell, full name: tunneling oxide passivated contact solar cell.

[0028] Poly-Si, Poly-crystalline silicon, full name: polycrystalline silicon.

[0029] PERC battery, Passivated Emitter and Rear Cell, is also known as a passivated emitter and rear cell.

[0030] HJT battery, Heterojunction with Intrinsic Thin Layer Cell, full name: heterojunction battery.

[0031] BC battery, Back Contact cell, full name: back contact battery.

[0032] like Figure 12-15 For example, the selective polycrystalline silicon passivated contact cell with anti-breakage grid pattern of the present invention includes an N-type silicon wafer substrate 1, on the front side of which a boron-doped emitter 2 and a front surface passivation antireflection film 10 are sequentially provided, and on the back side of the N-type silicon wafer substrate 1, there are spaced metal contact areas and non-metal contact areas.

[0033] The non-metallic contact area on the back side of the substrate has a recessed structure that extends inward into the substrate. A heavily doped region 7 extending inward into the substrate is located in the center of this recessed structure. The total area of ​​the recessed structure accounts for 90% to 95% of the back surface area of ​​the substrate, and the area of ​​the heavily doped region 7 accounts for 1% to 2% of the back surface area of ​​the substrate. In a single cell, there are one or more heavily doped regions 7 within the recessed structure, and the height difference between the bottom surface of the recessed structure and the back surface of the substrate is 2 to 5 μm. The heavily doped region 7 is formed by the diffusion of phosphorus atoms into the silicon substrate, and its doping concentration is 0.1 to 1.0E+20 cm⁻¹. -3 The phosphorus atoms can originate from the tunneling oxide layer and phosphorus-doped polysilicon layer during the preparation process, or from other pathways. The thickness of the heavily doped region 7 is 1~4 μm.

[0034] The metal contact area on the back side of the substrate has a tunneling oxide layer 3 and a phosphorus-doped polycrystalline silicon layer 5 sequentially arranged from the back side outwards. The tunneling oxide layer 3 is made of silicon dioxide (SiO₂). x The thickness of the tunneling oxide layer 3 is 0.5~2.5 nm, preferably 1.0~1.5 nm. The phosphorus doping concentration of the phosphorus atoms in the phosphorus-doped polycrystalline silicon layer 5 is 2.0~8.0E+20 cm-3, the sheet resistance is 40~150 Ω / sq, and the thickness of the phosphorus-doped polycrystalline silicon layer 5 is 60~200 nm.

[0035] In one specific embodiment, the width W1 of the tunneling oxide layer 3 and the phosphorus-doped polysilicon layer 5 in the metal contact region is 45 to 95 µm, and the width W2 of the non-metallic contact region between two adjacent phosphorus-doped polysilicon layers (5) is 830 to 870 µm.

[0036] Furthermore, a back surface passivation antireflection film 9 can be provided on the surface of the phosphorus-doped polysilicon layer 5 and the recessed structure (and the heavily doped region 7) on the back side of the N-type silicon wafer substrate 1.

[0037] The fabrication steps of a selectively passivated contact battery with an anti-breakage grid pattern are as follows: 1) The N-type silicon wafer is surface-cleaned to remove the damaged layer and then texturized. The thickness of the N-type silicon wafer is 100~180 μm. Sodium hydroxide and a texturizing additive are used for texturizing. The texturizing additive is a commercially available, conventional additive. The solution ratio is approximately texturizing additive:sodium hydroxide:water = 1:2:200. The reaction temperature is 80~85 °C. The height of the pyramid formed by texturizing ranges from 0.5~2 μm (see appendix). Figure 1 (As shown).

[0038] 2) Double-sided boron diffusion is performed on the N-type silicon wafer to form the emitter. The boron source for diffusion is boron tribromide or boron trichloride, and the peak diffusion temperature is 1000~1100 °C. After boron diffusion, the sheet resistance of the emitter is 320~480 Ω / sq, preferably 360~420 Ω / sq (see appendix). Figure 2 (As shown).

[0039] 3) Back surface polishing to remove the emitter formed by boron diffusion on the back side. The back surface of the silicon wafer is polished using sodium hydroxide and a commercially available additive. The solution ratio is approximately: additive:sodium hydroxide:water = 1:5:90. The reaction temperature is 55~60 °C, and the polishing depth is 5~8 μm (see appendix). Figure 3 (As shown).

[0040] 4) Growth of a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface. In a low-pressure chemical vapor deposition (LPCVD) system, an ultrathin tunneling oxide layer and an intrinsic polycrystalline silicon layer are grown across the entire back surface of the silicon wafer. The tunneling oxide layer is made of silicon dioxide (SiO₂). x The thickness is 0.5~2.5 nm, preferably 1.0~1.5 nm. The deposition temperature of intrinsic polycrystalline silicon is 610~620 °C, and the thickness is 60~200 nm. (See appendix) Figure 4 (As shown).

[0041] 5) Phosphorus diffusion is performed on the N-type silicon wafer to form a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer on the back side. Phosphorus oxychloride is used as the phosphorus source for diffusion, with a peak diffusion temperature of 800–900 °C and a diffusion time of 25–30 min. After phosphorus diffusion, a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer (PSG) are formed. The phosphorus doping concentration in the polycrystalline silicon layer (Poly-Si) is 2.0–8.0E+20 cm⁻³, the sheet resistance is 40–150 Ω / sq, and the thickness of the PSG layer is 25–30 nm. (See Appendix) Figure 5 (As shown).

[0042] 6) Laser doping to complete the fabrication of the back-side anti-breakage gate structure. A laser is used to pattern and heavily dope the back surface of the silicon wafer sample, removing localized tunneling oxide layers, phosphorus-doped polycrystalline silicon layers, and phosphorus-silicon glass layers. Phosphorus atoms from the removed phosphorus-silicon glass and phosphorus-doped polycrystalline silicon layers are then pushed into the silicon substrate to form a heavily doped layer similar to the anti-breakage gate structure. In Example 1, the number of anti-breakage gates (i.e., the number of heavily doped layers) in the single-cell cell is 1. In Example 2, the number of anti-breakage gates (i.e., the number of heavily doped layers) in the single-cell cell is 2. After laser doping, localized SiO₂ on the back side... x The Poly-Si (tunneling oxide / phosphorus-doped polysilicon layer) and PSG (phosphosilicate glass layer) layers are removed. Phosphorus atoms in the phosphorus-doped polysilicon layer diffuse into the silicon substrate at a depth of 3–6 μm, with a doping concentration of 0.1–1.0E+20 cm⁻¹. -3 The area of ​​the heavily doped region accounts for 1-2% of the back surface area of ​​the battery (1% in Example 1 and 2% in Example 2). The laser spot is a square spot with a length and width of 100-500 µm. The wavelength of the laser is 600-1100 nm and is at least one of nanosecond lasers, such as a 650 nm red laser, an 820 nm near-infrared laser, or a 1030 nm infrared laser. The laser frequency is 50-300 kHz, the scanning speed is 20-30 m / s, and the laser energy density is 0.5-5 J / cm². 2 (The results of Example 1 are attached.) Figure 6 , 7 As shown, Figure 6 It is a two-dimensional plan view. Figure 7 This is a cross-sectional view; the cross-section is located at... Figure 6 (AA in the text).

[0043] 7) Laser-assisted patterning to complete the patterning of the back phosphosilicate glass (PSG) layer. A laser is used to pattern the PSG layer, removing the PSG layer around the heavily doped regions and leaving the non-metallic contact areas. The PSG layer remains in the metallic contact areas. After laser patterning, a localized area of ​​the back PSG layer is removed, leaving space for the non-metallic contact areas. The laser spot is a square spot with dimensions of 100–500 µm, a wavelength of 350–540 nm, and is at least one of picosecond lasers, such as a 355 nm ultraviolet laser or a 532 nm green laser. The laser frequency is 50–300 kHz, the scanning speed is 30–50 m / s, and the laser energy density is 0.1–0.5 J / cm². 2 (The results of Example 1 are attached.) Figure 8 , 9 As shown, Figure 8 It is a two-dimensional plan view. Figure 9This is a cross-sectional view; the cross-section is located at... Figure 8 (BB in the middle).

[0044] 8) Wet chemical etching to form a selective polysilicon layer with an anti-gate breakage structure. The silicon wafer is then placed in a wet chemical etching bath and etched using a mixed solution of wet additives, KOH & NaOH, and water (ratio 1:5:90). As mentioned above, the areas without the PSG protective layer are etched away. In these areas, the doped polysilicon layer, tunneling oxide layer, and part of the back side of the wafer are etched away by the solution reaction. The doped polysilicon layer in areas not affected by laser etching is protected by PSG and remains intact in the solution. The reaction temperature is 60±10℃, the reaction time is 5~8 min, and the etching depth is 2~5 μm. After rinsing with pure water, the wafer is placed in a bath containing HF solution to remove the remaining PSG protective layer. After wet chemical etching, the unremoved SiO2... x The / Poly region (i.e., the metal contact region) occupies 5%–10% of the battery's back surface area, with a width of W1 (45–95 µm). The heavily doped region is located within the removed SiO₂. x Within the / Poly-Si region, i.e., within the recessed structure, the removed SiO x The total area of ​​the / Poly-Si region accounts for 90%~95% of the back surface area of ​​the silicon wafer, with a width of W2 (830~870 µm). (See Appendix for results of Example 1). Figure 10 (As shown). In Example 1, the number of anti-breakage grids in the cell is 1, meaning there is one heavily doped region within a single recessed structure. In Example 2, the number of anti-breakage grids in the cell is 2, meaning there are two heavily doped regions within a single recessed structure.

[0045] 9) Deposition of passivation and antireflection films on the front and rear surfaces. The passivation and antireflection films on the front and rear surfaces adopt a stacked film design, which is a combination of two materials such as alumina, silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, an alumina / silicon nitride passivation and antireflection film stacked design is adopted, wherein the preferred thickness of alumina is 2-10 nm, the preferred thickness of silicon nitride is 20-50 nm, and the refractive index of silicon nitride is 2.1-2.2 (see Appendix for results of Example 1). Figure 11 (As shown).

[0046] 10) Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are printed on the front and back surfaces (printing is done using screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front is 10–60 µm, the height is 5–10 µm, the grid spacing is 0.9–1.5 mm, and the number is 150–250. The width of the fine metal grid lines on the back is 10–30 µm, the height is 5–10 µm, the grid spacing is 0.90–0.95 mm, and the number is 200. The width of the main grid lines is 30–100 µm, the height is 2–8 µm, the grid spacing is 10–20 mm, and the number is 10–20. The sintering temperature is 700–850 °C; or a laser-assisted enhanced sintering process can be used to enhance contact and reduce contact resistivity (see Appendix for results of Example 1). Figures 12-14 As shown, Figure 12 It is a two-dimensional plan view. Figure 13 , 14 They are respectively Figure 12 The structural diagrams for positions CC and DD are shown; one spans the main gate, and the other spans the fine gate. The results of Example 2 are attached. Figure 15 (As shown). Example

[0047] The fabrication steps of a selectively passivated contact battery with an anti-breakage grid pattern are as follows: 1) The N-type silicon wafer is surface-cleaned to remove the damaged layer and then texturized. The thickness of the N-type silicon wafer is 100~180 μm. Sodium hydroxide and a texturizing additive are used for texturizing. The texturizing additive is a commercially available, conventional additive. The solution ratio is approximately texturizing additive:sodium hydroxide:water = 1:2:200. The reaction temperature is 80~85 °C. The height of the pyramid formed by texturizing ranges from 0.5~2 μm (see appendix). Figure 1 (As shown).

[0048] 2) Double-sided boron diffusion is performed on the N-type silicon wafer to form the emitter. The boron source for diffusion is boron tribromide or boron trichloride, and the peak diffusion temperature is 1000~1100 °C. After boron diffusion, the sheet resistance of the emitter is 320~480 Ω / sq, preferably 360~420 Ω / sq (see appendix). Figure 2 (As shown).

[0049] 3) Back surface polishing to remove the emitter formed by boron diffusion on the back side. The back surface of the silicon wafer is polished using sodium hydroxide and a commercially available additive. The solution ratio is approximately: additive:sodium hydroxide:water = 1:5:90. The reaction temperature is 55~60 °C, and the polishing depth is 5~8 μm (see appendix). Figure 3 (As shown).

[0050] 4) Growth of a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the back surface. In a plasma-enhanced chemical vapor deposition (PECVD) system, an ultrathin tunneling oxide layer and an in-situ phosphorus-doped polycrystalline silicon layer are grown across the entire back surface of the silicon wafer. The tunneling oxide layer is made of silicon dioxide and has a thickness of 0.5–2.5 nm, preferably 1.0–1.5 nm. The in-situ phosphorus-doped polycrystalline silicon is deposited at a temperature of 500–650 ºC and has a thickness of 80–200 nm.

[0051] 5) Annealing and thermal crystallization treatment. The silicon wafer samples undergo high-temperature annealing. During annealing, the microcrystalline silicon phase in the polycrystalline silicon layer is completely transformed into the polycrystalline silicon phase, completing crystallization. Simultaneously, the in-situ doped phosphorus atoms can be activated by the high temperature to form substitutional doping. The annealing temperature is 800–950 ºC, and the annealing time is 30–90 min. After annealing, a doped polycrystalline silicon layer and a phosphorus silicate glass (PSG) layer are formed. The phosphorus doping concentration in the polycrystalline silicon layer (Poly-Si) is 2.0–8.0E+20 cm⁻³, the sheet resistance is 40–150 Ω / sq, and the thickness of the PSG layer is 25–30 nm. (See Appendix) Figure 5 (As shown).

[0052] 6) Laser doping to complete the fabrication of the back-side anti-breakage gate structure. A laser is used to pattern and heavily dope the back surface of the silicon wafer sample, removing localized tunneling oxide layers, phosphorus-doped polycrystalline silicon layers, and phosphorus-silicon glass layers. Phosphorus atoms from the removed phosphorus-silicon glass and phosphorus-doped polycrystalline silicon layers are then pushed into the silicon substrate, forming a heavily doped layer similar to the anti-breakage gate structure. In this example, the number of anti-breakage gates (i.e., the number of heavily doped layers) in the single cell is 1. After laser doping, localized SiO₂ on the back side... x The Poly-Si (tunneling oxide / phosphorus-doped polysilicon layer) and PSG (phosphosilicate glass layer) layers are removed. Phosphorus atoms in the phosphorus-doped polysilicon layer diffuse into the silicon substrate at a depth of 3–6 μm, with a doping concentration of 0.1–1.0E+20 cm⁻¹. -3 The heavily doped region occupies 1% of the battery's back surface area. The laser spot is a square spot with a length and width of 100-500 µm. The laser wavelength is 600-1100 nm and is at least one of nanosecond lasers, such as a 650 nm red laser, an 820 nm near-infrared laser, or a 1030 nm infrared laser. The laser frequency is 50-300 kHz, the scanning speed is 20-30 m / s, and the laser energy density is 0.5-5 J / cm². 2 (See appendix) Figure 6 , 7 As shown, Figure 6 It is a two-dimensional plan view. Figure 7This is a cross-sectional view; the cross-section is located at... Figure 6 (AA in the text).

[0053] 7) Laser-assisted patterning to complete the patterning of the back phosphosilicate glass (PSG) layer. A laser is used to pattern the PSG layer, removing the PSG layer around the heavily doped regions and leaving the non-metallic contact areas. The PSG layer remains in the metallic contact areas. After laser patterning, a localized area of ​​the back PSG layer is removed, leaving space for the non-metallic contact areas. The laser spot is a square spot with dimensions of 100–500 µm, a wavelength of 350–540 nm, and is at least one of picosecond lasers, such as a 355 nm ultraviolet laser or a 532 nm green laser. The laser frequency is 50–300 kHz, the scanning speed is 30–50 m / s, and the laser energy density is 0.1–0.5 J / cm². 2 (See appendix) Figure 8 , 9 As shown, Figure 8 It is a two-dimensional plan view. Figure 9 This is a cross-sectional view; the cross-section is located at... Figure 8 (BB in the middle).

[0054] 8) Wet chemical etching to form a selective polysilicon layer with an anti-gate breakage structure. The silicon wafer is then placed in a wet chemical etching bath and etched using a mixed solution of wet additives, KOH & NaOH, and water (ratio 1:5:90). As mentioned above, the areas without the PSG protective layer are etched away. In these areas, the doped polysilicon layer, tunneling oxide layer, and part of the back side of the wafer are etched away by the solution reaction. The doped polysilicon layer in areas not affected by laser etching is protected by PSG and remains intact in the solution. The reaction temperature is 60±10℃, the reaction time is 5~8 min, and the etching depth is 2~5 μm. After rinsing with pure water, the wafer is placed in a bath containing HF solution to remove the remaining PSG protective layer. After wet chemical etching, the unremoved SiO2... x The / Poly region (i.e., the metal contact region) occupies 5%–10% of the battery's back surface area, with a width of W1 (45–95 µm). The heavily doped region is located within the removed SiO₂. x Within the / Poly-Si region, i.e., within the recessed structure, the removed SiO x The total area of ​​the / Poly-Si region accounts for 90%~95% of the back surface area of ​​the silicon wafer, with a width of W2 (830~870 µm). (See appendix) Figure 10 (As shown). In this example, the number of anti-breakage grids in the cell is 1, meaning there is one heavily doped region within a single recessed structure.

[0055] 9) Deposition of passivation and antireflection films on the front and rear surfaces. The passivation and antireflection films on the front and rear surfaces adopt a stacked film design, which is a combination of two materials such as alumina, silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, an alumina / silicon nitride passivation and antireflection film stacked design is adopted, wherein the preferred thickness of alumina is 2-10 nm, the preferred thickness of silicon nitride is 20-50 nm, and the refractive index of silicon nitride is 2.1-2.2 (see Appendix). Figure 11 (As shown).

[0056] 10) Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are printed on the front and back surfaces (printing is done using screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front is 10–60 µm, the height is 5–10 µm, the grid spacing is 0.9–1.5 mm, and the number is 150–250. The width of the fine metal grid lines on the back is 10–30 µm, the height is 5–10 µm, the grid spacing is 0.90–0.95 mm, and the number is 200. The width of the main grid lines is 30–100 µm, the height is 2–8 µm, the grid spacing is 10–20 mm, and the number is 10–20. The sintering temperature is 700–850 ℃; or a laser-assisted enhanced sintering process can be used to enhance contact and reduce contact resistivity (see appendix). Figures 12-14 As shown, Figure 12 It is a two-dimensional plan view. Figure 13 , 14 They are respectively Figure 12 The diagram shows the structures at positions CC and DD, one spanning the main gate and the other spanning the fine gate.

[0057] The fabrication steps of a selectively passivated contact battery with an anti-breakage grid pattern are as follows: 1) The N-type silicon wafer is surface-cleaned to remove the damaged layer and then texturized. The thickness of the N-type silicon wafer is 100~180 μm. Sodium hydroxide and a texturizing additive are used for texturizing. The texturizing additive is a commercially available, conventional additive. The solution ratio is approximately texturizing additive:sodium hydroxide:water = 1:2:200. The reaction temperature is 80~85 °C. The height of the pyramid formed by texturizing ranges from 0.5~2 μm (see appendix). Figure 1 (As shown).

[0058] 2) Double-sided boron diffusion is performed on the N-type silicon wafer to form the emitter. The boron source for diffusion is boron tribromide or boron trichloride, and the peak diffusion temperature is 1000~1100 °C. After boron diffusion, the sheet resistance of the emitter is 320~480 Ω / sq, preferably 360~420 Ω / sq (see appendix). Figure 2 (As shown).

[0059] 3) Back surface polishing to remove the emitter formed by boron diffusion on the back side. The back surface of the silicon wafer is polished using sodium hydroxide and a commercially available additive. The solution ratio is approximately: additive:sodium hydroxide:water = 1:5:90. The reaction temperature is 55~60 °C, and the polishing depth is 5~8 μm (see appendix). Figure 3 (As shown).

[0060] 4) Growth of a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface. In a low-pressure chemical vapor deposition (LPCVD) system, an ultrathin tunneling oxide layer and an intrinsic polycrystalline silicon layer are grown across the entire back surface of the silicon wafer. The tunneling oxide layer is made of silicon dioxide (SiO₂). x The thickness is 0.5~2.5 nm, preferably 1.0~1.5 nm. The deposition temperature of intrinsic polycrystalline silicon is 610~620 °C, and the thickness is 60~200 nm. (See Appendix) Figure 4 (As shown).

[0061] 5) Phosphorus diffusion is performed on the N-type silicon wafer to form a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer on the back side. Phosphorus oxychloride is used as the phosphorus source for diffusion, with a peak diffusion temperature of 800–900 °C and a diffusion time of 25–30 min. After phosphorus diffusion, a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer (PSG) are formed. The phosphorus doping concentration in the polycrystalline silicon layer (Poly-Si) is 2.0–8.0E+20 cm⁻³, the sheet resistance is 40–150 Ω / sq, and the thickness of the PSG layer is 25–30 nm. (See Appendix) Figure 5 (As shown).

[0062] 6) Laser ablation to pattern the back phosphosilicate glass (PSG) layer. A laser is used to ablate the phosphosilicate glass layer, removing the layer in the non-metallic contact areas while retaining it in the metallic contact areas. After laser ablation, a portion of the back phosphosilicate glass protective layer (PSG) is removed, leaving space for the non-metallic contact areas. The laser spot is a square spot with dimensions of 100–500 µm, a wavelength of 350–540 nm, and is at least one of a picosecond laser, such as a 355 nm ultraviolet laser or a 532 nm green laser. The laser frequency is 50–300 kHz, the scanning speed is 30–50 m / s, and the laser energy density is 0.1–0.5 J / cm². 2 .

[0063] 7) Wet chemical etching to form a selective polysilicon layer with an anti-gate breakage structure. The silicon wafer is then placed in a wet chemical etching bath and etched using a mixed solution of wet additives, KOH & NaOH, and water (ratio 1:5:90). Areas without the PSG protective layer are etched away; the doped polysilicon layer, tunneling oxide layer, and part of the back side of the wafer in these areas are etched away by the solution reaction. The doped polysilicon layer in areas not affected by laser etching is protected by PSG and remains intact in the solution. The reaction temperature is 60±10℃, the reaction time is 5~8 min, and the etching depth is 2~5 μm. After rinsing with pure water, the silicon wafer is placed in a bath containing HF solution to remove the remaining PSG protective layer. After wet chemical etching, any unremoved SiO₂... x The / Poly region (i.e., the metal contact region) occupies 5%–10% of the battery's back surface area, with a width of W1 (45–95 µm). The removed SiO₂... x The total area of ​​the / Poly-Si region accounts for 90% to 95% of the back surface area of ​​the silicon wafer, and its width is W2 (830 to 870 µm).

[0064] 8) Deposition of passivation and antireflection films on the front and back surfaces. The passivation and antireflection films on the front and back surfaces adopt a stacked film design, which is a combination of two materials such as alumina, silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, an alumina / silicon nitride passivation and antireflection film stacked design is adopted, wherein the preferred thickness of alumina is 2-10 nm, the preferred thickness of silicon nitride is 20-50 nm, and the refractive index of silicon nitride is 2.1-2.2.

[0065] 9) Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are printed on the front and back surfaces (printing is done using screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front is 10–60 µm, the height is 5–10 µm, the grid spacing is 0.9–1.5 mm, and the number is 150–250. The width of the fine metal grid lines on the back is 10–30 µm, the height is 5–10 µm, the grid spacing is 0.90–0.95 mm, and the number is 200. The width of the main grid lines is 30–100 µm, the height is 2–8 µm, the grid spacing is 10–20 mm, and the number is 10–20. The sintering temperature is 700–850 ℃; or a laser-assisted enhanced sintering process can be used to enhance contact and reduce contact resistivity (see appendix). Figure 16 ).

[0066] The selectively poly passivated contact cells obtained in Examples 1-3 and Comparative Example 1 were subjected to IV performance tests, and the test results are shown in Table 1.

[0067] Table 1

[0068] The IV performance testing method is as follows: First, simulate the solar spectrum and light intensity under standard test conditions, namely the "AM1.5G" spectrum and an irradiance of 1000 W / m², while precisely controlling the battery temperature at the standard temperature (usually 25°C). Next, connect the battery using a four-wire probe station and conduct the test. Typically, a digital source meter is used to precisely apply voltage and simultaneously measure current, or apply current and measure voltage. Finally, software controls the instrument, collects data, and calculates parameters.

[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications may still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions may be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A selective polycrystalline silicon passivated contact cell with an anti-breakage grid pattern, comprising an N-type silicon wafer substrate (1), characterized in that, The back surface of the N-type silicon substrate (1) includes spaced-apart metal contact regions and non-metal contact regions; wherein, The non-metallic contact area is provided with a recessed structure that is recessed into the substrate, and a heavily doped region (7) extending into the substrate is provided in the middle of the recessed structure; the total area of ​​the recessed structure accounts for 90% to 95% of the back surface area of ​​the substrate, and the area of ​​the heavily doped region (7) accounts for 1% to 2% of the back surface area of ​​the substrate.

2. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1, characterized in that... The metal contact area is provided with a tunneling oxide layer (3) and a phosphorus-doped polycrystalline silicon layer (5) from the back side of the substrate outward.

3. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1, characterized in that... In the cell, there are one or more heavily doped regions (7) in the recessed structure, and the height difference between the bottom surface of the recessed structure and the back surface of the substrate is 2~5μm.

4. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1 or 3, characterized in that... The heavily doped region (7) is formed by the diffusion of phosphorus atoms into the silicon substrate, and its doping concentration is 0.1~1.0E+20cm. -3 .

5. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1 or 3, characterized in that... The thickness of the heavily doped region (7) is 1~4 μm.

6. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 2, characterized in that... The material of the tunneling oxide layer (3) is silicon dioxide, and the thickness of the tunneling oxide layer (3) is 0.5~2.5 nm.

7. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 6, characterized in that... The thickness of the tunneling oxide layer (3) is 1.0~1.5 nm.

8. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1, characterized in that... The phosphorus doping concentration of the phosphorus atoms in the phosphorus-doped polycrystalline silicon layer (5) is 2.0~8.0E+20 cm-3, the sheet resistance is 40~150 Ω / sq, and the thickness of the phosphorus-doped polycrystalline silicon layer (5) is 60~200 nm.

9. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1, characterized in that... The width W1 of the tunneling oxide layer (3) and the phosphorus-doped polysilicon layer (5) is 45 to 95 µm, and the width W2 of the non-metallic contact area between two adjacent phosphorus-doped polysilicon layers (5) is 830 to 870 µm.

10. The selective polycrystalline silicon passivated contact battery with anti-breakage grid pattern according to claim 1, characterized in that... A boron-doped emitter (2) and a front surface passivation antireflection film (10) are sequentially provided on the front side of the N-type silicon wafer substrate (1), and a back surface passivation antireflection film (9) is provided on the surface of the phosphorus-doped polycrystalline silicon layer (5) and the recessed structure on the back side of the N-type silicon wafer substrate (1).

11. A method for preparing a selective polycrystalline silicon passivated contact cell with an anti-breakage grid pattern as described in claim 1, characterized in that... Includes the following steps: S1. Tunnel oxide layer and intrinsic polysilicon layer are grown on the back surface: Take an N-type silicon wafer substrate (1) with a boron-doped emitter on the front and a smooth back, and grow a tunnel oxide layer and an intrinsic polysilicon layer on the entire back surface. S2, Phosphorus diffusion: Phosphorus diffusion is performed on the back side of the N-type silicon wafer to form a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer; S3, Laser doping: Laser is used to pattern and heavily dope the back surface of the silicon wafer, removing the local tunneling oxide layer, phosphorus-doped polysilicon layer and phosphorus-silicon glass layer, and diffusing phosphorus atoms in the phosphorus-silicon glass layer and phosphorus-doped polysilicon layer in the corresponding area into the silicon wafer substrate by 3~6 μm to form a heavily doped region. S4. Laser film opening: The phosphosilicate glass layer is opened by laser to remove the phosphosilicate glass layer around the heavily doped region, leaving a non-metallic contact area, while the phosphosilicate glass layer is still retained in the metallic contact area. S5. Wet chemical etching: Wet chemical etching is performed on the non-metallic contact area on the back surface of the silicon wafer to remove the tunneling oxide layer and phosphorus-doped polysilicon layer in the area, and 2~5μm is etched into the silicon wafer substrate to form the recessed structure and heavily doped region (7). Then remove the phosphosilicate glass layer in the metal contact area.

12. A method for preparing a selective polycrystalline silicon passivated contact cell with an anti-breakage grid pattern as described in claim 1, characterized in that... Includes the following steps: S11. Tunnel oxide layer and intrinsic polycrystalline silicon layer are grown on the back surface: Take an N-type silicon wafer substrate (1) with a boron-doped emitter on the front and a smooth back, and grow a tunnel oxide layer and an in-situ phosphorus-doped polycrystalline silicon layer on the entire back surface. S22, Annealing and thermal crystallization treatment: The N-type silicon wafer is subjected to high-temperature annealing treatment, and after annealing, a doped polycrystalline silicon layer and a phosphosilicate glass layer are formed. S3, Laser doping: Laser is used to pattern and heavily dope the back surface of the silicon wafer, removing the local tunneling oxide layer, phosphorus-doped polysilicon layer and phosphorus-silicon glass layer, and diffusing phosphorus atoms in the phosphorus-silicon glass layer and phosphorus-doped polysilicon layer in the corresponding area into the silicon wafer substrate by 3~6 μm to form a heavily doped region. S4. Laser film opening: The phosphosilicate glass layer is opened by laser to remove the phosphosilicate glass layer around the heavily doped region, leaving a non-metallic contact area, while the phosphosilicate glass layer is still retained in the metallic contact area. S5. Wet chemical etching: Wet chemical etching is performed on the non-metallic contact area on the back surface of the silicon wafer to remove the tunneling oxide layer and phosphorus-doped polysilicon layer in the area, and 2~5μm is etched into the silicon wafer substrate to form the recessed structure and heavily doped region (7). Then remove the phosphosilicate glass layer in the metal contact area.

13. The preparation method according to claim 11 or 12, characterized in that... Includes the following steps: S6. Deposit passivation antireflection film: Deposit a surface passivation antireflection film on the back side of the silicon wafer and deposit a front surface passivation antireflection film on the front side of the silicon wafer; S7. Metal Electrode Printing and Sintering: Metallization patterns are printed on the front and back sides of the silicon wafer and then sintered to prepare metal electrodes.

14. The preparation method according to claim 11, characterized in that, In step S1, an ultrathin tunneling oxide layer and an intrinsic polycrystalline silicon layer are grown on the entire back surface of a silicon wafer in a low-pressure chemical vapor deposition apparatus. The material of the tunneling oxide layer is silicon dioxide, and the thickness of the tunneling oxide layer is 0.5~2.5 nm. The deposition temperature of the intrinsic polycrystalline silicon is 610~620 °C, and the thickness of the intrinsic polycrystalline silicon is 60~200 nm. In step S2, phosphorus diffusion is performed on the back side of the N-type silicon wafer. The phosphorus source for diffusion is phosphorus oxychloride, the peak diffusion temperature is 800~900 °C, and the phosphorus diffusion time is 25~30 min. After the phosphorus diffusion is completed, a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass layer are formed. The phosphorus doping concentration of phosphorus atoms in the phosphorus-doped polycrystalline silicon layer is 2.0~8.0E+20 cm-3, the sheet resistance is 40~150Ω / sq, and the thickness of the phosphorus-silicon glass layer is 25~30 nm. In step S3, a laser is used to pattern and heavily dope the back surface of the silicon wafer, pushing phosphorus atoms from the localized phosphorus-silicon glass and phosphorus-doped polycrystalline silicon layer into the silicon substrate. The phosphorus atoms diffuse 3-6 μm into the silicon substrate, forming a heavily doped region. The phosphorus doping concentration in the heavily doped region is 0.1-1.0E+20 cm⁻¹. -3 The area of ​​the heavily doped region accounts for 1% to 2% of the back surface area of ​​the silicon wafer. The laser spot is a square spot with a length and width of 100 to 500 µm. The wavelength of the laser is 600 to 1100 nm and is at least one of nanosecond lasers. In the unit cell, the number of heavily doped regions is ≥1. In step S4, the laser spot is a square spot with a length and width of 100~500 µm, the laser wavelength is 350~540 nm, and it is at least one of picosecond lasers; In step S5, a mixed solution of wet additive + KOH & NaOH + water is used to etch the silicon wafer. The reaction temperature of the solution is 60±10℃, the reaction time is 5~8 min, and the etching depth of the silicon wafer is 2~5μm. After wet chemical etching, the area of ​​the unremoved phosphorus-doped polysilicon layer accounts for 5% to 10% of the back surface area of ​​the battery, the width W1 of the unremoved phosphorus-doped polysilicon layer is 45 to 95 µm, the total area of ​​the etched area accounts for 90% to 95% of the back surface area of ​​the silicon wafer, and the width W2 between two adjacent phosphorus-doped polysilicon layers (5) is 830 to 870 µm.

15. The preparation method according to claim 12, characterized in that, In step S11, the material of the tunneling oxide layer is silicon dioxide, and the thickness of the tunneling oxide layer is 0.5~2.5 nm; the deposition temperature of the in-situ phosphorus-doped polycrystalline silicon layer is 500~650ºC, and its thickness is 80~200 nm. In step S12, the annealing temperature is 800~950 ºC and the annealing time is 30~90 min; the doping concentration of phosphorus atoms in the doped polycrystalline silicon layer is 2.0~8.0E+20 cm-3 and the sheet resistance is 40~150 Ω / sq; the thickness of the phosphorus silicon glass layer is 25~30 nm.

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