Apparatus and method for filling gap features of a substrate and related semiconductor devices

Abstract

The present disclosure relates to semiconductor processing, and in particular to apparatuses and methods for partially fabricating semiconductor devices using cyclic deposition-etch processes. The apparatus includes at least one reactor having a reaction chamber, a metal precursor source for delivering a metal precursor vapor, and an etchant source for delivering an etchant vapor. A vapor distribution and removal system supplies and subsequently removes these vapors to the reaction chamber. A sequence controller connected to the distribution and removal system includes a memory having a program that controls the flow of vapor from the metal precursor source during one or more deposition cycles.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor processing, and more particularly to apparatus and methods for partially fabricating semiconductor devices through cyclic deposition-etching processes. This disclosure further relates to related semiconductor devices, such as memory devices and their substructures. Background Technology

[0002] Semiconductor manufacturing processes used to create devices such as memory elements, transistors, integrated circuits, and their substructures typically involve multi-step processes that precisely manipulate materials at the atomic and nanoscale. These steps typically include deposition, etching, thermal annealing, photolithography, and doping—each of which usually requires specialized tools and precise control to achieve the desired device characteristics.

[0003] However, the increasing complexity of modern semiconductor devices, coupled with shrinking feature sizes and the introduction of advanced materials, has made it challenging to efficiently utilize a wide range of different tools. The need for tight integration between these processes, as well as the demand for improved uniformity, scalability, and yield, further amplifies these challenges.

[0004] In view of the above, there remains a need to simplify workflows, enhance compatibility between different manufacturing steps, and improve the overall efficiency of semiconductor manufacturing. Therefore, the purpose of this disclosure is to provide simplified and reliable apparatus and methods for controlled semiconductor processing. Summary of the Invention

[0005] This paper presents the discovery that, by using the apparatus and methods described herein, some or all of the aforementioned challenges can be addressed individually or in any combination, and the objectives can be achieved.

[0006] This synopsis provides a simplified introduction to the selection of concepts. These concepts are further described in detail in the following specific embodiments of exemplary models of this disclosure. This synopsis is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] Generally, the techniques disclosed herein relate to the field of semiconductor processing, and more specifically to apparatus and methods for simplifying deposition and etching processes to precisely shape and / or define one or more features (such as trenches, vias, or isolation components) of a semiconductor device.

[0008] In particular, the apparatus described herein enables the integration of deposition and etching processes within a single reactor (i.e., the same tooling). This configuration offers several key advantages over prior art reactors, reducing and advantageously eliminating the need for transferring the substrate between separate tools required by conventional apparatuses and methods.

[0009] Another advantage of combining metal film deposition and subsequent etching within a single reactor is improved semiconductor processing rates and reduced reliance on multiple tools. This integration increases throughput, reduces labor costs per substrate, and improves overall operational efficiency.

[0010] In addition, the described apparatus and methods can optimize existing workflows, thereby providing cost-effective and easy-to-implement solutions.

[0011] According to one aspect of this disclosure, an apparatus is provided, comprising:

[0012] - At least one reactor, comprising at least one reaction chamber configured and arranged for processing at least one semiconductor substrate; wherein the semiconductor substrate includes one or more gap features;

[0013] - A metal precursor source, which is configured and arranged to provide a vapor of at least one metal precursor, the at least one metal precursor comprising at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, cobalt, nickel and mixtures thereof;

[0014] - An etchant source, which is constructed and arranged to provide vapor of at least one etchant;

[0015] - A vapor distribution and removal system configured to supply vapors from a metal precursor source and an etchant source to at least one reaction chamber within a reactor, and to remove vapors from the reaction chamber; and

[0016] - A sequence controller, operably connected to a distribution and removal system, includes a memory containing a program configured to control the flow from a metal precursor source to a reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles; thereby, as a result of the deposition cycle, a metal-containing film is deposited to at least partially fill one or more gap features of a semiconductor substrate; and,

[0017] The program is also configured to control the flow from the etchant source to the reaction chamber by activating a vapor distribution and removal system during one or more etching cycles; thereby, as a result of the etching cycle, the metal-containing film undergoes subtractive etching.

[0018] In a particular embodiment, the apparatus further includes a reactant source configured and arranged to provide vapor of reactants; wherein a vapor distribution and removal system is further configured to provide vapor of the reactant source to the reactor; and wherein a program set on a memory is configured to control the flow of reactants from the reactant source to at least one reactor chamber during one or more deposition cycles.

[0019] In a particular embodiment, the reactants are selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

[0020] In a particular embodiment, the program set on the memory is also configured to control the flow from the metal precursor source to at least one reactor chamber by activating a vapor distribution and removal system during one or more deposition cycles included in a cyclic deposition process that is part of an atomic layer deposition (ALD) process.

[0021] In a particular embodiment, at least one semiconductor substrate further includes a material selected from the group consisting of silicon, silicon oxide, silicon germanium, carbon-doped silicon oxide, silicon nitride, silicon carbide, germanium, gallium arsenide, gallium nitride, glass, sapphire, and combinations thereof.

[0022] In certain embodiments, the metal precursor is a metal halide, a metal chalcogenide halide, or a metal-organic precursor.

[0023] In certain embodiments, the etchant comprises one or more halogen-containing etch compounds.

[0024] In a particular embodiment, the etchant comprises one or more halogen-containing etching compounds selected from the group consisting of: F2, Cl2, Br2, quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, HF, HCl, HBr, tetrafluoroboric acid, tetrachloroboric acid, tetrabromoboric acid, hexafluorosilicic acid, hexachlorosilicic acid, hexabromosilicic acid, tetrabutylammonium tetrafluoroborate, H2ZrF6, H2TiF6, HPF6, MoCl5, WCl5, ammonium hexafluorosilicate, ammonium hexachlorosilicate, ammonium hexabromosilicate, ammonium hexafluorotitanate, ammonium hexachlorotitanate, ammonium hexabromotitanate, thionyl chloride, and mixtures thereof.

[0025] In a particular embodiment, at least one reactor further includes a heating device configured to provide a temperature of 200°C to 800°C within the reactor chamber.

[0026] In a particular embodiment, at least one reactor further includes a pressure regulating mechanism configured to provide a pressure of 0.2 Torr to 200 Torr within the reactor chamber.

[0027] In a particular embodiment, the apparatus is designed such that one or more of at least one reactor is a vertical furnace, the vertical furnace including at least one reaction chamber configured to simultaneously receive and process multiple semiconductor substrates.

[0028] In a particular embodiment, the reactor includes a reactor shell surrounding at least one reaction chamber.

[0029] In a particular embodiment, the reactor includes a reactor shell surrounding at least a first reaction chamber and a second reaction chamber, as well as a disposal chamber configured for transferring a semiconductor substrate between the first and second reaction chambers; wherein a deposition cycle is performed in the first reaction chamber, and an etching cycle is performed in the second reaction chamber; and wherein a vapor distribution and removal system is further configured to selectively direct the flow of metal precursor vapor to the first reaction chamber and the flow of etchant vapor to the second reaction chamber.

[0030] In a particular embodiment, the reactor includes a reactor shell surrounding a single reaction chamber; wherein deposition and etching cycles are carried out in the (single) reaction chamber; and wherein a vapor distribution and removal system is further configured to selectively direct the flow of metal precursor vapor and etchant vapor to the (single) reaction chamber and remove it.

[0031] Another aspect of this disclosure provides a method for at least partially manufacturing a semiconductor substrate, the method comprising the following steps:

[0032] a) Providing at least one semiconductor substrate, including one or more gap features, into a reactor including at least one reactor chamber;

[0033] b) Performing one or more deposition cycles within a reactor chamber, each cycle comprising a metal precursor pulse, wherein at least a portion of the semiconductor substrate is contacted with the at least one metal precursor by introducing at least one metal precursor into the reactor; wherein the at least one metal precursor comprises at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, and mixtures thereof; thereby, as a result of the cycle, depositing a metal-containing film to at least partially fill one or more gap features of the semiconductor substrate; and;

[0034] c) Perform one or more etching cycles within the reactor chamber, each cycle comprising an etchant pulse, wherein at least a portion of the metal-containing film is brought into contact with at least one etchant by introducing at least one etchant into the reactor; thereby, as a result of the cycle, the metal-containing film undergoes subtractive etching.

[0035] In a particular embodiment, at least one deposition cycle further includes a reactant pulse, wherein at least a portion of the semiconductor substrate is contacted with the at least one reactant by introducing the at least one reactant into the reactor; wherein the at least one reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

[0036] Another aspect of this disclosure provides a semiconductor device including one or more gap features filled with a metal-containing film, the metal-containing film being prepared using an apparatus according to one aspect of this disclosure or a (preferred) embodiment thereof, or by a method according to one aspect of this disclosure or a (preferred) embodiment thereof.

[0037] In a particular embodiment, the reactor includes a reactor shell surrounding at least one reaction chamber; wherein the deposition cycle and etching cycle are performed without removing the semiconductor substrate from the reactor, particularly the reactor shell.

[0038] In a particular embodiment, the reactor includes a reactor shell surrounding at least a first reaction chamber and a second reaction chamber, and a disposal chamber configured for transferring a semiconductor substrate between the first reaction chamber and the second reaction chamber; and wherein a deposition cycle is performed in the first reaction chamber and an etching cycle is performed in the second reaction chamber without removing the semiconductor substrate from the reactor.

[0039] In a particular embodiment, the reactor includes a reactor shell surrounding a single reaction chamber; and wherein deposition and etching cycles are performed within the (single) reaction chamber without removing the semiconductor substrate from the reactor; preferably, the semiconductor substrate is not removed from the (single) reaction chamber.

[0040] In a particular embodiment, the semiconductor device is a memory device that includes at least one of a 3D-NAND device, a DRAM device, a 3D integrated device, or an integrated logic device, or a partially manufactured memory device structure that includes at least one of a 3D-NAND device structure, a DRAM device structure, a 3D integrated device structure, or a partially manufactured integrated logic device structure. Attached Figure Description

[0041] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to aid in understanding the embodiments shown in this disclosure.

[0042] Figure 1 An apparatus 100 according to an embodiment of the present disclosure is schematically shown, which includes a first reaction chamber 112 and a second reaction chamber 113 as described herein.

[0043] Figure 2 An apparatus 200 according to another embodiment of the present disclosure is schematically shown, which includes a reactor 201, the reactor 201 including a single reaction chamber 212 as described herein.

[0044] Figure 3A method 300 for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device according to embodiments of the present disclosure is described, wherein the reactor includes a single reaction chamber.

[0045] Figure 4 A method 400 for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device according to another embodiment of the present disclosure is described, wherein the reactor includes a single reaction chamber as described herein.

[0046] Figure 5 A method 500 for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device according to another embodiment of the present disclosure is described, wherein the reactor includes a single reaction chamber, wherein the reactor includes a first reaction chamber and a second reaction chamber as described herein.

[0047] Figure 6 A method 600 for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device according to another embodiment of the present disclosure is described, wherein the reactor includes a single reaction chamber, wherein the reactor includes a first reaction chamber and a second reaction chamber as described herein.

[0048] Figure 7 A method 700 for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device according to another embodiment of the present disclosure is described, wherein the reactor includes a single reaction chamber, wherein the reactor includes a first reaction chamber, a second reaction chamber and a third reaction chamber as described herein.

[0049] Figure 8 A vertical furnace system 900 according to an embodiment of the present disclosure is schematically shown, which includes at least one reaction chamber as described herein.

[0050] Figure 9 A cross-sectional view of a semiconductor memory device 800 according to an embodiment of the present disclosure is schematically shown, which is manufactured at least in part using the apparatus and / or methods as described herein. Detailed Implementation

[0051] Although certain embodiments and examples are disclosed below, those skilled in the art will understand that this disclosure extends beyond the specific embodiments and / or uses disclosed herein, as well as their obvious modifications and equivalents. Therefore, it is intended that the scope of this disclosure should not be limited to the specific disclosed embodiments described below.

[0052] In the following detailed description, the technology upon which this disclosure is based will be described through various aspects of this disclosure. It will be readily understood that the aspects of this disclosure, as generally described herein and illustrated in the accompanying drawings, can be arranged, substituted, combined, and designed in a variety of different configurations, all of which are clearly contemplated and form part of this disclosure. This description is intended to assist the reader in a more readily understanding of the technical concepts, but is not intended to limit the scope of this disclosure, which is limited only by the claims. Therefore, the following description is to be considered illustrative in nature, not restrictive.

[0053] As used herein, the singular forms “a,” “an,” and “the” include both singular and plural indicators unless the context clearly specifies otherwise. For example, “a step” means one step or more steps.

[0054] As used herein, the terms “comprising,” “comprises,” and “comprisedof” are synonymous with “including,” “includes,” “containing,” and “contains,” and are inclusive or open-ended, and do not exclude additional, unlisted members, elements, or method steps. The term also includes “consisting of” and “consisting essentially of,” which have their generally accepted meanings in patent terminology.

[0055] Although the terms "one or more" or "at least one," such as one or more members or at least one member of a group of members, are self-evident, by further example, the term specifically includes a reference to any one of the members, or a reference to any two or more of the members, for example, any ≥3, ≥4, ≥5, ≥6, or ≥7 of the members, and up to all of the members. In another example, "one or more" or "at least one" may refer to 1, 2, 3, 4, 5, 6, 7, or more.

[0056] Unless otherwise stated, the terms first, second, third, etc., in the specification and claims are used to distinguish similar elements and are not necessarily used to describe an order or chronological order. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments of this disclosure described herein can operate in orders other than those described or shown herein.

[0057] As used herein, when used in a list of two or more items, the term "and / or" means that any one of the listed items can be implemented individually, or any combination of two or more of the listed items can be implemented. For example, if the list is described as including groups A, B, and / or C, then the list can include A alone, B alone, C alone, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C.

[0058] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment," "in an embodiment," or "in a particular embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure. Moreover, while some embodiments described herein include some features included in other embodiments but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this disclosure and form different embodiments, as will be understood by those skilled in the art.

[0059] Descriptions of numerical ranges by endpoints include all integers and, where appropriate, fractions contained within the range (e.g., when referring to, for example, the quantity of elements, 1 to 5 may include 1, 2, 3, 4, and when referring to, for example, a measure, may also include 1.5, 2, 2.75, and 3.80). Descriptions of endpoints also include the endpoint values ​​themselves (e.g., 1.0 to 5.0 includes both 1.0 and 5.0). Any numerical range described herein is intended to include all subranges contained therein. This applies to numerical ranges, whether they are introduced by expressing "from…to…" or "between…and…" or other expressions.

[0060] As used herein, the terms “about” or “approximately” are used to provide flexibility for numerical or range endpoints by specifying that a given value may be “slightly above” or “slightly below” the value or endpoint, depending on the specific context. Therefore, when referring to measurable values ​​such as parameters, quantities, durations, etc., the terms “about” or “approximately” as used herein are intended to include variations in the specified value or endpoint, such as + / - 10% or less, preferably + / - 5% or less, more preferably + / - 1% or less, more preferably + / - 0.1% or less, provided that such variations are appropriate to be performed within the scope of the disclosed information.

[0061] Unless otherwise stated, the use of the terms “about” or “approximately” in relation to a particular number or range of numbers should also be understood to support such numerical terms or ranges for which the term “about” is not used. For example, the statement “about 30” should be interpreted as supporting not only values ​​slightly above and slightly below 30, but also the actual value of 30.

[0062] As used herein, the term "substantially" refers to the complete or near-complete extent or degree of an action, characteristic, property, state, structure, item, or result. For example, an object "substantially" enclosed would mean that the object is completely or almost completely enclosed. In some cases, the exact permissible degree of deviation from absolute completeness may depend on the specific context. However, in general, near-completeness will have the same overall result as if absolute and completeness were achieved. When used in a negative sense, the use of "substantially" also applies to referring to a complete or near-complete lack of an action, characteristic, property, state, structure, item, or result.

[0063] The terms “wt.%”, “vol%”, or “mol%” refer to the weight percentage, volume percentage, or mole percentage of a component based on the total weight, volume, or number of moles of the material comprising the component, respectively.

[0064] Reference may be made in this specification to apparatus, devices, structures, systems, or methods that provide "improved" performance (e.g., increased or decreased results, depending on the context). It should be understood that, unless otherwise stated, such "improvement" is a measure of benefit obtained based on comparison with prior art apparatus, devices, structures, systems, or methods. Furthermore, it should be understood that the degree of improved performance may vary among the disclosed embodiments, and the equivalence or consistency of the amount, degree, or implementation of improved performance is not considered universally applicable.

[0065] As used herein, relative terms such as “left,” “right,” “front,” “back,” “top,” “bottom,” “above,” “below,” etc., are used for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that these terms are interchangeable where appropriate, and that the embodiments described herein can operate in orientations other than those shown or described herein, unless the context explicitly specifies otherwise.

[0066] Objects described in this article as “adjacent” to each other reflect the functional relationship between the objects being described. That is, the term indicates that the objects being described must be adjacent in a manner that performs a specified function, which may be direct (i.e., physical) or indirect (i.e., close or near) contact, as appropriate in the context in which the phrase is used.

[0067] The objects described in this document as “connected” or “linked” reflect the functional relationship between the objects being described. That is, the term indicates that the objects being described must be connected in a way that performs a specified function, which may be a direct or indirect connection, either electrical or non-electrical (i.e., physical), as appropriate in the context in which the term is used.

[0068] Additionally, embodiments of this disclosure may include hardware, software, and electronic components or modules, which, for the purposes of discussion, may be shown and described as if most components were implemented solely in hardware. However, those skilled in the art, based on a reading of this particular embodiment, will recognize that, in at least one embodiment, the electronic aspects of this disclosure may be implemented in software (e.g., instructions stored on a non-transitory computer-readable medium) executable by one or more processing units (such as microprocessors and / or application-specific integrated circuits). Thus, it should be noted that the techniques of this disclosure may be implemented using multiple hardware and software-based devices and multiple different structural components. For example, the “server” and “computing device” described in the specification may include one or more processing units, one or more computer-readable medium modules, one or more input / output interfaces, and various connections of connectivity components.

[0069] As used herein, the term "semiconductor substrate" can refer to any one or more underlying materials that can be used to form devices, circuits, or films, or on which devices, circuits, or films can be formed. A "semiconductor substrate" can be continuous or discontinuous; rigid or flexible; solid or porous; and combinations thereof. A semiconductor substrate can include bulk materials (e.g., silicon (e.g., single-crystal silicon)), other group IV materials (e.g., germanium), or other semiconductor materials (e.g., group II-VI or group III-V semiconductor materials), and can include one or more layers overlying or underlying the bulk material. Furthermore, the substrate can include various features formed within or on at least a portion of the substrate layers, such as recesses, bumps, etc. For example, the substrate can include a bulk semiconductor material and an insulating or (high-k) dielectric material layer overlying at least a portion of the bulk semiconductor material.

[0070] Semiconductor substrates may include materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, sapphire, doped or undoped polycrystalline silicon, doped or undoped silicon, patterned or unpatterned silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, germanium, gallium arsenide, gallium nitride, glass, or combinations thereof.

[0071] As used herein, the term "semiconductor device structure" can refer to any portion of a processed or partially processed semiconductor structure, which includes or defines at least a portion of the active or passive components of a semiconductor device to be formed on or in a semiconductor substrate. For example, a semiconductor device structure may include active and passive components of an integrated circuit, such as, for example, transistors, memory elements, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

[0072] In this disclosure, "gas" can include materials that are gaseous at normal temperature and pressure (NTP), vaporized solids and / or vaporized liquids, and can consist of a single gas or a mixture of gases, depending on the context. Gases other than process gases or purge gases, i.e., gases not introduced through (gas) distribution and removal systems, other gas distribution devices, etc., can be used, for example, to seal reaction spaces, and can include sealing gases, such as rare gases.

[0073] As used herein, the term "membrane" or "layer" can encompass any continuous or discontinuous structure and material, including any material deposited using the apparatus and methods disclosed herein. For example, membranes and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partially or entirely molecular layers or partially or entirely atomic layers or atomic and / or molecular clusters, or layers composed of separate atoms and / or molecules. Membranes or layers can include materials or layers with pinholes, which can be continuous or discontinuous.

[0074] The embodiments described herein will be further described below with reference to apparatus for manufacturing semiconductor devices or substructures thereof. However, it should be understood that other systems that benefit from this apparatus configured to perform the cyclic deposition-etching process described herein may also be suitable for benefiting from the embodiments described herein. The apparatus described herein is illustrative and should not be construed or translated as limiting the scope of the embodiments described herein.

[0075] This disclosure provides an apparatus comprising:

[0076] - At least one reactor, comprising at least one reaction chamber configured and arranged for processing at least one semiconductor substrate; wherein the semiconductor substrate includes one or more gap features;

[0077] - A metal precursor source, which is configured and arranged to provide a vapor of at least one metal precursor, the metal precursor comprising at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, cobalt, nickel and mixtures thereof;

[0078] - An etchant source, which is constructed and arranged to provide vapor of at least one etchant;

[0079] - A vapor distribution and removal system configured to supply vapors from a metal precursor source and an etchant source to at least one reaction chamber within a reactor, and to remove vapors from the reaction chamber; and

[0080] - A sequence controller operably connected to the distribution and removal system includes a memory having a program configured to control the flow from the metal precursor source to the reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles; thereby, as a result of the deposition cycle, a metal-containing film is deposited to at least partially fill one or more gap features of the semiconductor substrate; and,

[0081] The program is also configured to control the flow from the etchant source to the reaction chamber by activating a vapor distribution and removal system during one or more etching cycles; thereby, as a result of the etching cycle, the metal-containing film undergoes subtractive etching.

[0082] In other words, this disclosure generally relates to a processing apparatus configured for processing a semiconductor substrate, and more specifically to a processing apparatus designed to simplify a process including deposition and etching steps. For example, this apparatus may be particularly suitable for constructing or partially constructing memory devices.

[0083] Advantageously, it has been found that the sequence controller can be configured to precisely control the introduction and removal of reactive gases during the deposition-etching process, resulting in well-controlled chemical reactions that provide uniform and reproducible films and other characteristics. Furthermore, the sequence controller can adjust the flow rate and introduction time to further optimize reaction kinetics.

[0084] Another advantage of this device is that the vapor distribution and removal system is configured to supply vapors from the metal precursor source and the etchant source to one or more reaction chambers of the same reactor.

[0085] In a particular embodiment, the apparatus may be configured such that the reactor includes a reactor shell surrounding at least a first reaction chamber, at least a second reaction chamber, and at least a processing chamber, the processing chamber being configured to transfer a semiconductor substrate between the first and second reaction chambers without removing it from the reactor, particularly the reactor shell; wherein a deposition cycle is performed in the first reaction chamber, and an etching cycle is performed in the second reaction chamber; and wherein a vapor distribution and removal system is further configured to selectively direct a metal precursor vapor stream to at least the first reaction chamber and an etchant vapor stream to at least the second reaction chamber.

[0086] Figure 1An apparatus 100 according to an embodiment of the present disclosure is schematically illustrated. The apparatus 100 includes a reactor 101, which includes a first reaction chamber 112 and a second reaction chamber 113. Additionally, the apparatus 100 includes a metal precursor source 102, an etchant source 103, optionally one or more reactant sources 104, a purge gas source 105, an exhaust system 106, and a sequence controller 107. The apparatus is configured to perform the methods disclosed herein and / or manufacture semiconductor devices, such as memory devices or substructures thereof.

[0087] The apparatus 100 may further include a storage device for holding semiconductor substrates. For example, the storage device may be a cassette storage turntable designed to store wafer cassettes, each cassette accommodating multiple semiconductor substrates. The storage device may be operatively connected to a substrate handler, such as a robotic arm, configured to transfer individual semiconductor substrates or cassettes between the storage device and reactor 101.

[0088] Reactor 101 may be enclosed within a suitable reactor shell that physically contains and isolates the first reaction chamber 112 and the second reaction chamber 113. For the avoidance of ambiguity, the reactor shell specifically refers to the structural enclosure forming part of the apparatus 100 described herein and should not be construed as including a cleanroom or other external environment in which the apparatus may be located. This shell is configured to form a closed system or tooling assembly, which advantageously allows deposition and etching steps to be performed within the same apparatus.

[0089] In a particular embodiment, the reactor housing is a sealed enclosure specifically designed to house a first reaction chamber and a second reaction chamber and isolate them from the external environment. The reactor housing may be provided with dedicated inlet ports or windows for maintenance and substrate transfer, designed to prevent contamination and leakage during operation. The reactor housing may be provided with ports for the controlled delivery and removal of gases, such as gases supplied by a metal precursor source, etchant source, and any optional reactant source, as well as ports for the exhaust system. The housing may be further equipped with integrated seals and barriers to prevent contamination from the external environment, thereby ensuring that the internal processing conditions remain unaffected by external environmental conditions.

[0090] Unlike a cleanroom that is typically surrounded by an environment to house the equipment, the reactor shell is structurally and functionally integrated with device 100. It does not rely on external environmental controls, such as those provided by a cleanroom air filtration system, to maintain the purity of the reaction environment. Instead, the reactor shell incorporates its own environmental control features, such as temperature regulation, pressure control, and airflow management, to accommodate the specific requirements of the deposition and etching processes.

[0091] Therefore, reactor 101 is provided with a first reaction chamber 112 and a second reaction chamber 113 for processing the semiconductor substrate without removing the semiconductor substrate from the reactor (especially the reactor shell). Utilizing a single reactor significantly reduces the processing time of the deposition-etch-deposition process by eliminating the need to transfer the substrate between different reactors or tools, which introduces significant delays and is operationally inefficient.

[0092] Reactor 101 may also include components such as insulating materials, heating elements, temperature sensors, tubes, syringes, flanges, frames and / or bases.

[0093] The apparatus 100 may include any number of suitable gas sources 102-105 connected via lines 108-111 to the first reaction chamber 112 and / or the second reaction chamber 113 within the reactor 101. The lines may include flow controllers, valves, heaters, etc. The exhaust 106 may include one or more vacuum pumps. Lines 108-111 and the exhaust 106 may be used as a distribution and removal system configured to supply vapors of (one or more) metal precursors, (one or more) etchants, and optionally (one or more) reactants to the first reaction chamber 108 and / or the second reaction chamber 109 within the reactor 101, and to remove vapors from the first reaction chamber 112 and / or the second reaction chamber 113 within the reactor 101.

[0094] In a non-limiting exemplary configuration, a metal precursor source 102, one or more optional reactant sources 104, and a purge gas source 105 may be connected to a first reaction chamber 112 configured to perform a deposition cycle. Additionally, an etchant source 103 and a purge gas source 105 may be connected to a second reaction chamber 113 configured to perform an etching cycle.

[0095] Metal precursor source 102 may include a container and at least one metal precursor as described herein—either alone or mixed with one or more carrier (e.g., inert) gases.

[0096] Etching source 103 may include a container and at least one etchant as described herein—either alone or mixed with one or more carrier gases (e.g., inert gases).

[0097] Optional reactant sources 104 may include one or more containers and one or more reactants as described herein—either alone or mixed with one or more carrier (e.g., inert) gases. For example, apparatus 100 may include: a first reactant source comprising a container and an oxide reactant; and a second reactant source comprising a container and a nitrogen reactant.

[0098] The purge gas source 105 may include one or more inert gases, such as N2 or rare gases (e.g., argon), as described herein.

[0099] The sequence controller 107 may include electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in the device 100. Such circuitry and components operate to introduce precursors, reactants, and purge gases from respective sources 102-105.

[0100] The sequence controller 107 may include a memory containing an executable program that can automate certain tasks, such as the flow rate and timing of gas pulse sequences, the temperature of the semiconductor substrate and / or reactor 101, the pressure within reactor 101, and various other operations that provide appropriate operation of the apparatus 100. The sequence controller 107 may also include control software to electrically or pneumatically control valves to control the inflow and outflow of precursors, etchants, reactants (e.g., oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, or sulfur reactants), and purge gases into and out of the first reaction chamber 112 and / or the second reaction chamber 113 within reactor 101. The sequence controller 107 may include modules, such as one or more software and / or hardware components, such as FPGAs or ASICs, to perform certain tasks. These modules may advantageously be configured to reside on an addressable storage medium of the control system and to perform one or more processes and activate the dispensing and removal systems during the deposition-etching process.

[0101] It should be understood that other configurations of the apparatus 100 are possible, including different numbers and types of metal precursors, etchants, reactants, and purge gas sources. Furthermore, it should be understood that the objective of selectively supplying vapor to at least one reaction chamber within the reactor 101 can be achieved using numerous arrangements of valves, conduits, metal precursor sources, etchant sources, reactant sources, and purge gas sources. Additionally, for the sake of simplicity, many components have been omitted in the schematic diagram of the apparatus, and these components may include, for example, various valves, manifolds, purgers, heaters, containers, vents, and / or bypasses.

[0102] During operation of apparatus 100, a semiconductor substrate, such as a wafer (not shown), may be transferred from a storage device to a first reaction chamber 112 and / or a second reaction chamber 113 within reactor 101 via a disposal device. Once the semiconductor substrate(s) have been transferred to at least one reaction chamber, one or more vapors, such as metal precursors, etchants, reactants, and / or purge gases, from various sources 102-105 may be introduced into the first reaction chamber 112 and / or the second reaction chamber 113 within reactor 101 via a dispensing and removal system (106 and 108-111) operably connected to sequence controller 107.

[0103] Advantageously, this paper has found that, such as Figure 1 The apparatus, schematically illustrated, allows for the deposition of a metal-containing film and subsequent etching of that film within the same reactor without the need for additional dedicated equipment. This results in a cost-effective technique that can reduce overall processing time.

[0104] Alternatively, and in other embodiments, the apparatus may be configured such that the reactor includes a reactor shell surrounding a single reaction chamber; wherein deposition and etching cycles are carried out in the reaction chamber; and wherein a vapor distribution and removal system is further configured to selectively direct and remove metal precursor vapor and etchant vapor streams into the reaction chamber.

[0105] In addition, technicians will realize that Figure 1 The configuration of the apparatus schematically illustrated herein can be readily adapted to include a reactor shell housing more than two reaction chambers as described herein, such as three, four, five, or more chambers. This extension remains within the scope of this disclosure as long as the reactor includes a transfer system, such as a disposal chamber, configured to transfer a semiconductor substrate between two or more reaction chambers without removing the semiconductor substrate from the reactor (particularly the reactor shell).

[0106] Figure 2 An apparatus 200 according to another embodiment of the present disclosure is schematically illustrated. The apparatus includes a reactor 201 comprising a first reactor 201, a metal precursor source 202, an etchant source 203, one or more optional reactant sources 204, a purge gas source 205, an exhaust gas 206, and a sequence controller 207. The apparatus 200 can be used to perform methods as disclosed herein and / or to form semiconductor devices (e.g., memory devices or substructures thereof).

[0107] Reactor 201 may be provided with a suitable (reactor) shell surrounding a single reaction chamber. This configuration forms a closed system or tool assembly.

[0108] Therefore, reactor 201 is provided with a single reaction chamber 212 for processing the semiconductor substrate without removing the semiconductor substrate from the reactor (specifically, the single reaction chamber). Utilizing a single reaction chamber significantly reduces the processing time of the deposition-etch-deposition process by eliminating the need to transfer the substrate between different reaction chambers, which introduces significant delays and is operationally inefficient.

[0109] The apparatus 200 may also include a storage device for storing semiconductor substrates, such as a cassette storage turntable configured to store wafer cassettes, each wafer cassette accommodating multiple semiconductor substrates. The storage device may be connected to a handler, such as a substrate handling robot, configured to transfer individual semiconductor substrates or cassettes between the storage device and the reactor 201.

[0110] Reactor 201 may also include components such as insulating materials, heating elements, temperature sensors, tubes, syringes, flanges, frames and / or bases.

[0111] The apparatus 200 may include any number of suitable gas sources 202-205 connected to the reaction chamber 212 within the reactor 201 via lines 208-211, which may include flow controllers, valves, heaters, etc. The exhaust 206 may include one or more vacuum pumps. Lines 208-211 and exhaust 206 may be used as a distribution and removal system configured to supply vapors of (one or more) metal precursors, (one or more) etchants, and optionally (one or more) reactants to at least one reaction chamber within the reactor 201, and to remove vapors from at least one reaction chamber within the reactor 201.

[0112] In a non-limiting exemplary configuration, a metal precursor source 202, optionally one or more reactant sources 204, and a purge gas source 205 may be connected to a reaction chamber 212 configured to perform a deposition cycle. Additionally, an etchant source 203 and a purge gas source 205 may be connected to a reaction chamber 212 configured to perform an etching cycle. Advantageously, this configuration provides that both deposition and etching steps can be performed within the same single reaction chamber without requiring the semiconductor substrate to be transferred to a separate reaction chamber or dedicated equipment.

[0113] Metal precursor source 202 may include a container and at least one metal precursor as described herein—either alone or mixed with one or more carrier (e.g., inert) gases.

[0114] Etching source 203 may include a container and at least one etchant described herein—either alone or mixed with one or more carrier gases (e.g., inert gases).

[0115] Optional reactant sources 204 may include one or more containers and one or more reactants as described herein—either alone or mixed with one or more carrier (e.g., inert) gases. For example, apparatus 200 may include: a first reactant source comprising a container and an oxide reactant; and a second reactant source comprising a container and a nitrogen reactant.

[0116] The purge gas source 205 may include one or more inert gases, such as N2 or rare gases (e.g., argon), as described herein.

[0117] The sequence controller 207 may include electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in the device 200. Such circuitry and components operate to introduce precursors, reactants, and purge gases from corresponding sources 202-205.

[0118] The sequence controller 207 may include a memory containing an executable program that can automate certain tasks, such as the flow and timing of gas pulse sequences, the temperature of the semiconductor substrate and / or reactor 201, the pressure within reactor 201, and various other operations, to provide proper operation of the apparatus 200. The sequence controller 207 may also include control software to electrically or pneumatically control valves to control the inflow and outflow of precursors, etchants, reactants (e.g., oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, or sulfur reactants), and purge gases into and out of the reaction chamber 212 within reactor 201. The sequence controller 207 may include modules, such as one or more software and / or hardware components, such as FPGAs or ASICs, to perform certain tasks. These modules may advantageously be configured to reside on an addressable storage medium of the control system and to perform one or more processes and activate the dispensing and removal systems during the deposition-etching process.

[0119] It should be understood that other configurations of the apparatus 200 are possible, including different numbers and types of metal precursors, etchants, reactants, and purge gas sources. Furthermore, it should be understood that the objective of selectively supplying vapor to at least one reaction chamber within the reactor 201 can be achieved using numerous arrangements of valves, conduits, metal precursor sources, etchant sources, reactant sources, and purge gas sources. Additionally, for the sake of simplicity, many components have been omitted in the schematic diagram of the apparatus, and these components may include, for example, various valves, manifolds, purgers, heaters, containers, vents, and / or bypasses.

[0120] During operation of apparatus 200, a semiconductor substrate, such as a wafer (not shown), can be transferred from a storage device to a reaction chamber 212 within reactor 201 via a disposal device. Once one or more semiconductor substrates have been transferred to reaction chamber 212, one or more vapors, such as metal precursors, etchants, reactants, and / or purge gases, from respective sources 202-205 can be introduced into reaction chamber 212 via dispensing and removal systems 206 and 208-211 operably connected to sequence controller 207.

[0121] Advantageously, this paper has found that, such as Figure 2The apparatus schematically illustrated can perform the deposition of a metal-containing film and subsequent etching of that film within the same reaction chamber without requiring additional dedicated equipment. Specifically, the apparatus can perform (1) a cyclic deposition-etch-deposition (deposition-etch-deposition) process, where each deposition cycle forms a portion of the desired film thickness, and (2) depositing the full desired film thickness followed by etching. The cyclic deposition-etch-deposition process can be performed entirely within a single reaction chamber, which increases throughput by eliminating the need for substrate transfer during the process. This results in a cost-effective and versatile technique that can reduce overall processing time while accommodating different manufacturing workflows.

[0122] In addition, technicians will realize that Figure 2 The configuration of the apparatus schematically shown can be readily adapted to include a reactor shell having more than one reaction chamber, such as two, three, four, or more reaction chambers. This is provided that at least one reaction chamber remains as per the reference. Figure 2 The configuration of a single reaction chamber in the described embodiments is an extension that remains within the scope of this disclosure. For example, the reactor may include two or more reaction chambers as described herein, such as three reaction chambers, four reaction chambers, etc., each reaction chamber enabling the processing of a semiconductor substrate within the single reaction chamber.

[0123] At least one reactor in this apparatus can be any suitable system for processing semiconductor substrates, such as an ALD reactor and a CVD reactor, equipped with appropriate equipment and means for providing precursors, reactants, and etchants. According to some embodiments, a nozzle reactor may be used. According to some embodiments, a cross-flow, batch, small-batch, or space ALD reactor may be used.

[0124] In some embodiments, the apparatus of the present invention may include a vertical furnace as a single reactor. In other embodiments, the apparatus may include a vertical furnace as a first reactor and further include a second reactor. In other embodiments, the apparatus may include a vertical furnace as a first reactor and further include a vertical furnace as a second reactor.

[0125] Vertical furnaces operate in a vertical configuration, which optimizes space utilization, enhances the uniformity of heat treatment, and allows for precise control of environmental conditions. At least one reaction chamber of the vertical furnace (e.g., a vertically oriented cylindrical or tubular structure) can be advantageously configured to simultaneously receive and process multiple semiconductor substrates. The reaction chamber can be made of a heat-resistant material such as silicon carbide, silicon, or quartz, and is typically surrounded to create a controlled, inert environment for processing the reaction. Processing gases, such as precursor gases, reactant gases, etchant gases, cleaning gases, and purge gases, can be supplied to the reaction chamber via one or more injectors.

[0126] In some embodiments, the apparatus of the present invention may include a vertical furnace comprising a first reaction chamber and a second reaction chamber, which may have a vertically oriented cylindrical or tubular structure. In other embodiments, the apparatus of the present invention may include a vertical furnace comprising a single reaction chamber, which may have a vertically oriented cylindrical or tubular structure.

[0127] The vertical furnace may also include a carrier constructed and arranged to hold semiconductor substrates, preferably in a vertically stacked configuration. Suitable carriers include boats designed to vertically hold multiple semiconductor substrates in a stacked configuration. The vertical furnace may also be equipped with a boat lift designed to raise the boat into and lower it from at least one reaction chamber within the vertical furnace. A loading station or substrate handler may be connected to the vertical furnace to load substrates into the boats before insertion into the furnace.

[0128] The vertical furnace may also include heating elements, which are typically arranged around the outer periphery of at least one reaction chamber to provide uniform heat.

[0129] In a preferred embodiment, the apparatus of this disclosure may be designed such that one or more of at least one reactor is a vertical furnace, the vertical furnace including at least one reaction chamber configured to simultaneously receive and process multiple semiconductor substrates.

[0130] In certain embodiments, the apparatus of this disclosure may be designed such that at least one reactor further includes a heating device configured to provide a temperature between 200°C and 800°C in at least one reaction chamber and / or a pressure regulating mechanism configured to provide a pressure between 0.2 Torr and 200 Torr in the reaction chamber.

[0131] Figure 8 A schematic diagram of an exemplary vertical furnace system 900 according to an embodiment of the present disclosure is shown. The system is designed to process semiconductor substrates, such as semiconductor wafers, in a high-temperature reaction chamber by automatically disposing of the substrate.

[0132] The vertical furnace system 900 includes a cassette transfer port 910, which serves as an entry point for introducing a cassette 950 containing a semiconductor substrate into the system 900. Adjacent to the cassette transfer port 910 is a cassette handling chamber 920, in which the cassette storing the semiconductor substrate is temporarily stored and prepared for further processing within the system.

[0133] The housing 950 may include a FOUP (front-opening integrated compartment) configured to dock at the substrate transfer port 930, enabling safe and controlled access to the substrate for subsequent processing. A substrate handling chamber 940 is located adjacent to the substrate transfer port 930 and provides a clean and isolated environment for substrate transfer.

[0134] The cassette 950 moves within the cassette handling chamber 920 via a cassette handling robot 960. The robot 960 may include a robotic arm configured to transfer the cassette between the cassette handling chamber 920 and the substrate handling chamber 940.

[0135] Within the substrate handling chamber 940, the substrate handling robot 970 facilitates the transfer of individual substrates from the cassette 950 to the boat 980, which is designed to hold the substrate firmly in a vertical orientation for processing.

[0136] Vertically above the boat 980 is a reaction chamber 990 in which high-temperature processes, such as chemical vapor deposition (CVD) or thermal oxidation, are performed. The reaction chamber 990 is thermally insulated and configured to maintain the precise environmental conditions necessary for processing the semiconductor substrate. The reaction chamber 990 can be configured according to any of the embodiments described herein and can incorporate features as detailed with reference to those embodiments.

[0137] In the context of this disclosure, semiconductor substrate(s) including one or more gap features are provided. As used herein, the term "gap feature" can refer to an opening or cavity disposed between two surfaces that are not planar. The term "gap feature" can also refer to an opening or cavity disposed between two opposing inclined sidewalls of two protrusions extending vertically from the surface of the semiconductor substrate, or between opposing inclined sidewalls of a recess extending vertically to the surface of the semiconductor substrate; such a gap feature may be referred to as a "vertical gap feature." The term "gap feature" can also refer to an opening or cavity disposed between two opposing, substantially horizontal surfaces, the horizontal surface defining the horizontal opening or cavity; such a gap feature may be referred to as a "horizontal gap feature."

[0138] In some embodiments, one or more gap features are predefined grooves or slots in memory cells. For example, in the context of a memory device, one or more gap features may include or form portions of various word lines or word line separators.

[0139] In some embodiments, the semiconductor substrate may further include a metallic material and a surface, such as, but not limited to, pure metals, metal nitrides, metal carbides, metal borides, combinations thereof, or mixtures thereof.

[0140] The apparatus described herein is configured such that a deposition cycle allows at least partial filling of one or more interstitial features with a metal-containing film, the metal-containing film comprising at least one metal selected from the group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), and mixtures thereof.

[0141] In certain embodiments, the metal precursor is a metal halide, a metal chalcogenide halide, or a metal-organic precursor as further defined herein.

[0142] The apparatus described herein is also configured such that the deposited metal-containing film can undergo subtractive etching due to etch cycles. As used herein, the term "subtractive etch" generally refers to a material removal process used in semiconductor manufacturing to (more) precisely define or shape features in a semiconductor substrate or deposited material layer by selectively removing unwanted material. Subtractive etching can be used to form features such as trenches, vias, or isolation components in a semiconductor device or a partially fabricated semiconductor device. For example, in the context of memory devices, subtractive etching may include removing portions of word line metal filler, thereby separating each word line from its adjacent word lines.

[0143] In a specific embodiment, the etchant includes one or more halogen-containing etch compounds.

[0144] In a particular embodiment, the etchant comprises one or more halogen-containing etching compounds selected from the group consisting of: fluorine (F2), chlorine (Cl2), bromine (Br2), quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), tetrafluoroboric acid (HBF4), tetrachloroboric acid (HBCl4), tetrabromoboric acid (HBBr4), hexafluorosilicic acid (H2SiF6), hexachlorosilicic acid (H2SiCl6), hexabromosilicic acid (H2SiBr6), and tetrabutyl tetrafluoroboronic acid. Ammonium, hexafluorozirconic acid (H2ZrF6), hexafluorotitanic acid (H2TiF6), hexafluorophosphate (HPF6), molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), ammonium hexafluorosilicate [(NH4)2SiF6], ammonium hexachlorosilicate [(NH4)2SiCl6], ammonium hexabromosilicate [(NH4)2SiBr6], ammonium hexafluorotitanic acid [(NH4)2TiF6], ammonium hexachlorotitanic acid [(NH4)2TiCl6], ammonium hexabromotitanic acid [(NH4)2TiBr6], thionyl chloride (SOCl2) and mixtures thereof.

[0145] Another aspect of this disclosure provides a method for at least partially manufacturing a semiconductor device or a substructure of a semiconductor device, the method comprising the following steps:

[0146] a) Disposing at least one semiconductor substrate, including one or more gap features, in a reactor including at least one reactor chamber;

[0147] b) Performing one or more deposition cycles within a reactor chamber, each cycle comprising a metal precursor pulse, wherein at least a portion of the semiconductor substrate is contacted with the at least one metal precursor by introducing at least one metal precursor into the reactor; wherein the at least one metal precursor comprises at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, and mixtures thereof; thereby, as a result of the cycle, depositing a metal-containing film to at least partially fill one or more gap features of the semiconductor substrate; and;

[0148] c) Perform one or more etching cycles within the reactor chamber, each cycle comprising an etchant pulse, wherein at least a portion of the metal-containing film is brought into contact with at least one etchant by introducing at least one etchant into the reactor; thereby, as a result of the cycle, the metal-containing film undergoes subtractive etching.

[0149] It should be clear that the (preferred) embodiments of the apparatus and related advantages according to one aspect of this disclosure are also (preferred) embodiments of the method for partially manufacturing a semiconductor device according to one aspect of this disclosure, and vice versa.

[0150] The methods(s) disclosed herein generally relate to the formation of features for semiconductor devices with specific electronic properties. In particular, the methods provide depositing a metal-containing film, also known in the context of memory devices, on a semiconductor substrate including one or more gap features (e.g., predefined trenches), followed by subtractive etching to remove excess metal-containing film and shape the structure into a desired pattern.

[0151] In some embodiments, the formed features can be used as a single word line or electrical connection for addressing and programming memory cells.

[0152] As used herein, the terms “deposition” or “cyclic deposition” or “cyclic deposition process” or “cyclical deposition process” refer to the process of sequentially introducing precursors (and / or reactants) into a reactor to deposit a layer or film on a semiconductor substrate, and include processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include ALD components and cyclic CVD components. Typically, one deposition cycle can form a metal-containing film or layer of about 0.10 nm. However, the experimental thickness can vary depending on the amount and type of cycle and the available reaction sites on the semiconductor substrate.

[0153] In some embodiments, the metal-containing film may have a growth rate of about 0.01 nm or less for each precursor(s), optional reactant(s), and purge (e.g., inert carrier gas) gas.

[0154] The term "atomic layer deposition" (ALD) refers to a vapor-phase deposition process in which deposition cycles, typically multiple consecutive deposition cycles, are performed in a reactor. When performed using alternating pulses of one or more precursor / reactant gases and purge (e.g., inert carrier gas) gases, the term atomic layer deposition, as used herein, is also intended to include processes specified by related terms such as chemical vapor deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas-source MBE, organometallic MBE, and chemical beam epitaxy.

[0155] In a preferred embodiment, the method includes a cyclic deposition process as part of an atomic layer deposition (ALD) process.

[0156] In ALD processes, during each cycle, a precursor (e.g., a metallic precursor) is typically introduced into the reactor and chemisorbed onto the deposition surface (e.g., a semiconductor substrate surface that may include previously deposited material from a previous ALD cycle or other materials), forming a material, such as about a monolayer or sub-monolayer, or several or more monolayers, that does not readily react with another precursor (i.e., a self-limiting reaction). Subsequently, in some cases, reactants (e.g., another precursor or reactant gas) may be introduced into the reactor to convert the chemisorbed precursor into the desired material on the deposition surface. The reactants are capable of further reacting with the precursor. It should be noted that, as used herein, an ALD process does not necessarily involve a series of self-limiting surface reactions.

[0157] Optionally, a purging step may be used during one or more repetitions, such as during each deposition cycle and / or etching cycle, to remove any excess metal precursors and / or excess reactants and / or reaction byproducts from the reactor. As used herein, the term "purging" may refer to the process of supplying an inert or substantially inert gas to the reactor between two interacting gas pulses. For example, a purging, for example using an inert gas (e.g., a rare gas), may be provided between a metal precursor pulse and a reactant pulse to avoid or at least minimize gas-phase interactions between the metal precursor and the reactant.

[0158] Optionally, prior to deposition, the method may provide a pre-cleaning step to remove any impurities from at least one reaction chamber and / or the semiconductor substrate to be processed.

[0159] Advantageously, the cyclic deposition process disclosed herein can be a thermal deposition process. In other words, in some embodiments, neither the pulses nor the purging in the cyclic deposition process employ plasma.

[0160] A cyclic deposition step, including one or more deposition cycles as described herein, may include heating the semiconductor substrate to a desired deposition temperature. In some embodiments of this disclosure, the semiconductor substrate may be heated to a temperature less than about 800°C. For example, and in some embodiments, the semiconductor substrate may be heated to a temperature between about 20°C and less than about 800°C, or less than about 650°C, or less than about 600°C, or between about 200°C and less than about 600°C, or between about 200°C and less than about 550°C, or between about 200°C and less than about 500°C, or between about 200°C and 450°C. In some cases, the temperature of the semiconductor substrate may be substantially the same during a cyclic etch step including one or more etch cycles. Alternatively, and in some cases, the temperature of the semiconductor substrate may be lower during a cyclic etch step including one or more etch cycles.

[0161] In addition to controlling the temperature of the semiconductor substrate, the pressure inside the reactor can also be adjusted. For example, and in some embodiments, the pressure inside the reactor during one or more deposition cycles can be less than 760 Torr, or between about 0.2 Torr and about 200 Torr, or between about 0.5 Torr and about 50 Torr, or between about 0.5 Torr and about 20 Torr.

[0162] In some embodiments, the cyclic deposition process employs plasma-enhanced deposition techniques. For example, the cyclic deposition process may include plasma-enhanced atomic layer deposition and / or plasma-enhanced chemical vapor deposition. In this case, any pulse in the cyclic deposition process may include generating plasma in a reactor.

[0163] In some embodiments, the methods disclosed herein may be a continuous vacuum deposition process or a continuous vacuum deposition-etching process.

[0164] Continuous vacuum deposition processes can include depositing materials (e.g., metal-containing films) onto a semiconductor substrate in a reactor without introducing atmospheric air or any interruption that would disrupt the controlled vacuum environment. This process involves maintaining a consistent vacuum pressure within the reactor. In certain embodiments, the methods disclosed herein provide for forming metal-containing films without any intermediate vacuum disruption. The advantage of avoiding intermediate vacuum disruption is that it eliminates the need for repeated vacuuming and purging, common in conventional batch deposition methods.

[0165] A continuous vacuum deposition-etching process may involve depositing material (e.g., a metal-containing film) onto a semiconductor substrate in a reactor, and then etching portions of the deposited material without introducing atmospheric air or any interruption that would disrupt the controlled vacuum environment. This process involves maintaining a consistent vacuum pressure within at least one reaction chamber. The advantage of avoiding intermediate vacuum disruption during the deposition and etching of the metal-containing film is that it eliminates the need for repeated evacuation, purging, and / or removal of the semiconductor substrate from the apparatus, which is common in conventional batch methods.

[0166] In certain embodiments, the method disclosed herein for forming a metal-containing film may include at least one deposition cycle, at least two deposition cycles, at least five deposition cycles, at least ten deposition cycles, at least twenty deposition cycles, at least forty deposition cycles, at least one hundred deposition cycles, at least two hundred deposition cycles, at least four hundred deposition cycles, at least six hundred deposition cycles, or at least one thousand deposition cycles. In some embodiments, these steps may be repeated at least one deposition cycle to a maximum of one thousand deposition cycles, or at least two deposition cycles to a maximum of one hundred deposition cycles, or at least five deposition cycles to a maximum of five hundred deposition cycles.

[0167] A deposition cycle may include one or more pulses. In some embodiments, at least one pulse involves a self-limiting surface reaction. In some embodiments, all pulses involve a self-limiting surface reaction. In the context of ALD, a self-limiting surface reaction refers to a chemical reaction that automatically stops or slows down once a certain threshold or coverage is reached on the surface, for example, once a complete monolayer or sub-monolayer is formed, the reaction stops by preventing further reaction with other metal precursors.

[0168] In some embodiments, the deposition cycle may include one or more metal precursor pulses, and / or optionally one or more reactant pulses.

[0169] In some embodiments, a deposition cycle may be followed by an etching cycle, and an etching cycle may be followed by another deposition cycle. Preferably, this deposition-etch-deposition process is carried out within the same reaction chamber without transferring to another reaction chamber. This can advantageously reduce processing time because time-consuming transfers between reaction chambers can be avoided.

[0170] In an alternative embodiment, the deposition cycle may be performed in the first reaction chamber, while the etching cycle may be performed in the second reaction chamber. The semiconductor substrate is then transferred from the first reaction chamber to the second reaction chamber using a suitable handler (robot). Preferably, the first and second reaction chambers are enclosed in a single reactor, particularly within the same reactor housing that surrounds both the first and second reaction chambers.

[0171] In some embodiments, one or more metal precursor pulses last from at least 0.01 s to at most 120 s, or from at least 0.01 s to at most 0.1 s, or from at least 0.01 s to at most 0.02 s, or from at least 0.02 s to at most 0.05 s, or from at least 0.05 s to at most 0.1 s, or from at least 0.1 s to at most 20 s, or from at least 0.1 s to at most 0.2 s, or from at least 0.2 s to at most 0.5 s, or from at least 0.5 s to at most 1.0 s, or from at least 1.0 s to at most 2.0 s, or from at least 2.0 s to at most 5.0 s, or from at least 5.0 s to at most 10.0 s, or from at least 10.0 s to at most 20.0 s.

[0172] In some embodiments, one or more optional reactant pulses last from at least 0.1 s to at most 20 s, or from at least 0.1 s to at most 0.2 s, or from at least 0.2 s to at most 0.5 s, or from at least 0.5 s to at most 1.0 s, or from at least 1.0 s to at most 2.0 s, or from at least 2.0 s to at most 5.0 s, or from at least 5.0 s to at most 10.0 s, or from at least 10.0 s to at most 20.0 s, or from at least 20.0 s to at most 120.0 s, or from at least 20.0 s to at most 50.0 s, or from at least 50.0 s to at most 80.0 s, or from at least 80.0 s to at most 120.0 s.

[0173] In some embodiments, one or more etchant pulses last from at least 0.1 s to at most 20 s, or from at least 0.1 s to at most 0.2 s, or from at least 0.2 s to at most 0.5 s, or from at least 0.5 s to at most 1.0 s, or from at least 1.0 s to at most 2.0 s, or from at least 2.0 s to at most 5.0 s, or from at least 5.0 s to at most 10.0 s, or from at least 10.0 s to at most 20.0 s, or from at least 20.0 s to at most 120.0 s, or from at least 20.0 s to at most 50.0 s, or from at least 50.0 s to at most 80.0 s, or from at least 80.0 s to at most 120.0 s.

[0174] In some cases, as used herein, the term "precursor" can refer to a compound that participates in a chemical reaction to produce another compound, particularly a compound that forms the membrane matrix or the main framework of the membrane. As used herein, "metal precursor" can generally refer to a compound that participates in a chemical reaction to produce a metal-containing membrane as disclosed herein.

[0175] In the context of this disclosure, at least one metal precursor comprises at least one metal (element) selected from the group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), and mixtures thereof. The metal precursor may include, for example, molybdenum precursors, tungsten precursors, ruthenium precursors, cobalt precursors, nickel precursors, or mixtures thereof. Preferably, at least one metal precursor comprises one or more molybdenum (Mo) precursors for producing molybdenum-containing films.

[0176] It should be understood that this deposition-etching method is not limited to producing a single film or layer of a material, but may include several combinations, such as two, three, four, five, six, seven, eight, nine, ten or more metal-containing films.

[0177] In a non-limiting exemplary embodiment, molybdenum-containing films and tungsten-containing films can be produced. Alternatively, a first molybdenum-containing film and a second molybdenum-containing film with different shapes and / or thicknesses can be produced.

[0178] In another non-limiting exemplary embodiment, a first metal-containing film (e.g., a first molybdenum-containing film) may be deposited, followed by subtractive etching, and a second metal-containing film (e.g., a second molybdenum-containing film) may then be deposited, optionally followed by subtractive etching.

[0179] In a preferred embodiment, the metal precursor is a metal halide, a metal chalcogenide halide, or a metal-organic precursor. Suitable metal-organic precursors may include cyclopentadienyl, amide, amine, imide, amidine, alkyl, alkoxide, diketoate, and / or diazadiene ligands.

[0180] Exemplary molybdenum precursors include molybdenum halide precursors. As used herein, the term "molybdenum halide precursor" generally refers to a compound comprising at least a molybdenum component and a halide component, wherein the halide component may include one or more of a chlorine component, a bromine component, or an iodine component. As a non-limiting example, a molybdenum halide precursor may include at least one of the following: molybdenum pentachloride (MoCl5), molybdenum tetrachloride (MoCl4), molybdenum hexachloride (MoCl6), molybdenum trichloride (MoCl3), molybdenum dichloride (MoCl2), molybdenum pentabromide (MoBr5), molybdenum tetrabromide (MoBr4), molybdenum hexabromide (MoBr6), molybdenum tribromide (MoBr3), molybdenum dibromide (MoBr2), molybdenum pentaiodide (MoI5), molybdenum tetraiodide (MoI4), molybdenum hexaiodide (MoI6), molybdenum triiodide (MoI3), or molybdenum diiodide (MoI2). In some embodiments, the molybdenum halide precursor may include a molybdenum sulfide, and in certain embodiments, the molybdenum halide precursor may include a molybdenum sulfide halide. For example, molybdenum chalcogenide halide precursors may include molybdenum oxyhalides selected from molybdenum oxychloride, molybdenum oxyiodide, or molybdenum oxybromine. In specific embodiments of this disclosure, molybdenum halide precursors may include molybdenum oxychloride, including (but not limited to) molybdenum trichloride (V) (MoOCl3), molybdenum tetrachloride (VI) (MoOCl4), or molybdenum dichloride (VI) (MoO2Cl2). Alternatively or additionally, molybdenum precursors may include organometallic molybdenum precursors, such as Mo(CO)6, Mo(tBuN)2(NMe2)2, Mo(NBu)2(StBu)2, (Me2N)4Mo, or (iPrCp)2MoH2.

[0181] Exemplary tungsten precursors include tungsten halide precursors. As used herein, the term "tungsten halide precursor" can generally refer to a compound comprising at least a tungsten component and a halide component, wherein the halide component may include one or more of a chlorine component, a bromine component, or an iodine component. As a non-limiting example, a tungsten halide precursor may include at least one of the following: tungsten pentachloride (WCl5), tungsten tetrachloride (WCl4), tungsten trichloride (WCl3), tungsten dichloride (WCl2), tungsten pentabromide (WBr5), tungsten tetrabromide (WBr4), tungsten tribromide (WBr3), tungsten dibromide (WBr2), tungsten pentaiodide (WI5), tungsten tetraiodide (WI4), tungsten triiodide (WI3), or tungsten diiodide (WI2). In some embodiments, the tungsten halide precursor may include a tungsten sulfide, and in certain embodiments, the tungsten halide precursor may include a tungsten sulfide halide. For example, a tungsten sulfide halide precursor may include tungsten halide selected from the group consisting of tungsten oxychloride, tungsten iodide, or tungsten oxybromide. Alternatively or concurrently, the tungsten precursor may comprise a cyclopentadienyl tungsten compound, a β-diketoate tungsten compound, an alkylamine tungsten compound, an amidoyl tungsten compound, or other organometallic tungsten compounds. In some embodiments, the organometallic tungsten precursor may comprise bis(tert-butylimino)bis(tert-butylamino)tungsten (VI), bis(isopropylcyclopentadienyl)tungsten (IV) dihydrogenide, or tetracarbonyl(1,5-cyclooctadiene)tungsten (O).

[0182] Exemplary ruthenium precursors include at least one of the following: ruthenium tetroxide (RuO4), bis(cyclopentadienyl)ruthenium(II), bis(ethylcyclopentadienyl)ruthenium(II), and triruthenium.

[0183] Exemplary cobalt precursors include organometallic cobalt precursors, such as cyclopentadienyl compounds, β-diketone cobalt compounds, or amidocobalt compounds, or other organometallic cobalt compounds. In some embodiments, the organometallic cobalt precursor may be selected from bis(acetylacetone)cobalt(II), bis(ethylcyclopentadienyl)cobalt(II), bis(2,2,6,6-tetramethyl-3,5-heptadecyl)cobalt(II), bis(1,4-di-tert-butyl-1,3-diazabutadiene)cobalt(II), or bis(N-tert-butyl-N'-ethylpropanediamine)cobalt(II). Alternatively, cobalt halides, such as cobalt chloride, cobalt bromide, or cobalt iodide, may be used.

[0184] Exemplary nickel precursors include nickel β-diketone compounds, nickel β-diketone imine compounds, amidine nickel compounds, cyclopentadienyl nickel compounds, nickel carbonyl compounds, and combinations thereof. Nickel precursors may also include one or more halide ligands. In a preferred embodiment, the precursor is a β-diketone nickel compound, such as bis(4-N-ethylamino-3-penten-2-N-ethylimine)nickel(II) [Ni(EtN-EtN-pent)2], a ketoimine nickel compound, such as bis(3Z)-4-n-butylamino-pent-3-en-2-one-nickel(II), an amidine nickel compound, such as methylcyclopentadienyl-isopropylacetamidine-nickel(II), a β-diketone nickel compound, such as Ni(acac)2, Ni(thd)2, or a cyclopentadienyl nickel compound, such as Ni(cp)2, Ni(Mecp)2, Ni(Etcp)2, or a derivative thereof, such as methylcyclopentadienyl-isopropylacetamidine-nickel(II). In a more preferred embodiment, the precursor is bis(4-N-ethylamino-3-penten-2-N-ethylimine)nickel(II).

[0185] At least one of the deposition cycles may further include a reactant pulse, wherein at least a portion of the semiconductor substrate is contacted with the at least one reactant by introducing the at least one reactant into the reactor. Preferably, the at least one reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

[0186] Exemplary oxide reactants include H2O, O2, O3, H2O2, N2O, NO2, N2O4, pyridine N-oxide and O2 plasma, or mixtures thereof.

[0187] Exemplary nitrogen reactants include NH3, N2H4, tert-butylhydrazine, 1,1-dimethylhydrazine, methylhydrazine, phenylhydrazine, tert-butylamine, isobutylamine, tert-amylamine, N2 plasma, NH3 plasma, and N2 / H2 plasma, or mixtures thereof.

[0188] Exemplary boron reactants include BH3, B2H6, and B. 10 H 14 BF3, BCl3, BBr3, BI3, B(CH3)3, B(CH2CH3)3, B(OCH3)3, B[N(CH3)2]3, BH3[S(CH3)2], borazane, trichloroborane, ammonia-borane, trimethylamine-borane, triethylamine-borane, pyridine-borane, dimethylamine-borane, 2-methylpyridine-borane, tert-butylamine-borane, tetrahydrofuran-borane and pinacolborane, or mixtures thereof.

[0189] Exemplary reduction reactants include H2, H2 plasma, N2 / H2 plasma, N2H4, tert-butylhydrazine, 1,1-dimethylhydrazine, formic acid, formalin, pinacolborane, B2H6, and B. 10 H 14 BH3[S(CH3)2], ammonia-borane, trimethylamine-borane, triethylamine-borane, pyridine-borane, dimethylamine-borane, 2-methylpyridine-borane, tert-butylamine-borane, tetrahydrofuran-borane, pinacol-borane, silane, diethylsilane, propane, bis(diethylamino)silane, diisopropylaminosilane and cyclohexadiene, or mixtures thereof.

[0190] Exemplary phosphorus reactants include phosphine (PH3), phosphorus halides, phosphorus oxyhalides, organophosphates, organophosphites, aminophosphine, alkylphosphine, and silylphosphine, or mixtures thereof.

[0191] Exemplary carbon reactants include H2, H2 plasma, N2 / H2 plasma, iodomethane, diiodomethane, iodoethane, 1,2-diiodoethane, bromoethane, 1,2-dibromoethane, bromobenzene, iodobenzene, 1-bromobutane, 1-iodobutane, dicyclopentadiene, acetylene, propargyl chloride, propargyl bromide, propargyl iodide, allyl chloride, allyl bromide, allyl iodide, and cyclohexadiene, or mixtures thereof.

[0192] Exemplary sulfur reactants include H2S, S8, S2Cl2, tert-butyl mercaptan, bis(trimethylsilyl) sulfide, 1,2-ethylenedithiol, dimethyl disulfide, diethyl disulfide, ditert-butyl disulfide, and carbon disulfide, or mixtures thereof.

[0193] As used herein, the terms “etching” or “cyclic etching” or “cyclic etching process” refer to the sequential introduction of etchant into a reactor to define or shape features in a semiconductor substrate or deposited material layer by selectively removing unwanted material.

[0194] In certain embodiments, etching of the deposited metal-containing film provided by the methods disclosed herein may include at least one etch cycle, at least two etch cycles, at least five etch cycles, at least ten etch cycles, at least twenty etch cycles, at least forty etch cycles, at least one hundred etch cycles, at least two hundred etch cycles, at least four hundred etch cycles, at least six hundred etch cycles, or at least one thousand etch cycles. In some embodiments, these steps may be repeated from at least one etch cycle to a maximum of 1,000 etch cycles, or from at least two etch cycles to a maximum of 100 etch cycles, or from at least five etch cycles to a maximum of 50 etch cycles. Each etch cycle may include one or more etchant pulses.

[0195] In some embodiments, one or more etchant pulses last from at least 0.1 s to at most 20 s, or from at least 0.1 s to at most 0.2 s, or from at least 0.2 s to at most 0.5 s, or from at least 0.5 s to at most 1.0 s, or from at least 1.0 s to at most 2.0 s, or from at least 2.0 s to at most 5.0 s, or from at least 5.0 s to at most 10.0 s, or from at least 10.0 s to at most 20.0 s, or from at least 20.0 s to at most 120.0 s, or from at least 20.0 s to at most 50.0 s, or from at least 50.0 s to at most 80.0 s, or from at least 80.0 s to at most 120.0 s.

[0196] During the etching step of this method, the same processing temperature as during the deposition step can be used, or a different temperature can be used. In some embodiments, the processing temperature (i.e., the substrate temperature) during the etching step can be less than about 800°C, or less than about 700°C, or less than about 600°C, or less than about 500°C, or less than about 400°C, or less than about 300°C, or even less than about 200°C. In some embodiments of this disclosure, the substrate temperature during the etching stage can be between 200°C and 800°C, or between 300°C and 700°C, or between 400°C and 600°C, or between 525°C and 575°C.

[0197] In addition to reaching the required processing temperature, i.e., the required substrate temperature, the reaction chamber pressure during the (partial) etching of the metal-containing film can be adjusted to be the same as the pressure used in the deposition step, or the reaction chamber pressure can be different from the pressure used in the deposition step. In some embodiments, the reaction chamber pressure can be adjusted to less than 760 Torr, or between about 0.2 Torr and about 200 Torr, or between about 0.5 Torr and about 50 Torr, or between about 0.5 Torr and about 20 Torr.

[0198] In some embodiments, the etching rate of the metal-containing film may be less than 10 angstroms per second, or less than 8 angstroms per second, or less than 6 angstroms per second, or less than 4 angstroms per second, or even less than 2 angstroms per second. For example, partial etching of the metal-containing film may include etching a thickness of less than 20 angstroms, or less than 10 angstroms, or even less than 5 angstroms. In some embodiments, the etchant may preferentially etch the metal-containing film near the entrance of one or more gap features, thereby maintaining an opening to the one or more gap features for subsequent metal gap filling processing.

[0199] Following the etchant pulse, each cycle may further include purging the reaction chamber. For example, etchant gas and reaction byproducts (if any) can be removed from the surface of the semiconductor substrate, for example, by pumping inert gas. In some embodiments of this disclosure, the purging process may include a purging cycle in which the semiconductor substrate surface is purged for a period of less than about 10.0 seconds, or less than about 5.0 seconds, or even less than about 2.0 seconds. Excess etchant gas and any possible reaction byproducts can be removed by means of a vacuum generated by a pumping system in fluid communication with the reaction chamber.

[0200] As used herein, the term "etcher" can refer to a chemical substance or reaction medium used in semiconductor manufacturing to selectively remove material from a substrate or thin film layer during an etching process. Suitable etchants as used herein include halogen-containing compounds.

[0201] In a particular embodiment, the etchant comprises one or more halogen-containing etching compounds selected from the group consisting of: fluorine (F2), chlorine (Cl2), bromine (Br2), quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), tetrafluoroboric acid (HBF4), tetrachloroboric acid (HBCl4), tetrabromoboric acid (HBBr4), hexafluorosilicic acid (H2SiF6), hexachlorosilicic acid (H2SiCl6), hexabromosilicic acid (H2SiBr6), tetrabutylammonium tetrafluoroborate, hexafluorozirconic acid (H2ZrF6), hexafluorotitanic acid (H2TiF6), hexafluorophosphate (H P F6), molybdenum pentachloride (MoCl5), tungsten pentachloride (WCl5), ammonium hexafluorosilicate ([(NH4)2SiF6]), ammonium hexachlorosilicate ([(NH4)2SiCl6]), ammonium hexabromosilicate ([(NH4)2SiBr6]), ammonium hexafluorotitanate ([(NH4)2TiF6]), ammonium hexachlorotitanate ([(NH4)2TiCl6]), ammonium hexabromotitanate ([(NH4)2TiBr6]), thionyl chloride (SOCl2) and mixtures thereof.

[0202] Figure 3 A method 300 for partially manufacturing a semiconductor device or a substructure of a semiconductor device according to embodiments of the present disclosure is described.

[0203] The method begins 301 when a semiconductor substrate, including one or more gap features, is provided to a reaction chamber constructed and arranged within a reactor. The semiconductor substrate can be any substrate as defined herein. The reactor can be a standalone reactor or part of a cluster of tools.

[0204] Cyclic deposition includes contacting one or more metal precursors with at least a portion of a semiconductor substrate during a metal precursor pulse 302. Optionally, a reaction chamber may be purged 303 after the metal precursor pulse 302. The metal precursor pulse 302 and the optional purge 303 may be repeated 304 any number of times to obtain a metal-containing film of desired thickness.

[0205] Next, method 300 continues by bringing one or more etchants into at least a portion of the formed metal-containing film during etchant pulse 305. Optionally, the reaction chamber may be purged 306 after etchant pulse 305. Etching pulse 305 and optional purge 306 may be repeated 307 any number of times.

[0206] When the features of a semiconductor device of desired shape and thickness are formed based on any combination of the foregoing steps, method 300 ends at 308. Once the method ends, the semiconductor substrate may be subjected to additional processes known in the art for forming semiconductor devices, such as memory device structures and / or memory devices.

[0207] Figure 4 A method 400 for partially manufacturing a semiconductor device or a substructure of a semiconductor device according to another embodiment of the present disclosure is described.

[0208] The method begins 401 after a semiconductor substrate, including one or more gap features, has been provided into a reaction chamber constructed and arranged within the reactor. The semiconductor substrate can be any substrate as defined herein. The reactor can be a standalone reactor or part of a cluster of tools.

[0209] Cyclic deposition includes bringing one or more metal precursors into at least partial contact with a semiconductor substrate during a metal precursor pulse 402. Optionally, a reaction chamber is purged 403 after the metal precursor pulse 402. The metal precursor pulse 402 and the optional purge 403 can be repeated 404 any number of times to obtain a metal-containing film of desired thickness.

[0210] Next, the cyclic deposition process continues by bringing one or more reactants into at least partial contact with the semiconductor substrate and / or the deposited metal-containing film during reactant pulse 405. Optionally, the reaction chamber 406 may be purged after reactant pulse 405. Reactant pulse 405 and optional purge 406 may be repeated 407 any number of times.

[0211] Next, method 400 continues by bringing one or more etchants into at least a portion of the formed metal-containing film during etchant pulse 408. Optionally, the reaction chamber may be purged 409 after etchant pulse 408. Etching pulse 408 and optional purge 409 may be repeated 410 any number of times.

[0212] When the features of a semiconductor device of desired shape and thickness are formed based on any combination of the foregoing steps, method 400 ends 411. Once the method ends, the semiconductor substrate may be subjected to additional processes known in the art for forming semiconductor devices, such as memory device structures and / or memory devices.

[0213] Figure 5 A method 500 for partially manufacturing a semiconductor device or a substructure of a semiconductor device according to yet another embodiment of the present disclosure is described.

[0214] The method begins 501 after a semiconductor substrate, including one or more gap features, has been provided into a first reaction chamber constructed and arranged within the reactor. The semiconductor substrate can be any substrate as defined herein. The reactor can be a standalone reactor or part of a cluster of tools.

[0215] Cyclic deposition includes contacting one or more metal precursors with at least a portion of a semiconductor substrate during a metal precursor pulse 502. Optionally, a first reaction chamber is purged 503 after the metal precursor pulse 502. The metal precursor pulse 502 and the optional purge 503 can be repeated 504 any number of times to obtain a metal-containing film of desired thickness.

[0216] After depositing the metal-containing film, the semiconductor substrate is transferred 505 from the first reaction chamber to a second reaction chamber constructed and arranged within the reactor. The process is then continued by bringing one or more etchants into at least a portion of the formed metal-containing film during an etchant pulse 506. Optionally, the second reaction chamber may be purged 507 after the etchant pulse 506. The etchant pulse 506 and the optional purging 507 may be repeated 508 any number of times.

[0217] When the features of a semiconductor device of desired shape and thickness are formed based on any combination of the foregoing steps, method 500 ends at 509. Once the method ends, the semiconductor substrate may be subjected to additional processes known in the art for forming semiconductor devices, such as memory device structures and / or memory devices.

[0218] Figure 6 A method 600 for partially manufacturing a semiconductor device or a substructure of a semiconductor device according to yet another embodiment of the present disclosure is described.

[0219] After a semiconductor substrate, including one or more gap features, has been provided into a first reaction chamber constructed and arranged within a reactor, method 600 begins 601. The semiconductor substrate can be any substrate as defined herein. The reactor can be a standalone reactor or part of a cluster of tools.

[0220] Cyclic deposition includes bringing one or more metal precursors into at least partial contact with a semiconductor substrate during a metal precursor pulse 602. Optionally, a first reaction chamber is purged 603 after the metal precursor pulse 602. The metal precursor pulse 602 and the optional purge 603 can be repeated 604 any number of times to obtain a metal-containing film of desired thickness.

[0221] Next, the cyclic deposition process continues by bringing one or more reactants into at least partial contact with the semiconductor substrate and / or the deposited metal-containing film during reactant pulse 605. Optionally, the first reaction chamber may be purged 606 after reactant pulse 605. Reactant pulse 605 and optional purge 606 may be repeated 607 any number of times.

[0222] After contacting the metal-containing film with one or more reactants, the semiconductor substrate is transferred 608 from the first reaction chamber to a second reaction chamber constructed and arranged within the reactor. The process is then continued by contacting at least a portion of the formed metal-containing film with one or more etchants in an etchant pulse 609. Optionally, the second reaction chamber may be purged 610 after the etchant pulse. The etchant pulse 609 and the optional purging 610 may be repeated 611 any number of times.

[0223] When individual word lines of desired shape and thickness are formed based on any combination of the above steps, method 600 ends at 612. Once the method ends, the semiconductor substrate may be subjected to additional processes known in the art for forming semiconductor devices, such as memory device structures and / or memory devices.

[0224] Figure 7 A method 700 for partially manufacturing a semiconductor device or a substructure of a semiconductor device according to yet another embodiment of the present disclosure is described.

[0225] Method 700 begins 701 after a semiconductor substrate, including one or more gap features, is provided into a first reaction chamber constructed and arranged within a reactor. The semiconductor substrate can be any substrate as defined herein. The reactor can be a standalone reactor or part of a cluster of tools.

[0226] Cyclic deposition includes contacting one or more metal precursors with at least a portion of a semiconductor substrate during a metal precursor pulse 702. Optionally, a first reaction chamber is purged 703 after the metal precursor pulse 702. The metal precursor pulse 702 and the optional purge 703 can be repeated 704 any number of times to obtain a metal-containing film of desired thickness.

[0227] After depositing the metal-containing film, the semiconductor substrate is transferred 705 from the first reaction chamber to a second reaction chamber constructed and arranged within the reactor. Next, a cyclic deposition process is continued by bringing one or more reactants into at least partial contact with the semiconductor substrate and / or the deposited metal-containing film during a reactant pulse 706. Optionally, the first reaction chamber may be purged 707 after the reactant pulse 706. The reactant pulse 706 and the optional purge 707 may be repeated 708 any number of times.

[0228] After contacting the metal-containing film with one or more reactants, the semiconductor substrate is transferred 709 from the second reaction chamber to a third reaction chamber constructed and arranged within the reactor. The process is then continued by contacting at least a portion of the formed metal-containing film with one or more etchants during an etchant pulse 710. Optionally, the second reaction chamber may be purged 711 after the etchant pulse. The etchant pulse 710 and the optional purge 711 may be repeated 712 any number of times.

[0229] When individual word lines of desired shape and thickness are formed based on any combination of the above steps, method 700 ends at 713. Once the method ends, the semiconductor substrate may be subjected to additional processes known in the art for forming semiconductor devices, such as memory device structures and / or memory devices.

[0230] Another aspect of this disclosure provides a semiconductor device including one or more gap features filled with a metal-containing film, the metal-containing film being prepared using an apparatus according to one aspect of this disclosure or a (preferred) embodiment thereof, or by a method according to one aspect of this disclosure or a (preferred) embodiment thereof.

[0231] It should be clear that the (preferred) embodiments and related advantages of the apparatus and method according to one aspect of this disclosure are also (preferred) embodiments of the semiconductor device according to one aspect of this disclosure, and vice versa.

[0232] In a particular embodiment, the semiconductor device of the present invention is a memory device. As used herein, the term "memory device" refers to an electronic component designed to store, retain, and retrieve digital information. It can employ various physical mechanisms known in the art to represent and store data in a manner that allows subsequent access and manipulation. Memory devices are integrated components of computing systems and electronic devices, facilitating tasks such as data storage, retrieval, processing, and transmission. In the context of memory devices, MIM capacitors are important components for data storage and retrieval. The methods disclosed herein are particularly suitable for producing MIM capacitors with high charge retention and fast charge release, thereby obtaining memory devices with more reliable data storage and retrieval. Non-limiting exemplary memory devices include at least one of 3D-NAND devices, DRAM devices, 3D integrated devices, or integrated logic devices, or partially manufactured memory device structures including at least one of 3D-NAND device structures, DRAM device structures, 3D integrated device structures, or partially manufactured integrated logic device structures.

[0233] In embodiments where the semiconductor device includes a (partially) manufactured DRAM device structure, the semiconductor substrate may include multiple features, the multiple features including multiple DRAM word lines.

[0234] Figure 9 A schematic cross-sectional view of an exemplary semiconductor memory device 800 according to an embodiment of the present disclosure is shown. Specifically, the figure depicts a channel cross-section of the 3D NAND device 800. The device 800 includes bit lines 810 that can be used to read and write data to the memory device via the drain or source of a plurality of transistors within a memory array (not shown).

[0235] Bit line 810 is located at the top of the memory string, opposite a bottom select gate 820 located at the base of the vertical memory string. The bottom select gate 820 controls the connection between the memory string and the source line, thereby enabling or disabling current flow during memory operations such as read, write, or erase. The bottom select gate 820 is positioned adjacent to a conductive channel 860, which acts as a conductive path for charge carriers between the source and drain terminals.

[0236] Arranged between bit line 810 and bottom select gate 820 are a plurality of floating gate transistors 840 configured to store charge representing binary data of the memory device. Each floating gate transistor 840 is associated with a specific word line 850 as described herein. The floating gate transistors 840 are vertically supported by spacers 870 that define the dimensions of the word line and the channel opening. The spacers 870 may include a dielectric material.

[0237] Word line 850 serves as the control gate for the floating-gate transistor and can be used to address and operate transistor 840 during memory operations. Each layer in the vertical stack includes word lines that control the floating-gate transistors at that layer. For example, in a memory string with 64 layers, there would be 64 word lines controlling 64 floating-gate transistors in the string. A shared channel in the vertical stack is connected to the drain 830, thereby enabling the flow of current required for memory operations.

Claims

1. An apparatus comprising: - At least one reactor, comprising at least one reaction chamber configured and arranged for processing at least one semiconductor substrate; wherein the semiconductor substrate includes one or more gap features; - A metal precursor source configured and arranged to provide a vapor of at least one metal precursor, said at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, cobalt, nickel, and mixtures thereof; - An etchant source, which is constructed and arranged to provide vapor of at least one etchant; - A vapor distribution and removal system configured to supply the vapors of the metal precursor source and the etchant source to the at least one reaction chamber within the reactor, and to remove the vapors from the reaction chamber; and A sequence controller, operably connected to the distribution and removal system, includes a memory containing a program configured to control the flow from the metal precursor source to the reaction chamber by activating the vapor distribution and removal system during one or more deposition cycles; thereby, as a result of the deposition cycle, a metal-containing film is deposited to at least partially fill the one or more gap features of the semiconductor substrate; and... The procedure is further configured to control the flow from the etchant source to the reaction chamber by activating the vapor distribution and removal system during one or more etching cycles; thereby, as a result of the etching cycle, the metal-containing film undergoes subtractive etching.

2. The apparatus of claim 1, further comprising a reactant source configured and arranged to provide vapor of reactants; wherein, The vapor distribution and removal system is further configured to supply the vapor from the reactant source to the reactor; and wherein the program disposed on the memory is configured to control the flow of the reactant from the reactant source to the at least one reactor chamber during the one or more deposition cycles.

3. The apparatus according to claim 1 or 2, wherein, The reactants are selected from the group consisting of: oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

4. The apparatus according to any one of claims 1 to 3, wherein, The program set on the memory is also configured to control the flow from the metal precursor source to the at least one reactor chamber by activating the vapor distribution and removal system during the one or more deposition cycles, the one or more deposition cycles being included in a cyclic deposition process as part of an atomic layer deposition process.

5. The apparatus according to any one of claims 1 to 4, wherein, The at least one semiconductor substrate further includes a material selected from the group consisting of silicon, silicon oxide, silicon germanium, carbon-doped silicon oxide, silicon nitride, silicon carbide, germanium, gallium arsenide, gallium nitride, glass, sapphire, and combinations thereof.

6. The apparatus according to any one of claims 1 to 5, wherein, The metal precursor is a metal halide, a metal chalcogenide halide, or a metal-organic precursor.

7. The apparatus according to any one of claims 1 to 6, wherein, The etchant includes one or more halogen-containing etching compounds.

8. The apparatus according to any one of claims 1 to 7, wherein, The etchant comprises one or more halogen-containing etching compounds selected from the group consisting of: F2, Cl2, Br2, quaternary ammonium fluoride, quaternary ammonium chloride, quaternary ammonium bromide, HF, HCl, HBr, tetrafluoroboric acid, tetrachloroboric acid, tetrabromoboric acid, hexafluorosilicic acid, hexachlorosilicic acid, hexabromosilicic acid, tetrabutylammonium tetrafluoroborate, H2ZrF6, H2TiF6, HPF6, MoCl5, WCl5, ammonium hexafluorosilicate, ammonium hexachlorosilicate, ammonium hexabromosilicate, ammonium hexafluorotitanate, ammonium hexachlorotitanate, ammonium hexabromotitanate, thionyl chloride, and mixtures thereof.

9. The apparatus according to any one of claims 1 to 8, wherein, The at least one reactor also includes a heating device configured to provide a temperature of 200°C to 800°C within the reactor chamber.

10. The apparatus according to any one of claims 1 to 9, wherein, The at least one reactor also includes a pressure regulating mechanism configured to provide a pressure between 0.2 Torr and 200 Torr within the reactor chamber.

11. The apparatus according to any one of claims 1 to 10, wherein, One or more of the at least one reactor is a vertical furnace, the vertical furnace including at least one reaction chamber configured to simultaneously receive and process multiple semiconductor substrates.

12. The apparatus according to any one of claims 1 to 11, wherein, The reactor includes a reactor shell and a disposal chamber, the reactor shell surrounding at least a first reaction chamber and a second reaction chamber, the disposal chamber being configured to transfer the semiconductor substrate between the first reaction chamber and the second reaction chamber; wherein the one or more deposition cycles are performed in the first reaction chamber and the one or more etching cycles are performed in the second reaction chamber; and wherein the vapor distribution and removal system is further configured to selectively direct the flow of the metal precursor vapor to at least the first reaction chamber and the flow of the etchant vapor to at least the second reaction chamber.

13. The apparatus according to any one of claims 1 to 11, wherein, The reactor includes a reactor shell surrounding a single reaction chamber; wherein the one or more deposition cycles and the one or more etching cycles are carried out within the reaction chamber; and wherein the vapor distribution and removal system is further configured to selectively direct the flow of the metal precursor vapor and etchant vapor into the reaction chamber and remove them.

14. A method for at least partially manufacturing a semiconductor device, the method comprising the steps of: a) Providing at least one semiconductor substrate, including one or more gap features, into a reactor including at least one reactor chamber; b) Perform one or more deposition cycles within the reactor chamber, each cycle including A metal precursor pulse, wherein at least a portion of the semiconductor substrate is contacted with the at least one metal precursor by introducing at least one metal precursor into the reactor; wherein the at least one metal precursor comprises at least one metal selected from the group consisting of molybdenum, tungsten, ruthenium, and mixtures thereof; Thus, as a result of the cycle, the metal-containing film is deposited to at least partially fill the one or more gap features of the semiconductor substrate; and, c) Perform one or more etching cycles within the reactor chamber, each cycle including Etching pulse, wherein at least a portion of the metal-containing film is brought into contact with the at least one etchant by introducing at least one etchant into the reactor; As a result of the cycle, at least a portion of the metal-containing film undergoes subtractive etching.

15. The method according to claim 14, wherein, The at least one deposition cycle further includes a reactant pulse, wherein at least a portion of the semiconductor substrate is in contact with the at least one reactant by introducing at least one reactant into the reactor.

16. The method according to claim 15, wherein, The at least one reactant is selected from the group consisting of oxide reactants, nitrogen reactants, boron reactants, reduction reactants, phosphorus reactants, carbon reactants, sulfur reactants, and combinations thereof.

17. The method according to any one of claims 14 to 16, wherein, The reactor includes a reactor shell and a disposal chamber, the reactor shell surrounding at least a first reaction chamber and a second reaction chamber, the disposal chamber being configured to transfer the semiconductor substrate between the first reaction chamber and the second reaction chamber; and wherein the one or more deposition cycles are performed in the first reaction chamber and the etching cycle is performed in the second reaction chamber without removing the semiconductor substrate from the reactor.

18. The method according to any one of claims 14 to 16, wherein, The reactor includes a reactor shell surrounding a single reaction chamber; and wherein the one or more deposition cycles and the one or more etching cycles are performed within the reaction chamber without removing the semiconductor substrate from the reactor.

19. A semiconductor device comprising one or more gap features filled with a metal-containing film, prepared using the means according to any one of claims 1 to 13 and / or by the method according to any one of claims 14 to 18.

20. The semiconductor device according to claim 19, wherein, The semiconductor device is a memory device comprising at least one of a 3D-NAND device, a DRAM device, a 3D integrated device, or an integrated logic device, or Partially manufactured memory device structures, including at least one of 3D-NAND device structures, DRAM device structures, 3D integrated device structures, or partially manufactured integrated logic device structures.

Images