Micro electrostatic chuck for chip to substrate bonding and method of manufacturing the same

Abstract

The present application relates to a micro electrostatic chuck for chip-to-substrate bonding and a manufacturing method thereof. The electrostatic chuck can be manufactured by using conventional semiconductor process and is provided with through-silicon via and dielectric via structures. Electrostatic chucks of different sizes can be detachably connected with multi-axis mechanical arms, so as to realize optimized chip-to-substrate bonding process.

Description

[0001] Cross-reference to related applications

[0002] This invention claims priority to U.S. Patent Application No. 18 / 939,538, filed on November 7, 2024. Technical Field

[0003] This invention relates to bonding heads used in semiconductor manufacturing, and more particularly, to micro electrostatic chucks (ESCs) for adsorbing thin semiconductor chips in chip-to-substrate bonding processes. Background Technology

[0004] In advanced semiconductor packaging processes, adsorbing and positioning thin chips (especially those prone to warping) presents significant challenges. Traditional bonding heads often lack the necessary control and stability for smaller, more fragile chips. As chip thickness continues to decrease dramatically, the need for miniature electrostatic chucks capable of safely adsorbing such chips without causing damage is becoming increasingly urgent.

[0005] Miniature electrostatic chucks address these challenges by providing localized electrostatic attraction to small-sized chips. The electrostatic attraction generated by the chuck mitigates warping effects, allowing the chip to adhere to the chuck surface for more uniform contact. However, manufacturing such specialized electrostatic chucks is costly, and replacement typically requires significant time and expense. The high cost and fixed structure of customized electrostatic chucks also limit their flexibility, making them unsuitable for chips of different sizes, thus increasing operating costs.

[0006] This invention presents a miniature electrostatic chuck manufactured using semiconductor manufacturing processes, offering several significant advantages. Leveraging mature semiconductor manufacturing technology, production costs can be significantly reduced, making the miniature electrostatic chuck economical and easy to manufacture. The ability to manufacture electrostatic chucks of different sizes provides strong flexibility; when necessary, a single miniature electrostatic chuck can simultaneously adsorb multiple chips. Furthermore, the detachable structure of the electrostatic chuck simplifies replacement and maintenance processes, reduces downtime, and improves process efficiency. This detachable feature further enhances adaptability, allowing for easy replacement when the adsorption surface ages or when the chuck size needs adjustment.

[0007] Therefore, this invention meets the specific adsorption requirements of thinner and warped chips, while improving cost-effectiveness, flexibility and operational efficiency in advanced packaging processes. Summary of the Invention

[0008] This invention provides a miniature electrostatic chuck for bonding heads, designed to adsorb fragile semiconductor chips (including those highly susceptible to severe warping). The electrostatic adsorption force applied by this miniature electrostatic chuck mitigates warping effects, more uniformly adsorbs chip surfaces, and improves stability during semiconductor processing. The electrostatic chuck is manufactured using semiconductor manufacturing processes and incorporates through-silicon via (TSV) and through-dielectric via (TDV) structures to achieve effective electrical connection between the base silicon layer and electrodes, wherein the electrodes are embedded within the body dielectric layer and located below the surface dielectric layer. During manufacturing, the TDVs are filled with conductive materials such as copper or tungsten and aligned with the TSVs to stably apply a bias voltage to the electrodes, thereby generating electrostatic adsorption force. These processes enable the electrostatic chuck to be produced in customizable sizes, providing a cost-effective solution adaptable to chips of various sizes, including configurations where a single electrostatic chuck simultaneously adsorbs multiple chips.

[0009] The bias voltage required to generate the electrostatic attraction force is provided by a power source located within the support structure, which may include a rechargeable battery. This structural design enables independent power supply, eliminating the need for external wiring and improving the versatility of the electrostatic chuck. In some implementations, the electrostatic chuck can be easily attached to and detached from the support structure, facilitating quick replacement and maintenance, reducing downtime, and rapidly adapting to changing chip adsorption requirements.

[0010] Furthermore, alignment structures can be fabricated on the surface of the electrostatic chuck using semiconductor manufacturing processes to ensure precise chip placement. These arrayed alignment marks are directly applied to the electrostatic chuck, facilitating accurate and consistent chip placement and further improving alignment precision. This invention provides a scalable, economical, and flexible solution to the challenge of securely holding warped and sensitive chips, significantly improving the cost efficiency, adaptability, and alignment accuracy of advanced semiconductor packaging processes. Attached Figure Description

[0011] To clearly describe the technical solution, the following explanation will refer to the accompanying drawings:

[0012] Figure 1 A schematic diagram of a bonding head with a miniature electrostatic chuck is shown as an example.

[0013] Figure 2 This document presents a flowchart illustrating the manufacturing process of electrostatic chucks based on semiconductor manufacturing techniques.

[0014] Figure 3 This diagram illustrates the evolution of the manufacturing process for electrostatic chucks.

[0015] Figure 4This diagram illustrates an alignment array on the surface of an electrostatic chuck used for the precise placement of multiple chips.

[0016] Figure 5 This image shows an example of placing an AI chip system containing multiple chips onto the surface of an electrostatic chuck. Detailed Implementation

[0017] To facilitate a full understanding of the invention, specific embodiments thereof will be described in detail below. While specific details are provided for ease of explanation, any modifications and variations consistent with the technical principles of the invention are considered appropriate. Certain well-known procedures and components are described selectively only to highlight the unique features of the invention.

[0018] Terminology definition:

[0019] Miniature Electrostatic Chuck (ESC): A compact adsorption device that uses electrostatic attraction to adsorb one or more chips for chip-to-substrate bonding.

[0020] Through-Silicon Via (TSV): An electrical connection structure that runs vertically through a silicon wafer and is often used to achieve interconnection between different layers or components in semiconductor devices.

[0021] Through-Dielectric Via (TDV): An electrical connection structure that penetrates vertically through a dielectric layer, used to achieve electrical connections between different layers or components in a semiconductor device.

[0022] Bulk Dielectric Layer: The main insulating layer in an electrostatic chuck, usually located above the silicon layer, serves to provide electrical insulation and mechanical support.

[0023] Surface Dielectric Layer: The outermost dielectric layer of an electrostatic chuck, typically made of ceramic material with specific thermal and dielectric properties, used to achieve electrostatic adsorption.

[0024] The Johnsen-Rahbek effect: a phenomenon used in some electrostatic chucks, which enhances electrostatic attraction by controlling leakage current.

[0025] Electrostatic Clamping Force: The force generated by applying a DC bias voltage to the internal electrodes of an electrostatic chuck can stably adsorb a chip or substrate onto the surface of the chuck.

[0026] Copper Pillar: A conductive structure within a through-silicon via (TSV) that acts as an electrical connector, enabling electrical connections between different layers.

[0027] Liner: An insulating layer (usually oxide) deposited inside through-holes (such as through-silicon vias and dielectric vias) to isolate conductive components such as copper pillars from the surrounding structure and prevent leakage.

[0028] Temporary Substrate: A removable support substrate used in the manufacturing process of electrostatic chucks to provide stability or protection during specific processing steps.

[0029] Blanket Silicon Etching: A silicon etching process performed uniformly on the wafer surface, typically used to expose through-silicon vias.

[0030] Dicing Process: The process of separating electrostatic chuck structures using mechanical or laser technology.

[0031] Bias Voltage: A DC voltage applied to the electrodes of an electrostatic chuck to generate electrostatic attraction.

[0032] Multi-axis robotic arm: A robotic arm with multiple degrees of freedom that can precisely adjust the position of an electrostatic chuck in three-dimensional space.

[0033] Alignment Array: Patterns (such as two-dimensional barcodes or variable key-size grids) on the surface of an electrostatic chuck provide positional information for the alignment system, which helps in the precise placement of the chip.

[0034] Reflectometry Sensor: A sensor that determines the position of an electrostatic chuck relative to a chip by measuring the optical characteristics of an alignment array.

[0035] Figure 1A schematic diagram of a bonding head 100 is shown as an example. The bonding head 100 includes a miniature electrostatic chuck 101 connected to a support 114. The support 114 has a built-in power supply 115 that provides a DC bias to generate an electrostatic attraction force, thereby adsorbing the substrate onto the upper surface of the electrostatic chuck 101. In some embodiments, the power supply 115 is a rechargeable battery installed inside the support 114. The support 114 is connected to a motion mechanism 118, which may be a multi-axis robotic arm. A six-axis robotic arm is typically used because it enables precise three-dimensional control, allowing movement along the X, Y, and Z axes and rotation (roll, pitch, and yaw) around these three axes, making it ideal for operations requiring complex positioning. The motion mechanism 118 is connected to an actuator 120.

[0036] The support member 114 is connected to the electrostatic chuck contact 112 via a bias contact 116. The bias contact is made of a conductive material and provides a DC bias to the miniature electrostatic chuck. These contacts can be made of various materials, including but not limited to copper, tungsten, aluminum, and tin-based alloys. In some embodiments, the contacts may be surrounded by a dielectric material (…). Figure 1 (Not shown in the image). The support 114 can also generate another electrostatic attraction force for adsorbing the electrostatic chuck 101. In this type of embodiment, the electrostatic attraction force for adsorbing the support 114 and the electrostatic chuck 101 is temporary. Once the electrostatic attraction force stops, the support 114 can be separated from the electrostatic chuck 101. In other embodiments, the electrostatic chuck 101 and the support 114 are permanently bonded together.

[0037] The electrostatic chuck 101 is composed of multiple layers of materials. Starting from the bottom, the electrostatic chuck 101 includes a silicon layer 102, the thickness of which ranges from 50 to 500 micrometers. Above the silicon layer 102 is a bulk dielectric layer 104 of the electrostatic chuck, which can be made of various materials, including but not limited to silicon dioxide, aluminum oxide, and aluminum nitride, and has a thickness between 1 and 50 micrometers. Above the bulk dielectric layer 104 is a surface dielectric layer 106, which can be a ceramic layer made of aluminum oxide or aluminum nitride, and has a thickness ranging from 0.1 to 1 micrometer. Electrodes 108 are disposed on the surface of the bulk dielectric layer 104 and are connected to electrostatic chuck contacts 112 through electrostatic chuck through-holes. The lower part of the electrostatic chuck through-hole is a silicon via 111, and the upper part is a dielectric via 110. Electrodes 108 obtain a DC bias voltage from a power supply 115, causing the electrostatic chuck 101 to generate electrostatic force, adsorbing one or more substrates onto its surface. The substrates here can be one or more chips. In chip-to-wafer bonding processes, the chips involved are typically thin and exhibit significant warpage. Miniature electrostatic chucks can stably hold these chips, resolving the problems caused by chip warpage.

[0038] Optionally, alignment marks (also referred to as alignment structures) 107 may be provided on the surface of the surface dielectric layer 106. These alignment marks may be fabricated using a semiconductor manufacturing process that includes standard patterning and metallization steps.

[0039] The surface area of ​​the electrostatic chuck 101 can be between 4 square millimeters and 858 square millimeters, where 858 square millimeters is approximately the size of an exposure area in a photolithography process.

[0040] Figure 2 This is a block diagram of a fabrication process 200 for a micro electrostatic chuck based on semiconductor manufacturing processes. Process 200 begins at step 202, where a through-silicon via (TSV) structure is formed on a silicon substrate (e.g., a 300 mm wafer). TSV formation typically involves patterning and etching steps to create the holes. Subsequently, a liner 124 (e.g., an atomic layer deposition (ALD) oxide layer) is deposited as an insulating layer. Next, these holes are filled with copper through seed layer deposition and electroplating processes, followed by a copper chemical mechanical polishing (CMP) step to remove excess copper / seed layer from the surface. After CMP, copper pillars 122 are formed, such as… Figure 3 The cross-section 302 is shown. The liner 124 provides electrical isolation between the copper pillar 122 and the silicon wafer. The depth of the copper pillar is between 50 and 500 micrometers. In another embodiment, tungsten material can be used to fill these voids, and titanium nitride or the like can be used as an insulating layer, deposited by plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition, followed by a chemical mechanical polishing step to form the pillar.

[0041] In step 204, a plasma-enhanced chemical vapor deposition (PVDC) or chemical vapor deposition (CVD) process is used to deposit a dielectric layer 104, such as a silicon dioxide layer with a thickness between 1 and 50 micrometers. Step 206 involves forming a dielectric via structure through a patterning and etching process. The dielectric via is aligned with the silicon via, but the size of the dielectric via may be smaller than that of the silicon via to allow for alignment deviations that may occur during photolithography. During the etching of the dielectric via, it is crucial to ensure that the liner 124 is not damaged, which prevents leakage paths from forming between the pillars (e.g., copper pillars 122) formed by filling the silicon vias and the silicon wafer.

[0042] like Figure 3As shown in section 304, the metal filling the via 126 is the same as the metal filling the through-silicon via (TSV). In some embodiments, a barrier layer is formed between the metal pillar of the TSV and the bulk dielectric material. In one embodiment, after the TSV process is completed, the electrode 108 is formed by patterning and metallization processes. In another embodiment, a dual-damascene process is used to fabricate the electrode 108 simultaneously with the formation of the TSV 126. In the dual-damascene process (which is commonly used in the art), the metals required for the TSV and the electrode are first deposited, followed by polishing.

[0043] In step 208, a surface dielectric layer 106 (such as a ceramic material like alumina or aluminum nitride) is deposited. Figure 3 Section 306 is shown in the figure. This step can be performed using a variety of deposition methods, including plasma-enhanced chemical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0044] In one implementation, the Johnson-Labec effect is employed to generate electrostatic attraction. The Johnson-Labec-based electrostatic chuck utilizes this effect to enhance the electrostatic attraction between the chuck and the substrate through controlled leakage current. To achieve optimal performance, the top ceramic layer must allow weak but stable leakage to maintain the Johnson-Labec effect. This layer needs to strike a balance between dielectric properties and weak conductivity, while also possessing high thermal conductivity for heat dissipation and effective resistance to plasma-induced abrasion. Furthermore, the layer must exhibit excellent mechanical strength and chemical stability to withstand harsh semiconductor processing environments.

[0045] In electrostatic chucks based on the Johnson-Labec effect, commonly used materials for the top ceramic layer include aluminum nitride (AlN) and alumina (AlN). Aluminum nitride is often chosen due to its high thermal conductivity, which helps dissipate heat during processing. Alumina, on the other hand, possesses excellent dielectric properties and maintains durability in complex processing environments. Both materials can be engineered to achieve the controlled leakage required for the Johnson-Labec effect, striking a balance between conductivity and mechanical and chemical stability, thus enabling long-term stable use.

[0046] Electrostatic chucks based on the Johnson-Labec effect can achieve adsorption without an external charge supply. They rely on the inherent properties of the top ceramic layer to establish a stable electrostatic attraction through controlled charge leakage, thus maintaining the adsorption force. This unique characteristic distinguishes them from other types of electrostatic chucks, which require a continuous charge supply or higher voltage to achieve similar adsorption effects.

[0047] The thickness of the surface dielectric layer 106 ranges from 0.1 to 1 micrometer. The DC bias applied to the electrode ranges from 100 volts to 1000 volts.

[0048] like Figure 3 As shown in section 308, in step 210, a silicon wafer is bonded to a temporary substrate 128 for through-silicon via (TSV) exposure. The temporary substrate 128 may be a glass substrate. Step 212 includes the TSV exposure process, which comprises a sequence of overall silicon etching, typically involving polishing, wet etching, and chemical mechanical polishing. After the TSV is exposed, electrostatic chuck contacts 112 can be formed by depositing a metal layer, followed by patterning and etching processes. Alternatively, electrostatic chuck contacts can be formed by electroplating metal pads onto a pre-defined photoresist pattern.

[0049] In step 214, the bonding with the temporary substrate 128 is released, such as... Figure 3 As shown in section 310, the separation of the micro electrostatic chuck is achieved through a cutting process (using mechanical force or laser cutting). In some embodiments, plasma etching can also be used to separate the chip.

[0050] Figure 4 A schematic diagram of the surface of a miniature electrostatic chuck 402 is shown, which includes an alignment array 404. In one embodiment, the alignment array includes a two-dimensional barcode. A two-dimensional barcode is a matrix encoding that stores data in both the X and Y axes and is typically composed of small squares, lines, or dots. For a specific location on the alignment array 404, an alignment device such as a high-precision camera can capture an image of the area. The captured image is unique and can be compared with a pre-stored image set to obtain two-dimensional positional information. A chip 408 is to be placed on the electrostatic chuck 402, with alignment marks 410 on its back. The alignment device guides the electrostatic chuck 402 to move so that the chip is placed at a designated location on the surface of the electrostatic chuck. In this way, multiple chips can be precisely placed onto the surface of the electrostatic chuck.

[0051] In another embodiment of the alignment array 404, a variable critical dimension (CD) grid is employed. This CD grid comprises a two-dimensional pattern, with each region having a unique arrangement of lines and spacing. When measured by an alignment device such as a reflectance measurement sensor, the unique optical characteristics of this region provide two-dimensional positional information for guiding the movement of the micro-electrophoretic chuck during chip placement. The grid pattern can be fabricated on a surface dielectric layer using photolithography, and the variation of the critical dimension can be controlled to give different regions unique optical characteristics. The reflectance spectrum of each region can be predetermined and stored in a memory cell. The unique spectrum of each region helps to accurately determine the position of the electrostatic chuck. The alignment device combines the chip position information measured using alignment marks on the back of the chip to guide the movement of the electrostatic chuck, precisely placing the chip at a designated location on the surface of the electrostatic chuck.

[0052] Figure 5 An example 500 demonstrates the placement of multiple chips from an artificial intelligence chip system onto the surface of an electrostatic chuck 502. This AI chip system includes multiple high-bandwidth memory (HBM) units 520, a graphics processing unit (GPU) 504, input / output (I / O) interfaces 506, and a cache 508. After placing these chips at designated locations on the surface of the electrostatic chuck 502, they can be integrally bonded to an interposer. To achieve this integral chip-to-substrate bonding, the height of each chip must be maintained within specified tolerances.

Claims

1. A bonding head system for processing semiconductor chips, characterized in that, include: A miniature electrostatic chuck, manufactured using semiconductor manufacturing processes, comprises a multi-layered structure. Silicon layer; A bulk dielectric layer, disposed on the silicon layer, is used to achieve electrical insulation; A surface dielectric layer disposed on the bulk dielectric layer; A conductive path extending through the silicon layer and the bulk dielectric layer, wherein the conductive path includes through-silicon vias and through-dielectric vias to apply a DC bias to an electrode beneath the surface dielectric layer, generating an electrostatic attraction force for adsorbing one or more semiconductor chips; and A support structure is provided for detachably supporting the miniature electrostatic chuck and providing bias voltage; wherein the support structure is connected to a moving mechanism, and the miniature electrostatic chuck has a flexible size configuration.

2. The system according to claim 1, characterized in that, The moving mechanism includes a multi-axis robotic arm.

3. The system according to claim 1, characterized in that, The thickness of the bulk dielectric layer is between 1 micrometer and 50 micrometers.

4. The system according to claim 1, characterized in that, The material of the bulk dielectric layer is selected from silicon dioxide, aluminum oxide, and aluminum nitride.

5. The system according to claim 1, characterized in that, The material of the surface dielectric layer is selected from aluminum oxide and aluminum nitride.

6. The system according to claim 1, characterized in that, The surface dielectric layer is used to provide controllable leakage current and enhance electrostatic adsorption through the Johnson-Labec effect.

7. The system according to claim 1, characterized in that, The silicon vias and dielectric vias are filled with conductive material selected from copper and tungsten.

8. The system according to claim 1, characterized in that, The system also includes an alignment structure disposed on a surface dielectric layer, the alignment structure being used to precisely place the semiconductor chip in a designated location.

9. The system according to claim 1, characterized in that, The area of ​​the miniature electrostatic chuck ranges from 4 square millimeters to 858 square millimeters.

10. The system according to claim 1, characterized in that, The bulk dielectric layer and the surface dielectric layer are deposited using the following processes: plasma-enhanced chemical vapor deposition, thermochemical vapor deposition, or atomic layer deposition.

11. The system according to claim 1, characterized in that, The DC bias is provided by a rechargeable battery disposed within the support structure.

12. The system according to claim 1, characterized in that, The DC bias is provided via a moving mechanism.

13. A method for manufacturing a miniature electrostatic chuck for adsorbing semiconductor chips, characterized in that, The method includes: Forming through-silicon vias in a silicon wafer; A bulk dielectric layer is deposited on the silicon wafer; Dielectric vias and electrodes are formed on the bulk dielectric layer; A surface dielectric layer is deposited on the bulk dielectric layer; The silicon wafer is bonded to a temporary substrate; Perform silicon via exposure process and form micro electrostatic chuck contacts; Debonding the surface dielectric layer from the temporary substrate; and The separation of the miniature electrostatic chuck is achieved through a cutting process.

14. The method according to claim 13, characterized in that, The bulk dielectric layer is made of silicon dioxide, aluminum oxide, and aluminum nitride, and is deposited using plasma-enhanced chemical vapor deposition or thermochemical vapor deposition processes.

15. The method according to claim 13, characterized in that, The surface dielectric layer is made of aluminum oxide and aluminum nitride, and is deposited using plasma-enhanced chemical vapor deposition, thermochemical vapor deposition, and atomic layer deposition processes.

16. The method according to claim 13, characterized in that, The method further includes providing a controllable leakage current through the surface dielectric layer to generate electrostatic attraction through the Johnson-Labec effect.

17. The method according to claim 13, characterized in that, The silicon vias and the dielectric vias are filled with conductive materials, the conductive materials being selected from copper and tungsten; wherein, copper is deposited by electroplating, and tungsten is deposited by chemical vapor deposition or atomic layer deposition.

18. The method according to claim 17, characterized in that, The method also includes removing some of the copper or tungsten through a chemical mechanical polishing process.

19. The method according to claim 13, characterized in that, The method further includes forming an alignment structure on the surface dielectric layer.

20. The method according to claim 19, characterized in that, The alignment structure includes a two-dimensional barcode and a variable key-size grid.

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