Method of manufacturing a semiconductor die and semiconductor die integrating deep trench isolation structures and cylindrical capacitors

Abstract

The present disclosure relates to a method of manufacturing a semiconductor die and a semiconductor die integrating a deep trench isolation structure and a pillar capacitor. A semiconductor body has a front side and a back side opposite to each other. A first trench and a second trench are formed simultaneously and extend through a portion of the semiconductor body. The first trench and the second trench each have a respective sidewall and a bottom. A first insulating layer having a first thickness is formed at the sidewall and the bottom of the first trench and the second trench. Subsequently, the first insulating layer is selectively removed only from the second trench. A second insulating layer having a respective second thickness is formed at the sidewall and the bottom of the second trench, the second thickness being smaller than the first thickness. The first trench and the second trench are filled with a layer of electrically conductive material.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102024000027624, filed on December 5, 2024, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This invention relates to a method for manufacturing a semiconductor die and a semiconductor die integrating a deep trench isolation (DTI) structure and a columnar capacitor. Background Technology

[0004] Cylinder capacitors, also known as columnar capacitors, are known to be used in the prior art. Cylinder capacitors are formed through an etching process on a semiconductor substrate, which results in the formation of vertical columns within the substrate. The structure of cylinder capacitors provides higher capacitance density, thus enabling the production of devices with high capacitance. High-capacitance capacitors are required in certain applications, such as DC-DC converters.

[0005] Furthermore, substrate-integrated columnar capacitors do not require large areas to route bias signals and allow for overcoming the need to integrate capacitors at levels above the substrate (e.g., in packages or PCBs), thereby saving production costs.

[0006] However, under current technology, the concurrent fabrication of pillar capacitors and deep trench isolation (DTI) structures on the same wafer or die requires separate manufacturing steps. This leads to an overall increase in cost and manufacturing time.

[0007] Therefore, there is a need to overcome these drawbacks and provide a manufacturing method in which the formation of pillar capacitors and deep isolation trenches on the same wafer or die can be carried out with minimal cost and time.

[0008] There is a need in the art to provide a method for manufacturing semiconductor dies and semiconductor dies in order to overcome the shortcomings of the prior art. Summary of the Invention

[0009] According to the present invention, a method for manufacturing a semiconductor die and a semiconductor die are provided.

[0010] In one embodiment, a method for manufacturing a semiconductor die includes the following steps: arranging a semiconductor body having a front side and a back side, the front side and the back side being opposite to each other in a direction; forming a first trench and a second trench passing through a portion of the semiconductor body in the direction, the first trench and the second trench each having a corresponding sidewall, an opening, and a bottom; forming a first insulating layer at the sidewall and bottom of the first trench, the first insulating layer having a first thickness and extending in a physically continuous manner at the sidewall and bottom of the first trench; forming a second insulating layer at the sidewall and bottom of the second trench, the second insulating layer having a corresponding second thickness and extending in a physically continuous manner at the sidewall and bottom of the second trench, the second thickness being less than the first thickness; and filling the first trench and the second trench with a conductive material.

[0011] Specifically, a third insulating layer of a third thickness is formed simultaneously with the formation of the first insulating layer on the sidewalls and bottom of the second trench. This third insulating layer is then removed before the formation of the second insulating layer.

[0012] Specifically, the formation of the first and third insulating layers includes oxides of the semiconductor material of the thermally grown semiconductor body or deposited insulating materials.

[0013] The method further includes the steps of: removing a selective portion of the first insulating layer at the bottom of the first trench, maintaining the physical continuity of the first insulating layer at the sidewalls of the first trench, while maintaining the physical continuity of the second insulating layer at the sidewalls and bottom of the second trench.

[0014] In one embodiment, a semiconductor die includes: a semiconductor body having a front side and a back side, the front side and the back side being opposite to each other in one direction; a first deep trench isolation (DTI) structure extending in the first trench through a portion of the semiconductor body and terminating within the semiconductor body in the first trench, the first trench having corresponding sidewalls, openings, and a bottom; a cylindrical capacitor extending in the second trench through a portion of the semiconductor body in the second trench in the same direction, the second trench having corresponding sidewalls, openings, and a bottom; the first DTI structure includes: a first insulating layer extending in a physically continuous manner at the sidewalls of the first trench, and a first conductive filler extending on the first insulating layer at the sidewalls of the first trench; the cylindrical capacitor includes: a second insulating layer extending in a physically continuous manner at the sidewalls and bottom of the second trench, and a second conductive filler extending on the second insulating layer at the sidewalls and bottom of the second trench, the second conductive filler being electrically insulated from the semiconductor body through the second insulating layer; wherein the thickness of the second insulating layer is less than the corresponding thickness of the first insulating layer. Attached Figure Description

[0015] To better understand the invention, preferred embodiments thereof will now be described with reference to the accompanying drawings by way of non-limiting example only, wherein:

[0016] Figure 1-10 The manufacturing steps of a die or wafer that houses a DTI structure and a cylindrical capacitor are shown. Detailed Implementation

[0017] Figure 1-10 A cross-sectional view in a triaxial reference system with mutually orthogonal X, Y, and Z axes shows a portion of die or wafer 1 at a corresponding manufacturing step. In the following text, die 1 will be referred to without loss of generality.

[0018] refer to Figure 1 The die 1 (in single-piece form) comprises a first region 1a and a second region 1b. The first region 1a is designed to accommodate a deep trench isolation structure (also known as deep trench isolation (DTI)) at the end of the manufacturing process. The second region 1b is designed to accommodate a cylindrical capacitor or columnar capacitor at the end of the manufacturing process. As will be apparent from the following description, advantageously, the manufacturing of the deep isolation trench in region 1a and the manufacturing of the cylindrical capacitor in region 1b share several processing steps, thereby allowing for savings in both manufacturing time and cost.

[0019] Refer again Figure 1 The die 1 includes a semiconductor body 2, which includes a substrate and optionally one or more epitaxial layers (not shown in detail) on the substrate. The semiconductor body 2 is made of, for example, silicon or silicon carbide, gallium nitride, or other semiconductor materials of the semiconductor-on-insulator (SOI) type. Furthermore, the semiconductor body 2 has a first conductivity type, particularly N-type (or, alternatively, P-type), having, for example, a conductivity of 1 x 10⁻⁶. 12 and 5x10 19 atoms / cm 3 Between (including boundaries), preferably within 1x10 13 and 5x10 16 atoms / cm 3 The dopant concentration between (including the boundary).

[0020] The semiconductor body 2 has an upper or front side 2a and a lower or bottom side 2b; the upper side 2a and the lower side 2b are substantially parallel to each other and opposite to each other along the Z-axis.

[0021] A layer stack 3 extends on the upper side 2a, which, in the context of this invention, functions as a hard mask for manufacturing steps of cylindrical capacitors and deep isolation trenches. However, it is apparent that one or more layers of the stack 3 may perform further functions in other regions of the die 1, or even within the same regions 1a and 1b (in the latter portion not shown in the figures, and which is not part of this invention).

[0022] In the embodiments described and illustrated herein, the stack 3 includes: a first mask layer 3a extending on the upper surface 2a of the semiconductor body and in particular in direct contact with the semiconductor body 2; a second mask layer 3b extending on the first mask layer 3a and in particular in direct contact with the first mask layer 3a; and a third mask layer 3c extending on the second mask layer 3b and in particular in direct contact with the second mask layer 3b.

[0023] The first mask layer 3a is made of a first insulating material, such as silicon dioxide (SiO2), silicon nitride (SiN, Si2N3), tetraethoxysilane (TEOS), or an amorphous layer of carbon and polycrystalline silicon forming a so-called "ashable hard mask" (AHM); the second mask layer 3b is made of a material that can be selectively etched relative to the material of the first mask layer 3a, such as polycrystalline silicon (especially undoped polycrystalline silicon); the third mask layer 3c is made of a second insulating material, particularly different from the first insulating material, such as silicon dioxide (SiO2), tetraethoxysilane (TEOS), or silicon nitride (SiN, Si2N3).

[0024] Clearly, stack 3 may include fewer than three layers, such as only two layers (first mask layer 3a and second mask layer 3b, or second mask layer 3b and third mask layer 3c); alternatively, stack 3 may be replaced by a single layer selected from one of the aforementioned layers 3a-3c. Alternatively, stack 3 may include four or more layers.

[0025] Leading to the formation Figure 1 The steps of chip 1 are known in themselves and therefore not described in detail. Generally, and only by way of example, starting with semiconductor body 2, the formation of the first mask layer 3a includes depositing a corresponding insulating material on the upper surface 2a using CVD (chemical vapor deposition) or sputtering or PVD technology, or using an oxide thermal growth of the material of semiconductor body 2; the formation of the second mask layer 3b includes depositing a corresponding material on the first mask layer 3a using CVD or sputtering or PVD technology; the formation of the third mask layer 3c includes depositing a corresponding material on the second mask layer 3b using CVD or sputtering or PVD technology, or using an oxide thermal growth of the material of the second mask layer.

[0026] For example, stack 3 has a total thickness between 0.25 μm and 7 μm (including the boundary) along the Z-axis. The first mask layer 3a has a thickness between 10 nm and 300 nm (including the boundary); the second mask layer 3b has a thickness between 0.2 μm and 1.5 μm (including the boundary); and the third mask layer 3c has a thickness between 0.02 μm and 2 μm (including the boundary).

[0027] refer to Figure 2A first trench 6 is formed in region 1a of chip 1, and a second trench 8 is formed in region 1b.

[0028] The first trench 6 is designed to form the DTI structure at the end of the manufacturing process; the second trench 8 is designed to accommodate the cylindrical capacitor at the end of the manufacturing process.

[0029] The formation of trenches 6 and 8 includes forming a first etch mask 10 (e.g., formed by photoresist) on the stack 3 (particularly on the third insulating layer 3c). The first etch mask 10 is photolithographically patterned to form a first aperture 10a extending completely through the first etch mask 10 in a first region 1a, and a second aperture 10b extending completely through the first etch mask 10 in a second region 1b.

[0030] The first hole 10a has the same shape and size as that desired for the first trench 6 (it should be noted that the size of the trench 6 may change during manufacturing, particularly may increase, depending on subsequent processing steps). For example, the hole 10a may have a circular, rectangular, rectangular with rounded edges, elliptical, or general polygonal shape, for example, having an extension along the X-axis between 1 μm and 4 μm, and an extension along the Y-axis greater than the extension along the X-axis, selected based on design requirements (size of chip 1, extent of the area to be electrically insulated by DTI, etc.), as will be apparent to those skilled in the art. As a non-limiting example, the extension along the Y-axis of the first trench 6 is between 5 μm and 3 mm.

[0031] The second hole 10b has the same shape and size as that desired for use in the second trench 8. For example, the hole 10b may have a circular, quadrilateral, quadrilateral with rounded edges, elliptical, or general polygonal shape, for example, having extensions between 50 nm and 1.5 μm along the X-axis and between 2 μm and 3 mm along the Y-axis, and in any case, it may be selected based on the design requirements of the cylindrical capacitor (voltage rating, low-power or high-power applications, etc.), as will be apparent to those skilled in the art.

[0032] Then, using the first etch mask 10, one or more etching operations are performed to remove layers 3a-3c forming the stack 3 and a portion of the semiconductor body 2. Specifically, one or more reactive ion etching (RIE) operations are performed using suitable etching chemicals, depending on the material of the stack 3 to be removed, followed by an anisotropic deep etching, such as deep reactive ion etching (DRIE), to etch the semiconductor body 2 along the Z-axis to the desired depth. For example, the corresponding depths (along the Z-axis from the upper surface 2a) of the first trench 6 and the second trench 8 are between 10 μm and 40 μm. The corresponding depths of trenches 6 and 8 may be equal to each other (except for negligible variations due to their fabrication processes) or different from each other. For example, depending on the material removal technique used, the depths of trenches 6 and 8 may depend on the dimensions of the openings 6c and 8c of trenches 6 and 8, such that although the etching used to form trenches 6 and 8 occurs simultaneously for both trenches 6 and 8, the corresponding depths may not be equal to each other. The actual etching rate depends on the size of the trench (in the XY plane) and is higher in trenches with larger opening sizes (in the XY plane); therefore, for the same etching time, a trench with a larger opening size will be able to have a greater depth (along the Z-axis) than a trench with a smaller opening size. In the case of this disclosure, by forming an opening 6c with a size (area, in the XY plane) greater than that of the opening 8c, a first trench 6 with a greater depth (along the Z-axis in the substrate 2) than the corresponding depth of the second trench 8 will be obtained.

[0033] In an alternative embodiment, by appropriately selecting the pressure and flow rate of the etching gas, any polymer byproducts formed during the etching step are driven away from the structure being formed, so that they do not deposit on the walls of the trenches thus formed. Those skilled in the art will appreciate that the removal of any etching byproducts can also be accomplished by a cleaning step.

[0034] Thus, the first trench 6 and the second trench 8 are formed, which extend completely through the stack 3 (i.e., through the insulating layers 3a-3c) and partially through the semiconductor body 2, extending from the upper surface 2a toward the lower surface 2b and terminating within the semiconductor body 2 at a certain distance from the lower surface 2b.

[0035] The first trench 6 has a sidewall 6a, a bottom 6b, and an opening 6c. The opening 6c of the first trench 6 is located at the stack 3 (specifically, at the insulating layer 3c), while the bottom 6b is located within the semiconductor body 2.

[0036] The second trench 8 has a sidewall 8a, a bottom 8b, and an opening 8c. The opening 8c of the second trench 8 is located at the stack 3 (specifically, at the insulating layer 3c), while the bottom 8b is located within the semiconductor body 2.

[0037] The sidewalls 6a and 8a of both the first groove 6 and the second groove 8 extend substantially along the Z-axis. "Substantially" in this context, and as claimed herein, means that in an electron microscope view, the sidewalls 6a and 8a may not be perfectly aligned with the Z-axis locally, but rather extend generally along or approximately along a straight line parallel to the Z-axis. The bottoms 6b and 8b of both the first groove 6 and the second groove 8 lie in or substantially lie in the XY plane (i.e., unless there are local variations caused by the manufacturing process).

[0038] Subsequently, Figure 3 The first etch mask 10 is removed. Then, during the same growth or deposition step, the steps of forming a first insulating layer 12 in the first trench 6 and forming a second insulating layer 14 in the second trench 8 are performed. The first insulating layer 12 completely covers the sidewalls 6a and bottom 6b of the first trench 6. The second insulating layer 14 completely covers the sidewalls 8a and bottom 8b of the second trench 8. The first and second insulating layers can be grown by a thermal oxidation process of the semiconductor body 2 through the exposed portions of the trenches 6, 8 (in which case the insulating layers 12, 14 are made of an oxide of the semiconductor body material, such as SiO2), or can be deposited by CVD or sputtering or PVD techniques (e.g., by depositing or growing SiO2, TEOS, SiN or other insulating materials).

[0039] The first insulating layer 12 and the second insulating layer 14 have corresponding first thicknesses t1 and t2, which are substantially equal to each other (unless there are insignificant variations due to their formation process), for example, between 0.1 μm and 2 μm.

[0040] In trenches 6 and 8, the thicknesses t1 and t2 at the sidewalls 6a and 8a are measured along the X-axis, while the thicknesses t1 and t2 at the bottoms 6b and 8b are measured along the Z-axis. Based on the selected process for forming insulating layers 12 and 14, the corresponding thicknesses t1 and t2 at the sidewalls 6a and 8a may differ from the corresponding thicknesses t1 and t2 at the bottoms 6b and 8b. In one embodiment, the first insulating layer 12 and the second insulating layer 14 have uniform thicknesses t1 and t2 along the sidewalls 6a and 8a and at the bottoms 6b and 8b.

[0041] Subsequently, Figure 4The method continues with a step of forming a second etch mask 20 by depositing a suitable material. For example, a polymeric material (particularly a photoresist) is deposited over the stack 3 and within the first trench 6 and the second trench 8. According to a non-limiting aspect of the invention, the formation of the second etch mask 20 includes completely filling at least the first trench 6 with photoresist. The second etch mask 20 also completely or partially fills the second trench 8. This step causes a photoresist layer to also be formed over the die 1 (i.e., over the stack 3). This layer can be thinned if necessary and appropriate.

[0042] The method then proceeds with a patterning step for the second etch mask 20 to completely remove it from the second region 1b of the die 1, but not from the first region 1a. For example, in the case of a negative photoresist, an exposure step for the second etch mask 20 is envisioned to protect the second region 1b so that the portion of the second etch mask 20 extending above the first trench 6 in the first region 1a is fully reticulated. In the case of a positive photoresist, the opposite is true.

[0043] The method then continues with an etching step (e.g., immersion in a solvent solution) to remove the second etch mask 20 from the second region 1b and generally from the surface of the die 1, except for the first region 1a that accommodates the first trench 6. Thus, the second etch mask 20 can be removed from the surface of the die 1 while the portion of the second etch mask 20 filling the first trench 6 remains unchanged.

[0044] Then, Figure 5 The third mask layer 3c is etched, for example by anisotropic dry etching (which is selective relative to the previously deposited oxide), and in particular, in the case of TEOS, by using CF4 / CHF3-based etching chemicals via RIE plasma. Figure 5 The etching stops at the surface of the second mask layer 3b, which in this case serves as an etch stop layer. Therefore, the etching of the third mask layer 3c is a masked etching, wherein the second etch mask 20 has previously been patterned to protect the first trench 6. Since the second etch mask 20 is absent in the second region 1b at the second trench 8 as described above, Figure 5The etching completely removes the third mask layer 3c in the second region 1b (particularly above the second trench 8). Furthermore, since the second insulating layer 14 extending in the second trench 8 is made of silicon dioxide, the etching simultaneously and completely removes the second insulating layer 14, thereby exposing the semiconductor body 2 at the sidewalls 8a and bottom 8b of the second trench 14. In cases where the third mask layer 3c and the second insulating layer 14 are made of two materials that cannot be removed with the same etching chemical, two consecutive etchings are performed using appropriate etching chemicals.

[0045] Then, Figure 6 The second etch mask 20 is completely removed from the die 1, that is, completely removed from region 1a and from the first trench 6. The first insulating layer 12 remains in the first trench 6, completely covering and physically continuous with the sidewalls 6a and bottom 6b of the first trench 6. The third mask layer 3c is also retained above the die 1.

[0046] Then, refer to again Figure 6 The process involves forming a third insulating layer 24 within the first trench 6 and a fourth insulating layer 26 within the second trench 8. This process includes thermal growth of an oxide of the semiconductor body 2 material (e.g., silicon dioxide-SiO2) or deposition of an insulating material, for example by CVD, sputtering, or ALD. The third insulating layer 24 is additional relative to the first insulating layer 12 and specifically covers the exposed surface of the first insulating layer 12 in the first trench 6. The fourth insulating layer 26 extends along the sidewalls 8a and bottom 8b of the second trench 8 in a physically continuous manner, completely covering the sidewalls 8a and bottom 8b of the second trench 8. Therefore, within the second trench 8, the semiconductor body 2 is completely electrically insulated by the fourth insulating layer 26.

[0047] The third insulating layer 24 has a thickness t3, which is less than the thickness t1 of the first insulating layer 12, along the X-axis at the sidewall 6a and along the Z-axis at the bottom 6b. Specifically, the thickness t3 along the X-axis at the sidewall 6a and along the Z-axis at the bottom 6b is included between 1 nm and 30 nm (inclusive). The value of t3 depends in any case on the desired withstand voltage; the values ​​mentioned refer to examples where the withstand voltage range varies between 1 V and 10 V. The thickness t3 along the X-axis at the sidewall 6a can have the same or different value as the thickness t3 along the Z-axis at the bottom 6b.

[0048] The fourth insulating layer 26 has a thickness t4, which is less than the thickness t2 of the second insulating layer 14, along the X-axis at the sidewall 8a and along the Z-axis at the bottom 8b. Specifically, the thickness t4 along the X-axis at the sidewall 8a and along the Z-axis at the bottom 8b is included between 1 nm and 30 nm (inclusive). As previously observed with respect to t3, the value of t4 also depends on the desired withstand voltage; the values ​​mentioned refer to examples where the withstand voltage range varies between 1 V and 10 V. The thickness t4 along the X-axis at the sidewall 8a can have the same or different value as the thickness t4 along the Z-axis at the bottom 8b.

[0049] In a non-limiting embodiment, the values ​​of t3 and t4 are equal to each other, depending on the formation process of the third insulating layer 24 and the fourth insulating layer 26. In a further non-limiting embodiment, the values ​​of t3 and t4 are different from each other, depending on the formation process of the third insulating layer 24 and the fourth insulating layer 26.

[0050] The following is for reference. Figure 7 and Figure 8 The described steps involve removing insulating layers 12 and 24 from the bottom 6b of trench 6. Figure 7 and Figure 8 These steps are optional, as the removal of insulation layers 12 and 24 from the bottom 6b of trench 6 can be omitted.

[0051] Subsequently, as Figure 7 As shown, the step of forming the third etch mask 30 is performed on the die 1 by depositing a suitable material. For example, a polymeric material (particularly a photoresist) is deposited over the die 1 and within the first trench 6 and the second trench 8. According to a non-limiting aspect, the formation of the third etch mask 30 (e.g., by deposition of the photoresist) includes at least the complete filling of the second trench 8. The third etch mask 30 also completely or partially fills the first trench 6. This step results in the formation of a thick photoresist layer also over the third mask layer 3c in the first region 1a and the second mask layer 3b in the second region 1b. If necessary and appropriate, this thick photoresist layer can be partially removed to reduce its thickness.

[0052] The method then proceeds with a patterning step of the third etch mask 30 to completely remove it from the first region 1a of the die 1, but not from the second region 1b. For example, in the case of a negative photoresist, an exposure step of the third etch mask 30 is envisioned to protect the first region 1a so that the photoresist layer extending in the second region 1b (above the second trench 8) is fully crosslinked. In the case of a positive photoresist, the opposite is true.

[0053] The method then continues with an etching step (e.g., immersion in a solvent solution) to remove the mask layer 30 from the first region 1a and generally from the surface of the die 1, except for the second region 1b that houses the second trench 8. Thus, the third etch mask 30 can be removed from the surface of the die 1, while the portion of the third etch mask 30 filling the second trench 8 remains unchanged.

[0054] Then, as Figure 8 As shown, the third mask layer 3c is etched by anisotropic dry etching, for example, in the case of TEOS, using CF4 / CHF3-based etching chemicals via RIE plasma, to completely remove the third mask layer 3c from the first region 1a. The anisotropic etching is performed along the Z-axis. In this same etching step, according to one aspect of the invention, the first insulating layer 12 and the third insulating layer 24 are also etched and partially removed. In fact, in the case where the first insulating layer 12 and the third insulating layer 24 are made of silicon oxide and the third mask layer is made of TEOS or silicon oxide, the etching chemicals used to remove the third mask layer 3c also remove the first insulating layer 12 and the third insulating layer 24. Since the etching is anisotropic as described above, the first insulating layer 12 and the third insulating layer 24 are removed only specifically from the bottom 6b of the first trench 6 and not from its sidewalls 6a.

[0055] Etching continues until the insulating layers 12 and 24 on the third mask layer 3c and the bottom 6b of the first trench 6 are completely removed, so that the corresponding portions of the semiconductor body 2 are exposed through the bottom 6b of the trench 6.

[0056] As previously described, in one embodiment, the removal of insulating layers 12 and 14 from the bottom 6c of the first trench 6 may be omitted. In this case, insulating layers 12 and 24 electrically insulate the interior of the first trench 6 from the substrate 2.

[0057] It should be noted that the possible partial or complete removal of the third mask layer 24 and / or the partial removal of the underlying first mask layer 12 does not impair the structure. Such removal is possible, though perhaps not desirable, and may be a result of the non-optimal anisotropy of the aforementioned etching (which, for example, preferentially but not exclusively, proceeds along the Z-axis).

[0058] Figure 8 The etching stops on the surface of the second mask layer 3b, which in this case serves as an etch stop layer.

[0059] Then, as Figure 9As shown, the third etch mask 30 is completely removed from the die 1, that is, completely removed from the second region 1b and from the second trench 8. The fourth insulating layer 26 remains in the second trench 8, completely covering and physically continuous with respect to the sidewalls 8a and bottom 8b of the second trench 8.

[0060] Finally, on die 1, and particularly within the first trench 6 and the second trench 8, a conductive layer 32 is formed (e.g., a deposition step), which is, for example, made of metal or doped polysilicon (e.g., having P-type conductivity and approximately 10). 18 Up to 10 21 at / cm 3 The conductive layer 32 is made of metal or N-type doped polysilicon. When the substrate 2 is P-type doped, the conductive layer 32 is made of metal or N-type doped polysilicon.

[0061] The conductive layer 32 extends in the first trench 6. Figure 10 The conductive layer 32 extends from the bottom 6b to the semiconductor body 2 and into electrical contact with it; more specifically, the conductive layer 32 extends electrically continuously between the semiconductor body 2 at the bottom 6b and the opening 6c of the first trench 6. The conductive layer 32 may completely or only partially fill the first trench 6 (while ensuring electrical contact with the semiconductor body 2 at the bottom 6b and electrical continuity up to the opening 6c).

[0062] The conductive layer 32 also extends in the second trench 8. Figure 10 The portion 36b) completely covers the fourth insulating layer 26 at the sidewalls 8a and bottom 8b of the second trench 8; more specifically, the conductive layer 32 extends electrically continuously over the entire extension of the fourth insulating layer 26 at both the sidewalls 8a and bottom 8b until it reaches the opening 8c of the second trench 8.

[0063] The conductive layer 32 may completely or only partially fill the second trench 8 (e.g., extending in a physically and electrically continuous manner along the sidewalls 8a and bottom 8b). A portion 36a of the conductive layer 32 extending in the first trench 6 is electrically insulated from a portion 36b of the conductive layer 32 extending in the second trench 8. This electrical insulation is achieved by appropriately patterning the conductive layer 32 above the die 1 to form conductive paths 38a, 38b that are separated from each other.

[0064] In the case of a cylindrical capacitor formed in the second trench 8, it should be noted that the first electrode of the capacitor is formed by the semiconductor body 2, and the second electrode of the capacitor is formed by the conductive layer 32 in the second trench 8.

[0065] In one embodiment, such as Figure 10As shown, the conductive layer 32 on the second mask layer 3b above the die 1 is not completely removed. Specifically, the conductive layer 32 above the die 1 is patterned to define at least a first conductive path 38a, which electrically contacts a portion 36a of the conductive layer 32 within the first trench 6, and to define at least a second conductive path 38b, which electrically contacts a portion 36b of the conductive layer 32 within the second trench 8. Electrical connections 40, 41 (e.g., wire bonding, solder bonding, etc.) contacting the first conductive path 38a and the second conductive path 38b are conceivable. Alternatively, in the case of an integrated circuit, the method continues with connections made via contacts at a first available wiring metal layer.

[0066] In another embodiment, the conductive layer 32 does not extend above the die 1. In this case, electrical connections to corresponding portions of the conductive layer 32 in the first trench 6 and the second trench 8 are provided by wire bonding or by solder balls or other elements suitable for forming direct electrical contact with the conductive material within the respective trenches 6, 8. Alternatively, in the case of an integrated circuit, the method continues by making connections via contacts at a first available wiring metal layer.

[0067] Thus, a DTI in region 1a and a cylindrical capacitor in region 1b of the same die 1 are formed. An electrically insulating ring that completely surrounds the cylindrical capacitor can be formed in a manner not shown in the figure (e.g., by implanting a P-type dopant, or by forming a deep trench, or by alternating P and N implantations).

[0068] Finally, it should be understood that modifications and variations can be made to the content described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

[0069] According to another embodiment, in forming trenches 6 and 8 Figure 2 After the steps, perform masking (similar to...). Figure 8 The mask 30) is formed to fill and protect the second trench 8. Then, according to the already referenced Figure 3 The described process performs the step of forming the first insulating layer 12 in the first trench 6. In this embodiment, since the second trench 8 is protected, the second insulating layer 14 is not formed and therefore does not need to be removed. The method then continues. Figure 6-10 The steps that have already been described.

[0070] According to another embodiment, the first trench 6 and the second trench 8 are not as referenced. Figure 2The trenches are not formed simultaneously as described, but rather in separate steps. For example, a first trench 6 is formed (according to the previously described process), and a first insulating layer 12 is formed in the absence of a second trench 8, as already described. After the formation of the first insulating layer 12, the second trench 8 is formed (according to the previously described process). The method then continues. Figure 6-10 The steps that have already been described.

[0071] These alternative embodiments allow for the avoidance of the formation step of the second insulating layer 14 in the second trench 8 and the subsequent removal of the second insulating layer 14.

[0072] Furthermore, the embodiments described herein can be extended to the fabrication of any type of trench-gate vertical conduction device, such as, but not limited to, VDMOS transistors or trench-gate power MOSFET devices. In this context, the steps described for fabricating the DTI structure are used to form the trench gate.

[0073] Furthermore, multiple DTI structures and / or multiple cylindrical capacitors can be fabricated on the same die 1. The same structure can also be used to insulate planar or non-planar components such as lateral power MOSFETs, CMOS, BJTs, JFETs, etc.

Claims

1. A method for manufacturing a semiconductor die, comprising the steps of: A semiconductor body having a front side and a back side is arranged, the front side and the back side being opposite to each other in one direction; A first trench and a second trench are formed extending from the front side into the semiconductor body along the direction therein, each having a corresponding opening, sidewall, and bottom; A first insulating layer is formed at the sidewalls and bottom of the first trench, the first insulating layer having a first thickness and extending in a physically continuous manner at the sidewalls and bottom of the first trench; A second insulating layer is formed at the sidewalls and bottom of the second trench, the second insulating layer having a corresponding second thickness and extending in a physically continuous manner at the sidewalls and bottom of the second trench; Wherein, the second thickness is less than the first thickness; and The first and second trenches are filled with conductive material.

2. The method according to claim 1, further comprising: A hard mask is formed extending on the front side of the semiconductor substrate; The steps of forming the first trench and the second trench include forming corresponding first holes and second holes in a hard mask until reaching the front side, and performing deep etching of the semiconductor body into the front side along the direction at the first holes and the second holes.

3. The method according to claim 1, further comprising: Simultaneously with the step of forming the first insulating layer, a third insulating layer with a third thickness is formed at the sidewalls and bottom of the second trench.

4. The method according to claim 3, wherein, The formation of the first insulating layer and the third insulating layer includes one of the following: an oxide of the semiconductor material of the thermally grown semiconductor body or a deposited insulating material.

5. The method of claim 3, further comprising the step of selectively removing the third insulating layer from the second trench while retaining the first insulating layer in the first trench.

6. The method according to claim 5, wherein, Selective removal includes the following steps: A first etching mask is formed within the first trench and the second trench; and The first etch mask is completely removed from the second trench to fully expose the second insulating layer, while the first etch mask remains in the first trench.

7. The method according to claim 3, further comprising: Simultaneously with the step of forming the second insulating layer, a step of forming a fourth insulating layer at the sidewalls and bottom of the first trench, wherein the fourth insulating layer has a corresponding fourth thickness that is less than the first thickness and the third thickness.

8. The method according to claim 7, wherein, Forming the second and fourth insulating layers includes, after the step of selectively removing the third insulating layer from the second trench, one of the following: thermally growing an oxide of the semiconductor material of the semiconductor body or depositing an insulating material in the first and second trenches.

9. The method according to claim 3, further comprising: A hard mask is formed extending on the front side of the semiconductor substrate; The hard mask includes: a first mask layer on the front side of the semiconductor body, a second mask layer on the first mask layer, and a third mask layer on the second mask layer; The first and third mask layers are made of corresponding insulating materials, and the second mask layer is made of a material that can be selectively removed relative to the material of the third mask layer; The third insulating layer is selectively removed from the second trench while the first insulating layer in the first trench is retained; Simultaneously with the step of selectively removing the third insulating layer from the second trench, a step of using the second mask layer as an etch stop layer to remove a selective portion of the third mask layer at the opening of the second trench.

10. The method according to claim 1, wherein, The first thickness is included between 0.1 μm and 2 μm, and the second thickness is included between 1 nm and 30 nm.

11. The method of claim 1, further comprising the steps of: removing a selective portion of the first insulating layer at the bottom of the first trench, maintaining the physical continuity of the first insulating layer at the sidewalls of the first trench, while maintaining the physical continuity of the second insulating layer at the sidewalls and bottom of the second trench.

12. The method according to claim 11, wherein, Removing a selective portion of the first insulating layer at the bottom of the first trench includes the following steps: A second etching mask is formed within the first and second trenches; Completely remove the second etch mask from the first trench while retaining the second etch mask within the second trench; and Anisotropic etching with a preferred etching direction along the direction is performed until the first insulating layer is completely removed at the bottom of the first trench.

13. The method of claim 11, further comprising: A hard mask is formed extending on the front side of the semiconductor substrate; The hard mask includes: a first mask layer on the front side of the semiconductor body, a second mask layer on the first mask layer, and a third mask layer on the second mask layer; Wherein, the first mask layer and the third mask layer are made of corresponding insulating materials, and the second mask layer is made of a material that can be selectively removed relative to the material of the third mask layer; and Simultaneously with the step of removing a selective portion of the first insulating layer at the bottom of the first trench, a second mask layer is used as an etch stop layer to remove a selective portion of the third mask layer at the opening of the first trench.

14. The method according to claim 1, wherein, The semiconductor body has a first conductivity, and wherein the conductive material filling the first and second trenches comprises doped polycrystalline silicon having a second conductivity opposite to the first conductivity.

15. A semiconductor die, comprising: A semiconductor body having a front side and a back side, the front side and the back side being opposite to each other along one direction; A first deep trench isolation (DTI) structure extends in the first trench through a first portion of the semiconductor body and terminates within the semiconductor body along the direction described above. The first trench has an opening, sidewalls, and a bottom. A cylindrical capacitor extends along the direction through a second portion of a semiconductor body in a second trench, the second trench having an opening, sidewalls, and a bottom; The first DTI structure includes: a first insulating layer extending in a physically continuous manner along the sidewalls of the first trench, and a first conductive filler extending on the first insulating layer along the sidewalls of the first trench; and The cylindrical capacitor includes: a second insulating layer extending in a physically continuous manner at the sidewalls and bottom of the second trench, and a second conductive filler extending on the second insulating layer at the sidewalls and bottom of the second trench; Wherein, the second conductive filler is electrically insulated from the semiconductor body through the second insulating layer; and The thickness of the second insulating layer is less than the corresponding thickness of the first insulating layer.

16. The semiconductor die according to claim 15, wherein, The semiconductor body has a first conductivity, and wherein the first conductive filler and the second conductive filler comprise doped polycrystalline silicon having a second conductivity opposite to the first conductivity.

17. The semiconductor die according to claim 15, wherein, The thickness of the first insulating layer is between 0.1 μm and 2 μm, and the thickness of the second insulating layer is between 1 nm and 30 nm.

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