A co-wos package architecture and a design method thereof for improving the yield of a layer and the integrity of a power supply in silicon

Abstract

The application discloses a CoWoS packaging architecture and a design method for improving the yield of a middle layer of silicon and power integrity, and is based on a CoWoS-L packaging architecture. An embedded chip is placed directly below a main chip power module, a DTC capacitor in the embedded chip is used to provide filtering for a large-current power domain, and power integrity design is optimized. An embedded chip for high-density interconnection wiring is placed directly below a chip interconnection module and a storage module, and super-large bandwidth is achieved. A conventional RDL wiring layer is used below other low-speed signals or low-power supplies, reliability risks and cost increases caused by using a whole silicon adapter plate for all modules of a chip are avoided, sufficient layout and wiring channels are provided for key modules, maximum utilization of the silicon adapter plate is achieved, and an optimal solution for cost and performance is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a CoWoS packaging architecture and its design method for improving silicon layer yield and power integrity. Background Technology

[0002] As Moore's Law approaches its physical limits, improvements in chip performance increasingly depend on breakthroughs in advanced packaging technologies. The CoWoS-S packaging solution, with silicon interposer as its core, has become the mainstream technology path for high-bandwidth memory (HBM) integration and multi-chip heterogeneous interconnection due to its advantages of high-density wiring and through-silicon vias (TSVs). It is widely used in high-end computing chip products such as NVIDIA GPUs and AMD accelerators.

[0003] Driven by the rapid evolution of AI technology, high-performance computing chips are developing towards ultra-large size (>5000mm²) and ultra-high power consumption (>2000W), with total computing power requirements exceeding 200 TOPS (INT8) and inter-core communication latency requirements below 10ns. This places stringent demands on the interconnect bandwidth, power stability, and mass production capabilities of packaging technologies. Traditional CoWoS-S packaging solutions achieve intermediate interconnection between the chip and the substrate through a single silicon interposer board, utilizing the excellent electrical properties of silicon to ensure high-bandwidth signal transmission. The size of these silicon interposer boards has expanded from the early 800mm² to over 2600mm². However, as chip size and power consumption further exceed existing technological thresholds, the inherent limitations of this solution become increasingly apparent, making it difficult to meet the demands of industrial applications.

[0004] In existing technologies, the packaging of ultra-large chips still uses a monolithic silicon interposer design. When the area of ​​the silicon interposer exceeds three times the area of ​​the photomask (approximately 2600 mm²), the manufacturing process requires multiple splicing exposure processes. This not only significantly increases the technical complexity of photolithography, etching, and other processes but also leads to an exponential increase in the probability of defects in the silicon interposer. Furthermore, large-size silicon interposers have a significant difference in coefficient of thermal expansion (CTE) compared to materials such as underfill and molding compound. This difference makes them prone to structural damage such as warping and cracking during packaging reflow soldering and high-temperature operating environments, significantly increasing reliability risks. In addition, the high material and processing costs of the monolithic large-size silicon interposer further drive up the packaging cost per chip.

[0005] High-power chips can operate at currents exceeding 200A, placing extremely high demands on the low-impedance design of the power distribution network (PDN). The equivalent impedance of the PDN must be controlled at the milliohm level across the DC to several GHz frequency bands to suppress voltage noise. Existing all-silicon adapter board solutions are limited by the structural characteristics of the silicon interposer. Parasitic parameters such as bonding wires and pin inductance (1~5nH) result in a high equivalent impedance of the PDN, failing to meet the low-impedance power supply requirements of high-current power domains. According to the voltage noise formula, when a chip experiences transient current changes of tens of amperes / microseconds, parasitic inductance can cause significant voltage drops and ripple (peak-to-peak values ​​up to 70mV), leading to timing errors and logic errors in the internal transistors, severely impacting computing performance and operational stability. Furthermore, existing solutions lack decoupling structures such as deep trench capacitors (DTCs), resulting in insufficient suppression of high-frequency noise, further exacerbating power integrity issues.

[0006] Existing CoWoS-S packaging solutions, when handling ultra-large chips, suffer from limitations such as silicon interposer manufacturing defects, chip-interposer bonding deviations, and difficulties in the underfill process, resulting in an overall packaging yield of only around 70%. This low yield leads to a significant increase in unit product manufacturing costs, falling far short of the industrialization requirement of a mass production pass rate of ≥99.5% for high-performance computing chips. Consequently, it cannot support the large-scale deployment needs of scenarios such as AI computing centers and industrial-grade high-performance computing.

[0007] In summary, existing CoWoS-S packaging solutions suffer from key technical challenges in the application of ultra-large size, ultra-high power consumption high-performance computing chips, including high manufacturing costs, significant reliability risks, insufficient power integrity, and low packaging yield. Therefore, there is an urgent need to propose a technical solution that can synergistically optimize the silicon interposer structure design and power distribution network impedance characteristics. This solution should significantly improve packaging yield and power integrity while ensuring high-bandwidth interconnects, reducing manufacturing costs and reliability risks, overcoming existing technical bottlenecks, and promoting the industrialization of high-performance computing chips. Summary of the Invention

[0008] The purpose of this invention is to provide a packaging impedance network design method to improve the yield and power integrity of silicon mid-layers, aiming to solve the problems of low yield, high cost and poor power integrity of existing CoWoS-S packages.

[0009] This invention provides a CoWoS packaging architecture that improves silicon layer yield and power integrity, comprising: The main chip includes a large power module, a storage module, and a chip interconnect module; Embedded chips are located below the key modules of the main chip; The redistribution layer is configured to connect the various chip circuits. The substrate, located at the bottom of the entire package structure, is configured to carry all upper components and provide paths for power distribution and signal transmission.

[0010] In one embodiment of the present invention, HBM is also included, which is disposed on the left and right sides of the main chip to provide memory access for the main chip.

[0011] In one embodiment of the present invention, microbumps are also included, which are disposed on the bottom of the main chip and HBM and directly connected to the redistribution layer below, for realizing electrical interconnection between the main chip and HBM and the redistribution layer, and transmitting signals and power.

[0012] In one embodiment of the present invention, copper pillars are also included, disposed around the embedded chip, for realizing a vertical electrical connection between the redistribution layer and the substrate, and for transmitting power and signals.

[0013] In one embodiment of the present invention, a decoupling capacitor is also included, disposed on the surface of the substrate, near the embedded chip, for filtering out power supply noise, providing power supply to the chip, and reducing voltage fluctuations.

[0014] In one embodiment of the present invention, flip-chip bonding bumps are also included for flip-chip bonding the entire module to the substrate to achieve electrical interconnection between the encapsulation layer and the substrate.

[0015] In one embodiment of the invention, solder balls are also included, which are configured as connection points between the package and the external PCB.

[0016] In one embodiment of the present invention, the embedded chip located below the main chip power module has an integrated DTC capacitor.

[0017] This invention also provides a CoWoS packaging architecture design method to improve silicon layer yield and power integrity, comprising: Determine the size and layout of the interfaces of the key modules of the main chip, including the power supply module, the storage module and the chip interconnect module; Create a CoWoS packaging architecture layout diagram to clarify the size and location of each embedded chip; An embedded chip is placed directly below the key module of the main chip. Arrange redistribution layers to connect the various chip circuits; Simulations were performed to obtain the impedance distribution network under different CoWoS package architecture layouts. The optimal CoWoS packaging architecture layout was obtained through comparison.

[0018] In one embodiment of the present invention, the embedded chip is implemented using a silicon interposer process or an interposer chip process, and is selectively distributed only below key modules. It is configured to perform the following operations: The large power module is filtered by a built-in DTC capacitor; or Provides silicon-based interconnect channels for storage modules and chip interconnect modules.

[0019] The present invention has the following beneficial effects: (1) By selectively placing EBDie (embedded chip), the packaging cost is significantly reduced, while avoiding the reliability risks associated with all-silicon adapter boards.

[0020] (2) Integrating DTC capacitors (deep trench capacitors) in critical areas effectively optimizes power integrity design, reduces power noise, and improves chip operation stability.

[0021] (3) Significantly improved packaging yield, from 70% in traditional solutions to over 95%, meeting the needs of large-scale mass production.

[0022] (4) It can support AI chip packaging with ultra-large size and ultra-high power consumption, which expands the application scenarios of CoWoS-L packaging. Attached Figure Description

[0023] Figure 1 This is a longitudinal section view of the CoWoS-L package provided in an embodiment of the present invention; Figure 2 An exploded view of the CoWoS-L packaging structure provided in an embodiment of the present invention; Figure 3 This is a diagram showing the layout of key module interfaces of the main chip provided in an embodiment of the present invention. Figure 4 This is a layout diagram of the CoWoS-L packaging architecture provided in an embodiment of the present invention; Figure 5 A CoWoS packaged PDN curve diagram provided for an embodiment of the present invention; Figure 6 This is a flowchart of a method provided in an embodiment of the present invention. Detailed Implementation

[0024] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0025] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0026] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0027] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0028] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0029] Figure 1 This is a longitudinal section view of the CoWoS-L package provided in an embodiment of the present invention.

[0030] Figure 2 An exploded view of the CoWoS-L packaging structure provided in an embodiment of the present invention.

[0031] like Figure 1 and Figure 2 As shown, in this embodiment, the CoWoS-L packaging structure includes: Main chip 10, located at the top center of the exploded view, is the core computing unit of the entire package (similar to the GPU core of an AI chip), used to perform the main computing tasks. Figure 3 As shown, the key modules of the main chip include a large power supply module 11, a storage module 12, and a chip interconnect module 13.

[0032] HBM20 (High Bandwidth Memory) is located on the left and right sides of the main chip 10, belonging to the same top-level chip layer as the main chip 10. HBM20 provides ultra-high bandwidth memory access for the main chip 10 and is a key storage component for AI / high-performance computing.

[0033] Microbumps 30 are located at the bottom of the top-level chips (main chip 10, HBM20) and are directly connected to the redistribution layer 40 below. They are used to realize high-density electrical interconnection between the main chip 10, HBM20 and the redistribution layer 40, and to transmit signals and power.

[0034] The redistribution layer 40 is located below the microbumps 30 and embedded above the metal wiring layer (the layer with fine lines in the figure) on the chip 50. It is used to redistribute the chip's I / O signals, realize the interconnection between different chips, and provide a transmission path for power / signal.

[0035] Embedded chip 50, located in the intermediate layer above RDL microbumps 30 and substrate 90, acts as a "silicon bridge" to achieve ultra-high density, low-latency interconnection between SoC and HBM, and is a core innovative component of CoWoS-L. Embedded chips 50 for different purposes are placed directly below key modules of the main chip 10. For example, for the large power module 11, an embedded chip 50 with a built-in large-capacity DTC capacitor is placed below it for power integrity considerations, optimizing the PDN impedance curve of this power domain and suppressing power noise. For the memory module 12 and the chip interconnect module 13, the embedded chip 50 mainly provides silicon-based interconnect channels (TSVs) with a minimum linewidth and spacing of 0.8µm, only 1 / 10 of the 8µm width of the redistribution layer 40 traces, significantly increasing wiring density. Under the same surface width, the signal bandwidth reaches 10 times that of the original redistribution layer 40.

[0036] Copper pillars 60, located around the embedded chip 50, are vertical metal pillar structures that penetrate the intermediate layer. They are used to achieve vertical electrical connection between the redistribution layer 40 and the flip-chip bonding bumps 80 below, and to transmit power and signals.

[0037] Decoupling capacitor 70 is disposed on the surface of substrate 90, near the area where chip 50 is embedded. It is used to filter out power supply noise, provide a stable power supply to the chip, and reduce voltage fluctuations.

[0038] Flip-chip bonding bumps 80 are connection bumps located between the intermediate layer (embedded chip 50, copper pillars 60, etc.) and the underlying substrate 90. They are used to flip-chip bond the entire module of the intermediate layer to the organic substrate, achieving electrical interconnection between the packaging layer and the substrate.

[0039] The substrate 90 is located at the bottom of the entire package structure as a carrier layer. It is used to carry all upper components, provide power distribution and signal transmission paths, and is connected to the external PCB board via bottom solder balls 100.

[0040] Solder balls 100 are located on the bottom layer of substrate 90 and serve as connection points between the package and the external PCB (printed circuit board) to achieve electrical connection between the entire chip system and the motherboard.

[0041] Figure 6 This is a flowchart of a method provided in an embodiment of the present invention.

[0042] like Figure 6 As shown, in this embodiment, the CoWoS packaging architecture design method includes: Step S1: Confirm the size and layout of the interfaces of the key modules of the main chip. The key modules include the power supply module, the storage module and the chip interconnect module.

[0043] Step S2: Determine the size and location of the embedded chips. Place embedded chips for different purposes directly below key modules. For example, in a large power module, for power integrity considerations, an embedded chip with a large-capacity DTC capacitor is needed to optimize the PDN impedance curve of this power domain and suppress power noise. For memory and chip interconnect modules, the embedded chips primarily provide silicon-based interconnect channels. With a minimum linewidth and spacing of 0.8µm, only 1 / 10 of the 8µm width of the redistribution layer traces, the wiring density is greatly increased. Under the same surface width, the signal bandwidth reaches 10 times that of the original redistribution layer.

[0044] Step S3: Create the CoWoS-L package architecture layout diagram. (e.g.) Figure 4 As shown, the size and position of each embedded chip are clearly defined. There are a total of 4 top-level chips and 4 embedded chips, which can realize a flexible, cost-effective packaging layout scheme.

[0045] Step S4: Power supply PDN impedance simulation comparison. For example... Figure 5 As shown, the impedance distribution networks (PDNs, Power Distribution Networks) for the three schemes—CoWoS-S without DTC capacitors, CoWoS-S with DTC capacitors, and CoWoS-L with DTC capacitors—are obtained, corresponding to curves 1 to 3, respectively. Curve 1 exhibits dual-impedance resonant points at 25.7MHz / 3.66mOhm and 51.3MHz / 2.57mOhm. Curve 2, based on the CoWoS-S package, adds a DTC capacitor within the silicon interposer, shifting the impedance frequency to lower frequencies and significantly reducing the impedance peak, with a maximum point of 23.4MHz / 1.65mOhm. Curve 3 goes a step further, splitting the entire silicon adapter board into multiple embedded chips. The capacitance value increases by 30% from 62uF to 80.6uF, the impedance frequency is reduced from two resonant peaks to a single resonant peak, and the resonant frequency is reduced to 7.85MHz, a reduction of 67%. The resonant peak value is reduced to 792uOhm, a reduction of 52%, making it the optimal power supply design.

[0046] Step S5: Obtain the optimal CoWoS-L packaging solution.

[0047] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A CoWoS packaging architecture for improving silicon layer yield and power integrity, characterized in that, include: The main chip includes a large power module, a storage module, and a chip interconnect module; Embedded chips are located below the key modules of the main chip; The redistribution layer is configured to connect the various chip circuits. The substrate, located at the bottom of the entire package structure, is configured to carry all upper components and provide paths for power distribution and signal transmission.

2. The packaging structure according to claim 1, characterized in that, It also includes HBM, which is located on the left and right sides of the main chip to provide memory access for the main chip.

3. The packaging structure according to claim 1, characterized in that, It also includes microbumps, which are located on the bottom of the main chip and HBM, directly connecting to the redistribution layer below, to enable electrical interconnection between the main chip and HBM and the redistribution layer, and to transmit signals and power.

4. The packaging structure according to claim 1, characterized in that, It also includes copper pillars, which are placed around the embedded chip to enable vertical electrical connections between the redistribution layer and the substrate for transmitting power and signals.

5. The packaging structure according to claim 1, characterized in that, It also includes decoupling capacitors, which are placed on the surface of the substrate, near the embedded chip, to filter out power supply noise, provide power to the chip, and reduce voltage fluctuations.

6. The packaging structure according to claim 1, characterized in that, It also includes flip-chip bonding bumps, used to flip-chip bond the entire module to the substrate, enabling electrical interconnection between the encapsulation layer and the substrate.

7. The packaging structure according to claim 1, characterized in that, It also includes solder balls, which are configured as connection points between the package and the external PCB.

8. The packaging structure according to claim 1, characterized in that, The embedded chip located below the main chip power module integrates a DTC capacitor.

9. A CoWoS packaging architecture design method for improving silicon layer yield and power integrity, characterized in that, include: Determine the size and layout of the interfaces of the key modules of the main chip, including the power supply module, the storage module and the chip interconnect module; Create a CoWoS packaging architecture layout diagram to clarify the size and location of each embedded chip; An embedded chip is placed directly below the key module of the main chip. Arrange redistribution layers to connect the various chip circuits; Simulations were performed to obtain the impedance distribution network under different CoWoS package architecture layouts. The optimal CoWoS packaging architecture layout was obtained through comparison.

10. The method according to claim 9, characterized in that, The embedded chip is implemented using silicon interposer board technology or interposer chip technology, and is selectively distributed only below key modules. It is configured to perform the following operations: The large power module is filtered by a built-in DTC capacitor; or Provides silicon-based interconnect channels for storage modules and chip interconnect modules.

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