Clock selection circuit, display device having the same, and method of driving the display device

Abstract

A clock selection circuit according to an embodiment of the present application includes an inverter receiving an input signal through a first input terminal, and a controller receiving at least one clock signal and outputting the clock signal when the input signal is supplied to the inverter.

Description

Technical Field

[0001] This invention relates to a clock selection circuit, a display device including the clock selection circuit, and a method for driving the display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being used in various electronic devices, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices use pixels to display images. A display device may include multiple scan drivers and emitter drivers to drive the pixels. Summary of the Invention

[0004] Technical issues The aspects and features of embodiments of the present invention are to provide a clock selection circuit capable of reducing or minimizing power consumption, a display device including the clock selection circuit, and a method for driving the display device.

[0005] Technical solution According to one or more embodiments of the present invention, a clock selection circuit includes: an inverter configured to receive an input signal via a first input terminal; and at least one controller configured to receive at least one clock signal and configured to output at least one clock signal when the input signal is supplied to the inverter.

[0006] According to one or more embodiments, the inverter includes a P-type first transistor and an N-type second transistor connected in series between a first power source and a second power source, the second power source having a voltage lower than that of the first power source, and the gate electrodes of the first transistor and the second transistor being connected to a first input terminal.

[0007] According to one or more embodiments, at least one of the controllers includes a first transmission gate connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first clock signal among at least one clock signal, the first transmission gate including a P-type third transistor and an N-type fourth transistor connected in parallel between the second input terminal and the first output terminal, the gate electrode of the third transistor being connected to a first node, the first node being a common node of the first transistor and the second transistor, and the gate electrode of the fourth transistor being connected to the first input terminal.

[0008] According to one or more embodiments, when an input signal is input to the first input terminal, the third transistor and the fourth transistor are turned on, and when no input signal is supplied, the third transistor and the fourth transistor are turned off.

[0009] According to one or more embodiments, at least one of the controllers further includes a second transmission gate connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second clock signal among at least one clock signal, the second transmission gate including a P-type fifth transistor and an N-type sixth transistor connected in parallel between the third input terminal and the second output terminal, the gate electrode of the fifth transistor being connected to a first node, and the gate electrode of the sixth transistor being connected to the first input terminal.

[0010] According to one or more embodiments, when an input signal is input to the first input terminal, the fifth transistor and the sixth transistor are turned on, and when no input signal is supplied, the fifth transistor and the sixth transistor are turned off.

[0011] According to one or more embodiments of the present invention, a display device includes: a pixel connected to a scan line, an emission control line, and a data line; a scan driver configured to supply a scan signal to the scan line; an emission driver configured to supply an emission control signal to the emission control line; and a clock controller configured to receive at least one clock signal driving the scan driver, and configured to determine whether to supply at least one clock signal to the scan driver in response to the emission control signal.

[0012] According to one or more embodiments, the clock controller is configured to receive transmit control signals sequentially in units of horizontal lines, and is configured to output at least one clock signal in units of horizontal lines in response to the transmit control signals.

[0013] According to one or more embodiments, the clock controller includes a plurality of clock selection circuits, the scan driver includes a plurality of stage circuits, and the i-th (i is a natural number greater than 0) clock selection circuit at the i-th horizontal line is configured to supply a corresponding clock signal from at least one clock signal to the i-th stage circuit at the i-th horizontal line when a transmit control signal is supplied to the i-th transmit control line.

[0014] According to one or more embodiments, the i-th clock selection circuit does not supply the corresponding clock signal to the i-th stage circuit when the transmit control signal is not supplied to the i-th transmit control line.

[0015] According to one or more embodiments, the i-th clock selection circuit includes: a first input terminal connected to the i-th transmit control line; an inverter connected to the first input terminal; and a controller connected to the first input terminal and a first node, the first node being the output node of the inverter, and the controller being configured to supply a corresponding clock signal to the i-th stage circuit when a transmit control signal is supplied to the first input terminal.

[0016] According to one or more embodiments, the inverter includes a P-type first transistor and an N-type second transistor connected in series between a first power source and a second power source, the second power source having a voltage lower than that of the first power source, and the gate electrodes of the first transistor and the second transistor being connected to a first input terminal.

[0017] According to one or more embodiments, the controller includes a first transmission gate connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first clock signal among at least one clock signal, the first transmission gate including a P-type third transistor and an N-type fourth transistor connected in parallel between the second input terminal and the first output terminal, the gate electrode of the third transistor being connected to a first node, and the gate electrode of the fourth transistor being connected to the first input terminal.

[0018] According to one or more embodiments, when the first transmission gate is turned on, a first clock signal is supplied to the i-th stage circuit via a first output terminal.

[0019] According to one or more embodiments, the controller further includes a second transmission gate connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second clock signal among at least one clock signal, the second transmission gate including a P-type fifth transistor and an N-type sixth transistor connected in parallel between the third input terminal and the second output terminal, the gate electrode of the fifth transistor being connected to a first node, and the gate electrode of the sixth transistor being connected to the first input terminal.

[0020] According to one or more embodiments, when the second transmission gate is turned on, the second clock signal is supplied to the i-th stage circuit via the second output terminal.

[0021] According to one or more embodiments, the scan line includes a first scan line and a second scan line at corresponding horizontal lines, and the scan driver includes a first scan driver configured to drive the first scan line and a second scan driver configured to drive the second scan line.

[0022] According to one or more embodiments, at least one clock signal includes at least one write clock signal for driving a first scan driver and at least one compensation clock signal for driving a second scan driver.

[0023] According to one or more embodiments, the clock controller includes a plurality of clock selection circuits, the first scan driver includes a plurality of write stage circuits, the second scan driver includes a plurality of compensation stage circuits, and the i-th clock selection circuit at the i-th horizontal line is configured to supply at least one corresponding write clock signal from at least one write clock signal to the i-th write stage circuit located at the i-th horizontal line when a transmit control signal is supplied to the i-th (i is a natural number greater than 0) transmit control line, and to supply at least one corresponding compensation clock signal from at least one compensation clock signal to the i-th compensation stage circuit located at the i-th horizontal line.

[0024] According to one or more embodiments, the i-th clock selection circuit is configured to not supply the corresponding write clock signal to the i-th write stage circuit and not supply the corresponding compensation clock signal to the i-th compensation stage circuit when the transmit control signal is not supplied to the i-th transmit control line.

[0025] According to one or more embodiments, the i-th clock selection circuit includes: a first input terminal connected to the i-th transmit control line; an inverter connected to the first input terminal; a first controller connected to the first input terminal and a first node, the first node being the output node of the inverter, and the first controller being configured to supply a corresponding write clock signal to the i-th write stage circuit when a transmit control signal is supplied to the first input terminal; and a second controller connected to the first input terminal and the first node, and configured to supply a corresponding compensation clock signal to the i-th compensation stage circuit when a transmit control signal is supplied to the first input terminal.

[0026] According to one or more embodiments, the inverter includes a P-type first transistor and an N-type second transistor connected in series between a first power source and a second power source, the second power source having a voltage lower than that of the first power source, and the gate electrodes of the first transistor and the second transistor being connected to a first input terminal.

[0027] According to one or more embodiments, a first controller includes: a first transmission gate connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first write clock signal among at least one write clock signal, and the first transmission gate being configured to be turned on when a transmit control signal is supplied to the first input terminal; and a second transmission gate connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second write clock signal among the at least one write clock signal, and the second transmission gate being configured to be turned on when a transmit control signal is supplied to the first input terminal.

[0028] According to one or more embodiments, the second controller includes: a first transmission gate connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first compensation clock signal among at least one compensation clock signal, and the first transmission gate being configured to be turned on when a transmit control signal is supplied to the first input terminal; and a second transmission gate connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second compensation clock signal among at least one compensation clock signal, and the second transmission gate being configured to be turned on when a transmit control signal is supplied to the first input terminal.

[0029] According to one or more embodiments of the present invention, a display device includes: a pixel connected to a first scan line, a second scan line, an emission control line, and a data line; a first scan driver configured to supply a first scan signal to the first scan line; a second scan driver configured to supply a second scan signal to the second scan line; an emission driver configured to supply an emission control signal to the emission control line; a first clock controller configured to receive at least one write clock signal driving the first scan driver and configured to determine whether to supply at least one write clock signal in response to the second scan signal; and a second clock controller configured to receive at least one compensation clock signal driving the second scan driver and configured to determine whether to supply at least one compensation clock signal in response to the emission control signal.

[0030] According to one or more embodiments, the first clock controller is further configured to receive the second scan signal sequentially in units of horizontal lines, and is configured to output at least one write clock signal in units of horizontal lines in response to the second scan signal.

[0031] According to one or more embodiments, the first clock controller includes a clock selection circuit at a horizontal line, and the i-th (i is a natural number greater than 0) clock selection circuit at the i-th horizontal line includes: an inverter configured to invert the i-th second scan signal; and a controller configured to output at least one corresponding write clock signal among write clock signals to the first scan driver when the i-th second scan signal and the output signal of the inverter are input, and not to output the corresponding write clock signal in other cases.

[0032] According to one or more embodiments, the second clock controller is further configured to receive transmit control signals sequentially in units of horizontal lines, and is configured to output at least one compensation clock signal in units of horizontal lines in response to the transmit control signals.

[0033] According to one or more embodiments, the second clock controller includes a clock selection circuit at a horizontal line, and the i-th (i is a natural number greater than 0) clock selection circuit at the i-th horizontal line includes: an inverter configured to invert the i-th transmit control signal; and a controller configured to output a corresponding compensation clock signal among at least one compensation clock signal to the second scan driver when the i-th transmit control signal and the output signal of the inverter are input, and not to output the corresponding compensation clock signal in other cases.

[0034] According to one or more embodiments of the present invention, a method for driving a display device includes: sequentially supplying emission control signals to pixels; outputting clock signals in units of horizontal lines when emission control signals are input; and sequentially supplying scan signals in response to clock signals input in units of horizontal lines.

[0035] The aspects and features of the embodiments of the present invention are not limited to those described above, and other technical aspects and features not described will be clearly understood by those skilled in the art from the following description.

[0036] Beneficial effects According to one or more embodiments of the present invention, a clock selection circuit, a display device including the clock selection circuit, and a method for driving the display device can reduce power consumption by selectively supplying a clock signal to a scan driver.

[0037] However, the effects, aspects and features of the present invention are not limited to those described above, and various extensions can be made without departing from the spirit and scope of the present invention. Attached Figure Description

[0038] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present invention.

[0039] Figure 2 It is shown Figure 1 A diagram of an embodiment of the clock controller shown.

[0040] Figure 3 It is shown Figure 2 The circuit diagram shows an embodiment of the clock selection circuit.

[0041] Figure 4 This is a diagram illustrating an embodiment of the clock selection circuit and stage circuit.

[0042] Figure 5 This is a waveform diagram illustrating an embodiment of a method for driving a clock selection circuit.

[0043] Figure 6 It is shown Figure 1 A diagram illustrating an embodiment of the pixels shown.

[0044] Figure 7 It shows the driver Figure 6 The waveform diagram shows an embodiment of the pixel method.

[0045] Figure 8 It is shown Figure 1 A diagram of an embodiment of the scan driver shown.

[0046] Figure 9 It is shown Figure 8 A diagram of an embodiment of the clock controller shown.

[0047] Figure 10 It is shown Figure 9 A diagram of an embodiment of the clock selection circuit shown.

[0048] Figure 11 It is shown Figure 1 A diagram of an embodiment of a scan driver and clock controller.

[0049] Figure 12 It is shown that it includes Figure 11 A circuit diagram of an embodiment of the clock selection circuit in each of the first and second clock controllers.

[0050] Figure 13a and Figure 13b It is shown Figure 1 A diagram illustrating an embodiment of the clock selection circuit and stage circuit of a display device. Detailed Implementation

[0051] In the following description, various embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the invention. The invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0052] For clarity in describing the invention, irrelevant parts have been omitted, and throughout the specification, identical or similar elements are indicated by the same reference numerals. Therefore, the reference numerals described above may be used in other figures.

[0053] Furthermore, since the dimensions and thicknesses of each configuration shown in the figures are arbitrarily illustrated for ease of description, the invention is not necessarily limited to the dimensions and thicknesses of each configuration shown in the figures. Thicknesses may have been exaggerated to clearly represent multiple layers and regions in the figures.

[0054] Furthermore, the statement "are the same" in the description can mean "are substantially the same." That is, the statement "are the same" can be one that is sufficient for a person skilled in the art to understand that they are the same. Other statements may also omit the word "substantially."

[0055] The accompanying drawings illustrate several embodiments in conjunction with functional blocks, units, and / or modules. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Furthermore, each block, unit, and / or module can be implemented by dedicated hardware, or by a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing functions different from those of the dedicated hardware. Additionally, in some embodiments, blocks, units, and / or modules can be physically separated into two or more interacting individual blocks, units, and / or modules without departing from the spirit and scope of the invention. Furthermore, in some embodiments, blocks, units, and / or modules can be physically combined into more complex blocks, units, and / or modules without departing from the spirit and scope of the invention.

[0056] The term "connection" between two configurations can refer to both electrical and physical connections, but is not limited to this. For example, "connection" used based on a circuit diagram can refer to an electrical connection, while "connection" used based on a cross-sectional view and a plan view can refer to a physical connection.

[0057] Although the terms "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, within the technical spirit of the invention, the first component described below may be referred to as the second component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0058] This invention is not limited to the embodiments disclosed below, and can be modified and implemented in various forms. Furthermore, each of the embodiments disclosed below can be implemented individually or in combination with at least one of the other embodiments.

[0059] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present invention.

[0060] Reference Figure 1 The display device 100 according to one or more embodiments of the present invention may include a pixel unit 110 (or a display panel), a timing controller 120, a scan driver 130, a data driver 140, a transmit driver 150, a power supply 160, and a clock controller 170.

[0061] Pixel unit 110 may include pixel PX, which is connected to a first scan line SL1 (first scan lines SL11, SL12, ... and SL1n), a second scan line SL2 (second scan lines SL21, SL22, ... and SL2n), a third scan line SL3 (third scan lines SL31, SL32, ... and SL3n), a fourth scan line SL4 (fourth scan lines SL41, SL42, ... and SL4n), data lines DL1, DL2, ... and DLm, transmission control lines EL (transmission control lines EL1, EL2, ... and ELn), and power lines PL1, PL2, PL3, and PL4 (here, n and m are natural numbers greater than 0). Here, pixel PX may be a sub-pixel.

[0062] For example, pixel PXij located in the i-th horizontal line (or pixel row) and j-th vertical line (or pixel column) (refer to...) Figure 6 It can be connected to the i-th first scan line SL1i (refer to...) Figure 6 ), the second scan line SL2i (refer to) Figure 6 ), the third scan line SL3i (refer to) Figure 6 ), the fourth scan line SL4i (refer to) Figure 6 ), the i-th transmit control line ELi (refer to) Figure 6 ), and the j-th data line DLj (refer to Figure 6 (Here, i is a natural number greater than 0 and equal to or less than n, and j is a natural number greater than 0 and equal to or less than m).

[0063] When the first scan signal is enabled and supplied to the first scan line SL1 (first scan lines SL11 to SL1n), pixel PX can be selected in units of horizontal lines (e.g., pixels PX connected to the same scan line can be classified as a horizontal line (or pixel row)), and the pixel PX selected by the first scan signal can receive data signals from the data lines (any one of data lines DL1 to DLm) connected to the pixel PX. The pixel PX receiving the data signal can generate light of a desired brightness (e.g., a predetermined brightness) in response to the voltage of the data signal.

[0064] In addition, Figure 1 In this invention, each pixel PX is connected to four scan lines SL1, SL2, SL3, and SL4, but the invention is not limited thereto. For example, the number of scan lines SL1, SL2, SL3, and SL4 connected to each pixel PX can be set differently according to the circuit structure of the pixel PX.

[0065] The scan driver 130 can receive scan drive signals SCS from the timing controller 120. The scan drive signals SCS may include scan start signals, etc., required to drive the scan driver 130. Furthermore, the scan driver 130 can receive selection clock signals sCK1 and sCK2 (selection clock signals sCK11, sCK12, ..., and sCK1n and selection clock signals sCK21, sCK22, ..., and sCK2n) from the clock controller 170. The scan driver 130 can generate enable first scan signals, enable second scan signals, enable third scan signals, and enable fourth scan signals simultaneously, in response to shifting the scan start signal using the selection clock signals sCK1 and sCK2.

[0066] Enabling the first scan signal, enabling the second scan signal, enabling the third scan signal, and enabling the fourth scan signal can mean that the gate turn-on voltage is supplied to scan lines SL1, SL2, SL3, and SL4. That is, the fact that the first scan signal is supplied to the first scan line SL1 can mean that the gate turn-on voltage that enables the transistor connected to the first scan line SL1 is supplied to the first scan line SL1. For example, a low-level enable scan signal can be supplied to a P-type transistor, and a high-level enable scan signal can be supplied to an N-type transistor. In this document, enabling the first scan signal, enabling the second scan signal, enabling the third scan signal, and enabling the fourth scan signal can use the same reference numerals GW, GC, GI, and GB (see reference 1) as the first scan signal, second scan signal, third scan signal, and fourth scan signal, respectively. Figure 6 ).

[0067] During the periods when the enable scan signal is not supplied to scan lines SL1, SL2, SL3, and SL4, a disable scan signal may be supplied to each of scan lines SL1, SL2, SL3, and SL4. Disabling the first scan signal, disabling the second scan signal, disabling the third scan signal, and disabling the fourth scan signal can mean that a gate cutoff voltage is supplied to scan lines SL1, SL2, SL3, and SL4. That is, the fact that the first scan signal is supplied to the first scan line SL1 can mean that a gate cutoff voltage that turns off the transistor connected to the first scan line SL1 is supplied to the first scan line SL1. For example, a high-level disable scan signal may be supplied to a P-type transistor, and a low-level disable scan signal may be supplied to an N-type transistor.

[0068] Scan driver 130 may include multiple scan drivers, such as... Figure 8The first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 are shown. At least two of the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 can be formed as a single driver, and each can be formed as a separate driver.

[0069] In one or more embodiments, the scan driver 130 may be provided as a separate integrated circuit (IC) in the display device 100. In one or more embodiments, the scan driver 130 may be formed together with the pixel PX during the formation process of the pixel unit 110. For example, the scan driver 130 may be formed in the pixel unit 110 as an oxide semiconductor thin-film transistor gate driver circuit (OSG) type or an amorphous silicon thin-film transistor gate driver circuit (ASG) type.

[0070] Data driver 140 can receive output data Dout and data drive signal DCS from timing controller 120. Data drive signal DCS may include sampling signals and / or timing signals required to drive data driver 140. Data driver 140 can generate a data signal based on data drive signal DCS and output data Dout. For example, data driver 140 can generate an analog data signal based on the grayscale level of output data Dout. Data driver 140 can supply data signals to data lines DL1 to DLm synchronously with an enable first scan signal.

[0071] Transmit driver 150 can receive transmit drive signal ECS from timing controller 120. Transmit drive signal ECS may include a transmit start signal and a clock signal required to drive transmit driver 150. Transmit driver 150 can generate a transmit disable control signal while shifting the transmit start signal in response to the clock signal.

[0072] A disable emit control signal can mean that a gate cutoff voltage is supplied to the emit control line EL. In other words, supplying a disable emit control signal can mean that a gate cutoff voltage that turns off the transistor connected to the emit control line EL is supplied to the emit control line EL. For example, a high-level disable emit control signal can be supplied to a P-type transistor, and a low-level disable emit control signal can be supplied to an N-type transistor. Furthermore, supplying a disable emit control signal to the emit control line EL can be described as supplying an emit control signal to the emit control line EL. In this document, the disable emit control signal may use the same reference numeral EM as the emit control signal.

[0073] During periods when the disable transmit control signal is not supplied to the transmit control line EL, the enable transmit control signal may be supplied to the transmit control line EL. The enable transmit control signal can mean that a gate-on voltage is supplied to the transmit control line EL. That is, supplying the enable transmit control signal can mean that a gate-on voltage that enables a transistor connected to the transmit control line EL is supplied to the transmit control line EL. For example, a low-level enable transmit control signal may be supplied to a P-type transistor, and a high-level enable transmit control signal may be supplied to an N-type transistor. In one or more embodiments, supplying the enable transmit control signal to the transmit control line EL can be described as stopping the supply of transmit control signals to the transmit control line EL. In one or more embodiments, supplying the disable transmit control signal to the transmit control line EL can be referred to as supplying transmit control signals to the transmit control line EL.

[0074] The timing controller 120 can receive input data Din and control signals CS from the host system via an interface. For example, the timing controller 120 can receive input data Din and control signals CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS can include various signals including a clock signal.

[0075] The timing controller 120 can generate a scan drive signal SCS, a data drive signal DCS, and a transmit drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the transmit drive signal ECS can be supplied to the scan driver 130, the data driver 140, and the transmit driver 150, respectively.

[0076] The timing controller 120 can rearrange the input data Din to match the specifications of the display device 100. Furthermore, the timing controller 120 can correct the input data Din to generate output data Dout and supply the output data Dout to the data driver 140. In one or more embodiments, the timing controller 120 can correct the input data Din in response to optical measurements taken during the process.

[0077] Furthermore, the timing controller 120 can supply the clock signals CK1 and CK2 required to drive the scan driver 130 to the clock controller 170. Figure 1 In this embodiment, two clock signals CK1 and CK2 are supplied to the clock controller 170, but the invention is not limited thereto. For example, the timing controller 120 may supply at least one clock signal to the clock controller 170 in correspondence with the stage circuitry included in the scan driver 130.

[0078] Clock controller 170 can receive a disable transmit control signal from transmit driver 150 and clock signals CK1 and CK2 from timing controller 120. Furthermore, clock controller 170 can sequentially output clock signals CK1 and CK2 in units of horizontal lines. Here, clock signals CK1 and CK2 output in units of horizontal lines can be referred to as selection clock signals sCK1 and sCK2.

[0079] In one or more embodiments, the clock controller 170 may output selection clock signals sCK11 and sCK21 corresponding to the first horizontal line during a period in which a transmit control signal is disabled and supplied to the first transmit control line EL1. Then, the scan driver 130 may, in response to the selection clock signals sCK11 and sCK21, output an enable first scan signal, an enable second scan signal, an enable third scan signal, and an enable fourth scan signal, respectively, to scan lines SL11, SL21, SL31, and SL41 located in (or at) the first horizontal line.

[0080] In one or more embodiments, the clock controller 170 may output selection clock signals sCK12 and sCK22 corresponding to the second horizontal line during a period in which a transmit control signal is disabled and supplied to the second transmit control line EL2. Then, the scan driver 130 may, in response to the selection clock signals sCK12 and sCK22, output an enable first scan signal, an enable second scan signal, an enable third scan signal, and an enable fourth scan signal to scan lines SL12, SL22, SL32, and SL42 located in the second horizontal line, respectively.

[0081] In one or more embodiments, the clock controller 170 may output selection clock signals sCK1n and sCK2n corresponding to the nth horizontal line during a period in which a transmit control signal is disabled from being supplied to the nth transmit control line ELn. Then, the scan driver 130 may, in response to the selection clock signals sCK1n and sCK2n, output an enable first scan signal, an enable second scan signal, an enable third scan signal, and an enable fourth scan signal to scan lines SL1n, SL2n, SL3n, and SL4n located in the nth horizontal line, respectively.

[0082] In one or more embodiments of the invention, clock controller 170 may be used to selectively supply clock signals CK1 and CK2. In this case, the stage circuitry included in the scan driver 130 and positioned for each horizontal line receives the selected clock signals sCK1 and sCK2 only during the period in which the enable scan signal is generated, and does not receive the selected clock signals sCK1 and sCK2 during other periods. That is, in one or more embodiments of the invention, clock controller 170 can selectively supply clock signals CK1 and CK2, and thus power consumption can be reduced.

[0083] Power supply 160 can generate various types of power required to drive display device 100. For example, power supply 160 can generate first driving power VDD, second driving power VSS, first initialization power Vint1, and second initialization power Vint2.

[0084] The first driving power VDD can be the power that supplies driving current to pixel PX. The second driving power VSS can be the power that receives driving current from pixel PX. During the period when pixel PX is set to the transmit state, the first driving power VDD can be set to a voltage higher than the voltage of the second driving power VSS.

[0085] The first initialization power Vint1 can be the driving transistor included in each of the pixels PX ( Figure 6 The voltage used to initialize the gate electrode of the first transistor M21 shown is [not specified]. The first initialization power Vint1 can be set to a voltage value lower than that of the data signal. The second initialization power Vint2 can be [not specified] the voltage value used to initialize the light-emitting elements LD (see reference [not specified]) included in each of the pixels PX. Figure 6 The initial voltage of the first electrode (or anode electrode) of the light-emitting element (LD). The second initial power Vint2 may have the voltage value at which the light-emitting element (LD) is cut off when the second initial power Vint2 is supplied to the first electrode of the light-emitting element (LD).

[0086] For example, such as Figure 6 As shown, the first driving power VDD generated by power supply 160 can be supplied to the first power line PL1, the second driving power VSS can be supplied to the second power line PL2, the first initialization power Vint1 can be supplied to the third power line PL3, and the second initialization power Vint2 can be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 can be commonly connected to the pixel PX, but the invention is not limited thereto.

[0087] In one or more embodiments, the first power line PL1 may be composed of multiple power lines, and these multiple power lines may be connected to different pixels PX. In one or more embodiments, the second power line PL2 may be composed of multiple power lines, and these multiple power lines may be connected to different pixels PX. In one or more embodiments, the third power line PL3 may be composed of multiple power lines, and these multiple power lines may be connected to different pixels PX. In one or more embodiments, the fourth power line PL4 may be composed of multiple power lines, and these multiple power lines may be connected to different pixels PX. In other words, in one or more embodiments of the present invention, a pixel PX may be connected to any one of the first power lines PL1, any one of the second power lines PL2, any one of the third power lines PL3, and any one of the fourth power lines PL4.

[0088] In one or more embodiments of the present invention, the display device 100 may include a flat display device, a curved display device in which a portion of the pixel unit 110 is bent, a flexible display device in which a portion of the pixel unit 110 can be folded and / or bent, and a stretchable display device in which a portion of the pixel unit 110 can be expanded and contracted.

[0089] In one or more embodiments of the present invention, the display device 100 may be a device for displaying moving images and / or still images, and may include portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). In one or more embodiments of the present invention, the display device 100 may include electronic devices such as televisions, laptop computers, monitors, billboards, or Internet of Things (IoT) devices.

[0090] Figure 2 It is shown Figure 1 A diagram of an embodiment of the clock controller shown.

[0091] Reference Figure 2According to one or more embodiments of the present invention, a clock controller 170 may include a plurality of clock selection circuits COS1, COS2, ..., COSi, ..., COSn-1 and COSn. The clock selection circuits COS may be connected to a first clock line CKL1 and a second clock line CKL2. For example, the second input terminal IN2 of each of the odd-numbered clock selection circuits COS1, ..., COSi, ... and COSn may be connected to the first clock line CKL1 to which the first clock signal CK1 is supplied, and the third input terminal IN3 may be connected to the second clock line CKL2 to which the second clock signal CK2 is supplied. Furthermore, the second input terminal IN2 of each of the even-numbered clock selection circuits COS2, ... and COSn-1 may be connected to the second clock line CKL2 to which the second clock signal CK2 is supplied, and the third input terminal IN3 may be connected to the first clock line CKL1 to which the first clock signal CK1 is supplied.

[0092] The clock selection circuit (COS) can be positioned for each horizontal line, and each clock selection circuit (COS) can be connected to the transmit control line EL corresponding to the horizontal line in which it is positioned. For example, the first input terminal IN1 of the first clock selection circuit COS1 positioned in the first horizontal line can be connected to the first transmit control line EL1, and the first input terminal IN1 of the nth clock selection circuit COSn positioned in the nth horizontal line can be connected to the nth transmit control line ELn.

[0093] In one or more embodiments, the first clock selection circuit COS1 may output clock signals CK1 and CK2 during a period in which a disable transmit control signal is supplied to the first transmit control line EL1. Here, the clock signals CK1 and CK2 output from the first clock selection circuit COS1 may be selection clock signals sCK11 and sCK21. For example, when the disable transmit control signal is supplied to the first transmit control line EL1, the first clock selection circuit COS1 may output a first selection clock signal sCK11 (or the first clock signal CK1) to the first output terminal OUT1 and a second selection clock signal sCK21 (or the second clock signal CK2) to the second output terminal OUT2.

[0094] The second clock selection circuit COS2 can output clock signals CK1 and CK2 during the period when the transmit control signal is disabled and supplied to the second transmit control line EL2. Here, the clock signals CK1 and CK2 output from the second clock selection circuit COS2 can be selection clock signals sCK12 and sCK22. For example, when the transmit control signal is disabled and supplied to the second transmit control line EL2, the second clock selection circuit COS2 can output a first selection clock signal sCK12 (or a second clock signal CK2) to the first output terminal OUT1, and a second selection clock signal sCK22 (or a first clock signal CK1) to the second output terminal OUT2.

[0095] Similarly, the i-th clock selection circuit COSi can output selection clock signals sCK1i and sCK2i during the period when the transmit control signal is disabled and supplied to the i-th transmit control line ELi, the (n-1)-th clock selection circuit COSn-1 can output selection clock signals sCK1n-1 and sCK2n-1 during the period when the transmit control signal is disabled and supplied to the (n-1)-th transmit control line ELn-1, and the n-th clock selection circuit COSn can output selection clock signals sCK1n and sCK2n during the period when the transmit control signal is disabled and supplied to the n-th transmit control line ELn.

[0096] Figure 3 It is shown Figure 2 The circuit diagram shows an embodiment of the clock selection circuit. Figure 3 The i-th clock selection circuit COSi (also referred to herein as clock selection circuit COSi) is shown, and the remaining clock selection circuits may have substantially the same circuit configuration as the i-th clock selection circuit COSi.

[0097] Reference Figure 3 The clock selection circuit COSi according to one or more embodiments of the present invention may include an inverter 172 and a controller 174.

[0098] Inverter 172 is connected to the first input terminal IN1. The first input terminal IN1 is connected to the i-th transmit control line ELi and receives the disable transmit control signal EM (transmit control signal or input signal) from the i-th transmit control line ELi. Inverter 172 can invert the disable transmit control signal EM to generate the enable transmit control signal / EM (inverted transmit control signal or inverted input signal). Here, the disable transmit control signal EM can have a high-level voltage, and the enable transmit control signal / EM can have a low-level voltage.

[0099] In one or more embodiments, inverter 172 may include a first transistor M1 and a second transistor M2 connected in series between a first power source VGH and a second power source VGL. The first power source VGH may be set to a high-level voltage, and the second power source VGL may be set to a low-level voltage lower than the voltage level of the first power source VGH.

[0100] The first transistor M1 can be connected between the first power source VGH and the first node N1 (or output node), and the gate electrode of the first transistor M1 can be connected to the first input terminal IN1. The first transistor M1 can be turned off when a disable transmit control signal EM (high-level voltage) is supplied, and can be turned on when a low-level voltage signal is supplied to the gate electrode. For this purpose, the first transistor M1 can be configured as a P-type transistor.

[0101] The second transistor M2 can be connected between the first node N1 and the second power source VGL, and the gate electrode of the second transistor M2 can be connected to the first input terminal IN1. The second transistor M2 can be turned on when a disable emitter control signal EM (high-level voltage) is supplied, and can be turned off when a low-level voltage signal is supplied to the gate electrode. For this purpose, the second transistor M2 can be configured as an N-type transistor. The first node N1 can be the common node of the first transistor M1 and the second transistor M2.

[0102] When the transmit disable control signal EM is supplied to the first input terminal IN1, the controller 174 can electrically connect the second input terminal IN2 to the first output terminal OUT1 and the third input terminal IN3 to the second output terminal OUT2. For this purpose, the controller 174 may include a first transmission gate TG1 and a second transmission gate TG2.

[0103] A first transmission gate TG1 can be connected between the second input terminal IN2 and the first output terminal OUT1. The first transmission gate TG1 controls the electrical connection between the second input terminal IN2 and the first output terminal OUT1 in response to a disable transmit control signal EM and an enable transmit control signal / EM. For this purpose, the first transmission gate TG1 may include a third transistor M3 and a fourth transistor M4.

[0104] The third transistor M3 can be connected between the second input terminal IN2 and the first output terminal OUT1, and the gate electrode of the third transistor M3 can be connected to the first node N1. The third transistor M3 can be turned on when the enable transmit control signal / EM is supplied to the first node N1 to electrically connect the second input terminal IN2 and the first output terminal OUT1. For this purpose, the third transistor M3 can be configured as a P-type transistor.

[0105] The fourth transistor M4 can be connected between the second input terminal IN2 and the first output terminal OUT1, and the gate electrode of the fourth transistor M4 can be connected to the first input terminal IN1. The fourth transistor M4 can be turned on when the disable emitter control signal EM is supplied to the first input terminal IN1 to electrically connect the second input terminal IN2 and the first output terminal OUT1. For this purpose, the fourth transistor M4 can be configured as an N-type transistor.

[0106] The second transmission gate TG2 can be connected between the third input terminal IN3 and the second output terminal OUT2. The second transmission gate TG2 controls the electrical connection between the third input terminal IN3 and the second output terminal OUT2 in response to the disable transmit control signal EM and the enable transmit control signal / EM. For this purpose, the second transmission gate TG2 may include a fifth transistor M5 and a sixth transistor M6.

[0107] The fifth transistor M5 can be connected between the third input terminal IN3 and the second output terminal OUT2, and the gate electrode of the fifth transistor M5 can be connected to the first node N1. The fifth transistor M5 can be turned on when the enable transmit control signal / EM is supplied to the first node N1 to electrically connect the third input terminal IN3 and the second output terminal OUT2. For this purpose, the fifth transistor M5 can be configured as a P-type transistor.

[0108] The sixth transistor M6 can be connected between the third input terminal IN3 and the second output terminal OUT2, and the gate electrode of the sixth transistor M6 can be connected to the first input terminal IN1. The sixth transistor M6 can be turned on when the disable transmit control signal EM is supplied to the first input terminal IN1 to electrically connect the third input terminal IN3 and the second output terminal OUT2. For this purpose, the sixth transistor M6 can be configured as an N-type transistor.

[0109] Figure 4 This is a diagram illustrating an embodiment of the clock selection circuit and stage circuit. Figure 4 The i-th stage circuit STi (also referred to herein as stage circuit STi) connected to the i-th clock selection circuit COSi is shown. The stage circuit STi can be included in the scan driver 130 and can be formed for each horizontal line.

[0110] Reference Figure 4 The stage circuit STi can receive the previous stage output signal OSi-1 (or the start signal FLM) through the input terminal INa, and output the output signal OSi through the output terminal OUTa. The stage circuit STi may include an input unit 131 and an output unit 133.

[0111] Input unit 131 can be connected to the first output terminal OUT1 and the second output terminal OUT2 of clock selection circuit COSi. When the first selection clock signal sCK1i is output to the first output terminal OUT1 and the second selection clock signal sCK2i is output to the second output terminal OUT2, input unit 131 can supply the previous stage output signal OSi-1, which is input to input terminal INa, to output unit 133.

[0112] Therefore, input unit 131 may include a first input transistor M1a and a second input transistor M2a connected to the transmission gate. The first input transistor M1a and the second input transistor M2a may be connected in parallel between input terminal INa and output unit 133.

[0113] The first input transistor M1a can be configured as a P-type transistor and can be turned on or off in response to a first selection clock signal sCK1i supplied from the first output terminal OUT1. The second input transistor M2a can be configured as an N-type transistor and can be turned on or off in response to a second selection clock signal sCK2i supplied from the second output terminal OUT2.

[0114] Output unit 133 can output output signal OSi to output terminal OUTa in response to the previous stage output signal OSi-1 supplied from input unit 131. Here, output signal OSi can be supplied to scan lines as an enable scan signal. For example, output signal OSi can be supplied to scan lines (at least one of scan lines SL1i, SL2i, SL3i, and SL4i) as an enable first scan signal, enable second scan signal, enable third scan signal, and / or enable fourth scan signal.

[0115] Output unit 133 may include a first inverter 135 and a second inverter 137. The first inverter 135 generates an inverted output signal by inverting the previous stage output signal OSi-1. The second inverter 137 generates the output signal OSi by inverting the inverted output signal from the first inverter 135.

[0116] The first inverter 135 may include a third transistor M31 and a fourth transistor M41 connected in series between a first power source VGH and a second power source VGL. The third transistor M31 may be connected between the first power source VGH and the output node NO, and its gate electrode may be connected to the input unit 131. The fourth transistor M41 may be connected between the output node NO and the second power source VGL, and its gate electrode may be connected to the input unit 131. The third transistor M31 may be configured as a P-type transistor, and the fourth transistor M41 may be configured as an N-type transistor.

[0117] The second inverter 137 may include a fifth transistor M51 and a sixth transistor M61 connected in series between a first power source VGH and a second power source VGL. The fifth transistor M51 may be connected between the first power source VGH and the output terminal OUTa, and its gate electrode may be connected to the output node NO. The sixth transistor M61 may be connected between the output terminal OUTa and the second power source VGL, and its gate electrode may be connected to the output node NO. The fifth transistor M51 may be configured as a P-type transistor, and the sixth transistor M61 may be configured as an N-type transistor.

[0118] Furthermore, in one or more embodiments of the present invention, the stage circuit STi may include various currently known configurations. For example, the stage circuit STi may include an input unit 131 having a transmission gate that receives the previous stage output signal OSi-1 (or the start signal FLM) through an input terminal INa, and other configurations may include various currently known configurations.

[0119] Figure 5 This is a waveform diagram illustrating an embodiment of a method for driving a clock selection circuit.

[0120] Reference Figures 2 to 5 The first clock signal CK1 can be input to the first clock line CKL1, and the second clock signal CK2 can be input to the second clock line CKL2. Here, the first clock signal CK1 and the second clock signal CK2 can be signals with the same period and opposite phase.

[0121] At the first time point t1, a transmit disable control signal EM is supplied to the i-th transmit control line ELi. The transmit disable control signal EM can be supplied to the first input terminal IN1 of the i-th clock selection circuit COSi via the i-th transmit control line ELi. Then, the second transistor M2 included in the i-th clock selection circuit COSi is turned on. When the second transistor M2 is turned on, the voltage of the second power source VGL can be supplied to the first node N1.

[0122] Here, the voltage of the second power source VGL supplied to the first node N1 can be supplied to the third transistor M3 and the fifth transistor M5 as an enable transmit control signal / EM, and thus the third transistor M3 and the fifth transistor M5 can be turned on. Furthermore, the disable transmit control signal EM to be supplied to the i-th transmit control line ELi can be supplied to the fourth transistor M4 and the sixth transistor M6, and thus the fourth transistor M4 and the sixth transistor M6 can be turned on.

[0123] When the third transistor M3 and the fourth transistor M4 are turned on, the first clock line CKL1 and the first output terminal OUT1 are electrically connected, and therefore the first clock signal CK1 (i.e., the first selection clock signal sCK1i) can be output to the first output terminal OUT1.

[0124] When the fifth transistor M5 and the sixth transistor M6 are turned on, the second clock line CKL2 and the second output terminal OUT2 can be electrically connected, and therefore the second clock signal CK2 (i.e., the second selection clock signal sCK2i) can be output to the second output terminal OUT2. In other words, the i-th clock selection circuit COSi can output the selection clock signals sCK1i and sCK2i during the period when the transmit control signal EM is disabled and supplied to the i-th transmit control line ELi.

[0125] When the clock selection signals sCK1i and sCK2i are output from the i-th clock selection circuit COSi, the output signal OSi can be generated in the i-th stage circuit STi in response to the previous stage output signal OSi-1. The output signal OSi can be supplied to the scan line as an enable scan signal.

[0126] At the second time point t2, the supply of the disable transmit control signal EM to the i-th transmit control line ELi can be stopped. Then, the first transistor M1 can be turned on, and thus the voltage of the first power source VGH can be supplied to the first node N1. In this case, the third transistor M3 to the sixth transistor M6 can be set to the off state, and thus the supply of the selection clock signals sCK1i and sCK2i can be stopped.

[0127] In other words, in one or more embodiments of the present invention, the selection clock signals sCK1i and sCK2i can be supplied only during the period in which the output signal OSi is generated in the stage circuit STi, and the supply of the selection clock signals sCK1i and sCK2i can be stopped during other periods. When the supply of the selection clock signals sCK1i and sCK2i is stopped, the input transistors M1a and M2a included in the input unit 131 of the stage circuit STi can be prevented from periodically turning on and off, and thus power consumption can be reduced.

[0128] Figure 6 It is shown Figure 1 A diagram illustrating an embodiment of the pixels shown. Figure 6 The pixel PXij is shown as being located in the i-th horizontal line and the j-th vertical line.

[0129] Reference Figure 6According to one or more embodiments of the present invention, pixel PXij can be connected to corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELi, and DLj. For example, pixel PXij can be connected to the i-th first scan line SL1i (also referred to herein as the first scan line SL1i), the i-th second scan line SL2i (also referred to herein as the second scan line SL2i), the i-th third scan line SL3i (also referred to herein as the third scan line SL3i), the i-th fourth scan line SL4i (also referred to herein as the fourth scan line SL4i), the i-th transmit control line ELi (also referred to herein as the transmit control line ELi), and the j-th data line DLj (also referred to herein as the data line DLj). In one or more embodiments, pixel PXij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4.

[0130] The i-th third scan line SL3i can be the (i-1)-th second scan line SL2i-1. The i-th fourth scan line SL4i can be the (i-1)-th first scan line SL1i-1. In this case, the signals required to drive the actual pixel PXij can be the first scan signal GW, the second scan signal GC, and the transmit control signal EM. That is, the i-th third scan line SL3i can be driven by the second scan signal GC of the previous pixel row, and the i-th fourth scan line SL4i can be driven by the first scan signal GW of the previous pixel row.

[0131] A pixel PXij according to one or more embodiments of the present invention may include a light-emitting element LD and a pixel circuit for controlling the amount of current supplied to the light-emitting element LD.

[0132] The light-emitting element (LD) can be connected between a first electric power line PL1 and a second electric power line PL2. For example, the first electrode (or anode electrode) of the LD can be electrically connected to the first electric power line PL1 via a sixth transistor M26, a third node N23, a first transistor M21, a second node N22, and a fifth transistor M25, and the second electrode (or cathode electrode) of the LD can be electrically connected to the second electric power line PL2. The LD can generate light of a desired brightness (e.g., a predetermined brightness) in response to the amount of current supplied from the first electric power line PL1 to the second electric power line PL2 via pixel circuitry.

[0133] The light-emitting element (LD) can be selected as an organic light-emitting diode (OLED). Alternatively, the LD can be selected as an inorganic light-emitting diode (LED), such as a micro LED or a quantum dot LED. Furthermore, the LD can be a device composed of a combination of organic and inorganic materials. Although... Figure 6The pixel PXij is shown to include a single light-emitting element LD, but in one or more embodiments, the pixel PXij may include multiple light-emitting elements LD, and the multiple light-emitting elements LD may be connected in series, in parallel, or in a series-parallel combination.

[0134] The pixel circuit may include a first transistor M21 (e.g., a driving transistor), a second transistor M22 (e.g., a switching transistor), a third transistor M23, a fourth transistor M24, a fifth transistor M25, a sixth transistor M26, a seventh transistor M27, and a storage capacitor Cst.

[0135] The first electrode of the first transistor M21 (or driving transistor) can be connected to the second node N22, and the second electrode can be connected to the third node N23. Furthermore, the gate electrode of the first transistor M21 can be connected to the first node N21. The first transistor M21 can control the amount of current supplied from the first power line PL1 to the second power line PL2 via the light-emitting element LD in response to the voltage of the first node N21.

[0136] The second transistor M22 can be connected between the data line DLj and the second node N22. Furthermore, the gate electrode of the second transistor M22 can be electrically connected to the first scan line SL1i. The second transistor M22 can be turned on when the first scan signal GW is supplied to the first scan line SL1i, thereby electrically connecting the data line DLj and the second node N22.

[0137] The first electrode of the third transistor M23 can be connected to the first node N21, and the second electrode can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the third transistor M23 can be electrically connected to the third scan line SL3i. The third transistor M23 can be turned on when the third scan signal GI is enabled and supplied to the third scan line SL3i to supply the voltage of the first initialization power Vint1 to the first node N21. The first initialization power Vint1 can be set to a voltage lower than the voltage of the data signal supplied to the data line DLj.

[0138] The fourth transistor M24 can be connected between the first node N21 and the third node N23. Furthermore, the gate electrode of the fourth transistor M24 can be electrically connected to the second scan line SL2i. The fourth transistor M24 can be turned on when the second scan signal GC is supplied to the second scan line SL2i to electrically connect the first node N21 and the third node N23. That is, when the fourth transistor M24 is turned on, the first transistor M21 can be connected as a diode (e.g., the first transistor M21 can be connected as a diode).

[0139] The first electrode of the fifth transistor M25 can be electrically connected to the first power line PL1, and the second electrode can be connected to the second node N22. Furthermore, the gate electrode of the fifth transistor M25 can be electrically connected to the emitter control line ELi. The fifth transistor M25 can be turned off when the emitter control signal EM is disabled and supplied to the emitter control line ELi, and when the emitter control signal EM (or the emitter control signal EM disabled) is not supplied (or the emitter control signal EM enabled (see reference...)). Figure 5 When supplied, it is activated.

[0140] The sixth transistor M26 can be connected between the third node N23 and the first electrode of the light-emitting element LD. Furthermore, the gate electrode of the sixth transistor M26 can be electrically connected to the emission control line ELi. The sixth transistor M26 can be turned off when the emission control signal EM is supplied to the emission control line ELi and turned on when the emission control signal EM (or the emission control signal EM is disabled) is not supplied. The sixth transistor M26 can also be turned on when the emission control signal / EM (see reference) is enabled. Figure 5 When supplied to the transmit control line ELi, it is turned on.

[0141] The first electrode of the seventh transistor M27 can be connected to the first electrode of the light-emitting element LD, and the second electrode can be electrically connected to the fourth power line PL4. Furthermore, the gate electrode of the seventh transistor M27 can be electrically connected to the fourth scan line SL4i. The seventh transistor M27 can be turned on when the fourth scan signal GB is supplied to the fourth scan line SL4i to supply the voltage of the second initialization power Vint2 to the first electrode of the light-emitting element LD.

[0142] When the voltage of the second initialization power Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Since the residual voltage in the parasitic capacitor of the light-emitting element LD is discharged (or removed), undesirable weak light emission can be prevented. Therefore, the black level performance of pixel PXij can be improved.

[0143] A storage capacitor Cst can be connected between the first power line PL1 and the first node N21. The storage capacitor Cst can store the voltage applied to the first node N21.

[0144] In one or more embodiments, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be formed of polysilicon semiconductor transistors. For example, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 may include a polysilicon semiconductor layer formed by a low-temperature polysilicon (LTPS) process as an active layer (e.g., a transistor channel). Furthermore, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage for turning on the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be a low level. Because polysilicon semiconductor transistors have the advantage of fast response speed, they can be used in switching elements requiring fast switching.

[0145] In one or more embodiments, the third transistor M23 and the fourth transistor M24 may be formed of oxide semiconductor transistors. For example, the third transistor M23 and the fourth transistor M24 may be N-type oxide semiconductor transistors (e.g., NMOS transistors) and may include an oxide semiconductor layer as an active layer (e.g., a transistor channel). Therefore, the gate turn-on voltage for turning on the third transistor M23 and the fourth transistor M24 may be a high level.

[0146] Oxide-semiconductor (OSB) transistors can be fabricated at low temperatures and have a lower charge mobility than polysilicon (PSB) transistors. In other words, OSB transistors exhibit excellent cutoff current characteristics. Therefore, when the third transistor M23 and the fourth transistor M24 are formed using OSB transistors, leakage current due to low-frequency driving can be reduced or minimized, thus improving display quality.

[0147] Figure 7 It shows the driver Figure 6 The waveform diagram shows an embodiment of the pixel method.

[0148] Reference Figure 6 and Figure 7 A frame period can include a non-transmit period P_NE, which can include an initialization period P_INT, a compensation period P_C, and a write period P_W. The write period P_W can be included in the compensation period P_C.

[0149] During the non-emission period P_NE, the emission disable control signal EM (i.e., a high-level voltage) can be supplied. In this case, the fifth transistor M25 and the sixth transistor M26 can be turned off in response to the emission disable control signal EM, and the pixel PXij can stop emitting light.

[0150] During the initialization period P_INT, the third scan signal GI can be high (i.e., the third scan signal GI can be enabled). In this case, the third transistor M23 can be turned on in response to the enabled third scan signal GI, and the voltage of the first initialization power Vint1 of the third power line PL3 can be provided to the first node N21.

[0151] Subsequently, during the compensation period P_C, the second scan signal GC can be high (i.e., the second scan signal GC can be an enable signal). The fourth transistor M24 can be turned on in response to the enable signal GC, and the first transistor M21 can be connected as a diode (e.g., the first transistor M21 can be connected as a diode).

[0152] During the write phase P_W, the first scan signal GW can be low (i.e., the first scan signal GW can be an enabled first scan signal GW). In this case, the second transistor M22 can be turned on in response to the enabled first scan signal GW, and the data signal can be provided from the j-th data line DLj to the second node N22. Furthermore, because the fourth transistor M24 is turned on in response to the enabled second scan signal GC, the data signal can be transmitted from the second node N22 to the first node N21 via the first transistor M21 and the fourth transistor M24. Because the first transistor M21 is connected in a diode manner through the turned-on fourth transistor M24, the first node N21 can have a voltage in which the threshold voltage of the first transistor M21 is compensated in the data signal.

[0153] Before the write period P_W, the fourth scan signal GB can be at a low level (i.e., the fourth scan signal GB can be enabled). In this case, the seventh transistor M27 can be turned on in response to the enabled fourth scan signal GB, and the voltage of the second initialization power Vint2 can be supplied to the first electrode of the light-emitting element LD.

[0154] After this, the non-transmit period P_NE can end, and the transmit control signal EM can be low (i.e., the transmit control signal EM can be the enable transmit control signal / EM (refer to...)). Figure 5In this configuration, the fifth transistor M25 and the sixth transistor M26 are turned on in response to a low-level transmit control signal EM. When the fifth transistor M25 and the sixth transistor M26 are turned on, a current flow path is formed through the first power line PL1, the fifth transistor M25, the first transistor M21, the sixth transistor M26, and the light-emitting element LD to the second power line PL2. At this time, according to the operation of the first transistor M21, a drive current corresponding to the voltage of the first node N21 can flow through the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the drive current.

[0155] Figure 8 It is shown Figure 1 A diagram of an embodiment of the scan driver shown. Figure 9 It is shown Figure 8 A diagram illustrating an embodiment of the clock controller. Figure 8 The clock controller 170a and the transmitter driver 150 are also shown.

[0156] Reference Figure 8 and Figure 9 The scan driver 130 may include a first scan driver 132 for sequentially outputting a first scan signal GW, a second scan driver 134 for sequentially outputting a second scan signal GC, a third scan driver 136 for sequentially outputting a third scan signal GI, and a fourth scan driver 138 for sequentially outputting a fourth scan signal GB. In one or more embodiments, the third scan driver 136 may be replaced by the second scan driver 134, and the fourth scan driver 138 may be replaced by the first scan driver 132.

[0157] The first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 can be driven in response to different clock signals. In this case, the clock controller 170a can supply different selection clock signals GW_sCK, GC_sCK, GI_sCK, and GB_sCK to the corresponding first scan driver 132, second scan driver 134, third scan driver 136, and fourth scan driver 138.

[0158] Timing controller 120 (reference) Figure 1 The clock controller 170a can be supplied with clock signals GW_CK1 and GW_CK2 (or write clock signals) required to drive the first scan driver 132 via clock lines GW_CKL1 and GW_CKL2. The second input terminal IN2, included in each clock selection circuit COS, can be connected to clock line GW_CKL1, and the third input terminal IN3 can be connected to clock line GW_CKL2.

[0159] The timing controller 120 can supply the clock signals GC_CK1 and GC_CK2 (or compensation clock signals) required to drive the second scan driver 134 to the clock controller 170a via clock lines GC_CKL1 and GC_CKL2. The fourth input terminal IN4, included in each clock selection circuit COS, can be connected to the clock line GC_CKL1, and the fifth input terminal IN5 can be connected to the clock line GC_CKL2.

[0160] The timing controller 120 can supply the clock signals GI_CK1 and GI_CK2 required to drive the third scan driver 136 to the clock controller 170a via clock lines GI_CKL1 and GI_CKL2. The sixth input terminal IN6, included in each clock selection circuit COS, can be connected to the clock line GI_CKL1, and the seventh input terminal IN7 can be connected to the clock line GI_CKL2.

[0161] The timing controller 120 can supply the clock signals GB_CK1 and GB_CK2 required to drive the fourth scan driver 138 to the clock controller 170a via clock lines GB_CKL1 and GB_CKL2. The eighth input terminal IN8, included in each clock selection circuit COS, can be connected to the clock line GB_CKL1, and the ninth input terminal IN9 can be connected to the clock line GB_CKL2.

[0162] Clock controller 170a can receive a disable transmit control signal EM from transmit driver 150 and clock signals GW_CK1, GW_CK2, GC_CK1, GC_CK2, GI_CK1, GI_CK2, GB_CK1, and GB_CK2 from timing controller 120. Clock controller 170a can sequentially output selection clock signals GW_sCK, GC_sCK, GI_sCK, and GB_sCK in horizontal line order in response to the disable transmit control signal EM supplied in horizontal line units.

[0163] In one or more embodiments, the clock controller 170a may output selection clock signals GW_sCK11, GW_sCK21, GC_sCK11, GC_sCK21, GI_sCK11, GI_sCK21, GB_sCK11, and GB_sCK21 corresponding to the first horizontal line during the period in which the transmit control signal EM is disabled and supplied to the first transmit control line EL1. For example, the clock selection signal GW_sCK11 can be output to the first output terminal OUT1 of the first clock selection circuit COS1, the clock selection signal GW_sCK21 can be output to the second output terminal OUT2, the clock selection signal GC_sCK11 can be output to the third output terminal OUT3, the clock selection signal GC_sCK21 can be output to the fourth output terminal OUT4, the clock selection signal GI_sCK11 can be output to the fifth output terminal OUT5, the clock selection signal GI_sCK21 can be output to the sixth output terminal OUT6, the clock selection signal GB_sCK11 can be output to the seventh output terminal OUT7, and the clock selection signal GB_sCK21 can be output to the eighth output terminal OUT8.

[0164] Here, the selection clock signals GW_sCK11 and GW_sCK21 can be supplied to the first scan driver 132, the selection clock signals GC_sCK11 and GC_sCK21 can be supplied to the second scan driver 134, the selection clock signals GI_sCK11 and GI_sCK21 can be supplied to the third scan driver 136, and the selection clock signals GB_sCK11 and GB_sCK21 can be supplied to the fourth scan driver 138.

[0165] The first scan driver 132, which receives the selection clock signals GW_sCK11 and GW_sCK21, can supply the first scan signal GW (see reference) to the first scan line SL11. Figure 6 The second scan driver 134, which receives the selection clock signals GC_sCK11 and GC_sCK21, can supply the second scan line SL21 with the enable signal GC (see reference). Figure 6 The third scan driver 136, which receives the selection clock signals GI_sCK11 and GI_sCK21, can supply the third scan line SL31 with the enable signal GI (see reference). Figure 6 The fourth scan driver 138, which receives the selection clock signals GB_sCK11 and GB_sCK21, can supply the fourth scan line SL41 with the enable signal GB (see reference). Figure 6 ).

[0166] In one or more embodiments, the clock controller 170a may output selection clock signals GW_sCK12, GW_sCK22, GC_sCK12, GC_sCK22, GI_sCK12, GI_sCK22, GB_sCK12, and GB_sCK22 corresponding to the second horizontal line during the period in which the transmit control signal EM is disabled and supplied to the second transmit control line EL2. For example, the clock selection signal GW_sCK12 can be output to the first output terminal OUT1 of the second clock selection circuit COS2, the clock selection signal GW_sCK22 can be output to the second output terminal OUT2, the clock selection signal GC_sCK12 can be output to the third output terminal OUT3, the clock selection signal GC_sCK22 can be output to the fourth output terminal OUT4, the clock selection signal GI_sCK12 can be output to the fifth output terminal OUT5, the clock selection signal GI_sCK22 can be output to the sixth output terminal OUT6, the clock selection signal GB_sCK12 can be output to the seventh output terminal OUT7, and the clock selection signal GB_sCK22 can be output to the eighth output terminal OUT8.

[0167] Here, the selection clock signals GW_sCK12 and GW_sCK22 can be output to the first scan driver 132, the selection clock signals GC_sCK12 and GC_sCK22 can be supplied to the second scan driver 134, the selection clock signals GI_sCK12 and GI_sCK22 can be supplied to the third scan driver 136, and the selection clock signals GB_sCK12 and GB_sCK22 can be supplied to the fourth scan driver 138.

[0168] A first scan driver 132, receiving selection clock signals GW_sCK12 and GW_sCK22, can supply an enable signal GW to the first scan line SL12. A second scan driver 134, receiving selection clock signals GC_sCK12 and GC_sCK22, can supply an enable signal GC to the second scan line SL22. A third scan driver 136, receiving selection clock signals GI_sCK12 and GI_sCK22, can supply an enable signal GI to the third scan line SL32. A fourth scan driver 138, receiving selection clock signals GB_sCK12 and GB_sCK22, can supply an enable signal GB to the fourth scan line SL42.

[0169] In one or more embodiments, the clock controller 170a may output selection clock signals GW_sCK1n, GW_sCK2n, GC_sCK1n, GC_sCK2n, GI_sCK1n, GI_sCK2n, GB_sCK1n, and GB_sCK2n corresponding to the nth horizontal line during the period in which the transmit control signal EM is disabled and supplied to the nth transmit control line ELn. For example, the clock selection signal GW_sCK1n can be output to the first output terminal OUT1 of the nth clock selection circuit COSn, the clock selection signal GW_sCK2n can be output to the second output terminal OUT2, the clock selection signal GC_sCK1n can be output to the third output terminal OUT3, the clock selection signal GC_sCK2n can be output to the fourth output terminal OUT4, the clock selection signal GI_sCK1n can be output to the fifth output terminal OUT5, the clock selection signal GI_sCK2n can be output to the sixth output terminal OUT6, the clock selection signal GB_sCK1n can be output to the seventh output terminal OUT7, and the clock selection signal GB_sCK2n can be output to the eighth output terminal OUT8.

[0170] Here, the selection clock signals GW_sCK1n and GW_sCK2n can be supplied to the first scan driver 132, the selection clock signals GC_sCK1n and GC_sCK2n can be supplied to the second scan driver 134, the selection clock signals GI_sCK1n and GI_sCK2n can be supplied to the third scan driver 136, and the selection clock signals GB_sCK1n and GB_sCK2n can be supplied to the fourth scan driver 138.

[0171] A first scan driver 132, receiving selection clock signals GW_sCK1n and GW_sCK2n, can supply an enable signal GW to the first scan line SL1n. A second scan driver 134, receiving selection clock signals GC_sCK1n and GC_sCK2n, can supply an enable signal GC to the second scan line SL2n. A third scan driver 136, receiving selection clock signals GI_sCK1n and GI_sCK2n, can supply an enable signal GI to the third scan line SL3n. A fourth scan driver 138, receiving selection clock signals GB_sCK1n and GB_sCK2n, can supply an enable signal GB to the fourth scan line SL4n.

[0172] The clock selection circuit (COS) can be positioned for each horizontal line, and each clock selection circuit (COS) can be connected to the transmit control line EL corresponding to the horizontal line in which it is positioned. For example, the first input terminal IN1 of the first clock selection circuit COS1 positioned in the first horizontal line can be connected to the first transmit control line EL1, and the first input terminal IN1 of the nth clock selection circuit COSn positioned in the nth horizontal line can be connected to the nth transmit control line ELn.

[0173] Figure 10 It is shown Figure 9 A diagram of an embodiment of the clock selection circuit shown. Figure 10 The i-th clock selection circuit COSi is shown. In the description... Figure 10 At that time, briefly describe and Figure 3 The configuration is the same or similar to the configuration.

[0174] Reference Figure 10 According to one or more embodiments of the present invention, the clock selection circuit COSi may include an inverter 172 and controllers 174a, 174b, 174c and 174d.

[0175] Inverter 172 is connected to the first input terminal IN1. The first input terminal IN1 is connected to the i-th transmit control line ELi and receives the disable transmit control signal EM from the i-th transmit control line ELi. Inverter 172 can generate an enable transmit control signal / EM by inverting the disable transmit control signal EM. Here, the disable transmit control signal EM can have a high-level voltage, and the enable transmit control signal / EM can have a low-level voltage.

[0176] Inverter 172 may include a first transistor M1 and a second transistor M2 connected in series between a first power source VGH and a second power source VGL. The first power source VGH may be set to a high-level voltage, and the second power source VGL may be set to a low-level voltage lower than the voltage level of the first power source VGH.

[0177] The first transistor M1 can be connected between the first power source VGH and the first node N1, and the gate electrode of the first transistor M1 can be connected to the first input terminal IN1. The first transistor M1 can be turned off when the disable emitter control signal EM is supplied, and can be turned on when a low-level voltage signal is supplied to the gate electrode. For this purpose, the first transistor M1 can be configured as a P-type transistor.

[0178] The second transistor M2 can be connected between the first node N1 and the second power source VGL, and the gate electrode of the second transistor M2 can be connected to the first input terminal IN1. The second transistor M2 can be turned on when the disable transmit control signal EM is supplied, and can be turned off when a low-level voltage signal is supplied to the gate electrode. For this purpose, the second transistor M2 can be configured as an N-type transistor.

[0179] When the transmit disable control signal EM is supplied to the first input terminal IN1, the first controller 174a can electrically connect the second input terminal IN2 to the first output terminal OUT1 and the third input terminal IN3 to the second output terminal OUT2. For this purpose, the first controller 174a may include a first transmission gate TG11 and a second transmission gate TG12.

[0180] The first transmission gate TG11 can be connected between the second input terminal IN2 and the first output terminal OUT1. The first transmission gate TG11 controls the electrical connection between the second input terminal IN2 and the first output terminal OUT1 in response to the disable transmit control signal EM and the enable transmit control signal / EM. For this purpose, the first transmission gate TG11 may include a third transistor M3a and a fourth transistor M4a.

[0181] The third transistor M3a can be connected between the second input terminal IN2 and the first output terminal OUT1, and the gate electrode of the third transistor M3a can be connected to the first node N1. The third transistor M3a can be turned on when the enable transmit control signal / EM is supplied to the first node N1 to electrically connect the second input terminal IN2 and the first output terminal OUT1. For this purpose, the third transistor M3a can be configured as a P-type transistor.

[0182] The fourth transistor M4a can be connected between the second input terminal IN2 and the first output terminal OUT1, and the gate electrode of the fourth transistor M4a can be connected to the first input terminal IN1. The fourth transistor M4a can be turned on when the disable transmit control signal EM is supplied to the first input terminal IN1 to electrically connect the second input terminal IN2 and the first output terminal OUT1. For this purpose, the fourth transistor M4a can be configured as an N-type transistor.

[0183] The second transmission gate TG12 can be connected between the third input terminal IN3 and the second output terminal OUT2. The second transmission gate TG12 controls the electrical connection between the third input terminal IN3 and the second output terminal OUT2 in response to the disable transmit control signal EM and the enable transmit control signal / EM. For this purpose, the second transmission gate TG12 may include a fifth transistor M5a and a sixth transistor M6a.

[0184] The fifth transistor M5a can be connected between the third input terminal IN3 and the second output terminal OUT2, and the gate electrode of the fifth transistor M5a can be connected to the first node N1. The fifth transistor M5a can be turned on when the enable transmit control signal / EM is supplied to the first node N1 to electrically connect the third input terminal IN3 and the second output terminal OUT2. For this purpose, the fifth transistor M5a can be configured as a P-type transistor.

[0185] The sixth transistor M6a can be connected between the third input terminal IN3 and the second output terminal OUT2, and the gate electrode of the sixth transistor M6a can be connected to the first input terminal IN1. The sixth transistor M6a can be turned on when the disable emitter control signal EM is supplied to the first input terminal IN1, so as to electrically connect the third input terminal IN3 and the second output terminal OUT2. For this purpose, the sixth transistor M6a can be configured as an N-type transistor.

[0186] When the transmit disable control signal EM is supplied to the first input terminal IN1, the second controller 174b can electrically connect the fourth input terminal IN4 to the third output terminal OUT3 and the fifth input terminal IN5 to the fourth output terminal OUT4. For this purpose, the second controller 174b may include a first transmission gate TG21 and a second transmission gate TG22.

[0187] The first transmission gate TG21 can be connected between the fourth input terminal IN4 and the third output terminal OUT3. When the disable transmit control signal EM is input to the first input terminal IN1 and the enable transmit control signal / EM is input to the first node N1, the first transmission gate TG21 can electrically connect the fourth input terminal IN4 and the third output terminal OUT3. For this purpose, the first transmission gate TG21 may include a P-type third transistor M3b and an N-type fourth transistor M4b, with the gate electrode of the P-type third transistor M3b connected to the first node N1 and the gate electrode of the N-type fourth transistor M4b connected to the first input terminal IN1.

[0188] The second transmission gate TG22 can be connected between the fifth input terminal IN5 and the fourth output terminal OUT4. When the disable transmit control signal EM is input to the first input terminal IN1 and the enable transmit control signal / EM is input to the first node N1, the second transmission gate TG22 can electrically connect the fifth input terminal IN5 and the fourth output terminal OUT4. For this purpose, the second transmission gate TG22 may include a P-type fifth transistor M5b and an N-type sixth transistor M6b, with the gate electrode of the P-type fifth transistor M5b connected to the first node N1 and the gate electrode of the N-type sixth transistor M6b connected to the first input terminal IN1.

[0189] When the transmit disable control signal EM is supplied to the first input terminal IN1, the third controller 174c can electrically connect the sixth input terminal IN6 to the fifth output terminal OUT5 and the seventh input terminal IN7 to the sixth output terminal OUT6. For this purpose, the third controller 174c may include a first transmission gate TG31 and a second transmission gate TG32.

[0190] The first transmission gate TG31 can be connected between the sixth input terminal IN6 and the fifth output terminal OUT5. When the disable transmit control signal EM is input to the first input terminal IN1 and the enable transmit control signal / EM is input to the first node N1, the first transmission gate TG31 can electrically connect the sixth input terminal IN6 and the fifth output terminal OUT5. For this purpose, the first transmission gate TG31 may include a P-type third transistor M3c and an N-type fourth transistor M4c, with the gate electrode of the P-type third transistor M3c connected to the first node N1 and the gate electrode of the N-type fourth transistor M4c connected to the first input terminal IN1.

[0191] The second transmission gate TG32 can be connected between the seventh input terminal IN7 and the sixth output terminal OUT6. When the disable transmit control signal EM is input to the first input terminal IN1 and the enable transmit control signal / EM is input to the first node N1, the second transmission gate TG32 can electrically connect the seventh input terminal IN7 and the sixth output terminal OUT6. For this purpose, the second transmission gate TG32 may include a P-type fifth transistor M5c and an N-type sixth transistor M6c, with the gate electrode of the P-type fifth transistor M5c connected to the first node N1 and the gate electrode of the N-type sixth transistor M6c connected to the first input terminal IN1.

[0192] When the transmit disable control signal EM is supplied to the first input terminal IN1, the fourth controller 174d can electrically connect the eighth input terminal IN8 to the seventh output terminal OUT7 and the ninth input terminal IN9 to the eighth output terminal OUT8. For this purpose, the fourth controller 174d may include a first transmission gate TG41 and a second transmission gate TG42.

[0193] The first transmission gate TG41 can be connected between the eighth input terminal IN8 and the seventh output terminal OUT7. When the disable transmit control signal EM is input to the first input terminal IN1 and the enable transmit control signal / EM is input to the first node N1, the first transmission gate TG41 can electrically connect the eighth input terminal IN8 and the seventh output terminal OUT7. For this purpose, the first transmission gate TG41 may include a P-type third transistor M3d and an N-type fourth transistor M4d, with the gate electrode of the P-type third transistor M3d connected to the first node N1 and the gate electrode of the N-type fourth transistor M4d connected to the first input terminal IN1.

[0194] The second transmission gate TG42 can be connected between the ninth input terminal IN9 and the eighth output terminal OUT8. When the disable transmit control signal EM is input to the first input terminal IN1 and the enable transmit control signal / EM is input to the first node N1, the second transmission gate TG42 can electrically connect the ninth input terminal IN9 and the eighth output terminal OUT8. For this purpose, the second transmission gate TG42 may include a P-type fifth transistor M5d and an N-type sixth transistor M6d, with the gate electrode of the P-type fifth transistor M5d connected to the first node N1 and the gate electrode of the N-type sixth transistor M6d connected to the first input terminal IN1.

[0195] When describing the operation process, when the disable transmit control signal EM is supplied to the i-th transmit control line ELi, the enable transmit control signal / EM can be supplied to the first node N1 through the inverter 172.

[0196] Then, transistors M3a to M3d, M4a to M4d, M5a to M5d and M6a to M6d in each of the controllers 174a to 174d can be turned on, and thus can output selection clock signals GW_sCK1i, GW_sCK2i, GC_sCK1i, GC_sCK2i, GI_sCK1i, GI_sCK2i, GB_sCK1i and GB_sCK2i.

[0197] like Figure 7 As shown, the disable transmit control signal EM is supplied to overlap with the enable scan signals GW, GC, GI, and GB. Therefore, when the select clock signals GW_sCK1i, GW_sCK2i, GC_sCK1i, GC_sCK2i, GI_sCK1i, GI_sCK2i, GB_sCK1i, and GB_sCK2i are output during the period in which the disable transmit control signal EM is supplied, the scan signals GW, GC, GI, and GB can be generated stably.

[0198] although Figure 10 Four controllers 174a to 174d are shown, but the invention is not limited thereto. Clock selection circuit COS (see reference). Figure 9 It may include an inverter 172 and one or more controllers. The number of controllers included in the clock selection circuit COS can be set differently to correspond to the number of scan drivers.

[0199] In addition, Figure 3 and Figure 10In the present invention, inverter 172, included in the clock selection circuit COS, receives a disable transmit control signal EM, but the invention is not limited thereto. For example, inverter 172 may receive the widest signal among signals supplied in units of horizontal lines (e.g., scan signals and transmit control signals, etc.) that overlaps with other signals.

[0200] Figure 11 It is shown Figure 1 A diagram of an embodiment of a scan driver and clock controller. Figure 11 The image also shows a transmitter driver 150.

[0201] Reference Figure 11 The scan driver 130 may include a signal GW for sequentially outputting an enable signal for the first scan (see reference). Figure 6 The first scan driver 132a and the second scan enable signal GC (refer to) for sequentially outputting the second scan signal (refer to) Figure 6 The second scan driver 134a. In this case, Figure 1 The third scan line SL3 shown can be driven by the second scan driver 134a, and Figure 1 The fourth scan line SL4 shown can be driven by the first scan driver 132a.

[0202] Timing controller 120 (reference) Figure 1 The clock signals GW_CK1 and GW_CK2 required to drive the first scan driver 132a can be supplied to the first clock controller 171 via clock lines GW_CKL1 and GW_CKL2. The first clock controller 171 may include a first clock selection circuit positioned for each horizontal line, including a second input terminal IN2a in each first clock selection circuit (see reference). Figure 12 It can be connected to the clock line GW_CKL1, and the third input terminal IN3a (refer to...) Figure 12 It can be connected to the clock line GW_CKL2.

[0203] Timing controller 120 can supply clock signals GC_CK1 and GC_CK2 required to drive the second scan driver 134a to second clock controller 173 via clock lines GC_CKL1 and GC_CKL2. Second clock controller 173 may include second clock selection circuitry positioned for each horizontal line, including a second input terminal IN2b in each second clock selection circuitry (see reference). Figure 12 It can be connected to the clock line GC_CKL1, and the third input terminal IN3b (refer to...) Figure 12 It can be connected to the clock line GC_CKL2.

[0204] The first clock controller 171 may receive an enable second scan signal GC from the second scan driver 134a and clock signals GW_CK1 and GW_CK2 from the timing controller 120. The first clock controller 171 may output clock signals GW_CK1 and GW_CK2 sequentially in horizontal line units in response to the enable second scan signal GC supplied in horizontal line units.

[0205] In one or more embodiments, the first clock controller 171 may output selection clock signals GW_sCK11 and GW_sCK21 corresponding to the first horizontal line during the period in which the second scan signal GC is enabled and supplied to the second scan line SL21. The first scan driver 132a that receives the selection clock signals GW_sCK11 and GW_sCK21 may supply the first scan signal GW to the first scan line SL11 to enable the first scan signal GW.

[0206] In one or more embodiments, the first clock controller 171 may output selection clock signals GW_sCK12 and GW_sCK22 corresponding to the second horizontal line during the period in which the second scan signal GC is enabled and supplied to the second scan line SL22. The first scan driver 132a that receives the selection clock signals GW_sCK12 and GW_sCK22 may supply the first scan signal GW to the first scan line SL12.

[0207] In one or more embodiments, the first clock controller 171 may output selection clock signals GW_sCK1n and GW_sCK2n corresponding to the nth horizontal line during the period in which the second scan signal GC is enabled and supplied to the second scan line SL2n. The first scan driver 132a that receives the selection clock signals GW_sCK1n and GW_sCK2n may supply the first scan signal GW to the first scan line SL1n.

[0208] like Figure 7 As shown, the second scan signal GC supplied to the i-th second scan line SL2i is supplied to overlap with the first scan signal GW supplied to the i-th first scan line SL1i. Therefore, even if the second scan signal GC is supplied to the first clock controller 171, the first scan signal GW can be stably generated in units of horizontal lines.

[0209] The second clock controller 173 can receive a disable transmit control signal EM from the transmit driver 150 (see reference). Figure 12 The second clock controller 173 can sequentially output clock signals GC_CK1 and GC_CK2 in horizontal line order in response to a disable transmit control signal EM supplied in horizontal line units.

[0210] In one or more embodiments, the second clock controller 173 may output selection clock signals GC_sCK11 and GC_sCK21 corresponding to the first horizontal line during a period in which the transmit control signal EM is disabled and supplied to the transmit control line EL1. The second scan driver 134a, which receives the selection clock signals GC_sCK11 and GC_sCK21, may supply an enable second scan signal GC to the second scan line SL21.

[0211] In one or more embodiments, the second clock controller 173 may output selection clock signals GC_sCK12 and GC_sCK22 corresponding to the second horizontal line during the period in which the transmit control signal EM is disabled and supplied to the transmit control line EL2. The second scan driver 134a, which receives the selection clock signals GC_sCK12 and GC_sCK22, may supply an enable second scan signal GC to the second scan line SL22.

[0212] In one or more embodiments, the second clock controller 173 may output selection clock signals GC_sCK1n and GC_sCK2n corresponding to the nth horizontal line during the period in which the transmit control signal EM is disabled and supplied to the transmit control line ELn. The second scan driver 134a, which receives the selection clock signals GC_sCK1n and GC_sCK2n, may supply an enable second scan signal GC to the second scan line SL2n.

[0213] Figure 12 It is shown that it includes Figure 11 A circuit diagram of an embodiment of the clock selection circuit in each of the first and second clock controllers. Figure 12 The i-th first clock selection circuit COS1i and the i-th second clock selection circuit COS2i are shown. In the description... Figure 12 At that time, briefly describe and Figure 3 The configuration is similar to that of the previous one.

[0214] Reference Figure 12 The first clock selection circuit COS1i may include an inverter 172a and a controller 176a.

[0215] Inverter 172a is connected to a first input terminal IN1a. The first input terminal IN1a can be connected to the i-th second scan line SL2i and can receive an enable second scan signal GC from the i-th second scan line SL2i. Inverter 172a may include a P-type first transistor M11a and an N-type second transistor M12a connected in series between a first power source VGH and a second power source VGL.

[0216] When the second scan signal GC is enabled and input to the first input terminal IN1a, the controller 176a can electrically connect the second input terminal IN2a to the first output terminal OUT1a and the third input terminal IN3a to the second output terminal OUT2a. For this purpose, the controller 176a may include a first transmission gate TG1a and a second transmission gate TG2a.

[0217] The first transmission gate TG1a can be connected between the second input terminal IN2a and the first output terminal OUT1a. When the second scan signal GC is enabled and input to the first input terminal IN1a, the first transmission gate TG1a can electrically connect the second input terminal IN2a and the first output terminal OUT1a. For this purpose, the first transmission gate TG1a may include a P-type third transistor M13a and an N-type fourth transistor M14a.

[0218] The second transmission gate TG2a can be connected between the third input terminal IN3a and the second output terminal OUT2a. When the second scan signal GC is enabled and input to the first input terminal IN1a, the second transmission gate TG2a can electrically connect the third input terminal IN3a and the second output terminal OUT2a. For this purpose, the second transmission gate TG2a may include a P-type fifth transistor M15a and an N-type sixth transistor M16a.

[0219] When the enable signal GC for the second scan is input, the first clock selection circuit COS1i can output selection clock signals GW_sCK1i and GW_sCK2i, and the operation of the first clock selection circuit COS1i can be synchronized with... Figure 3 The operation of the clock selection circuit COSi is similar to or the same.

[0220] The second clock selection circuit COS2i may include an inverter 172b and a controller 176b.

[0221] Inverter 172b is connected to the first input terminal IN1b. The first input terminal IN1b can be connected to the i-th transmit control line ELi and can receive the disable transmit control signal EM from the i-th transmit control line ELi. Inverter 172b may include a P-type first transistor M11b and an N-type second transistor M12b connected in series between the first power source VGH and the second power source VGL.

[0222] When the transmit disable control signal EM is input to the first input terminal IN1b, the controller 176b can electrically connect the second input terminal IN2b to the first output terminal OUT1b and the third input terminal IN3b to the second output terminal OUT2b. For this purpose, the controller 176b may include a first transmission gate TG1b and a second transmission gate TG2b.

[0223] The first transmission gate TG1b can be connected between the second input terminal IN2b and the first output terminal OUT1b. When the transmit disable control signal EM is input to the first input terminal IN1b, the first transmission gate TG1b can be electrically connected between the second input terminal IN2b and the first output terminal OUT1b. For this purpose, the first transmission gate TG1b may include a P-type third transistor M13b and an N-type fourth transistor M14b.

[0224] The second transmission gate TG2b can be connected between the third input terminal IN3b and the second output terminal OUT2b. When the transmit disable control signal EM is input to the first input terminal IN1b, the second transmission gate TG2b can electrically connect the third input terminal IN3b and the second output terminal OUT2b. For this purpose, the second transmission gate TG2b may include a P-type fifth transistor M15b and an N-type sixth transistor M16b.

[0225] When the transmit disable control signal EM is input, the second clock selection circuit COS2i can output select clock signals GC_sCK1i and GC_sCK2i, and the operation of the second clock selection circuit COS2i can be synchronized with... Figure 3 The operation of the clock selection circuit COSi is similar to or the same.

[0226] Figure 13a and Figure 13b It is shown Figure 1 A diagram illustrating an embodiment of the clock selection circuit and stage circuit of a display device. Figure 13a and Figure 13b This illustrates the case where the input cells of the STi stage circuit include only P-type transistors or N-type transistors. When describing... Figure 13a and Figure 13b At that time, the same reference numerals were assigned to the same figures. Figure 3 (or Figure 4 The configuration is the same as the previous one, and detailed descriptions are omitted.

[0227] Reference Figure 13a and Figure 13b The clock selection circuit COSi includes an inverter 172 and a controller 178.

[0228] When the transmit disable control signal EM is supplied to the first input terminal IN1, the controller 178 can electrically connect the second input terminal IN2 and the first output terminal OUT1. The second input terminal IN2 can be connected to the clock line CKL1 and can receive the clock signal CK1 from the clock line CKL1.

[0229] The controller 178 may include a transmission gate TG1c connected between the second input terminal IN2 and the first output terminal OUT1. The transmission gate TG1c may include a P-type third transistor M3 and an N-type fourth transistor M4.

[0230] The gate electrode of the third transistor M3 can be connected to the first node N1, and the third transistor M3 can be turned on when the enable transmit control signal / EM is supplied to the first node N1. The gate electrode of the fourth transistor M4 can be connected to the first input terminal IN1, and the fourth transistor M4 can be turned on when the disable transmit control signal EM is supplied to the first input terminal IN1. That is, when the disable transmit control signal EM is supplied to the first input terminal IN1, the clock selection circuit COSi can supply the selection clock signal sCK1i to the first output terminal OUT1.

[0231] The input unit 131a or 131b of the stage circuit STi may include a transistor M1b or M1c. For example, input unit 131a may include a P-type first input transistor M1b. For example, input unit 131b may include an N-type first input transistor M1c.

[0232] When the selection clock signal sCK1i is supplied, input units 131a and 131b can supply the previous stage output signal OSi-1 to output units 133a and 133b. The output units 133a and 133b can be configured using various currently known circuits.

[0233] Although the above description has been made with reference to embodiments of the present invention, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the claims.

Claims

1. A clock selection circuit, comprising: An inverter is configured to receive an input signal via a first input terminal; as well as At least one controller is configured to receive at least one clock signal and to output the clock signal when the input signal is supplied to the inverter.

2. The clock selection circuit according to claim 1, wherein, The inverter includes a P-type first transistor and an N-type second transistor connected in series between a first power source and a second power source, wherein the second power source has a voltage lower than that of the first power source. The gate electrode of the first transistor and the gate electrode of the second transistor are connected to the first input terminal.

3. The clock selection circuit according to claim 2, wherein, The controller includes a first transmission gate connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first clock signal. The first transmission gate includes a P-type third transistor and an N-type fourth transistor connected in parallel between the second input terminal and the first output terminal. The gate electrode of the third transistor is connected to the first node, which is a common node of the first transistor and the second transistor, and the gate electrode of the fourth transistor is connected to the first input terminal.

4. The clock selection circuit according to claim 3, wherein, When the input signal is input to the first input terminal, the third transistor and the fourth transistor are turned on, and when the input signal is not supplied, the third transistor and the fourth transistor are turned off.

5. The clock selection circuit according to claim 3, wherein, The controller further includes a second transmission gate connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second clock signal. The second transmission gate includes a P-type fifth transistor and an N-type sixth transistor connected in parallel between the third input terminal and the second output terminal. The gate electrode of the fifth transistor is connected to the first node, and the gate electrode of the sixth transistor is connected to the first input terminal.

6. The clock selection circuit according to claim 5, wherein, When the input signal is input to the first input terminal, the fifth transistor and the sixth transistor are turned on, and when the input signal is not supplied, the fifth transistor and the sixth transistor are turned off.

7. A display device, comprising: Pixels are connected to scan lines, emission control lines, and data lines; A scan driver is configured to supply scan signals to the scan lines; A transmit driver is configured to supply transmit control signals to the transmit control line; as well as A clock controller is configured to receive at least one clock signal driving the scan driver and is configured to determine whether to supply the clock signal to the scan driver in response to the transmit control signal.

8. The display device according to claim 7, wherein, The clock controller is configured to receive the transmit control signal sequentially in units of horizontal lines, and is configured to output the clock signal in units of horizontal lines in response to the transmit control signal.

9. The display device according to claim 8, wherein, The clock controller includes multiple clock selection circuits, and the scan driver includes multiple stages of circuitry. Specifically, the i-th (i is a natural number) clock selection circuit at the i-th horizontal line is configured to supply the clock signal to the i-th stage circuit at the i-th horizontal line when the transmit control signal is supplied to the i-th transmit control line.

10. The display device according to claim 9, wherein, The i-th clock selection circuit does not supply the clock signal to the i-th stage circuit when the transmit control signal is not supplied to the i-th transmit control line.

11. The display device according to claim 9, wherein, The i-th clock selection circuit includes: The first input terminal is connected to the i-th transmit control line; Inverter, connected to the first input terminal; and A controller is connected to the first input terminal and the first node, the first node being the output node of the inverter, and the controller is configured to supply the clock signal to the i-th stage circuit when the transmit control signal is supplied to the first input terminal.

12. The display device according to claim 11, wherein, The inverter includes a P-type first transistor and an N-type second transistor connected in series between a first power source and a second power source, wherein the second power source has a voltage lower than that of the first power source. The gate electrode of the first transistor and the gate electrode of the second transistor are connected to the first input terminal.

13. The display device according to claim 11, wherein, The controller includes a first transmission gate connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first clock signal. The first transmission gate includes a P-type third transistor and an N-type fourth transistor connected in parallel between the second input terminal and the first output terminal. The gate electrode of the third transistor is connected to the first node, and the gate electrode of the fourth transistor is connected to the first input terminal.

14. The display device according to claim 13, wherein, When the first transmission gate is turned on, the first clock signal is supplied to the i-th stage circuit via the first output terminal.

15. The display device according to claim 13, wherein, The controller further includes a second transmission gate connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second clock signal. The second transmission gate includes a P-type fifth transistor and an N-type sixth transistor connected in parallel between the third input terminal and the second output terminal. The gate electrode of the fifth transistor is connected to the first node, and the gate electrode of the sixth transistor is connected to the first input terminal.

16. The display device according to claim 15, wherein, When the second transmission gate is turned on, the second clock signal is supplied to the i-th stage circuit via the second output terminal.

17. The display device according to claim 8, wherein, The scan lines include a first scan line and a second scan line respectively located at the horizontal line, and The scan driver includes a first scan driver configured to drive the first scan line and a second scan driver configured to drive the second scan line.

18. The display device according to claim 17, wherein, The clock signal includes at least one write clock signal for driving the first scan driver and at least one compensation clock signal for driving the second scan driver.

19. The display device according to claim 18, wherein, The clock controller includes multiple clock selection circuits, the first scan driver includes multiple write stage circuits, and the second scan driver includes multiple compensation stage circuits. When the transmit control signal is supplied to the i-th (i is a natural number) transmit control line, the i-th clock selection circuit at the i-th horizontal line is configured to supply the write clock signal to the i-th write stage circuit at the i-th horizontal line, and is configured to supply the compensation clock signal to the i-th compensation stage circuit at the i-th horizontal line.

20. The display device according to claim 19, wherein, When the transmit control signal is not supplied to the i-th transmit control line, the i-th clock selection circuit does not supply the write clock signal to the i-th write stage circuit and does not supply the compensation clock signal to the i-th compensation stage circuit.

21. The display device according to claim 19, wherein, The i-th clock selection circuit includes: The first input terminal is connected to the i-th transmit control line; Inverter, connected to the first input terminal; A first controller, connected to the first input terminal and a first node, the first node being the output node of the inverter, and configured to supply the write clock signal to the i-th write stage circuit when the transmit control signal is supplied to the first input terminal; and A second controller is connected to the first input terminal and the first node, and is configured to supply the compensation clock signal to the i-th compensation stage circuit when the transmit control signal is supplied to the first input terminal.

22. The display device according to claim 21, wherein, The inverter includes a P-type first transistor and an N-type second transistor connected in series between a first power source and a second power source, wherein the second power source has a voltage lower than that of the first power source. The gate electrode of the first transistor and the gate electrode of the second transistor are connected to the first input terminal.

23. The display device according to claim 21, wherein, The first controller includes: A first transmission gate is connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first write clock signal, and the first transmission gate is configured to turn on when the transmit control signal is supplied to the first input terminal; and A second transmission gate is connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second write clock signal, and the second transmission gate is configured to be turned on when the transmit control signal is supplied to the first input terminal.

24. The display device according to claim 22, wherein, The second controller includes: A first transmission gate is connected between a first output terminal and a second input terminal, the second input terminal being connected to a first clock line configured to receive a first compensated clock signal, and the first transmission gate is configured to turn on when the transmit control signal is supplied to the first input terminal; and A second transmission gate is connected between a second output terminal and a third input terminal, the third input terminal being connected to a second clock line configured to receive a second compensation clock signal, and the second transmission gate is configured to be turned on when the transmit control signal is supplied to the first input terminal.

25. A display device, comprising: Pixels are connected to the first scan line, the second scan line, the emission control line, and the data line; A first scan driver is configured to supply a first scan signal to the first scan line; A second scan driver is configured to supply a second scan signal to the second scan line; A transmit driver is configured to supply transmit control signals to the transmit control line; A first clock controller is configured to receive at least one write clock signal driving the first scan driver, and is configured to determine whether to supply the write clock signal in response to the second scan signal; as well as A second clock controller is configured to receive at least one compensation clock signal driving the second scan driver, and is configured to determine whether to supply the compensation clock signal in response to the transmit control signal.

26. The display device according to claim 25, wherein, The first clock controller is further configured to receive the second scan signal sequentially in units of horizontal lines, and is configured to output the write clock signal in units of the horizontal lines in response to the second scan signal.

27. The display device according to claim 26, wherein, The first clock controller includes a clock selection circuit at the horizontal line, and The clock selection circuit at the i-th horizontal line (where i is a natural number) includes: An inverter is configured to invert and output the i-th second scan signal; and The controller is configured to output the write clock signal to the first scan driver when the i-th second scan signal and the output signal of the inverter are input, and not to output the write clock signal under other circumstances.

28. The display device according to claim 25, wherein, The second clock controller is further configured to receive the transmit control signal sequentially in units of horizontal lines, and is configured to output the compensated clock signal in units of horizontal lines in response to the transmit control signal.

29. The display device according to claim 28, wherein, The second clock controller includes a clock selection circuit at the horizontal line, and The clock selection circuit at the i-th horizontal line (where i is a natural number) includes: An inverter is configured to invert and output the i-th transmit control signal; and The controller is configured to output the compensation clock signal to the second scan driver when the i-th transmit control signal and the output signal of the inverter are input, and not to output the compensation clock signal under other circumstances.

30. A method for driving a display device, the method comprising: Sequentially supply transmission control signals to the pixels; When the transmit control signal is input, a clock signal is output in units of horizontal lines; as well as Scan signals are supplied sequentially in response to the clock signal input in units of the horizontal lines.

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