Through-electrode substrate intermediate, through-electrode substrate, through-electrode substrate with element, and semiconductor device

Abstract

The present disclosure provides a through electrode substrate intermediate body having: a glass substrate having a first surface and a second surface facing the first surface, and having a through hole; a through electrode disposed in the through hole of the glass substrate; an elastic insulating layer disposed on the first surface side of the glass substrate; a via hole passing through the elastic insulating layer and electrically connected to the through electrode; a via hole pad portion disposed on the side of the elastic insulating layer opposite the glass substrate and electrically connected to the via hole; and a wiring substrate connection pad portion disposed on the side of the elastic insulating layer opposite the glass substrate and electrically connected to a wiring substrate, the elastic insulating layer having a concave-convex shape including a plurality of convex portions and a plurality of concave portions on the surface of the side of the via hole pad portion and the wiring substrate connection pad portion.

Description

Technical Field

[0001] This disclosure relates to a through-electrode substrate intermediate, a through-electrode substrate, a through-electrode substrate with components, and a semiconductor device. Background Technology

[0002] Various technologies have been proposed in the past that involve intermediary layers that relay motherboards and chips with different terminal pitches (see Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-73684 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] As an interposer, a through-electrode substrate with a through-electrode is known to be used. Furthermore, types of interposers include, for example, silicon interposers, organic interposers, and glass interposers. Among these, organic interposers and glass interposers have attracted the most attention due to their cost-effectiveness.

[0008] However, the coefficient of thermal expansion of organic materials such as glass epoxy used in organic interposers is significantly different from that of semiconductor materials such as silicon used in components. Therefore, when semiconductor device manufacturing processes involve heating, or when semiconductor devices are used in high-temperature environments, the difference in the coefficient of thermal expansion between organic and semiconductor materials causes stress at the junctions, pads, and wiring of the electrical connections between the organic interposer and the components, which can easily lead to cracks and open circuits.

[0009] On the other hand, in the glass interlayer, the difference between the coefficient of thermal expansion of the glass substrate used in the glass interlayer and the coefficient of thermal expansion of the semiconductor material can be minimized.

[0010] However, the coefficient of thermal expansion of the glass substrate is quite different from that of the glass epoxy substrate commonly used to manufacture motherboards. Therefore, when semiconductor device manufacturing processes involve heating, or when semiconductor devices are used in high-temperature environments, the difference in the coefficient of thermal expansion between the glass substrate of the glass interposer and the glass epoxy substrate of the motherboard causes stress in the joints, pads, and wiring of the electrical connections between the glass interposer and the motherboard, which can easily lead to cracks and open circuits.

[0011] This disclosure was made in view of the above facts, and its main objective is to provide a through electrode substrate intermediate capable of suppressing open circuits, a through electrode substrate, a through electrode substrate with components, and a semiconductor device.

[0012] Methods for solving problems

[0013] One embodiment of this disclosure provides a through-electrode substrate intermediate, comprising: a glass substrate having a first surface and a second surface facing the first surface, and having a through hole; a through electrode disposed in the through hole of the glass substrate; an elastic insulating layer disposed on the first surface side of the glass substrate; a via penetrating the elastic insulating layer and electrically connected to the through electrode; a via pad disposed on the side of the elastic insulating layer opposite to the glass substrate and electrically connected to the via; and a wiring substrate connection pad disposed on the side of the elastic insulating layer opposite to the glass substrate and electrically connected to the wiring substrate, wherein the elastic insulating layer has an uneven shape including a plurality of protrusions and a plurality of recesses on the surfaces of the via pad and the wiring substrate connection pad.

[0014] Another embodiment of the present invention provides a through electrode substrate having the through electrode substrate intermediate body described above; and a snake belly wiring layer disposed on the side of the elastic insulating layer in the through electrode substrate intermediate body, including a snake belly shaped portion having a plurality of peaks and a plurality of valleys, and electrically connecting the via pad portion to the wiring substrate connection pad portion.

[0015] Another embodiment of this disclosure provides a through electrode substrate with elements, having the through electrode substrate described above; and elements mounted on the through electrode substrate.

[0016] Another embodiment of this disclosure provides a semiconductor device having the aforementioned through electrode substrate with elements; and a wiring substrate having wiring substrate connection pads electrically connected to the through electrode substrate.

[0017] Another embodiment of this disclosure provides a through-electrode substrate comprising: a glass substrate having a first surface and a second surface facing the first surface, and having a first through-hole; a through-electrode disposed within the first through-hole of the glass substrate; a coated insulating layer disposed on the first surface side of the glass substrate, at least covering the boundary between the through-electrode and the glass substrate, and having a second through-hole connecting the first through-hole; a first via disposed within the second through-hole of the coated insulating layer and electrically connected to the through-electrode; an elastic insulating layer disposed on the surface of the coated insulating layer opposite to the glass substrate and having a third through-hole; a second via disposed within the third through-hole of the elastic insulating layer and electrically connected to the first via; and a wiring substrate connection pad disposed on the surface of the elastic insulating layer opposite to the coated insulating layer, electrically connected to the second via and electrically connected to the wiring substrate.

[0018] Another embodiment of this disclosure provides a through electrode substrate with elements, having the through electrode substrate described above; and elements mounted on the through electrode substrate.

[0019] Another embodiment of this disclosure provides a semiconductor device having the aforementioned through electrode substrate with elements; and a wiring substrate having wiring substrate connection pads electrically connected to the through electrode substrate.

[0020] Invention Effects

[0021] This invention can suppress circuit breakers. Attached Figure Description

[0022] Figure 1 These are schematic top views and cross-sectional views illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0023] Figure 2 These are schematic top views and cross-sectional views illustrating the through electrode substrate in the first embodiment of this disclosure.

[0024] Figure 3 This is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the first embodiment of this disclosure.

[0025] Figure 4 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment of the present disclosure.

[0026] Figure 5 These are schematic top views and cross-sectional views illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0027] Figure 6 These are schematic top views and cross-sectional views illustrating the through electrode substrate in the first embodiment of this disclosure.

[0028] Figure 7 This is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the first embodiment of this disclosure.

[0029] Figure 8 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment of the present disclosure.

[0030] Figure 9 This is a schematic cross-sectional view illustrating the elastic insulating layer of the through-electrode substrate intermediate of the present disclosure.

[0031] Figure 10 This is a schematic cross-sectional view illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0032] Figure 11 This is a schematic top view illustrating the through-electrode substrate intermediate in the first embodiment of this disclosure.

[0033] Figure 12 This is a schematic cross-sectional view illustrating the cross-sectional shape of the through hole in the glass substrate of the through electrode substrate intermediate body of the present disclosure.

[0034] Figure 13 It is a schematic cross-sectional view illustrating the gap and expansion generated by the through-electrode substrate.

[0035] Figure 14 This is a schematic cross-sectional view illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0036] Figure 15 This is a schematic cross-sectional view illustrating the glass substrate and the covered insulating layer through the electrode substrate intermediate in the first embodiment of this disclosure.

[0037] Figure 16 This is a schematic cross-sectional view illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0038] Figure 17 This is a schematic cross-sectional view illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0039] Figure 18 This is a schematic cross-sectional view illustrating the through electrode substrate intermediate in the first embodiment of this disclosure.

[0040] Figure 19 This is a schematic cross-sectional view illustrating the elastic insulating layer and the snake-belly wiring layer through the electrode substrate in the first embodiment of this disclosure.

[0041] Figure 20 This is a schematic top view illustrating the through-electrode substrate intermediate in the first embodiment of this disclosure.

[0042] Figure 21 This is a schematic cross-sectional view illustrating the through electrode substrate in the first embodiment of this disclosure.

[0043] Figure 22 These are schematic top views and cross-sectional views illustrating the through electrode substrate in the first embodiment of this disclosure.

[0044] Figure 23 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0045] Figure 24 This is a schematic cross-sectional view illustrating a through electrode substrate with elements according to the second embodiment of this disclosure.

[0046] Figure 25 This is a schematic cross-sectional view illustrating a semiconductor device in the second embodiment of this disclosure.

[0047] Figure 26 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0048] Figure 27 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0049] Figure 28 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0050] Figure 29 This is a schematic cross-sectional view illustrating the elastic insulating layer of the through-electrode substrate of the present disclosure.

[0051] Figure 30 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0052] Figure 31 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0053] Figure 32 This is a schematic cross-sectional view illustrating the insulating layer covering the electrode substrate in the second embodiment of this disclosure.

[0054] Figure 33 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0055] Figure 34 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure.

[0056] Figure 35 This is a schematic cross-sectional view illustrating the through electrode substrate in the second embodiment of this disclosure. Detailed Implementation

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be limited to the description of the embodiments given below. In addition, in order to make the description clearer, the width, thickness, shape, etc. of various parts are sometimes shown schematically compared with the embodiments. These are just examples and should not be used to limit the interpretation of the present disclosure. Furthermore, in this specification and various drawings, the same symbols are sometimes added for the same elements as described in the foregoing drawings, and detailed descriptions are appropriately omitted.

[0058] In this specification, the term "on top" or "below" when referring to the arrangement of other components on a component includes, unless otherwise specified, the following two situations: other components are arranged directly on or below a component in contact with it; or other components are arranged above or below a component, separated by another component. Similarly, the term "on the surface" or "on the surface" when referring to the arrangement of other components on the surface of a component includes, unless otherwise specified, the following two situations: other components are arranged directly on or below a component in contact with it; or other components are arranged above or below a component, separated by another component.

[0059] This disclosure includes two embodiments, which will be described below.

[0060] I. First Implementation

[0061] First, the through electrode substrate intermediate, through electrode substrate, through electrode substrate with components, and semiconductor device of the first embodiment of this disclosure will be described.

[0062] A. Intermediate body penetrating the electrode substrate

[0063] The through-electrode substrate intermediate of this embodiment includes: a glass substrate having a first surface and a second surface facing the first surface, and having a through hole; a through electrode disposed in the through hole of the glass substrate; an elastic insulating layer disposed on the first surface side of the glass substrate; a via penetrating the elastic insulating layer and electrically connected to the through electrode; a via pad disposed on the side of the elastic insulating layer opposite to the glass substrate and electrically connected to the via; and a wiring substrate connection pad disposed on the side of the elastic insulating layer opposite to the glass substrate and electrically connected to the wiring substrate. The elastic insulating layer has an uneven shape including a plurality of protrusions and a plurality of recesses on the surfaces of the via pad and the wiring substrate connection pad.

[0064] Figure 1 (a) and Figure 1 (b) is a schematic top view and cross-sectional view showing an example of the through-electrode substrate intermediate in this embodiment. Figure 1 (b) is Figure 1 (a) is a cross-sectional view along line AA. For example... Figure 1 (a) and Figure 1As shown in (b), the through electrode substrate intermediate 1 includes: a glass substrate 2 having a first surface 2a and a second surface 2b facing the first surface 2a, and having a through hole 2c; a through electrode 3 disposed in the through hole 2c of the glass substrate 2; a first wiring layer 4 disposed on the first surface 2a side of the glass substrate 2, electrically connected to the through electrode 3, and containing a conductive layer 4a; an elastic insulating layer 5 disposed on the side of the first wiring layer 4 opposite to the glass substrate 2; a via 6 passing through the elastic insulating layer 5 and electrically connected to the first wiring layer 4; a via pad portion 7 disposed on the side of the elastic insulating layer 5 opposite to the first wiring layer 4 and electrically connected to the via 6; and a wiring substrate connection pad portion 8 disposed on the side of the elastic insulating layer 5 opposite to the first wiring layer 4 and electrically connected to the wiring substrate. The elastic insulating layer 5 has a concave-convex shape 9 on the surface of the via pad portion 7 and the wiring substrate connection pad portion 8, which includes a plurality of protrusions 9a and a plurality of recesses 9b.

[0065] Figure 2 (a) and Figure 2 (b) is a schematic top view and cross-sectional view showing an example of a through electrode substrate having a through electrode substrate intermediate in this embodiment. Figure 2 (b) is Figure 2 (a) AA-line cross section. Figure 2 (a) and Figure 2 (b) is a through-electrode substrate with Figure 1 (a) and Figure 1 Example of a through-electrode substrate intermediate shown in (b). Figure 2 (a) and Figure 2 As shown in (b), the through electrode substrate 20 has: a through electrode substrate intermediate 1; and a snake belly wiring layer 22 disposed on the side of the elastic insulating layer 5 in the through electrode substrate intermediate 1, including a snake belly shaped portion 21 having a plurality of peak portions 21a and a plurality of valley portions 21b, and electrically connecting the via pad portion 7 to the wiring substrate connection pad portion 8.

[0066] Figure 3 This is a schematic cross-sectional view showing an example of a through electrode substrate with components having a through electrode substrate intermediate in this embodiment. Figure 3 It is a through-electrode substrate with components. Figure 1 (a) and Figure 1 Example of a through-electrode substrate intermediate shown in (b). Figure 3 As shown, the through electrode substrate 30 with components includes: a through electrode substrate 20; a first bonding portion 31 electrically connected to a component connection pad portion 11 of the through electrode substrate 20; and a component 32 electrically connected to the first bonding portion 31.

[0067] Figure 4This is a schematic cross-sectional view showing an example of a semiconductor device having a through-electrode substrate intermediate in this embodiment. Figure 4 Semiconductor devices have Figure 1 (a) and Figure 1 Example of a through-electrode substrate intermediate shown in (b). Figure 4 As shown, the semiconductor device 40 includes: a through electrode substrate 20; a through electrode substrate 20; a first bonding portion 31 electrically connected to a component connection pad portion 11 of the through electrode substrate 20; a component 32 electrically connected to the first bonding portion 31; a second bonding portion 41 electrically connected to a wiring substrate connection pad 8 of the through electrode substrate 20; and a wiring substrate 42 electrically connected to the second bonding portion 41.

[0068] For example, if the first bonding portion is a solder bonding portion, during the reflow soldering process in the semiconductor device manufacturing process, when the through electrode substrate and the component are bonded via the solder bonding portion, the through electrode substrate and the component expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficients between the through electrode substrate and the component is large, stress will be generated at the bonding pads where the first bonding portion connects to the component, easily causing cracks and open circuits. Furthermore, for example, in the case of using a semiconductor device in a high-temperature environment, if the difference in thermal expansion coefficients between the through electrode substrate and the component is large, stress will be generated at the bonding pads where the first bonding portion connects to the component, easily causing cracks and open circuits.

[0069] To address this, the through-electrode substrate in this embodiment has a glass substrate, and the through-electrode substrate is used as a so-called glass interlayer. Therefore, the difference in thermal expansion coefficients between the glass substrate and the semiconductor material can be reduced, suppressing stress generated at the first junction and the component connection pad. Thus, cracks and open circuits at the first junction and the component connection pad can be suppressed.

[0070] Furthermore, for example, if the second bonding portion is a solder bonding portion, during the reflow soldering process in the semiconductor device manufacturing process, when the through electrode substrate and the wiring substrate are bonded via the solder bonding portion, the through electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate is large, an open circuit can easily occur between the through electrode substrate and the wiring substrate. In addition, for example, when the semiconductor device is used in a high-temperature environment, if the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate is large, stress will be generated at the pad portion for connecting the second bonding portion and the wiring substrate, which can easily cause cracks and open circuits.

[0071] To address this, in this embodiment, the elastic insulating layer is elastic and has an uneven shape on the surface of the via pad portion and the wiring substrate connection pad portion, and the surface of the elastic insulating layer on the surface of the via pad portion and the wiring substrate connection pad portion has extensibility. Furthermore, as the surface of the elastic insulating layer on the surface of the via pad portion and the wiring substrate connection pad portion expands and contracts, the via tilts and deforms. In this way, as the surface of the elastic insulating layer on the surface of the via pad portion and the wiring substrate connection pad portion expands and contracts, the via tilts and deforms, thereby mitigating the stress caused by the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate. Therefore, cracks and open circuits in the second joint and the wiring substrate connection pad portion can be suppressed.

[0072] Furthermore, in this embodiment, the surface of the elastic insulating layer has an uneven shape, thereby the snake-belly wiring layer disposed on the surface of the elastic insulating layer will have a snake-belly shaped portion that follows the uneven shape of the elastic insulating layer. In addition, the snake-belly wiring layer has elasticity due to the snake-belly shaped portion. By expanding and contracting the snake-belly wiring layer, the stress caused by the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate can be further mitigated. Therefore, cracks and open circuits in the pad portion connecting the second bonding portion to the wiring substrate can be effectively suppressed.

[0073] Figure 5 (a) and Figure 5 (b) is a schematic top view and cross-sectional view showing another example of the through-electrode substrate intermediate in this embodiment. Figure 5 (b) is Figure 5 (a) is a cross-sectional view along line AA. For example... Figure 5 (a) and Figure 5 As shown in (b), the through-electrode substrate intermediate 1 includes: a glass substrate 2 having a first surface 2a and a second surface 2b facing the first surface 2a, and having a through hole 2c; a through electrode 3 disposed within the through hole 2c of the glass substrate 2; an elastic insulating layer 5 disposed on the first surface 2a side of the glass substrate 2; a via 6 penetrating the elastic insulating layer 5 and electrically connected to the through electrode 3; a via pad portion 7 disposed on the side of the elastic insulating layer 5 opposite to the glass substrate 2 and electrically connected to the via 6; and a wiring substrate connection pad portion 8 disposed on the side of the elastic insulating layer 5 opposite to the glass substrate 2 and electrically connected to the wiring substrate. The elastic insulating layer 5 has a concave-convex shape 9 including a plurality of protrusions 9a and a plurality of recesses 9b on the surfaces of the via pad portion 7 and the wiring substrate connection pad portion 8. Furthermore, the via 6 in the elastic insulating layer 5 is smaller in top view from the side of the glass substrate 2 than the through electrode 3 is smaller in top view from the side of the first surface 2a of the glass substrate 2; the elastic insulating layer 5 is configured to cover the boundary α between the through electrode 3 and the glass substrate 2. Figure 5 (a) and Figure 5 (b) The through-electrode substrate intermediate 1 shown is relative to the above Figure 1 (a) and Figure 1 (b) The through electrode substrate intermediate 1 is different in that it does not have a first wiring layer 4 disposed on the first surface 2a side of the glass substrate 2, electrically connected to the through electrode 3 and the via pad 7, and includes a conductive layer 4a.

[0074] Figure 6 (a) and Figure 6 (b) is a schematic top view and cross-sectional view showing another example of a through electrode substrate having a through electrode substrate intermediate in this embodiment. Figure 6 (b) is Figure 6 (a) AA-line cross section. Figure 6 (a) and Figure 6 (b) is a through-electrode substrate with Figure 5 (a) and Figure 5 (b) shows an example of a through-electrode substrate intermediate. Figure 6 (a) and Figure 6 In example (b), besides the through-electrode substrate intermediate, and... Figure 2 (a) and Figure 2 The example shown in (b) is the same.

[0075] Figure 7 This is a schematic cross-sectional view showing another example of a through electrode substrate with components having a through electrode substrate intermediate in this embodiment. Figure 7 It is a through-electrode substrate with components. Figure 5 (a) and Figure 5 Example of a through-electrode substrate intermediate shown in (b). Figure 7 In addition to the intermediate body that penetrates the electrode substrate, it is also related to... Figure 3 The example shown is the same.

[0076] Figure 8 This is a schematic cross-sectional view showing another example of a semiconductor device having a through-electrode substrate intermediate in this embodiment. Figure 8 Semiconductor devices have Figure 5 (a) and Figure 5 Example of a through-electrode substrate intermediate shown in (b). Figure 8 In addition to the intermediate body that penetrates the electrode substrate, it is also related to... Figure 4 The example shown is the same.

[0077] In this embodiment, Figure 5 (a) and Figure 5 (b) As shown in the through electrode substrate intermediate, it can also function as Figure 1 (a) and Figure 1 (b) shows the same effect as the through electrode substrate intermediate.

[0078] Therefore, this implementation method can improve connection reliability.

[0079] The following describes the various structures of the through electrode substrate intermediate in this embodiment.

[0080] 1. Elastic insulation layer

[0081] The elastic insulating layer of this embodiment is disposed on the first surface of the glass substrate, and has a concave-convex shape including a plurality of protrusions and a plurality of recesses on the surface of the through-hole pad portion and the wiring substrate connection pad portion.

[0082] (1) Concave-convex shape

[0083] The elastic insulating layer has a textured surface on the side of the via pad and the wiring board connection pad, which includes multiple protrusions and multiple recesses.

[0084] In the semiconductor device having a through-electrode substrate intermediate according to this embodiment, in the uneven shape, the height difference between adjacent protrusions and concave portions is preferably smaller than the thickness of the elastic insulating layer. This height difference is, for example, 50 μm or less, or 15 μm or less, or 10 μm or less. If the height difference is too large, the serpentine wiring layer disposed on the side of the via pad portion of the elastic insulating layer and the wiring substrate connection pad portion may touch the wiring substrate. On the other hand, the height difference is, for example, 1 μm or more, or 3 μm or more, or 5 μm or more. If the height difference is too small, the side of the elastic insulating layer on the side of the via pad portion and the wiring substrate connection pad portion may be difficult to expand and contract. Specifically, the height difference is 1 μm or more and 50 μm or less, or 3 μm or more and 15 μm or less, or 5 μm or more and 10 μm or less. The height difference between adjacent protrusions and concave portions, for example, is... Figure 9 As shown, denoted by the symbol H1, it is the distance between adjacent protrusions and concave portions in the normal direction of the first surface of the glass substrate.

[0085] The height difference between adjacent protrusions and concave sections was determined based on cross-sectional images of the through-electrode substrate intermediate taken using a scanning electron microscope (SEM). The height difference between adjacent protrusions and concave sections was set as the arithmetic mean of the height differences at any 10 locations.

[0086] The spacing between adjacent protrusions in the concave-convex shape is, for example, 2 μm or more, or 5 μm or more, or 6 μm or more. On the other hand, the spacing between adjacent protrusions is, for example, 20 μm or less, or 10 μm or less, or 9 μm or less. The larger the spacing within the aforementioned range, the better. A larger spacing reduces the stress amplitude of the serpentine wiring layer on the side of the via pad portion of the elastic insulating layer and the wiring substrate connection pad portion. Therefore, when the serpentine wiring layer is repeatedly subjected to thermal stress, open circuits can be suppressed, and connection reliability can be improved. Specifically, the spacing is 2 μm or more and 20 μm or less, or 5 μm or more and 10 μm or less, or 6 μm or more and 9 μm or less. The spacing between adjacent protrusions, for example, is... Figure 9 As shown, it is represented by the symbol P1.

[0087] The spacing between adjacent protrusions was determined based on cross-sectional images of the through-electrode substrate intermediate taken using a scanning electron microscope (SEM). The spacing between adjacent protrusions was set as the arithmetic mean of the spacings at any 10 locations.

[0088] In a concave-convex shape, the convex and concave parts can be arranged regularly or irregularly.

[0089] Regarding the cross-sectional shape of the protrusion, it is preferable that the top of the protrusion has a curvature; the cross-sectional shape of the protrusion can be, for example, semi-circular or semi-elliptical. Similarly, regarding the cross-sectional shape of the concave portion, it is preferable that the bottom of the concave portion has a curvature; the cross-sectional shape of the concave portion can be, for example, semi-circular or semi-elliptical. With this shape, the breakage of the basalt wiring layer on the side of the via pad portion disposed on the elastic insulating layer and the wiring substrate connection pad portion can be suppressed.

[0090] On the surface of the via pad portion of the elastic insulating layer that connects to the wiring substrate pad portion, the uneven shape should be provided at least in the area where the brachiocephalic wiring layer is provided. For example, on the surface of the elastic insulating layer that connects to the wiring substrate pad portion, the uneven shape can be provided on the entire surface or only partially. For example, in Figure 1 In (b), in the area where the basalt wiring layer is configured, a concave-convex shape 9 is provided. For example, in Figure 10 In addition to the area where the basalt wiring layer is configured, a raised / lower shape 9 is also provided in the adjacent through-electrodes 3, in the area between the wiring substrate connection pad 8 corresponding to the via pad 7 electrically connected to one through-electrode 3 and the via pad 7b electrically connected to another through-electrode 3. Furthermore, in Figure 10In this configuration, uneven shapes 9 are also provided in areas other than the via pad portion 7 and the wiring substrate connection pad portion 8. Furthermore, although not shown, if uneven shapes are provided across the entire surface of the elastic insulating layer on the side where the via pad portion and the wiring substrate connection pad portion are located, then, as described later, the vise-belly wiring layer can also serve as the via pad portion and the wiring substrate connection pad portion. In this case, uneven shapes are also provided in the area of ​​the via pad portion and the wiring substrate connection pad portion on the surface of the elastic insulating layer on the side where the via pad portion and the wiring substrate connection pad portion are located.

[0091] (2) Characteristics of elastic insulating layer

[0092] In the elastic insulating layer, the elastic modulus measured by nanoindentation is preferably 5 GPa or less, more preferably 1 GPa or less. If the above elastic modulus is within the above range, the stress caused by the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate can be mitigated. On the other hand, the above elastic modulus is, for example, 0.01 GPa or more, or 0.05 GPa or more. Specifically, the above elastic modulus is preferably 0.01 GPa or more and 5 GPa or less, more preferably 0.05 GPa or more and 1 GPa or less.

[0093] The elastic modulus was determined according to ISO 14577 at 25°C using nanoindentation. An apparatus, for example, the HYSITRON "TI950 TriboIndenter" was used. A Glass indenter was used. The surface into which the Glass indenter was pressed into the elastic insulating layer was the side facing the connection pads between the via pads and the wiring board. The measurement conditions were: maximum indentation depth 100 nm, load time 5 seconds, hold time 5 seconds, and unload time 5 seconds. Measurements were taken at any five locations, and the arithmetic mean was used as the elastic modulus.

[0094] Furthermore, in the elastic insulating layer, the rate of thermogravimetric change after heating at 260°C for 1 hour is preferably 3% or less. If the above-mentioned rate of thermogravimetric change is within the above range, sufficient heat resistance can be obtained.

[0095] The rate of change of thermogravimetric weight was determined by thermogravimetric analysis (TGA). The measurement conditions are as described below. The thermogravimetric measuring device used was a "TGA550" manufactured by TA Instruments.

[0096] <Measurement Conditions>

[0097] • Atmosphere: Nitrogen atmosphere

[0098] • Heating rate: 10℃ / min

[0099] • Duration: 1 hour

[0100] (3) Materials of the elastic insulating layer

[0101] Materials used as elastic insulating layers include, for example, elastomers. Examples of elastomers include styrene-based elastomers, olefin-based elastomers, urethane-based elastomers, amide-based elastomers, nitrile-based elastomers, vinyl chloride-based elastomers, ester-based elastomers, 1,2-polybutadiene-based elastomers, fluorinated elastomers, polysiloxane rubber, polyurethane rubber, fluorinated rubber, polybutadiene-based elastomers, polyisobutylene, polystyrene-butadiene, and polychloroprene. Furthermore, the materials used for elastic insulating layers can also be photosensitive.

[0102] (4) Morphology of the elastic insulating layer

[0103] In this embodiment, for example, Figure 5 As shown in (b), the elastic insulating layer 5 is configured to at least cover the boundary α between the electrode 3 and the glass substrate 2, and can also serve as a subsequent insulating layer. The insulating layer will be described later.

[0104] The thickness of the elastic insulating layer can be, for example, 5 μm or more, or 15 μm or more, or 50 μm or more. If the thickness of the elastic insulating layer is within the above range, the surface of the elastic insulating layer on the side where the via pad portion is connected to the wiring substrate pad portion is prone to expansion and contraction. On the other hand, the thickness of the elastic insulating layer can be, for example, 200 μm or less, or 100 μm or less, or 60 μm or less. If the thickness of the elastic insulating layer is too thick, the thickness of the entire intermediate body penetrating the electrode substrate may become thicker. Specifically, the thickness of the elastic insulating layer can be 5 μm or more and 200 μm or less, or 15 μm or more and 100 μm or less, or 50 μm or more and 60 μm or less.

[0105] In this specification, the thickness of each layer is determined based on cross-sectional images of the through-electrode substrate intermediate taken using a scanning electron microscope (SEM). The thickness is set as the arithmetic mean of the thicknesses at any five locations.

[0106] (5) Method for forming elastic insulating layer

[0107] The elastic insulating layer can be formed by coating the aforementioned material. Furthermore, as a method for forming the uneven shape, for example, molding using a mold can be employed.

[0108] 2. Via

[0109] In this embodiment, the via penetrates the above-mentioned elastic insulating layer and is electrically connected to the through electrode.

[0110] As for the material of a via, there are no special restrictions as long as the material is conductive. The conductive materials commonly used for vias can be used, and the appropriate selection can be made according to the shape or formation method of the via.

[0111] As a method for forming vias, general via forming methods can be used, and the appropriate method can be selected according to the shape of the via. In a via forming method, firstly, a through-hole is formed in an elastic insulating layer, and then a via is formed within the through-hole in the elastic insulating layer. Examples of methods for forming through-holes in the elastic insulating layer include laser processing, photolithography, and shaping using a mold. In the case of shaping using a mold, a rough and uneven shape can be formed on the surface of the elastic insulating layer using a mold, and simultaneously, a through-hole is formed in the elastic insulating layer using the same mold. Furthermore, examples of methods for forming vias within the through-hole in the elastic insulating layer include PVD methods such as vacuum evaporation and sputtering, or CVD methods and plating methods. Alternatively, a conductive material can be filled into the through-hole in the elastic insulating layer to form the via, and a via pad portion can be formed using this conductive material. Furthermore, in the case of plating, firstly, a through-hole is formed in the elastic insulating layer. Then, a seed layer is formed on the entire surface of the elastic insulating layer using a sputtering method or similar technique. Next, a photoresist layer is formed on the seed layer. Then, the photoresist layer is patterned to form openings for through-hole pads. Finally, electroplating is applied to the openings of the photoresist layer to form a plating layer, thereby simultaneously forming the through-hole and the through-hole pads. In this case, the through-hole and the through-hole pads have both a seed layer and a plating layer.

[0112] 3. Through-hole pad section

[0113] In this embodiment, the via pad is disposed on the side of the elastic insulating layer opposite to the glass substrate and is electrically connected to the via.

[0114] There are no particular restrictions on the material used for the via pads, as long as it is conductive; conductive materials commonly used in wiring can be used. Examples of conductive materials include metals such as copper, molybdenum, titanium, tungsten, tantalum, aluminum, gold, silver, nickel, and palladium, alloys of at least one of these metals, or metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). Copper is preferred.

[0115] There are no particular restrictions on the top view shape of the via pad, such as circle, ellipse, square, and rectangle.

[0116] The thickness of the via pad is the same as that of a typical wiring. The thickness of the via pad can be, for example, 0.05 μm or more and 100 μm or less, or 0.1 μm or more and 50 μm or less, or 0.2 μm or more and 10 μm or less. This ensures sufficient conductivity.

[0117] As a method for forming the through-hole pad portion, general wiring formation methods can be used, such as dry film deposition methods like CVD or sputtering, or methods that form a conductive film by plating and then pattern the conductive film by photolithography. Alternatively, as described above, vias and through-hole pad portions can be formed simultaneously.

[0118] 4. Pads for connecting wiring substrates

[0119] In this embodiment, the solder pad for connecting the wiring substrate is disposed on the side of the elastic insulating layer opposite to the glass substrate and is electrically connected to the wiring substrate.

[0120] The material, top view shape, thickness, and forming method of the pad portion for wiring substrate connection are the same as those of the pad portion for via described above.

[0121] The via pads and the wiring board connection pads are electrically connected via a brass wiring layer. Therefore, the via pads and the wiring board connection pads are arranged adjacent to each other.

[0122] In this case, the distance between the via pad and the wiring substrate connection pad is appropriately set according to the size of the through electrode substrate intermediate body, for example, it can be 50μm or more, or 200μm or more. If the above distance is too short, the length of the snake-belly wiring layer tends to be too short, making it difficult for the snake-belly wiring layer to expand and contract, and there is a possibility of easy breakage. If the above distance is within the above range, the length of the snake-belly wiring layer can be ensured, and the stress amplitude can be reduced. Therefore, when the snake-belly wiring layer is repeatedly subjected to thermal stress, breakage can be suppressed and connection reliability can be maintained. On the other hand, the above distance is, for example, 1000μm or less, or 500μm or less, or 300μm or less. If the above distance is too long, the length of the snake-belly wiring layer tends to be too long, which may reduce electrical characteristics. Specifically, the above distance is 50μm or more and 1000μm or less, or 100μm or more and 500μm or less, or 200μm or more and 300μm or less. The distance from the via pad to the wiring board connection pad is the distance from the center of the via pad to the center of the wiring board connection pad.

[0123] Furthermore, as described above, if the surface of the via pad portion and the wiring substrate connection pad portion of the elastic insulating layer is provided with an uneven shape across the entire surface, then, as will be described later, when the basalt wiring layer also serves as the via pad portion and the wiring substrate connection pad portion, it will be difficult to distinguish between the via pad portion and the wiring substrate connection pad portion. In this case, for a semiconductor device having a through-electrode substrate intermediate, the distance from the via through the elastic insulating layer to the first junction portion in the through-electrode substrate intermediate can be within the aforementioned range. The distance from the via to the first junction portion is the distance from the center of the via to the center of the first junction portion.

[0124] The via pad 7 and the wiring board connection pad 8, for example, Figure 1 (a) and Figure 11 As shown, the arrangement is preferably radial when viewed from above. This facilitates the mitigation of stress caused by the difference in thermal expansion coefficients between the through electrode substrate and the wiring substrate. In this case, it can be done as follows: Figure 1 As shown in (a), the via pad 7 and the wiring board connection pad 8 are arranged radially with the via pad 7 on the outside and the wiring board connection pad 8 on the inside. Alternatively, it can be arranged as follows... Figure 11 As shown, the via pad 7 and the wiring board connection pad 8 are arranged radially with the via pad 7 on the inside and the wiring board connection pad 8 on the outside.

[0125] Among them, preferred ones are as follows Figure 11 As shown, the via pad 7 and the wiring substrate connection pad 8 are arranged radially with the via pad 7 on the inside and the wiring substrate connection pad 8 on the outside. When the wiring substrate connection pad is positioned further out than the via pad, for a semiconductor device having a through electrode substrate intermediate, the through electrode substrate and the wiring substrate are electrically connected, and the second joint supporting the through electrode substrate is positioned on the outside. Therefore, the through electrode substrate and the wiring substrate are horizontally stable. This allows for stable soldering. Furthermore, when the wiring substrate connection pad is positioned further out than the via pad, the stress caused by the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate will generate compressive stress on the brachiocephalic wiring layer. On the other hand, when the wiring substrate connection pad is positioned further inward than the via pad, the stress caused by the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate will generate tensile stress on the brachiocephalic wiring layer. Compared to tensile stress, compressive stress is less likely to cause a break in the brachiocephalic wiring layer. Therefore, it is preferable to position the wiring substrate connection pads further outward than the via pads.

[0126] Furthermore, the pads for connecting the wiring substrate are preferably arranged in a regular pattern when viewed from above. This results in a more uniform thermal runout at the second junction where the through-electrode substrate and the wiring substrate are electrically connected during the manufacturing process of a semiconductor device using a through-electrode substrate intermediate. The result is improved yield.

[0127] 5. Glass substrate

[0128] The glass substrate of this embodiment has a first surface and a second surface facing the first surface, and has a through hole extending through the thickness direction.

[0129] Because of the good flatness of the glass substrate, fine wiring can be formed with small pitch. In addition, the coefficient of thermal expansion of the glass substrate can be adjusted by its composition, thus allowing the selection of a glass substrate with an ideal coefficient of thermal expansion.

[0130] Examples of glass used as glass substrates include alkali-free glass and quartz.

[0131] The coefficient of thermal expansion of the glass substrate is preferably 2 ppm / ℃ or higher and 9 ppm / ℃ or lower. If the coefficient of thermal expansion of the glass substrate is within the above range, the difference between the coefficient of thermal expansion of the glass substrate and the coefficient of thermal expansion of the component can be sufficiently reduced.

[0132] In this specification, the coefficient of thermal expansion is the coefficient of linear expansion. The coefficient of thermal expansion is determined by thermomechanical analysis (TMA) in accordance with JIS R3102:1995.

[0133] There are no particular restrictions on the top view shape of the glass substrate; for example, rectangles, squares, and other shapes can be used.

[0134] The top view shape of the through hole in the glass substrate is, for example, approximately circular. Furthermore, examples of the cross-sectional shape of the through hole 2c in the glass substrate 2 include... Figure 1 (b) shows the straight bar shape; as Figure 12 As shown in (a), the inverted cone shape has a larger opening diameter on the first surface 2a than on the second surface 2b; Figure 12 As shown in (b), it is a conical shape with a smaller opening diameter on the first face 2a side than on the second face 2b side; Figure 12 (c) shows an hourglass shape with a portion that is the smallest diameter at a predetermined position between the first surface 2a and the second surface 2b; and as shown in Figure 12 As shown in (d), the designated position between the first face 2a and the second face 2b forms an arc shape with the maximum diameter. Figure 12 (a)~ Figure 12(d) is a schematic cross-sectional view illustrating the cross-sectional shape of a through-hole in a glass substrate. As described later, when a coated insulating layer is disposed on the first surface of the glass substrate, the cross-sectional shape of the through-hole in the glass substrate is preferably either an inverted cone shape or an hourglass shape. Furthermore, regarding the individual cross-sectional shape of the through-hole in the glass substrate, the opening edge E1 of the through-hole 2c on the first surface 2a of the glass substrate 2, the opening edge E2 of the through-hole 2c on the second surface 2b of the glass substrate 2, and the minimum and maximum diameters of the through-hole 2c in the glass substrate 2 are preferably curved surfaces with curvature. This can suppress the occurrence of an open circuit between the through electrode and the via or conductive layer that contacts the through electrode.

[0135] The thickness of the glass substrate can be, for example, 100 μm or more, or 200 μm or more, or 300 μm or more, or 400 μm or more. By setting the thickness of the glass substrate within the above range, the increase in glass substrate deflection can be suppressed. Therefore, it is possible to avoid difficulties in handling the glass substrate during the manufacturing process, or to avoid the glass substrate bending caused by internal stress of films, etc., disposed on the first or second surface of the glass substrate. On the other hand, the thickness of the glass substrate can be, for example, 2000 μm or less, or 1000 μm or less, or 800 μm or less. If the thickness of the glass substrate is within the above range, the time required for the process of forming through holes in the glass substrate is shortened.

[0136] 6. Through electrode

[0137] In this embodiment, the through electrode is disposed in the through hole of the glass substrate.

[0138] As a through electrode, its shape is not particularly limited as long as it can electrically connect the first and second surfaces of the glass substrate. The through electrode can be, for example, a through electrode that fills the through hole in the glass substrate, also known as a filled via; or a through electrode disposed only on the sidewall of the through hole in the glass substrate, also known as a conformal via. Furthermore, if the through electrode is a conformal via, a hollow portion can be disposed within the through hole, or a resin portion can be filled within the through hole.

[0139] If the through electrode is a conformal via and a hollow portion is disposed within the through hole, then the through electrode is integrally formed with the conductive layer constituting the first wiring layer or the conductive layer constituting the second wiring layer, as described below.

[0140] There are no particular restrictions on the material of the through electrode, as long as it is conductive. The conductive materials commonly used in through electrodes can be used, and the selection can be appropriate based on the shape or forming method of the through electrode. Examples of materials for through electrodes include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, or alloys containing these metals.

[0141] The through-electrode can be a single layer or a multilayer consisting of multiple layers stacked together. For example, the through-electrode can have a seed layer disposed on the sidewall of the through-hole in the glass substrate, and a plating layer disposed on the opposite sidewall of the seed layer. The material of the seed layer can be appropriately selected from seed layer materials used in general plating methods. The seed layer material is preferably a conductive material that has good adhesion to the glass substrate, such as compounds of titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, or alloys thereof. If the plating layer contains copper, the seed layer material is preferably capable of suppressing copper diffusion into the glass substrate, such as titanium nitride, molybdenum nitride, or tantalum nitride. The plating layer material is preferably a conductive material that has good adhesion to the seed layer, such as the material of the through-electrode described above.

[0142] Furthermore, the through electrode preferably has an adhesive layer disposed on the sidewall of the through hole in the glass substrate. The adhesive layer improves the adhesion between the glass substrate and the through electrode. The adhesive layer provides high adhesion to the glass substrate. Additionally, the adhesive layer may also function to suppress the diffusion of metal elements from the through electrode into the glass substrate via the sidewall of the through hole. When the through electrode has an adhesive layer, the through electrode sequentially comprises an adhesive layer, a seed layer, and a plating layer, starting from the sidewall of the through hole in the glass substrate.

[0143] If the conductive material constituting the through electrode is copper, the material of the sealing layer can be, for example, titanium, titanium oxide, titanium nitride, molybdenum, molybdenum nitride, tantalum, or tantalum nitride. Furthermore, the sealing layer can be a single layer or multiple layers. Preferably, the main component of the sealing layer includes titanium oxide.

[0144] Furthermore, if the through electrode is a conformal via and the through hole is filled with resin, the resin material can be, for example, epoxy resin, acrylic resin, polyimide, polyamide, polyester, etc.

[0145] As a method for forming a through electrode, a general through electrode forming method can be used, and it can be appropriately selected according to the shape of the through electrode. Examples of methods for forming a through electrode include PVD methods such as vacuum evaporation and sputtering, or CVD methods and deposition methods.

[0146] 7. Insulating layer and second via

[0147] The through-electrode substrate intermediate of this embodiment has: a covered insulating layer disposed between the glass substrate and the elastic insulating layer, covering at least the boundary between the through-electrode and the glass substrate, and having a second through-hole connecting the through-hole; and a second via disposed in the second through-hole of the covered insulating layer, electrically connected to the through-electrode, and electrically connected to the via pad portion.

[0148] When manufacturing semiconductor devices by inserting through-electrode substrates between components and the motherboard, heat treatment processes such as annealing or reflow soldering are performed. Figure 13 (a) and Figure 13 (b) is a schematic diagram illustrating the heat treatment process of the through-electrode substrate during semiconductor device manufacturing. Figure 13 (a) shows a through-electrode substrate in which the through-hole 2c is filled with the through-electrode 3. During heat treatment, as shown... Figure 13 As shown in (b), due to the difference in thermal expansion between the glass substrate 2 and the through electrode 3, a gap G may be generated between the glass substrate 2 and the through electrode 3. Furthermore, during heat treatment, as... Figure 13 As shown in (b), due to the difference in thermal expansion between the glass substrate 2 and the through electrode 3, the through electrode 3 may bulge relative to the main surface of the glass substrate 2. Furthermore, during heat treatment, residual moisture or hydrogen gases in the material constituting the through electrode 3 may be released, potentially causing the through electrode 3 to lift. If such a gap or expansion occurs, the conductive layer or pads located near the boundary between the through electrode and the glass substrate may become disconnected. Additionally, wiring connected to the pads may also become disconnected.

[0149] exist Figure 14 In the intermediate body 1 of the through electrode substrate, there are: an insulating layer 15 disposed between the glass substrate 2 and the elastic insulating layer 5, covering at least the boundary α between the through electrode 3 and the glass substrate 2, and having a second through hole 15c connecting the through hole 3; and a second via 16 disposed in the second through hole 15c of the insulating layer 15, electrically connected to the through electrode 3, and electrically connected to the via pad portion 7. Figure 14 In the middle, a first wiring layer 4 is disposed between the covered insulating layer 15 and the elastic insulating layer 5, and a second via 16 is electrically connected to the via 6 and the via pad 7 via the conductive layer 4a of the first wiring layer 4 and the fourth via 4c.

[0150] The insulating layer 15, as described below, can be made of resin. Figure 14As shown, when the insulating layer 15 is configured as the boundary α between the glass substrate 2 and the through electrode 3, since a portion of the insulating layer 15 contacts a portion of the through electrode 3, even if gas is released from inside the through electrode 3 during heat treatment, the gas can be released to the outside through the insulating layer 15. Therefore, the conductive layer 4a of the first wiring layer 4, which is disposed near the boundary α, can avoid expansion. Furthermore, by configuring the insulating layer 15 as the boundary α between the glass substrate 2 and the through electrode 3, even if a gap is generated between the through electrode 3 and the glass substrate 2 during heat treatment, the insulating layer 15 can cover the gap between the through electrode 3 and the glass substrate 2, thus preventing the conductive layer 4a of the first wiring layer 4 located at the boundary α from becoming open-circuited. Furthermore, even if gaps or expansion during heat treatment cause a step difference between the through electrode 3 and the glass substrate 2, the covering insulating layer 15 can absorb the step difference between the through electrode 3 and the glass substrate 2. Therefore, the conductive layer 4a of the first wiring layer 4 disposed near the boundary α can avoid the generation of steep step differences.

[0151] like Figure 5 The through-electrode substrate intermediate 1 shown has an elastic insulating layer 5 that also serves as a covering insulating layer, and the elastic insulating layer 5 is configured to cover at least the boundary α between the through-electrode 3 and the glass substrate 2. Furthermore, the via 6 also serves as a second via.

[0152] As described above, the elastic insulating layer can be made of an elastomer. Figure 5 As shown, when the elastic insulating layer 5, which also serves as a coating insulating layer, is configured at the boundary α between the coated glass substrate 2 and the through electrode 3, since a portion of the elastic insulating layer 5 contacts a portion of the through electrode 3, even if gas is released from inside the through electrode 3 during heat treatment, the gas can be released to the outside through the elastic insulating layer 5. Therefore, the via pad portion 7 located near the boundary α can avoid expansion. Furthermore, by configuring the elastic insulating layer 5 at the boundary α between the coated glass substrate 2 and the through electrode 3, even if a gap is generated between the through electrode 3 and the glass substrate 2 during heat treatment, the elastic insulating layer 5 can cover the gap between the through electrode 3 and the glass substrate 2, thus preventing the via pad portion 7 located at the boundary α from becoming open-circuited. In addition, even if a gap or expansion during heat treatment causes a step difference between the through electrode 3 and the glass substrate 2, the elastic insulating layer 5 can absorb the step difference between the through electrode 3 and the glass substrate 2, thus preventing the generation of steep step differences in the via pad portion 7 located near the boundary α. In addition, it can suppress the occurrence of open circuits in the brass wiring layer connected to the via pads.

[0153] By configuring the insulating layer as the boundary between the coated glass substrate and the through electrode, open circuits in the conductive layer or pads located near the boundary between the through electrode and the glass substrate can be avoided. This results in improved yield and reliability.

[0154] The insulating coating preferably contacts the glass substrate directly. The insulating coating has a second through-hole that extends through the thickness direction and connects to the through-hole in the glass substrate.

[0155] The material for the insulating layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamide-imide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetheretherketone, polyethersulfone, polycarbonate, polyetherimide, epoxy resin, phenolic resin, polyphenylene ether, acrylic resin, polyolefin, polycyclic olefin, and liquid crystal polymers. Examples of polyolefins include polyethylene and polypropylene. Examples of polycyclic olefins include polynorbornene.

[0156] The method for forming the second through hole can be appropriately selected according to the material of the insulating layer, for example, photolithography or laser processing. In the case of photolithography, the material of the insulating layer can be a photosensitive material, or a resist pattern can be formed on the insulating layer.

[0157] Figure 15 (a)~ Figure 15 (c) is a schematic cross-sectional view illustrating the arrangement of through holes and the covering insulating layer in a glass substrate that exemplifies the through-holes in the intermediate electrode substrate. Figure 15 (a)~ Figure 15 In (c), structures other than the glass substrate and the covering insulating layer are omitted. For example... Figure 15 As shown in (a), the second through hole 15c in the insulating layer 15 is connected to the through hole 2c in the glass substrate 2. The central axis C1 of the through hole 2c in the glass substrate 2 is preferably substantially aligned with the central axis C2 of the second through hole 15c in the insulating layer 15.

[0158] Furthermore, the opening diameter d2 of the second through hole 15c of the coated insulating layer 15 on the glass substrate 2 side is preferably smaller than the opening diameter d1 of the through hole 2c of the glass substrate 2 on the first surface 2a side. d2 / d1 is, for example, 0.5 or more and less than 1.0, or 0.6 or more and less than 0.9.

[0159] The opening diameter d1 of the through hole 2c of the glass substrate 2 on the first surface 2a side is, for example, 50 μm or more and 100 μm or less, or it may be 60 μm or more and 90 μm or less. On the other hand, the opening diameter d2 of the second through hole 15c covered by the insulating layer 15 on the glass substrate 2 side is not particularly limited, for example, it is 40 μm or more and 85 μm or less, or it may be 50 μm or more and 80 μm or less.

[0160] Furthermore, the edge E4 of the opening of the second through-hole 15c on the side of the glass substrate 2 covered by the insulating layer 2 is preferably disposed further inside the edge E1 of the opening of the through-hole 2c on the first surface 2c of the glass substrate 2. By configuring the insulating layer with this second through-hole, the boundary α between the glass substrate 2 and the through electrode 3 can be covered by the insulating layer 15.

[0161] The cross-sectional shape of the second through hole 15c of the covered insulating layer 15 is, for example, as shown in the figure. Figure 15 (b) shows an inverted conical shape, such that the opening diameter d2 of the second through-hole 15c on the glass substrate 2 side is preferably smaller than the opening diameter d3 on the opposite side of the glass substrate. If the second through-hole is inverted conical, the angle θ between the sidewall SS of the second through-hole 15c and the surface of the insulating layer 2 opposite to the glass substrate 2 side, viewed in cross-section, will be an obtuse angle. Therefore, even if the through electrode 3 expands, stress concentration can be avoided near the edge E3 of the opening of the second through-hole 15c on the surface of the insulating layer 2 opposite to the glass substrate 2 side. Therefore, it is possible to prevent open circuits in the pad portion or conductive layer disposed on the surface of the insulating layer opposite to the glass substrate.

[0162] The aforementioned angle θ is not particularly limited; for example, it can be greater than 90 degrees and less than 130 degrees, or greater than 100 degrees and less than 120 degrees. By making the angle θ fall within the aforementioned range, it is possible to further prevent open circuits in the pad portion or conductive layer disposed on the side opposite to the glass substrate covered by the insulating layer. On the other hand, if the aforementioned angle θ is too large, the opening diameter d3 of the second through hole 15c on the opposite side of the glass substrate 2 becomes too large, which may not be suitable for high-density mounting.

[0163] like Figure 15 As shown in (c), in cross-section, the opening edge E3 of the second through hole 15c on the side of the insulating layer 15 opposite to the glass substrate 2 preferably has a curved surface. By making the edge E3 a curved surface, it is possible to further prevent the pads or conductive layer disposed on the side of the insulating layer opposite to the glass substrate from being open-circuited.

[0164] A second via is disposed within the second through-hole covered with an insulating layer. The second via is electrically connected to the through electrode and the via pad portion. Preferably, the second via is directly connected to the through electrode.

[0165] The second via can be a via that fills the second through hole of the covered insulation layer, also known as a filled via; or a via that is only disposed on the sidewall of the second through hole of the covered insulation layer, also known as a conformal via.

[0166] The material for the second via is the same as that for the through electrode described above. Preferably, the material of the through electrode and the material of the second via are the same.

[0167] The second via is formed, for example, by electroplating. When the conductive layer of the first wiring layer (described later) is disposed on the side of the insulating layer opposite to the glass substrate, it is preferable that the second via is formed simultaneously with the conductive layer of the first wiring layer. Furthermore, when the aforementioned elastic insulating layer also serves as the insulating layer, it is preferable that the second via is formed simultaneously with the via pad portion.

[0168] 8. Second insulating layer and third via

[0169] The intermediate body of the through electrode substrate in this embodiment has: a second coated insulating layer disposed on the second surface of the glass substrate, covering at least the boundary between the through electrode and the glass substrate, and having a third through hole connecting the through hole; and a third via disposed in the third through hole of the second coated insulating layer and electrically connected to the through electrode.

[0170] exist Figure 16 In the intermediate body 1 of the through electrode substrate, there are: an insulating layer 17 disposed on the second surface 2b side of the glass substrate 2, covering at least the boundary β between the through electrode 3 and the glass substrate 2, and having a third through hole 17c connecting the through hole 3; and a third via 18 disposed in the third through hole 17c of the second insulating layer 17, electrically connected to the through electrode 3, and electrically connected to the component connection pad portion 11. Figure 16 In the second insulating layer 17, a second wiring layer 12 is disposed on the side opposite to the glass substrate 2. A third via 18 is electrically connected to the component connection pad portion 11 via the conductive layer 12a of the second wiring layer 12 and the fifth via 12c.

[0171] The second insulating layer has the same effect as the aforementioned insulating layer. The second insulating layer and the third via are the same as the aforementioned insulating layer and the aforementioned second via.

[0172] 9. First wiring layer

[0173] The intermediate body of the through electrode substrate in this embodiment may have a first wiring layer disposed between the glass substrate and the elastic insulating layer and electrically connected to the through electrode.

[0174] The first wiring layer has at least one conductive layer and may further have an interlayer insulating layer. The conductive layer can be one layer or two or more layers. When the first wiring layer has two or more conductive layers, the conductive layers are stacked in the thickness direction with an interlayer insulating layer in between. Furthermore, the conductive layers are electrically connected via vias. For example, in… Figure 17 In the first wiring layer 4, starting from the glass substrate 2 side, there are conductive layer 4a, interlayer insulating layer 4b, conductive layer 4a, interlayer insulating layer 4b, and conductive layer 4a in sequence, and each conductive layer 4a is electrically connected by a fourth via 4c.

[0175] There are no particular restrictions on the materials used for the conductive layer, as long as they are conductive; the conductive materials commonly used in intermediate layer wiring can be used. Examples of conductive materials include metallic materials such as metals or metal oxides, conductive resins containing conductive fillers and resins, and conductive polymers.

[0176] The thickness of the conductive layer can be, for example, 0.1 μm or more, or 0.5 μm or more, or 1 μm or more, or 3 μm or more, or 5 μm or more. On the other hand, the thickness of the conductive layer can be, for example, 20 μm or less, or 15 μm or less. For example, when the conductive layer is formed by sputtering, a relatively thin conductive layer can be obtained. Furthermore, when the conductive layer is formed by plating, for example, a relatively thick conductive layer can be obtained.

[0177] The conductive layer can be formed using either an additive or a subtractive method. For example, an additive method involves forming a resist pattern using photolithography, and then plating the exposed portions of the resist pattern to obtain a patterned wiring layer. When using electroplating, a conductive film can be formed on the first surface of the glass substrate or on the opposite side of the interlayer insulating layer before forming the resist pattern. For a subtractive method, for example, a resist pattern can be formed on a conductive layer formed across the entire first surface of the glass substrate, and then etched to obtain a patterned conductive layer.

[0178] The material for the interlayer insulation layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamide-imide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetheretherketone, polyethersulfone, polycarbonate, polyetherimide, epoxy resin, phenolic resin, polyphenylene ether, acrylic resin, polyolefin, polycyclic olefin, and liquid crystal polymers. Examples of polyolefins include polyethylene and polypropylene. Examples of polycyclic olefins include polynorbornene.

[0179] The thickness of the interlayer insulation layer is, for example, 1.5 μm or more, or 2.5 μm or more. On the other hand, the thickness of the interlayer insulation layer is, for example, 6 μm or less. The thickness of the interlayer insulation layer is, for example, 1.5 μm or more and 6 μm or less, or 2.5 μm or more and 6 μm or less.

[0180] Methods for forming interlayer insulating layers include, for example, photolithography and printing.

[0181] 10. Second wiring layer

[0182] The intermediate body of the through electrode substrate in this embodiment may have a second wiring layer disposed on the second side of the glass substrate and electrically connected to the through electrode.

[0183] The second wiring layer has at least one conductive layer and may further have an interlayer insulating layer. The conductive layer can be one layer or two or more layers. When the second wiring layer has two or more conductive layers, the conductive layers are stacked in the thickness direction with an interlayer insulating layer in between. Furthermore, the conductive layers are electrically connected via vias. For example, in… Figure 18 In the second wiring layer 12, starting from the glass substrate 2 side, there are sequentially conductive layers 12a, interlayer insulating layers 12b, conductive layers 12a, interlayer insulating layers 12b, conductive layers 12a, interlayer insulating layers 12b, and conductive layers 12a, and each conductive layer 12a is electrically connected by a fifth via 12c. The conductive layer 12a located on the surface of the second wiring layer 12 opposite to the glass substrate 2 includes component connection pads 11.

[0184] The conductive layer and interlayer insulating layer in the second wiring layer are the same as those in the first wiring layer.

[0185] The top view shape of the component connection pad is the same as the top view shape of the via pad described above.

[0186] B. Through-electrode substrate

[0187] The through electrode substrate of this embodiment has the through electrode substrate intermediate body and a snake belly wiring layer disposed on the side of the elastic insulating layer in the through electrode substrate intermediate body, including a snake belly shaped portion having a plurality of peaks and a plurality of valleys, and electrically connecting the via pad portion to the wiring substrate connection pad portion.

[0188] Figure 2 (a) and Figure 2 (b) is a schematic top view and cross-sectional view showing an example of a through-electrode substrate in this embodiment. Figure 2 (b) is Figure 2 (a) is a cross-sectional view along line AA. For example... Figure 2 (a) and Figure 2 As shown in (b), the through electrode substrate 20 has the through electrode substrate intermediate 1 and a snake belly wiring layer 22 disposed on the side of the elastic insulating layer 5 in the through electrode substrate intermediate 1. The snake belly shaped portion 21 has a plurality of peak portions 21a and a plurality of valley portions 21b, and electrically connects the via pad portion 7 to the wiring substrate connection pad portion 8.

[0189] Figure 3This is a schematic cross-sectional view showing an example of a through-electrode substrate with components in this embodiment. (See diagram below.) Figure 3 As shown, the through electrode substrate 30 with components includes a through electrode substrate 20; a first bonding portion 31 electrically connected to a component connection pad portion 11 of the through electrode substrate 20; and a component 32 electrically connected to the first bonding portion 31.

[0190] Figure 4 This is a schematic cross-sectional view illustrating an example of a semiconductor device having a through-electrode substrate in this embodiment. (See diagram below.) Figure 4 As shown, the semiconductor device 40 includes a through electrode substrate 20; a through electrode substrate 20; a first bonding portion 31 electrically connected to a component connection pad portion 11 of the through electrode substrate 20; a component 32 electrically connected to the first bonding portion 31; a second bonding portion 41 electrically connected to a wiring substrate connection pad 8 of the through electrode substrate 20; and a wiring substrate 42 electrically connected to the second bonding portion 41.

[0191] In this embodiment, as described in item "A. Through-electrode substrate intermediate" above, the through-electrode substrate includes a glass substrate, and is used as a so-called glass interlayer. Therefore, the difference in thermal expansion coefficients between the glass substrate and the semiconductor material can be reduced, suppressing stress generated between the first bonding portion and the component connection pad portion. Therefore, cracks and open circuits between the first bonding portion and the component connection pad portion can be suppressed.

[0192] Furthermore, as described in item "A. Through-electrode substrate intermediate" above, the elastic insulating layer is elastic and has an uneven shape on the surface of the via pad portion and the wiring substrate connection pad portion. Therefore, the surface of the elastic insulating layer on the side of the via pad portion and the wiring substrate connection pad portion has extensibility. Moreover, as the surface of the elastic insulating layer on the side of the via pad portion and the wiring substrate connection pad portion expands and contracts, the via tilts and deforms. In this way, as the surface of the elastic insulating layer on the side of the via pad portion and the wiring substrate connection pad portion expands and contracts, the via tilts and deforms, thereby mitigating the stress caused by the difference in the coefficients of thermal expansion between the through-electrode substrate and the wiring substrate. Therefore, cracks and open circuits between the second joint and the component connection pad portion can be suppressed.

[0193] Furthermore, as described in item "A. Through-electrode substrate intermediate" above, the surface of the elastic insulating layer in this embodiment has an uneven shape. Therefore, the snake-belly wiring layer disposed on the surface of the elastic insulating layer will have a snake-belly shaped portion that follows the uneven shape of the elastic insulating layer. In addition, the snake-belly wiring layer, by having the snake-belly shaped portion, possesses elasticity. Through this elasticity, the snake-belly wiring layer can further mitigate the stress caused by the difference in the coefficients of thermal expansion between the through-electrode substrate and the wiring substrate. Therefore, cracks and open circuits between the second bonding portion and the component connection pad portion can be effectively suppressed.

[0194] Therefore, this implementation method can improve connection reliability.

[0195] The following describes the various structures of the through electrode substrate in this embodiment.

[0196] 1. Through-electrode substrate intermediate

[0197] The intermediate material for the through electrode substrate has been described in detail in "A. Through Electrode Substrate" above, so the description is omitted here.

[0198] 2. Belly-shaped wiring layer

[0199] The snake-belly wiring layer of this embodiment is disposed on the side of the elastic insulating layer in the intermediate body of the through electrode substrate, includes a snake-belly shaped portion having multiple peaks and multiple valleys, and electrically connects the via pad portion to the wiring substrate connection pad portion.

[0200] (1) Snake belly shape part

[0201] The snake-belly wiring layer includes a snake-belly shaped portion with multiple peaks and multiple valleys.

[0202] For the semiconductor device with a through-electrode substrate according to this embodiment, the height difference between adjacent peaks and valleys in the basalt-shaped portion is preferably smaller than the thickness of the second junction portion that electrically connects the through-electrode substrate and the wiring substrate. This height difference is, for example, 50 μm or less, or 15 μm or less, or 10 μm or less. If the height difference is too large, the basalt wiring layer may touch the wiring substrate. On the other hand, the height difference is, for example, 1 μm or more, or 3 μm or more, or 5 μm or more. If the height difference is too small, the basalt wiring layer may be difficult to stretch. This height difference is, for example, 1 μm or more and 50 μm or less, or 3 μm or more and 15 μm or less, or 5 μm or more and 10 μm or less. The height difference between adjacent peaks and valleys, for example, is... Figure 19 As shown, denoted by the symbol H2, it represents the distance between adjacent peaks and valleys in the normal direction of the first surface of the glass substrate.

[0203] The height difference between adjacent peaks and valleys was determined using a scanning electron microscope (SEM) to capture a cross-sectional image of the intermediate body through the electrode substrate. The height difference between adjacent peaks and valleys was set as the arithmetic mean of the height differences at any 10 locations.

[0204] The spacing between adjacent peaks in the snake-belly shaped portion is, for example, 2 μm or more, or 5 μm or more, or 6 μm or more. On the other hand, the spacing between adjacent peaks is, for example, 20 μm or less, or 10 μm or less, or 9 μm or less. Within the aforementioned range, a larger spacing is better. A larger spacing reduces the stress amplitude of the snake-belly wiring layer. Therefore, when the snake-belly wiring layer is repeatedly subjected to thermal stress, circuit breaks can be suppressed, and connection reliability can be improved. Specifically, the spacing is 2 μm or more and 20 μm or less, or 5 μm or more and 10 μm or less, or 6 μm or more and 9 μm or less. The spacing between adjacent peaks is, for example, 2 μm or more and 5 μm or more and 10 μm or less, or 6 μm or more and 9 μm or less. Figure 19 As shown, it is represented by the symbol P2.

[0205] The spacing between adjacent peaks was determined based on cross-sectional images of the through-electrode substrate taken using a scanning electron microscope (SEM). The spacing between adjacent peaks was set as the arithmetic mean of the spacings at any 10 locations.

[0206] The peaks and valleys in the serpentine shape can be arranged regularly or irregularly.

[0207] (2) Morphology of the snake belly wire layer

[0208] The brass-belly wiring layer is configured as a pad for electrical connection vias and a pad for connecting the wiring substrate.

[0209] As for the top view shape of the brachiocephalic wiring layer, it is sufficient to configure it as a pad for connecting electrical connection vias and a pad for connecting the wiring substrate. For example, such as Figure 2 The straight line shown in (a) is as follows: Figure 20 The curves shown, as well as wavy lines, sawtooth lines, and right-angled lines not illustrated, are examples. When the top view of the braided wiring layer is not a straight line, the length of the braided wiring layer increases. Therefore, stress amplitude can be reduced. Consequently, when the braided wiring layer is repeatedly subjected to thermal stress, it can suppress open circuits and improve connection reliability.

[0210] The length of the snake-belly wiring layer is appropriately set according to the size of the through-electrode substrate, for example, it can be 50 μm or more, 100 μm or more, or 200 μm or more. If the length of the snake-belly wiring layer is too short, it will be difficult to expand and contract, and there is a possibility of open circuit. If the length of the snake-belly wiring layer is within the above range, the stress amplitude can be reduced. Therefore, when the snake-belly wiring layer is repeatedly subjected to thermal stress, open circuit can be suppressed and connection reliability can be maintained. On the other hand, the length of the snake-belly wiring layer is, for example, 1000 μm or less, 500 μm or less, or 300 μm or less. If the length of the snake-belly wiring layer is too long, the electrical characteristics may be reduced. Specifically, the length of the snake-belly wiring layer is 50 μm or more and 1000 μm or less, 100 μm or more and 500 μm or less, or 200 μm or more and 300 μm or less. The length of the snake-belly wiring layer is the length of the snake-belly wiring layer in top view.

[0211] The length of the snake-belly interconnect layer is not particularly limited. For example, as described later, when the material of the snake-belly interconnect layer is non-stretchable, the thickness of the snake-belly interconnect layer can be, for example, 1 nm or more, 100 nm or more, or 1000 nm or more. Furthermore, in this case, the thickness of the snake-belly interconnect layer can be, for example, 100 μm or less, 10 μm or less, or 3 μm or less. That is, in this case, the thickness of the snake-belly interconnect layer can be, for example, 1 nm or more and 100 μm or less, 100 nm or more and 10 μm or less, or 1000 nm or more and 3 μm or less. On the other hand, as described later, when the material of the snake-belly interconnect layer is stretchable, the thickness of the snake-belly interconnect layer can be, for example, 5 μm or more, 10 μm or more, or 20 μm or more. Furthermore, in this case, the thickness of the snake-belly interconnect layer can be, for example, 60 μm or less, 50 μm or less, or 40 μm or less. In other words, under these circumstances, the thickness of the snake belly wiring layer can be, for example, 5μm or more and 60μm or less, 10μm or more and 50μm or less, or 20μm or more and 40μm or less.

[0212] The width of the snake belly wiring layer is, for example, more than 10 μm and less than 100 μm.

[0213] As described above, if the surface of the via pad portion of the elastic insulating layer and the pad portion for connecting the wiring substrate are provided with an uneven shape across the entire surface, the vitreous wiring layer can also serve as the via pad portion and the pad portion for connecting the wiring substrate. For example Figure 21In this case, if the surface of the elastic insulating layer 5 on the side where the via pad 7 connects to the wiring substrate pad 8 is provided with an uneven shape 9, then the basalt wiring layer 22 also serves as the via pad 7 and the wiring substrate pad 8. In this case, even in the area where the via pad 7 connects to the wiring substrate pad, an uneven shape is provided on the surface of the elastic insulating layer on the side where the via pad 7 connects to the wiring substrate pad.

[0214] (3) Physical properties of the snake belly wire layer

[0215] The elastic modulus of the snake-belly wiring layer, measured by nanoindentation, is, for example, 100 MPa or more, or 200 MPa or more. On the other hand, the aforementioned elastic modulus is, for example, 300 GPa or less, or 200 GPa or less, or 100 GPa or less. In other words, the aforementioned elastic modulus is 100 MPa or more and 300 GPa or less, 100 MPa or more and 200 GPa or less, 200 MPa or more and 200 GPa or less, or 200 MPa or more and 100 GPa or less.

[0216] (4) Materials of the snake belly wiring layer

[0217] The material of the snake-belly wiring layer can be stretchable or non-stretchable. Examples of non-stretchable materials include metals such as gold, silver, copper, aluminum, platinum, and chromium, or alloys containing these metals. On the other hand, examples of stretchable materials include conductive compositions comprising conductive particles and elastomers. In this case, the snake-belly wiring layer contains conductive particles and elastomers. Examples of conductive particles include particles of gold, silver, copper, nickel, palladium, platinum, and carbon. Furthermore, examples of elastomers include styrene-based elastomers, acrylic elastomers, olefin elastomers, urethane elastomers, polysiloxane rubber, polyurethane rubber, fluororubber, nitrile rubber, polybutadiene, and polychloroprene.

[0218] (5) Methods for forming snake belly wiring layers

[0219] There are no particular limitations on the method for forming the brachiocephalic wiring layer. For example, when the material of the brachiocephalic wiring layer is not elastic, methods such as vapor deposition, sputtering, plating, metal foil transfer, and lamination can be used to form the conductive film, and then the conductive film can be patterned using photolithography. On the other hand, when the material of the brachiocephalic wiring layer is elastic, for example, a method can be used to print a conductive composition containing conductive particles and an elastomer into a pattern using a general printing method.

[0220] 3. First polymer layer

[0221] In this embodiment, the through-electrode substrate preferably has a first polymer layer between the elastic insulating layer and the brachiocephalic wiring layer. For example, in Figure 22 In this configuration, a first polymer layer 23 is disposed between the elastic insulating layer 5 and the brass-belly wiring layer 22. The first polymer layer reduces the stress and stress amplitude experienced by the brass-belly wiring layer.

[0222] The elastic modulus of the first polymer layer is preferably greater than that of the elastic insulating layer. If the elastic modulus of the first polymer layer is smaller than that of the elastic insulating layer, and it is too soft, the stress on the brass-belly wiring layer may be uneven. Therefore, the stress may concentrate in a certain area, raising concerns about open circuits in the brass-belly wiring layer.

[0223] The elastic modulus of the first polymer layer, measured by nanoindentation, is, for example, below 20 GPa. If the elastic modulus is too high, there is a concern that the first polymer layer may fracture and the brass-belly wiring layer may break. On the other hand, as described above, the elastic modulus of the first polymer layer is preferably greater than that of the elastic insulating layer, while there is no particular limitation on the lower limit of the first polymer layer.

[0224] Polyimide and parylene are preferred as materials for the first polymer layer.

[0225] The first polymer layer, viewed from above, should be disposed at least in the area where the brachiocere wiring layer is disposed. For example, Figure 22 For example, the first polymer layer 23 is preferably not disposed in areas other than those where the brass wiring layer 22 is disposed. The expansion and contraction of the via pad portion of the elastic insulating layer on the side of the pad portion for connecting the wiring substrate may be suppressed by the first polymer layer.

[0226] The first polymer layer is configured such that, viewed from above, it has an opening on the via pad and the wiring substrate connection pad, and the basalt wiring layer is electrically connected to the via pad and the wiring substrate connection pad.

[0227] When viewed from above, the first polymer layer also has a snake-belly shaped portion in the area overlapping the snake-belly wiring layer.

[0228] The width of the first polymer layer is, for example, greater than 1 nm and less than 100 μm.

[0229] 4. Second polymer layer

[0230] In this embodiment, the through-electrode substrate preferably has a second polymer layer on the side of the basalt wiring layer opposite to the elastic insulating layer. For example, in Figure 22 In this process, a second polymer layer 24 is disposed on the side of the brass-belly wiring layer 22 opposite to the elastic insulating layer 5. The second polymer layer can reduce the stress and stress amplitude experienced by the brass-belly wiring layer.

[0231] Of the first polymer layer and the second polymer layer, it is preferable to have at least one of them, more preferably at least the first polymer layer, and even more preferably both the first polymer layer and the second polymer layer. For example, in Figure 22 The first polymer layer 23 and the second polymer layer 24 are configured in the middle.

[0232] The elastic modulus, material, and thickness of the second polymer layer are the same as those of the first polymer layer.

[0233] The second polymer layer, viewed from above, should be disposed at least in the area where the brachiocere wiring layer is disposed. For example, Figure 22 For example, the second polymer layer 24 is preferably not disposed in areas other than those where the brass wiring layer 22, via pad portion 7, and wiring substrate connection pad portion 8 are disposed. The expansion and contraction of the via pad portion and wiring substrate connection pad portion side of the elastic insulating layer may be suppressed by the second polymer layer.

[0234] Moreover, as Figure 22 In the example, when viewed from above, the second polymer layer 24 is preferably configured to overlap the via pad portion 7 and the wiring substrate connection pad portion 8.

[0235] When viewed from above, the second polymer layer also has a snake-belly shaped portion in the area overlapping the snake-belly wiring layer.

[0236] C. Through-electrode substrate with components

[0237] The through electrode substrate with components in this embodiment includes the through electrode substrate described above; and components mounted on the through electrode substrate described above.

[0238] Figure 3 This is a schematic cross-sectional view showing an example of a through-electrode substrate with components in this embodiment. (See attached image.) Figure 3 As shown, the through electrode substrate 30 with components includes the through electrode substrate 20 described above; a first bonding portion 31 electrically connected to the component connection pad portion 11 of the through electrode substrate 20; and a component 32 electrically connected to the first bonding portion 31.

[0239] The through-electrode substrate with components in this embodiment has the above-mentioned through-electrode substrate, thus enabling the suppression of open circuits and improving connection reliability.

[0240] The following describes the various structures of the through electrode substrate with components in this embodiment.

[0241] 1. Through-electrode substrate

[0242] The through-electrode substrate has been described in detail in "B. Through-electrode substrate" above, so the description is omitted here.

[0243] 2. Components

[0244] Examples of components used in this embodiment include active components such as ICs, transistors, and diodes, as well as passive components such as resistors, capacitors, and inductors. Other examples of components include IC chips, LSI chips, and MEMS chips.

[0245] A component connection pad extends through the electrode substrate, and a component is mounted via a first bonding portion. The first bonding portion can be a bonding portion commonly used for mounting components. Materials used for the first bonding portion include, for example, solder, gold or gold alloy, conductive paste, anisotropic conductive paste, and anisotropic conductive film.

[0246] Furthermore, a filler resin portion can be configured by filling the space between the through electrode substrate and the component with a filler resin. Alternatively, a molding resin portion covering the component can be configured by sealing the component with a molding resin.

[0247] D. Semiconductor devices

[0248] The semiconductor device of this embodiment includes the through electrode substrate with the above-mentioned components; and a wiring substrate with wiring substrate connection pads electrically connected to the through electrode substrate.

[0249] Figure 4 This is a schematic cross-sectional view showing an example of the semiconductor device in this embodiment. (e.g.) Figure 4 As shown, the semiconductor device 40 includes a through electrode substrate 20; a through electrode substrate 20; a first bonding portion 31 electrically connected to a component connection pad portion 11 of the through electrode substrate 20; a component 32 electrically connected to the first bonding portion 31; a second bonding portion 41 electrically connected to a wiring substrate connection pad 8 of the through electrode substrate 20; and a wiring substrate 42 electrically connected to the second bonding portion 41.

[0250] The semiconductor device of this embodiment has the through electrode substrate with the above-mentioned components, thus enabling it to suppress open circuits and improve connection reliability.

[0251] The following describes the various structures of the semiconductor device in this embodiment.

[0252] 1. Through-electrode substrate with components

[0253] The through-electrode substrate with components has been described in detail in "C. Through-electrode substrate with components" above, so the description is omitted here.

[0254] 2. Wiring substrate

[0255] In this embodiment, a general wiring substrate can be used.

[0256] The wiring substrate connection pad portion that passes through the electrode substrate is electrically connected to the wiring substrate via the second bonding portion. The material of the second bonding portion is the same as that of the first bonding portion described above.

[0257] 3. Uses

[0258] The application of the semiconductor device in this embodiment is not particularly limited, and examples include notebook computers, tablet computers, mobile phones, smartphones, digital cameras, digital clocks, servers, etc.

[0259] II. Second Implementation

[0260] Next, the through electrode substrate, the through electrode substrate with components, and the semiconductor device of the second embodiment of this disclosure will be described in detail.

[0261] A. Through-electrode substrate

[0262] The through-electrode substrate of this embodiment includes: a glass substrate having a first surface and a second surface facing the first surface, and having a first through-hole; a through-electrode disposed in the first through-hole of the glass substrate; a coated insulating layer disposed on the first surface side of the glass substrate, covering at least the boundary between the through-electrode and the glass substrate, and having a second through-hole connecting the first through-hole; a first via disposed in the second through-hole of the coated insulating layer and electrically connected to the through-electrode; an elastic insulating layer disposed on the surface of the coated insulating layer opposite to the glass substrate and having a third through-hole; a second via disposed in the third through-hole of the elastic insulating layer and electrically connected to the first via; and a wiring substrate connection pad disposed on the surface of the elastic insulating layer opposite to the coated insulating layer, electrically connected to the second via and electrically connected to the wiring substrate.

[0263] Figure 23 This is a schematic cross-sectional view showing an example of a through-electrode substrate in this embodiment. (See attached image.) Figure 23As shown, the through electrode substrate 101 includes: a glass substrate 102 having a first surface 102a and a second surface 102b facing the first surface 102a, and having a first through hole 102c; a through electrode 103 disposed within the first through hole 102c of the glass substrate 102; a coated insulating layer 104 disposed on the first surface 102a side of the glass substrate 102, covering the boundary α between the through electrode 103 and the glass substrate 102, and having a second through hole 104c connecting the first through hole 102c; a first via 105 disposed within the second through hole 104c of the coated insulating layer 104, electrically connected to the through electrode 103; and a first wiring layer 106 disposed within the second through hole 104c of the coated insulating layer 104. On the side of the insulating layer 104 opposite to the glass substrate 102, there is a first conductive layer 106a electrically connected to the first via 105; an elastic insulating layer 107 disposed on the side of the insulating layer 104 opposite to the glass substrate 102 and having a third through hole 107c; ​​a second via 108 disposed in the third through hole 107c of the elastic insulating layer 107 and electrically connected to the first via 105 via the first conductive layer 106a of the first wiring layer 106; and a wiring substrate connection pad portion 109 disposed on the side of the elastic insulating layer 107 opposite to the insulating layer 104, electrically connected to the second via 108, and electrically connected to the wiring substrate.

[0264] Figure 23 This is a schematic cross-sectional view showing an example of a through-electrode substrate with components in this embodiment. Figure 23 In the process, the through electrode substrate 101 further includes: a component connection pad portion 111, disposed on the second surface 102b side of the glass substrate 102, electrically connected to the through electrode 103, and electrically connected to the component. For example... Figure 23 As shown, the through electrode substrate 120 with components includes: a through electrode substrate 101; a first bonding portion 121, which is electrically connected to a component bonding pad portion 111 of the through electrode substrate 101; and a component 122, which is electrically connected to the first bonding portion 121.

[0265] Figure 25 This is a schematic cross-sectional view illustrating an example of a semiconductor device having a through-electrode substrate in this embodiment. (See diagram below.) Figure 25 As shown, the semiconductor device 130 includes: a through electrode substrate 1; a first bonding portion 121 electrically connected to a component connection pad portion 111 of the through electrode substrate 101; a component 122 electrically connected to the first bonding portion 121; a second bonding portion 131 electrically connected to a wiring substrate connection pad 109 of the through electrode substrate 101; and a wiring substrate 132 electrically connected to the second bonding portion 131.

[0266] For example, if the first bonding portion is a solder bonding portion, during the reflow soldering process in the semiconductor device manufacturing process, when the through electrode substrate and the component are bonded via the solder bonding portion, the through electrode substrate and the component will expand due to heat and then contract due to cooling. At this time, if the difference in the coefficients of thermal expansion between the through electrode substrate and the component is large, stress will be generated at the bonding pad of the first bonding portion and the component, which can easily cause cracks and open circuits. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in the coefficients of thermal expansion between the through electrode substrate and the component is large, stress will be generated at the bonding pad of the first bonding portion and the component, which can easily cause cracks and open circuits.

[0267] To address this, the through-electrode substrate 101 in this embodiment includes a glass substrate 102, and the through-electrode substrate 101 is used as a so-called glass interlayer. Therefore, the difference in thermal expansion coefficients between the glass substrate 102 and the component 122 can be reduced, suppressing stress generated between the first bonding portion 121 and the component connection pad portion 111. Thus, cracks and open circuits between the first bonding portion 121 and the component connection pad portion 111 can be suppressed.

[0268] Furthermore, for example, if the second bonding portion is a solder bonding portion, during the reflow soldering process in the semiconductor device manufacturing process, when the through electrode substrate and the wiring substrate are bonded via the solder bonding portion, the through electrode substrate and the wiring substrate will expand due to heat and then contract due to cooling. At this time, if the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate is large, an open circuit can easily occur between the through electrode substrate and the wiring substrate. In addition, for example, when the semiconductor device is used in a high-temperature environment, if the difference in the coefficients of thermal expansion between the through electrode substrate and the wiring substrate is large, stress will be generated at the pad portion connecting the second bonding portion and the wiring substrate, which can easily cause cracks and open circuits.

[0269] To address this, this embodiment employs an elastic insulating layer 107, which provides flexibility to the surface of the elastic insulating layer 107 on the side of the wiring substrate connection pad 109. Furthermore, if the surface of the elastic insulating layer 107 on the side of the wiring substrate connection pad 109 expands or contracts, the second via 108 disposed within the third through-hole 107c of the elastic insulating layer 107 will tilt and deform accordingly. In this way, when the surface of the elastic insulating layer 107 on the side of the wiring substrate connection pad 109 expands or contracts, the second via 108 will tilt and deform accordingly, thereby mitigating the stress caused by the difference in thermal expansion coefficients between the through electrode substrate 101 and the wiring substrate 132. Therefore, cracks and breaks in the second joint 131 and the wiring substrate connection pad 109 can be suppressed.

[0270] Figure 26 This is a schematic cross-sectional view showing another example of a through-electrode substrate in this embodiment. Figure 26In the through-electrode substrate 101 shown, the elastic insulating layer 107 also serves as the covering insulating layer 104, and the second via 108 also serves as the first via 105. For example... Figure 26 As shown, the through electrode substrate 101 includes: a glass substrate 102 having a first surface 102a and a second surface 102b facing the first surface 102a, and having a first through hole 102c; a through electrode 103 disposed within the first through hole 102c of the glass substrate 102; and an elastic insulating layer 107 (coated with an insulating layer 104, having a second through hole 104c connecting the first through hole 102c) disposed on the first surface 102a side of the glass substrate 102, covering the through electrode 3 and the glass substrate. The boundary α of the board 102 has a third through hole 107c connecting the first through hole 102c; a second via 108 (first via 105) is disposed in the third through hole 107c of the elastic insulating layer 107 (the second through hole 104c of the covered insulating layer 104) and electrically connected to the through electrode 3; and a wiring substrate connection pad 109 is disposed on the side of the elastic insulating layer 107 opposite to the glass substrate 102, electrically connected to the second via 108, and electrically connected to the wiring substrate.

[0271] In this embodiment, Figure 26 The through-electrode substrate shown can also function with Figure 23 The same effect is achieved with the through-electrode substrate shown.

[0272] Here, when a semiconductor device is manufactured by inserting a through electrode substrate between the component and the motherboard, heat treatment processes such as annealing or reflow soldering are performed. Figure 13 (a) and Figure 13 (b) is a schematic diagram illustrating the heat treatment process of the through-electrode substrate during semiconductor device manufacturing. Figure 13 (a) shows a through electrode substrate in which a through electrode 103 is filled in the first through hole 102c. During heat treatment, it will... Figure 13 As shown in (b), due to the difference in the coefficients of thermal expansion between the glass substrate 102 and the through electrode 103, a gap G may be generated between the glass substrate 102 and the through electrode 103. Furthermore, during heat treatment, as... Figure 13 As shown in (b), due to the difference in the coefficients of thermal expansion between the glass substrate 102 and the through electrode 103, the through electrode 103 may bulge relative to the first or second surface of the glass substrate 102. Furthermore, during heat treatment, residual moisture or hydrogen gaseous components in the material constituting the through electrode 103 may be released, potentially causing the through electrode 103 to lift. If such a gap or expansion occurs, the conductive layer or pads disposed near the boundary between the through electrode and the glass substrate may become disconnected. Additionally, wiring connected to the pads may also become disconnected.

[0273] In this embodiment, the coated insulating layer 104, as described below, can be made of resin. Figure 23 As shown, when the insulating layer 104 is configured as the boundary α between the glass substrate 102 and the through electrode 103, since a portion of the insulating layer 104 contacts a portion of the through electrode 103, even if gas is released from inside the through electrode 103 during heat treatment, the gas can be released to the outside through the insulating layer 104. Therefore, the first conductive layer 106a of the first wiring layer 106 disposed near the boundary α can avoid expansion. Furthermore, by configuring the insulating layer 104 as the boundary α between the glass substrate 102 and the through electrode 103, even if a gap is generated between the through electrode 103 and the glass substrate 102 during heat treatment, the insulating layer 104 can cover the gap between the through electrode 103 and the glass substrate 102, thus preventing the first conductive layer 106a of the first wiring layer 106 located at the boundary α from becoming open-circuited. Furthermore, even if gaps or expansion during heat treatment cause a step difference between the through electrode 103 and the glass substrate 102, the covering insulating layer 104 can absorb the step difference between the through electrode 103 and the glass substrate 102. Therefore, the first conductive layer 106a of the first wiring layer 106 disposed near the boundary α can avoid the generation of steep step differences.

[0274] Furthermore, in this embodiment, the elastic insulating layer 7, as described below, can be an elastomer. Figure 26 As shown, when the elastic insulating layer 107 also serves as the covering insulating layer 104, and the elastic insulating layer 107 is configured to cover the boundary α between the glass substrate 102 and the through electrode 103, since a portion of the elastic insulating layer 107 contacts a portion of the through electrode 103, even if gas is released from inside the through electrode 103 during heat treatment, the gas can be released to the outside through the elastic insulating layer 107. Therefore, expansion can be avoided in the wiring substrate connection pad portion 109 located near the boundary α. Furthermore, by configuring the elastic insulating layer 107 to cover the boundary α between the glass substrate 102 and the through electrode 103, even if a gap is generated between the through electrode 103 and the glass substrate 102 during heat treatment, the gap between the through electrode 103 and the glass substrate 102 can be covered by the elastic insulating layer 107, thus preventing the wiring substrate connection pad portion 109 located at the boundary α from becoming open-circuited. Furthermore, even if gaps or expansion during heat treatment cause a step difference between the through electrode 103 and the glass substrate 102, the elastic insulating layer 107 can absorb the step difference between the through electrode 103 and the glass substrate 102. Therefore, the wiring substrate connection pad portion 109 disposed near the boundary α can avoid the generation of steep step differences.

[0275] In this way, by configuring the covering insulating layer as the boundary between the covered glass substrate and the through electrode, open circuits in the conductive layer or pads located near the boundary between the through electrode and the glass substrate can be avoided. This results in improved yield.

[0276] Therefore, this implementation method can improve connection reliability.

[0277] The following describes the various structures of the through electrode substrate in this embodiment.

[0278] 1. Elastic insulation layer

[0279] In this embodiment, the elastic insulating layer is disposed on the side opposite to the glass substrate covered by the insulating layer, and has a third through hole that penetrates the covered insulating layer in the thickness direction.

[0280] (1) Characteristics of elastic insulating layer

[0281] The characteristics of the elastic insulating layer in this embodiment are the same as those described in the first embodiment above, "A. Through electrode substrate intermediate 1. Elastic insulating layer (2) Characteristics of elastic insulating layer", so the description is omitted here. In addition, there is only one difference, that is, the surface of the elastic insulating layer pressed in by the Glass indenter is the surface of the wiring substrate connection pad portion of the elastic insulating layer.

[0282] (2) Material of elastic insulating layer

[0283] The material of the elastic insulating layer in this embodiment is the same as that described in the first embodiment above, “A. Through electrode substrate intermediate 1. Elastic insulating layer (3) Material of elastic insulating layer”, so the description is omitted here.

[0284] (3) Concave-convex shape

[0285] The elastic insulating layer preferably has an uneven shape including multiple protrusions and multiple recesses on the surface of the wiring substrate on the side of the pad portion for connection. For example, in Figure 27 In the process, the elastic insulating layer 107 has a textured shape 110 on the surface of the wiring substrate connection pad portion 109 side, including a plurality of protrusions 110a and a plurality of recesses 110b. Furthermore, for example in... Figure 28In this design, the elastic insulating layer 107 also serves as the covering insulating layer 104, and the elastic insulating layer 107 has a concave-convex shape 110 on the surface of the wiring substrate connection pad portion 109 side, including a plurality of protrusions 110a and a plurality of portions 110b. The elastic insulating layer 107 is elastic, and because it has a concave-convex shape 110 on the surface of the wiring substrate connection pad portion 109 side, the extensibility of the surface of the elastic insulating layer 107 on the side of the wiring substrate connection pad portion 109 is improved. When the surface of the elastic insulating layer 107 on the side of the wiring substrate connection pad portion 109 expands or contracts, the stress caused by the difference in thermal expansion coefficients between the through electrode substrate and the wiring substrate can be further mitigated. Therefore, cracks and open circuits between the second joint and the wiring substrate connection pad portion can be effectively suppressed.

[0286] In the uneven shape, the height difference between adjacent protrusions and concave portions is preferably smaller than the thickness of the elastic insulating layer. This height difference is, for example, 50 μm or less, or 15 μm or less, or 10 μm or less. If the height difference is too large, the surface of the wiring substrate connection pad in the elastic insulating layer may touch the wiring substrate. On the other hand, the height difference is, for example, 1 μm or more, or 3 μm or more, or 5 μm or more. If the height difference is too small, the improved stretchability effect provided by the uneven shape may not be fully obtained. Specifically, the height difference is 1 μm or more and 50 μm or less, or 3 μm or more and 15 μm or less, or 5 μm or more and 10 μm or less. The height difference between adjacent protrusions and concave portions, for example, is... Figure 29 As shown, denoted by the symbol H1, it is the distance between adjacent protrusions 110a and concave portions 110b in the normal direction of the first surface of the glass substrate.

[0287] The height difference between adjacent protrusions and concave sections was determined based on cross-sectional images of the through-electrode substrate taken using a scanning electron microscope (SEM). The height difference between adjacent protrusions and concave sections was set as the arithmetic mean of the height differences at any 10 locations.

[0288] The spacing between adjacent protrusions in the concave-convex shape is not particularly limited. The aforementioned spacing can be, for example, 2 μm or more, 5 μm or more, or 6 μm or more. On the other hand, the aforementioned spacing can be, for example, 20 μm or less, 10 μm or less, or 9 μm or less. Specifically, the aforementioned spacing can be 2 μm or more and 20 μm or less, 5 μm or more and 10 μm or less, or 6 μm or more and 9 μm or less. The spacing between adjacent protrusions is, for example,... Figure 29 As shown, denoted by the symbol P1, it represents the distance between the centers of adjacent protrusions 110a.

[0289] The spacing between adjacent protrusions was determined based on cross-sectional images of the through-electrode substrate taken using a scanning electron microscope (SEM). The spacing between adjacent protrusions was set as the arithmetic mean of the spacings at any 10 locations.

[0290] The convex and concave parts in a concave-convex shape can be arranged regularly or irregularly.

[0291] Regarding the cross-sectional shape of the protrusion, it is preferable that the top of the protrusion is curved. Examples of the cross-sectional shape of the protrusion include a semi-circular or semi-elliptical shape. Similarly, regarding the cross-sectional shape of the concave portion, it is preferable that the bottom of the concave portion is curved. Examples of the cross-sectional shape of the concave portion include a semi-circular or semi-elliptical shape. If the wiring board connection pad portion is disposed on the concave-convex shape of the elastic insulating layer, and the protrusion and concave portion have the shapes described above, then the open circuit of the wiring board connection pad portion can be suppressed.

[0292] The location of the raised / lower shape on the surface of the wiring substrate connection pads in the elastic insulating layer is not particularly limited. The raised / lower shape can be configured on the entire surface or only partially on the surface of the wiring substrate connection pads in the elastic insulating layer. For example, in... Figure 27 and Figure 28 In the elastic insulating layer 107, on the surface of the wiring substrate connection pad portion 109 side, a portion is provided with an uneven shape 110. For example, in Figure 30 and Figure 31 In the elastic insulating layer 107, on the surface of the wiring substrate connection pad portion 109 side, a concave shape 110 is arranged across the entire surface. For example, Figure 27 , Figure 28 , Figure 30 , Figure 31 As shown, on the surface of the elastic insulating layer 107 on the side of the wiring substrate connection pad portion 109, a concave-convex shape 110 is preferably disposed at least in the region between adjacent wiring substrate connection pad portions 109. As described above, the concave-convex shape can further mitigate the stress caused by the difference in thermal expansion coefficients between the through electrode substrate and the wiring substrate. Therefore, for a semiconductor device having a through electrode substrate, cracks and open circuits between the second junction portion and the wiring substrate connection pad portion can be effectively suppressed.

[0293] (4) Morphology of the elastic insulating layer

[0294] In this embodiment, as described above, the elastic insulating layer may or may not serve as the covering insulating layer. Preferably, the elastic insulating layer does not serve as the covering insulating layer, i.e., both the elastic insulating layer and the covering insulating layer are provided separately. The covering insulating layer will be described later.

[0295] The thickness of the elastic insulating layer can be, for example, 5 μm or more, or 15 μm or more, or 50 μm or more. If the thickness of the elastic insulating layer is within the above range, the surface of the wiring substrate connection pad portion in the elastic insulating layer is prone to expansion and contraction. On the other hand, the thickness of the elastic insulating layer can be, for example, 200 μm or less, or 100 μm or less, or 60 μm or less. If the thickness of the elastic insulating layer is too thick, it may increase the overall thickness of the through electrode substrate. Specifically, the thickness of the elastic insulating layer is 5 μm or more and 200 μm or less, or 15 μm or more and 100 μm or less, or 50 μm or more and 60 μm or less.

[0296] In this specification, the thickness of each layer is determined based on cross-sectional images of the through-electrode substrate taken using a scanning electron microscope (SEM). The thickness is set as the arithmetic mean of the thicknesses at any five locations.

[0297] (5) Method for forming elastic insulating layer

[0298] The elastic insulating layer can be formed by coating the aforementioned material. Furthermore, the method for forming the third through-hole can be appropriately selected according to the material of the elastic insulating layer; for example, photolithography, laser processing, or die forming can be used. In the case of photolithography, the material of the elastic insulating layer can be a photosensitive material, or a resist pattern can be formed on the elastic insulating layer. In the case of die forming, a rough and uneven shape can be formed on the surface of the elastic insulating layer using a die, and the third through-hole can also be formed on the elastic insulating layer using the same die. Furthermore, as a method for forming the rough and uneven shape, die forming can be used as an example.

[0299] 2. Second via

[0300] In this embodiment, the second via is disposed in the third through hole of the above-mentioned elastic insulating layer and is electrically connected to the pad portion for connecting the first via and the wiring substrate.

[0301] As for the material of the second via, there are no special restrictions as long as the material is conductive. The conductive material used for general vias can be used, and it can be appropriately selected according to the shape or formation method of the via.

[0302] As a method for forming the second via, a general via forming method can be used, and the appropriate method can be selected according to the via shape, etc. The method for forming the second via firstly involves forming a third through-hole in the elastic insulating layer, and then forming the second via within the third through-hole in the elastic insulating layer. Examples of methods for forming the via within the third through-hole in the elastic insulating layer include PVD methods such as vacuum evaporation and sputtering, or CVD methods and plating methods. Alternatively, a via can be formed by filling the third through-hole in the elastic insulating layer with a conductive material, and simultaneously forming a wiring substrate connection pad portion with this conductive material. Furthermore, in the case of plating, firstly, a third through-hole is formed on the elastic insulating layer, then a seed layer is formed on the entire surface of the elastic insulating layer using a sputtering method or the like. Next, a photoresist layer is formed on the seed layer. Then, the photoresist layer is patterned to have openings for the wiring substrate connection pads. Finally, electroplating is applied to the openings of the photoresist layer to form a plating layer, while simultaneously forming the second through-hole and the wiring substrate connection pads. In this case, the second through-hole and the wiring substrate connection pads have both a seed layer and a plating layer.

[0303] 3. Covered insulation layer

[0304] In this embodiment, the coated insulating layer is configured to cover at least the boundary between the electrode and the glass substrate, and has a second through hole connected to the first through hole and penetrating the coated insulating layer in the thickness direction.

[0305] The insulating coating is preferably in direct contact with the glass substrate.

[0306] The material for the insulating layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamide-imide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetheretherketone, polyethersulfone, polycarbonate, polyetherimide, epoxy resin, phenolic resin, polyphenylene ether, acrylic resin, polyolefin, polycyclic olefin, and liquid crystal polymers. Examples of polyolefins include polyethylene and polypropylene. Examples of polycyclic olefins include polynorbornene.

[0307] Figure 32 (a)~ Figure 32 (c) is a schematic cross-sectional view illustrating the arrangement of the first through-hole and the covering insulating layer in a glass substrate with an through-electrode substrate. Figure 32 (a)~ Figure 32 In (c), structures other than the glass substrate and the covering insulating layer are omitted. For example... Figure 32 As shown in (a), the second through hole 104c in the coated insulating layer 104 is connected to the first through hole 102c in the glass substrate 102. The central axis C1 of the first through hole 102c in the glass substrate 102 is preferably substantially aligned with the central axis C2 of the second through hole 104c in the coated insulating layer 104.

[0308] Furthermore, the opening diameter d2 of the second through-hole 104c of the coated insulating layer 104 on the glass substrate 102 side is preferably smaller than the opening diameter d1 of the first through-hole 102c of the glass substrate 102 on the first surface 102a side. The ratio of d2 / d1 is, for example, 0.5 or more and less than 1.0, or it may be 0.6 or more and less than 0.9. The opening diameter d1 of the first through-hole 102c of the glass substrate 102 on the first surface 102a side is, for example, 50 μm or more and less than 100 μm, or it may be 60 μm or more and less than 90 μm. On the other hand, the opening diameter d2 of the second through-hole 104c of the coated insulating layer 104 on the glass substrate 102 side is not particularly limited, for example, it is 40 μm or more and less than 85 μm, or it may be 50 μm or more and less than 80 μm.

[0309] Furthermore, the edge E4 of the opening of the second through-hole 104c on the side of the glass substrate 102 covered by the insulating layer 104 is preferably disposed further inside the edge E1 of the opening of the first through-hole 102c on the first surface 102c of the glass substrate 102. By configuring the insulating layer 104 having this second through-hole 104c, the boundary α between the glass substrate 102 and the through electrode 103 can be covered by the insulating layer 104.

[0310] The cross-sectional shape of the second through hole 104c of the covered insulating layer 104, for example, is as follows: Figure 32 (b) shows an inverted conical shape, such that the opening diameter d2 of the second through-hole 104c on the glass substrate 2 side is preferably smaller than the opening diameter d3 of the second through-hole 104c on the opposite side of the glass substrate 102 side. If the second through-hole 104c is inverted conical, the angle θ between the sidewall SS of the second through-hole 104c and the surface of the covered insulating layer 104 opposite to the glass substrate 102 side, viewed in cross-section along the thickness direction of the covered insulating layer 104, becomes an obtuse angle. Therefore, even if the through electrode 103 expands, stress concentration can be avoided near the edge E3 of the opening of the second through-hole 104c on the surface of the covered insulating layer 104 opposite to the glass substrate 102 side. Therefore, it is possible to prevent open circuits in the pad portion or conductive layer disposed on the surface of the covered insulating layer opposite to the glass substrate.

[0311] The aforementioned angle θ is not particularly limited; for example, it can be greater than 90 degrees and less than 130 degrees, or greater than 100 degrees and less than 120 degrees. By keeping the aforementioned angle θ within the above range, it is possible to further prevent open circuits in the pad portion or conductive layer disposed on the side opposite to the glass substrate covered by the insulating layer. On the other hand, if the aforementioned angle θ is too large, the opening diameter d3 of the second through hole 104c on the opposite side of the glass substrate 102 side will be too large, which may not be suitable for high-density mounting.

[0312] For example, Figure 32As shown in (c), when viewed in cross-section along the thickness direction of the insulating layer 104, the opening edge E3 of the second through hole 104c on the side of the insulating layer 104 opposite to the glass substrate 102 preferably has a curved surface. By making the edge E3 curved, it is possible to further prevent the pad portion or conductive layer disposed on the side of the insulating layer opposite to the glass substrate from being open-circuited.

[0313] The method for forming the second through hole can be appropriately selected according to the material of the insulating layer, for example, photolithography or laser processing. In the case of photolithography, the material of the insulating layer can be a photosensitive material, or a resist pattern can be formed on the insulating layer.

[0314] 4. First via

[0315] In this embodiment, the first via is disposed within the second through-hole covered by the above-mentioned insulating layer and is electrically connected to the through electrode, the second via, and the wiring board connection pad. Preferably, the first via is directly connected to the through electrode.

[0316] The first via can be a via that fills the second through hole of the covered insulation layer, also known as a filled via; or a via that is only disposed on the sidewall of the second through hole of the covered insulation layer, also known as a conformal via.

[0317] The material of the first via is the same as that of the through electrode described later. Preferably, the material of the through electrode and the material of the first via are the same.

[0318] The first via is formed, for example, by electroplating. When the conductive layer of the first wiring layer (described later) is disposed on the side of the covered insulating layer opposite to the glass substrate, it is preferable that the first via is formed simultaneously with the conductive layer of the first wiring layer. Furthermore, when the aforementioned elastic insulating layer also serves as the covered insulating layer, it is preferable that the first via is formed simultaneously with the pad portion for connecting the wiring substrate.

[0319] 5. Glass substrate

[0320] The glass substrate of this embodiment has a first surface and a second surface facing the first surface, and has a first through hole that penetrates the glass substrate in the thickness direction.

[0321] Because of the good flatness of the glass substrate, fine wiring can be formed with small pitch. In addition, the coefficient of thermal expansion of the glass substrate can be adjusted by its composition, thus allowing the selection of a glass substrate with an ideal coefficient of thermal expansion.

[0322] Examples of glass used as glass substrates include alkali-free glass and quartz.

[0323] The coefficient of thermal expansion of the glass substrate is preferably, for example, 2 ppm / ℃ or higher and 9 ppm / ℃ or lower.

[0324] If the coefficient of thermal expansion of the glass substrate is within the above range, the difference between the coefficient of thermal expansion of the glass substrate and the coefficient of thermal expansion of the component can be sufficiently reduced.

[0325] In this specification, the coefficient of thermal expansion is the coefficient of linear expansion. The coefficient of thermal expansion is determined by thermomechanical analysis (TMA) in accordance with JIS R3102:1995.

[0326] There are no particular restrictions on the top view shape of the glass substrate; for example, rectangles, squares, and other shapes can be used.

[0327] The top view shape of the first through-hole in the glass substrate is, for example, approximately circular. Furthermore, the cross-sectional shape of the first through-hole 102c in the glass substrate 102 can be exemplified by, for example, as shown below. Figure 23 The shown straight bar shape; such as Figure 12 As shown in (a), the inverted cone shape has a larger opening diameter on the first surface 102a side than on the second surface 102b side; Figure 12 As shown in (b), the opening diameter on the first face 102a side is smaller than the opening diameter on the second face 102b side, forming a positive cone shape; Figure 12 (c) shows an hourglass shape with a portion that is the smallest diameter at a predetermined position between the first surface 102a and the second surface 102b; and as shown in Figure 12 As shown in (d), the designated position between the first face 102a and the 102nd face 2b forms an arc shape with the maximum diameter. Figure 12 (a)~ Figure 12 (d) is a schematic cross-sectional view illustrating the cross-sectional shape of the first through-hole in the glass substrate. The cross-sectional shape of the first through-hole in the glass substrate is preferably either an inverted cone shape or an hourglass shape. Furthermore, regarding the individual cross-sectional shape of the first through-hole in the glass substrate, the opening edge E1 of the first through-hole 102c on the first surface 102a of the glass substrate 102, the opening edge E2 of the first through-hole 102c on the second surface 102b of the glass substrate 102, and the minimum and maximum diameter portions of the first through-hole 102c in the glass substrate 102 preferably have curved surfaces. This can suppress the occurrence of open circuits between the through electrode and the via or conductive layer contacting the through electrode.

[0328] The thickness of the glass substrate can be, for example, 100 μm or more, or 200 μm or more, or 300 μm or more, or 400 μm or more. By setting the thickness of the glass substrate within the above range, the increase in glass substrate deflection can be suppressed. Therefore, it is possible to avoid difficulties in handling the glass substrate during the manufacturing process, or to avoid the glass substrate bending caused by internal stress of films, etc., disposed on the first or second surface of the glass substrate. On the other hand, the thickness of the glass substrate can be, for example, 2000 μm or less, or 1000 μm or less, or 800 μm or less. If the thickness of the glass substrate is within the above range, the time required for the process of forming through holes in the glass substrate is shortened. Specifically, the thickness of the glass substrate can be 100 μm or more and 2000 μm or less, or 200 μm or more and 1000 μm or less, or 300 μm or more and 1000 μm or less, or 400 μm or more and 800 μm or less.

[0329] 6. Through electrode

[0330] In this embodiment, the through electrode is disposed in the first through hole of the glass substrate.

[0331] As a through electrode, its shape is not particularly limited as long as it can electrically connect the first and second surfaces of the glass substrate. The through electrode can be, for example, a through electrode that fills the first through hole of the glass substrate, also known as a filled via; or a through electrode disposed only on the sidewall of the first through hole of the glass substrate, also known as a conformal via. Furthermore, if the through electrode is a conformal via, a hollow portion can be disposed within the first through hole, or a resin portion can be filled within the through hole. Considering that thermal expansion or gas can easily cause problems with the through electrode, to fully utilize the effect of this embodiment, the through electrode is preferably a filled form in which the first through hole is filled with a conductive material.

[0332] Other items of the through electrode are the same as those described in the first embodiment above, namely "A. Through electrode substrate intermediate 6. Through electrode", so they are omitted here.

[0333] 7. Pads for connecting wiring substrates

[0334] In this embodiment, the wiring substrate connection pad is disposed on the side of the elastic insulating layer opposite to the glass substrate and is electrically connected to the second via and the wiring substrate. The wiring substrate connection pad is directly connected to the second via without routing. That is, the wiring substrate connection pad directly contacts the second via. Furthermore, as described later, in this embodiment, the wiring substrate connection pad in the through electrode substrate is electrically connected to the wiring substrate via a second joint, without routing. In other words, on the side of the elastic insulating layer opposite to the glass substrate, there is no routing for electrically connecting the wiring substrate connection pad to the second via, nor is there routing for electrically connecting the wiring substrate connection pad to the wiring substrate.

[0335] There are no particular restrictions on the material used for the pads in wiring substrate connections, as long as the material is conductive; generally, conductive materials used in wiring can be used. Examples of conductive materials include metals such as copper, molybdenum, titanium, tungsten, tantalum, aluminum, gold, silver, nickel, and palladium, including alloys selected from at least one of these metals, or metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). Copper is preferred.

[0336] There are no particular limitations on the top view shape of the pad portion used for wiring board connection; for example, it can be circular, elliptical, square, or rectangular.

[0337] The thickness of the pad portion for wiring substrate connection is the same as the thickness of general wiring. The thickness of the pad portion for wiring substrate connection is, for example, 0.05 μm or more and 100 μm or less, or 0.1 μm or more and 50 μm or less, or 0.2 μm or more and 10 μm or less. This ensures sufficient conductivity.

[0338] As a method for forming the pad portion for wiring substrate connection, a general wiring formation method can be used, such as a dry film formation method of PVD such as CVD or sputtering, or a method of forming a conductive film by plating and then patterning the conductive film by photolithography.

[0339] Furthermore, the pads for connecting the wiring substrate are preferably arranged in a regular pattern when viewed from above. This ensures that, during the manufacturing process of a semiconductor device using a through-electrode substrate, the second junction where the through-electrode substrate and the wiring substrate are electrically connected receives uniform thermal stress. The result is improved yield.

[0340] 8. First wiring layer

[0341] The through electrode substrate of this embodiment may have a first wiring layer disposed between the covered insulating layer and the elastic insulating layer, and electrically connected to the first via and the second via.

[0342] The first wiring layer has at least a first conductive layer. The first wiring layer may further have a first interlayer insulating layer and a fourth via. The first conductive layer can be one layer or two or more layers. When the first wiring layer has two or more first conductive layers, each first conductive layer is stacked in the thickness direction with a first interlayer insulating layer in between. Furthermore, each first conductive layer is electrically connected via a fourth via. For example, in… Figure 33 In the first wiring layer 106, starting from the glass substrate 2 side, there are a first conductive layer 106a, a first interlayer insulating layer 106b, a first conductive layer 106a, a first interlayer insulating layer 106b, and a first conductive layer 106a in sequence, and each first conductive layer 106a is electrically connected by a fourth via 106c.

[0343] There are no particular restrictions on the material used for the first conductive layer, as long as it is conductive; conductive materials commonly used in intermediate layer wiring can be used. Examples of conductive materials include metallic materials such as metals or metal oxides, conductive resins containing conductive fillers and resins, and conductive polymers.

[0344] The thickness of the first conductive layer is, for example, 0.1 μm or more, or 0.5 μm or more, or 1 μm or more, or 3 μm or more, or 5 μm or more. On the other hand, the thickness of the first conductive layer is, for example, 20 μm or less, or 15 μm or less. The thickness of the first conductive layer is, for example, 0.1 μm or more and 20 μm or less, or 0.5 μm or more and 15 μm or less, or 1 μm or more and 15 μm or less, or 3 μm or more and 15 μm or less, or 5 μm or more and 15 μm or less. For example, when the first conductive layer is formed by sputtering, a relatively thin first conductive layer can be obtained. Furthermore, for example, when the first conductive layer is formed by plating, a relatively thick first conductive layer can be obtained.

[0345] The first conductive layer can be formed by either an additive or a subtractive method. For example, by forming a resist pattern using photolithography and then plating the exposed portions of the resist pattern, a patterned wiring layer can be obtained. In the case of electroplating, before forming the resist pattern, a conductive film can also be formed on the first surface of the glass substrate or on the surface of the first interlayer insulating layer opposite to the glass substrate. For example, by forming a resist pattern on a conductive layer formed across the entire first surface of the glass substrate and then etching the exposed portions of the resist pattern, a patterned first conductive layer can be obtained.

[0346] The material for the first interlayer insulation layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamide-imide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetheretherketone, polyethersulfone, polycarbonate, polyetherimide, epoxy resin, phenolic resin, polyphenylene ether, acrylic resin, polyolefin, polycyclic olefin, and liquid crystal polymers. Examples of polyolefins include polyethylene and polypropylene. Examples of polycyclic olefins include polynorbornene.

[0347] The thickness of the first interlayer insulation layer is, for example, 1.5 μm or more, or 2.5 μm or more. On the other hand, the thickness of the first interlayer insulation layer is, for example, 6 μm or less. The thickness of the first interlayer insulation layer is, for example, 1.5 μm or more and 6 μm or less, or 2.5 μm or more and 6 μm or less.

[0348] Methods for forming the first interlayer insulating layer include, for example, photolithography and printing.

[0349] As the fourth via, it is the same as the second via mentioned above.

[0350] 9. Second insulating layer and third via

[0351] The through electrode substrate of this embodiment has: a second coated insulating layer disposed on the second surface of the glass substrate, covering at least the boundary between the through electrode and the glass substrate, and having a fourth through hole connecting the first through hole; and a third through hole disposed in the fourth through hole of the second coated insulating layer and electrically connected to the through electrode.

[0352] exist Figure 34 and Figure 35 In the embodiment, the through-electrode substrate 1 has: a second coated insulating layer 113 disposed on the second surface 102b side of the glass substrate 102, covering at least the boundary β between the through-electrode 103 and the glass substrate 102, and having a fourth through-hole 113c connecting the first through-hole 102c; and a third via 114 disposed within the fourth through-hole 113c of the second coated insulating layer 113, electrically connected to the through-electrode 103, and electrically connected to the component connection pad portion 111. Figure 34 and Figure 35 In the second insulating layer 113, a second wiring layer 112 comprising a second conductive layer 112a, a second interlayer insulating layer 112b, and a fifth via 112c is disposed on the side opposite to the glass substrate 102. A third via 114 is electrically connected to the component connection pad portion 111 via the second conductive layer 112a and the fifth via 112c of the second wiring layer 112.

[0353] The second insulating layer has the same effect as the aforementioned insulating layer. The second insulating layer and the third via are the same as the aforementioned insulating layer and the aforementioned first via.

[0354] 10. Second wiring layer

[0355] The through electrode substrate of this embodiment may have: a second wiring layer disposed on the second side of the glass substrate and electrically connected to the through electrode.

[0356] The second wiring layer has at least a second conductive layer. The second wiring layer may further have a second interlayer insulating layer and a fifth via. The second conductive layer can be one layer or two or more layers. When the second wiring layer has two or more second conductive layers, each second conductive layer is stacked in the thickness direction with a second interlayer insulating layer in between. Furthermore, each second conductive layer is electrically connected via a fifth via. For example, in… Figure 34 and Figure 35 In this second wiring layer 112, starting from the glass substrate 102 side, it sequentially includes a second conductive layer 112a, a second interlayer insulating layer 112b, another second conductive layer 112a, another second interlayer insulating layer 112b, another second conductive layer 112a, another second interlayer insulating layer 112b, and another second conductive layer 112a. Each of the second conductive layers 112a is electrically connected by a fifth via 112c. The second conductive layer 112a located on the surface of the second wiring layer 112 opposite to the glass substrate 102 includes a component connection pad portion 111.

[0357] The second conductive layer and the insulating layer between the second and third layers in the second wiring layer are the same as the first conductive layer and the insulating layer between the first and third layers in the first wiring layer.

[0358] The top view shape of the component connection pad is the same as the top view shape of the wiring board connection pad described above.

[0359] B. Through-electrode substrate with components

[0360] The through electrode substrate with components in this embodiment includes the through electrode substrate described above, and components mounted on the through electrode substrate.

[0361] Figure 24 This is a schematic cross-sectional view showing an example of a through-electrode substrate with components in this embodiment. (See attached image.) Figure 24 As shown, the through electrode substrate 20 with components includes the through electrode substrate 101 described above; a first bonding portion 121 electrically connected to the component bonding pad portion 111 of the through electrode substrate 101; and a component 122 electrically connected to the first bonding portion 121.

[0362] The through-electrode substrate with components in this embodiment has the above-mentioned through-electrode substrate, thus enabling the suppression of open circuits and improving connection reliability.

[0363] The following describes the various structures of the through electrode substrate with components in this embodiment.

[0364] 1. Through-electrode substrate

[0365] The through-electrode substrate has been described in detail in "A. Through-electrode substrate" above, so the description is omitted here.

[0366] 2. Components

[0367] The components in this embodiment are the same as those described in the first embodiment above, namely "C. Through electrode substrate 2. Component with component", so the description is omitted here.

[0368] C. Semiconductor devices

[0369] The semiconductor device of this embodiment includes: the through electrode substrate with the above-mentioned components; and a wiring substrate with wiring substrate connection pads electrically connected to the through electrode substrate.

[0370] Figure 25 This is a schematic cross-sectional view showing an example of the semiconductor device in this embodiment. (e.g.) Figure 25 As shown, the semiconductor device 130 includes: the aforementioned through electrode substrate 101; a first bonding portion 121 electrically connected to a component connection pad portion 111 of the through electrode substrate 101; a component 122 electrically connected to the first bonding portion 121; a second bonding portion 131 electrically connected to a wiring substrate connection pad 109 of the through electrode substrate 1; and a wiring substrate 132 electrically connected to the second bonding portion 131.

[0371] The semiconductor device of this embodiment has the through electrode substrate with the above-mentioned components, thus enabling it to suppress open circuits and improve connection reliability.

[0372] The following describes the various structures of the semiconductor device in this embodiment.

[0373] 1. Through-electrode substrate with components

[0374] The through-electrode substrate with components has been described in detail in "B. Through-electrode substrate with components" above, so the description is omitted here.

[0375] 2. Wiring substrate

[0376] In this embodiment, a general wiring substrate can be used.

[0377] The wiring substrate connection pad of the through electrode substrate is electrically connected to the wiring substrate via the second joint.

[0378] The material used for the second joint is the same as that used for the first joint.

[0379] 3. Uses

[0380] The application of the semiconductor device in this embodiment is not particularly limited, and examples include notebook computers, tablet computers, mobile phones, smartphones, digital cameras, digital clocks, servers, etc.

[0381] Furthermore, this disclosure is not limited to the embodiments described above. The embodiments described above are examples, and any embodiment that has a substantially identical structure and performs the same function as the technical concept described in the claims of this disclosure is included within the technical scope of this disclosure.

[0382] This disclosure provides the following invention.

[0383] [1] A through-electrode substrate intermediate, comprising:

[0384] A glass substrate has a first surface and a second surface facing the first surface, and has a through hole;

[0385] A through electrode is disposed within the through hole of the glass substrate.

[0386] An elastic insulating layer is disposed on the first surface side of the glass substrate.

[0387] Through-hole, penetrating the above-mentioned elastic insulating layer and electrically connected to the above-mentioned through-hole electrode;

[0388] The via pad is disposed on the side of the elastic insulating layer opposite to the glass substrate and is electrically connected to the via; and

[0389] The wiring substrate connection pad is disposed on the side of the elastic insulating layer opposite to the glass substrate and is electrically connected to the wiring substrate. The elastic insulating layer has a concave-convex shape including multiple protrusions and multiple recesses on the side of the via pad and the wiring substrate connection pad.

[0390] [2] The through-electrode substrate intermediate as described in [1] has the following characteristics:

[0391] An insulating layer is disposed between the glass substrate and the elastic insulating layer, at least covering the boundary between the through electrode and the glass substrate, and having a second through hole connecting the through hole; and

[0392] The second via is disposed in the second through hole covered by the above-mentioned insulating layer, electrically connected to the through electrode, and electrically connected to the via pad portion.

[0393] [3] As described in [2], the through electrode substrate intermediate, wherein the elastic insulating layer also serves as the covered insulating layer, and the via also serves as the second via.

[0394] [4] The through-electrode substrate intermediate as described in any of [1] to [3] has the following characteristics:

[0395] The component connection pad is disposed on the second side of the glass substrate, electrically connected to the through electrode, and electrically connected to the component.

[0396] [5] The through-electrode substrate intermediate as described in any of [1] to [4] has the following characteristics:

[0397] A second insulating layer is disposed on the second surface of the glass substrate, covering at least the boundary between the through electrode and the glass substrate, and has a third through hole connecting the through hole; and

[0398] The third via is disposed in the third through hole of the second covered insulating layer and is electrically connected to the through electrode.

[0399] [6] A through-electrode substrate comprising:

[0400] The through-electrode substrate intermediate as described in any of [1] to [5]; and

[0401] The snake-belly wiring layer is disposed on the side of the elastic insulating layer in the intermediate body of the through electrode substrate, and includes a snake-belly shaped portion having multiple peaks and multiple valleys, and electrically connects the via pad portion to the wiring substrate connection pad portion.

[0402] [7] A through-electrode substrate with elements, comprising:

[0403] [6] The through-electrode substrate described therein; and

[0404] The component is mounted on the aforementioned through electrode substrate.

[0405] [8] A semiconductor device having:

[0406] [7] The through-electrode substrate with components described therein; and

[0407] Wiring substrate, with wiring substrate connection pads electrically connected to the aforementioned through electrode substrate.

[0408] [9] A through-electrode substrate, comprising:

[0409] A glass substrate has a first surface and a second surface facing the first surface, and has a first through hole;

[0410] A through electrode is disposed within the first through hole of the glass substrate.

[0411] An insulating layer is disposed on the first surface of the glass substrate, covering at least the boundary between the through electrode and the glass substrate, and having a second through hole connecting the first through hole; and

[0412] The first via is disposed in the second through hole covered with the above-mentioned insulating layer and is electrically connected to the through electrode.

[0413] An elastic insulating layer is disposed on the side opposite to the glass substrate covered by the insulating layer, and has a third through hole;

[0414] The second via is disposed within the third through hole of the aforementioned elastic insulating layer and is electrically connected to the aforementioned first via; and

[0415] The wiring substrate connection pad is disposed on the side opposite to the covered insulating layer of the above-mentioned elastic insulating layer, electrically connected to the above-mentioned second via, and electrically connected to the wiring substrate.

[0416]

[10] As described in [9], the through electrode substrate has an uneven shape on the side of the wiring substrate connection pad portion, which includes a plurality of protrusions and a plurality of recesses.

[0417]

[11] As described in [9] or

[10] , the through electrode substrate wherein the cross-sectional shape of the second through hole in the thickness direction of the covered insulating layer is an inverted cone shape.

[0418]

[12] The through electrode substrate described in any of [9] to

[11] , wherein, in a cross-sectional view in the thickness direction of the covered insulating layer, the edge of the opening of the second through hole on the surface of the covered insulating layer opposite to the glass substrate has a curved surface.

[0419]

[13] The through electrode substrate as described in any of [9] to

[12] , wherein the elastic insulating layer also serves as the covered insulating layer, and the second via also serves as the first via.

[0420]

[14] The through electrode substrate as described in any of [9] to

[13] has:

[0421] The component connection pad is disposed on the second side of the glass substrate, electrically connected to the through electrode, and electrically connected to the component.

[0422]

[15] The through electrode substrate as described in any of [9] to

[14] has:

[0423] A second insulating layer is disposed on the second surface of the glass substrate, covering at least the boundary between the through electrode and the glass substrate, and having a fourth through hole connecting the first through hole; and

[0424] The third via is disposed in the fourth through hole of the second covered insulating layer and is electrically connected to the through electrode.

[0425]

[16] A through-electrode substrate with elements, comprising:

[0426] The through-electrode substrate described in any of [9] to

[15] ; and

[0427] The component is mounted on the aforementioned through electrode substrate.

[0428]

[17] A semiconductor device having:

[0429] As described in

[16] , a through-electrode substrate with components; and

[0430] Wiring substrate, with wiring substrate connection pads electrically connected to the aforementioned through electrode substrate.

[0431] Explanation of reference numerals in the attached figures

[0432] 1: Through-electrode substrate intermediate; 2, 102: Glass substrate; 2a, 102a: First surface of glass substrate; 2b, 102b: Second surface of glass substrate; 3, 103: Through-electrode; 4: First wiring layer; 4a: Conductive layer; 5: Elastic insulating layer; 6: Via; 7: Via pad portion; 8: Wiring substrate connection pad portion; 9: Undulated shape; 9a: Raised portion; 9b: Recessed portion; 11: Component connection pad 15: Covered insulating layer; 16: Second via; 17: Second covered insulating layer; 18: Third via; 20: Through electrode substrate; 21: Belly-shaped portion; 21a: Peak portion; 21b: Valley portion; 22: Belly-shaped wiring layer; 30: Through electrode substrate with component; 31: First bonding portion; 32: Component; 40: Semiconductor device; 41: Second bonding portion; 42: Wiring substrate; 101: Through electrode substrate; 104: Covered insulating layer; 104c: Second through-hole; 105: First via; 106: First wiring layer; 106a: First conductive layer; 106b: First interlayer insulating layer; 106c: Fourth via; 107: Elastic insulating layer; 107c: Third through-hole; 108: Second via; 109: Pad portion for wiring substrate connection; 110: Undulated shape; 110a: Protrusion; 110b: Recess; 111 112: Component connection pad; 112: Second wiring layer; 112a: Second conductive layer; 112b: Second interlayer insulating layer; 112c: Fifth via; 113: Second covered insulating layer; 113c: Fourth through-hole; 114: Third via; 120: Through electrode substrate with component; 121: First bonding portion; 122: Component; 130: Semiconductor device; 131: Second bonding portion; 132: Wiring substrate.

Claims

1. A through-electrode substrate intermediate, comprising: A glass substrate having a first surface and a second surface facing the first surface, and having a through hole; A through electrode is disposed within the through hole in the glass substrate; An elastic insulating layer is disposed on the first surface side of the glass substrate; A via, which penetrates the elastic insulating layer and is electrically connected to the through electrode; A via pad is disposed on the side of the elastic insulating layer opposite to the glass substrate and electrically connected to the via; and The wiring substrate connection pad is disposed on the side of the elastic insulating layer opposite to the glass substrate and is electrically connected to the wiring substrate. The elastic insulating layer has a concave-convex shape including multiple protrusions and multiple recesses on the surface of the through-hole pad portion and the wiring substrate connection pad portion.

2. The through-electrode substrate intermediate according to claim 1, comprising: An insulating layer is disposed between the glass substrate and the elastic insulating layer, at least covering the boundary between the through electrode and the glass substrate, and having a second through hole connecting the through hole; and The second via is disposed within the second through hole covered by the insulating layer, electrically connected to the through electrode, and electrically connected to the via pad portion.

3. The through-electrode substrate intermediate according to claim 2, wherein, The elastic insulating layer also serves as the covered insulating layer, and the via also serves as the second via.

4. The through-electrode substrate intermediate according to claim 1, comprising: The component connection pad is disposed on the second surface of the glass substrate, electrically connected to the through electrode, and electrically connected to the component.

5. The through-electrode substrate intermediate according to claim 1, comprising: A second insulating layer is disposed on the second surface of the glass substrate, at least covering the boundary between the through electrode and the glass substrate, and has a third through hole connecting the through hole; and The third via is disposed within the third through hole of the second covered insulating layer and is electrically connected to the through electrode.

6. A through-electrode substrate, comprising: The through-electrode substrate intermediate according to any one of claims 1 to 5; and The snake-belly wiring layer, disposed on the side of the elastic insulating layer in the intermediate body of the through electrode substrate, includes a snake-belly shaped portion having multiple peaks and multiple valleys, and electrically connects the via pad portion to the wiring substrate connection pad portion.

7. A through-electrode substrate with components, comprising: The through-electrode substrate of claim 6; and Components mounted on the through electrode substrate.

8. A semiconductor device comprising: The through-electrode substrate with elements as described in claim 7; and Wiring substrate, which is electrically connected to the wiring substrate connection pad of the through electrode substrate.

9. A through-electrode substrate, comprising: A glass substrate having a first surface and a second surface facing the first surface, and having a first through hole; A through electrode is disposed within the first through hole in the glass substrate; An insulating layer is disposed on the first surface side of the glass substrate, covering at least the boundary between the through electrode and the glass substrate, and having a second through hole connecting the first through hole; as well as The first via is disposed within the second through hole of the covered insulating layer and is electrically connected to the through electrode; An elastic insulating layer is disposed on the side opposite to the glass substrate covered by the insulating layer and has a third through hole; The second via is disposed within the third through hole of the elastic insulating layer and is electrically connected to the first via; as well as The wiring substrate connection pad is disposed on the side opposite to the covered insulating layer of the elastic insulating layer, electrically connected to the second via, and electrically connected to the wiring substrate.

10. The through-electrode substrate according to claim 9, wherein, The elastic insulating layer has a concave-convex shape including multiple protrusions and multiple recesses on the side of the pad portion for connecting the wiring substrate.

11. The through-electrode substrate according to claim 9, wherein, The cross-sectional shape of the second through hole in the thickness direction of the covered insulation layer is an inverted cone.

12. The through-electrode substrate according to claim 9, wherein, In a cross-sectional view along the thickness of the covered insulating layer, the edge of the opening of the second through hole on the surface of the covered insulating layer opposite to the glass substrate has a curved surface.

13. The through-electrode substrate according to claim 9, wherein, The elastic insulating layer also serves as the covered insulating layer, and the second via also serves as the first via.

14. The through-electrode substrate according to claim 9, comprising: The component connection pad is disposed on the second side of the glass substrate, electrically connected to the through electrode, and electrically connected to the component.

15. The through-electrode substrate according to claim 9, comprising: A second insulating layer is disposed on the second surface of the glass substrate, at least covering the boundary between the through electrode and the glass substrate, and having a fourth through hole connecting the first through hole; and The third via is disposed within the fourth through hole of the second covered insulating layer and is electrically connected to the through electrode.

16. A through-electrode substrate with elements, comprising: The through-electrode substrate according to any one of claims 9 to 15; and Components mounted on the through electrode substrate.

17. A semiconductor device comprising: The through-electrode substrate with elements as described in claim 16; and Wiring substrate, which is electrically connected to the wiring substrate connection pad of the through electrode substrate.

Images