Array substrate, display panel and display device

Abstract

An array substrate (100) includes a substrate (10), a first conductive layer (20), a first transistor (30), a second signal line (40) and a common electrode layer (50). The first conductive layer (20) is arranged on one side of the substrate (10), and the first conductive layer (20) includes a first signal line (21) and a light shielding pattern (22). The first transistor (30) is arranged on the side of the first conductive layer (20) away from the substrate (10), and includes a first semiconductor layer (31) and a first gate (32) arranged on the side of the first semiconductor layer (31) away from the substrate (10), and the orthogonal projection of the first semiconductor layer (31) on the substrate (10) partially overlaps the orthogonal projection of the light shielding pattern (22) on the substrate (10). The second signal line (40) is arranged on the side of the first gate (32) of the first transistor (30) away from the substrate (10), the second signal line (40) is electrically connected with the first transistor (30), and the orthogonal projection of the second signal line (40) on the substrate (10) partially overlaps the orthogonal projection of the first signal line (21) on the substrate (10). The common electrode layer (50) is arranged on the side of the second signal line (40) away from the substrate (10), and is electrically connected with the first signal line (21).

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, display devices such as mobile phones, televisions, computers and the like have been widely applied. People have higher and higher requirements for display devices, and high resolution and high refresh rate are an important development direction of display devices. The improvement of resolution and refresh rate will put forward higher requirements for display panels, and how to improve the charging efficiency of display panels and reduce the power consumption of display panels is a technical problem to be solved at present.

[0003] SUMMARY

[0004] In one aspect, an array substrate is provided. The array substrate includes a substrate, a first conductive layer, a first transistor, a second signal line and a common electrode layer. The first conductive layer is disposed on one side of the substrate, and the first conductive layer includes a first signal line and a light shielding pattern. The first transistor is disposed on a side of the first conductive layer away from the substrate, and includes a first semiconductor layer and a first gate electrode disposed on a side of the first semiconductor layer away from the substrate, a projection of the first semiconductor layer on the substrate at least partially overlaps a projection of the light shielding pattern on the substrate. The second signal line is disposed on a side of the first semiconductor layer of the first transistor away from the substrate, the second signal line is electrically connected to the first transistor, and a projection of the second signal line on the substrate partially overlaps a projection of the first signal line on the substrate. The common electrode layer is disposed on a side of the second signal line away from the substrate, and is electrically connected to the first signal line.

[0005] In some embodiments, the array substrate further includes a pixel electrode layer. The pixel electrode layer is disposed on a side of the common electrode layer away from the substrate, and includes a pixel electrode and a connection pattern. The pixel electrode is electrically connected to the first transistor, and the connection pattern is respectively electrically connected to the common electrode layer and the first signal line.

[0006] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area. The first signal line includes a first sub-line and a plurality of second sub-lines. The first sub-line is located in the peripheral area and at least partially surrounds the display area. The plurality of second sub-lines are located in the display area, extend along a first direction, and are spaced apart along a second direction. At least one end of each of the second sub-lines is electrically connected to the first sub-line. The second signal line extends along the second direction. A projection of the second signal line on the substrate partially overlaps a projection of the second sub-lines on the substrate and does not overlap a projection of the first sub-line on the substrate. The connection pattern is located in the peripheral area and is electrically connected to the first sub-line. The first direction intersects the second direction.

[0007] In some embodiments, the array substrate further includes a first insulating layer, a second insulating layer, a first via, a third insulating layer, a fourth insulating layer, and a second via. The first insulating layer is disposed between the first conductive layer and the first semiconductor layer. The second insulating layer is disposed between the first gate and the second signal line. The first via penetrates the second insulating layer. The third insulating layer is disposed between the second signal line and the common electrode layer. At least part of the third insulating layer is located in the first via and contacts the first insulating layer through the first via. The fourth insulating layer is disposed between the common electrode layer and the pixel electrode layer. The second via penetrates the fourth insulating layer, the third insulating layer, and the first insulating layer and exposes part of the first sub-line. A projection of the second via on the substrate is located within a projection of the first via on the substrate. The connection pattern is electrically connected to the first sub-line through the second via.

[0008] In some embodiments, the array substrate further comprises a first insulating layer, a second insulating layer, a third via, a first transfer block, a third insulating layer, a fourth insulating layer, and a fourth via. The first insulating layer is disposed between the first conductive layer and the first semiconductor layer. The second insulating layer is disposed between the first gate and the second signal line. The third via penetrates the second insulating layer and the first insulating layer and exposes a portion of the first sub-line. The first transfer block is disposed on a side of the second insulating layer away from the substrate, the first transfer block is at least partially located in the third via, and is electrically connected to the first sub-line through the third via. The third insulating layer is disposed between the second signal line and the common electrode layer. The fourth insulating layer is disposed between the common electrode layer and the pixel electrode layer. The fourth via penetrates the fourth insulating layer and the third insulating layer and exposes a portion of the first transfer block, and a projection of the fourth via on the substrate covers a projection of the third via on the substrate. The connection pattern is at least partially located in the fourth via and is electrically connected to the first transfer block through the fourth via.

[0009] In some embodiments, the first transfer block and the second signal line comprise the same material and are disposed in the same layer.

[0010] In some embodiments, the array substrate further comprises a fifth via. The fifth via penetrates the fourth insulating layer and exposes a partial area of the common electrode layer. A portion of the connection pattern is located in the fifth via and is electrically connected to the common electrode layer through the fifth via.

[0011] In some embodiments, a projection of the fifth via on the substrate at least partially overlaps a projection of the first sub-line on the substrate.

[0012] In some embodiments, the array substrate further comprises an auxiliary wire. The auxiliary wire is located in the peripheral area and is disposed on a side of the common electrode layer close to the substrate, and the auxiliary wire is disposed in parallel with the common electrode layer.

[0013] In some embodiments, the array substrate further comprises a sixth via, the sixth via at least penetrates the fourth insulating layer and the third insulating layer and exposes a portion of the auxiliary wire. A portion of the connection pattern is located in the sixth via and is electrically connected to the auxiliary wire through the sixth via.

[0014] In some embodiments, the auxiliary wire includes a first wire extending along the second direction and being disposed in the same layer and of the same material as the second signal line. The sixth via penetrates through the fourth insulating layer and the third insulating layer and exposes a portion of the first wire, and the connection pattern is electrically connected to the first wire through the sixth via.

[0015] In some embodiments, the auxiliary wire further includes a second wire extending along the second direction, and the second wire is disposed in the same layer and of the same material as the first gate. The array substrate further includes a seventh via penetrating through the second insulating layer, and the first wire is electrically connected to the second wire through the seventh via.

[0016] In some embodiments, the first wire and the second wire have their orthographic projections on the substrate at least partially overlap with the orthographic projection of the first sub-line on the substrate, respectively.

[0017] In some embodiments, the array substrate further includes a third signal line configured to form the first gate, and the orthographic projection of the third signal line on the substrate partially overlaps with the orthographic projection of the first sub-line on the substrate. The second wire includes a plurality of wire segments spaced apart from each other with a first interval between adjacent two wire segments, and the third signal line passes through the first interval and is spaced apart from the wire segments.

[0018] In some embodiments, the array substrate further includes a first pad disposed between the first signal line and the second signal line, and the orthographic projection of the first pad on the substrate partially overlaps with the orthographic projection of the second signal line and the first signal line on the substrate, respectively.

[0019] In some embodiments, the orthographic projection of the first pad on the substrate covers the area where the orthographic projections of the second signal line and the first signal line on the substrate overlap with each other.

[0020] In some embodiments, the first pad and the first semiconductor layer are disposed in the same layer and of the same material.

[0021] In some embodiments, the first transistor further includes a gate insulating layer between the first semiconductor layer and the first gate. The array substrate further includes a second pad having its orthographic projection on the substrate partially overlap with the orthographic projection of the second signal line and the first signal line on the substrate, respectively. The second pad includes a first sub-portion and a second sub-portion stacked, the first sub-portion is disposed in the same layer and of the same material as the first gate, and the second sub-portion is located at the gate insulating layer.

[0022] In some embodiments, a projection of the second bump block on the substrate covers a region where a projection of the second signal line on the substrate and a projection of the first signal line on the substrate coincide with each other.

[0023] In some embodiments, the first sub-portion is electrically connected with the second signal line.

[0024] In some embodiments, a dimension of the second sub-portion in a direction perpendicular to the substrate is greater than a dimension of the second insulating layer in the direction perpendicular to the substrate.

[0025] In some embodiments, the array substrate includes a display region and a peripheral region surrounding the display region. The first transistor is located in the display region, and the first gate extends beyond an edge of the first semiconductor layer in a width direction of a channel structure of the first transistor. The array substrate further includes a second transistor located in the peripheral region, including a second semiconductor layer and a second gate located on a side of the second semiconductor layer away from the substrate, and an end of the second gate extends beyond an edge of the second semiconductor layer in a width direction of a channel structure of the second transistor.

[0026] In some embodiments, a distance by which the end of the first gate extends beyond the edge of the first semiconductor layer in the width direction of the channel structure of the first transistor is greater than or equal to 3 μm. And / or, a distance by which the end of the second gate extends beyond the edge of the second semiconductor layer in the width direction of the channel structure of the second transistor is greater than or equal to 3 μm.

[0027] In some embodiments, the second semiconductor layer includes a plurality of sub-semiconductor layers spaced apart in the width direction of the channel structure of the second transistor, and each of the sub-semiconductor layers has a dimension in the width direction of the channel structure of the second transistor less than or equal to 20 μm.

[0028] In some embodiments, a material of the second semiconductor layer includes a metal oxide semiconductor material. The second semiconductor layer includes a first region and two second regions located on two sides of the first region. A projection of the first region on the substrate is located within a range of a projection of the second gate on the substrate, and a projection of the second region on the substrate coincides with a projection of the second gate on the substrate near an edge of the first region. The second region is more conductive than the first region.

[0029] In another aspect, a display panel is provided, including the array substrate in any of the above embodiments, an opposite substrate, and a liquid crystal layer. The opposite substrate is arranged opposite to the array substrate. The liquid crystal layer is arranged between the array substrate and the opposite substrate.

[0030] In another aspect, a display device is provided. The display device includes the display panel as described in the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0032] FIG. 1 is a plan view of a display device according to some embodiments;

[0033] FIG. 2 is a structural view of a liquid crystal display device according to some embodiments;

[0034] FIG. 3 is a plan view of an array substrate according to some embodiments;

[0035] FIG. 4 is a cross-sectional view along the section line A1-A1 in FIG. 3;

[0036] FIG. 5 is a cross-sectional view along the section line B1-B1 in FIG. 3;

[0037] FIG. 6 is another plan view of an array substrate according to some embodiments;

[0038] FIG. 7 is another plan view of an array substrate according to some embodiments;

[0039] FIG. 8 is a cross-sectional view along the section line B2-B2 in FIG. 7;

[0040] FIG. 9 is another plan view of an array substrate according to some embodiments;

[0041] FIG. 10 is a cross-sectional view along the section line B3-B3 in FIG. 9;

[0042] FIG. 11 is a cross-sectional view of an array substrate according to some embodiments;

[0043] FIG. 12 is another plan view of an array substrate according to some embodiments;

[0044] FIG. 13 is a cross-sectional view along the section line A2-A2 in FIG. 12;

[0045] FIG. 14 is another plan view of an array substrate according to some embodiments;

[0046] FIG. 15 is a sectional view along section line A3-A3 in FIG. 14;

[0047] FIG. 16 is a structural diagram of a transistor according to some embodiments;

[0048] FIG. 17 is a structural diagram of a second transistor according to some embodiments. DETAILED DESCRIPTION

[0049] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0050] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open, inclusive, meaning, i.e., "including, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the present disclosure, terms such as "lower", "below", "above", and "upper" are used to explain the relationship between the components shown in the drawings. The terms can be relative concepts and described based on the direction represented in the drawings, or based on the order of process steps formed, but are not limited thereto.

[0052] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0053] The term "opposite" means that a first element can be opposite to a second element, directly or indirectly. In the case where a third element is interposed between the first element and the second element, the first element and the second element can be understood as being indirectly opposite to each other, although they are still opposite to each other.

[0054] Hereinafter, the terms "first", "second", "third", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implying a specific number of the technical features indicated. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0055] In describing some embodiments, "coupled" and "connected", and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate media. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0056] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0057] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0058] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0059] In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0060] As used herein, "about", "approximately", or "around" includes the stated value and the average value within an acceptable range of deviation from the specific value, as determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the specific quantity (i.e., limitations of the measurement system).

[0061] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions approximating the recited condition within an acceptable range of deviation, where the acceptable range of deviation is as determined by one of ordinary skill in the art taking into account the measurement at issue and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation of, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation of, for example, within 5°. "Equal" includes absolute equality and near equality, where near equality can have an acceptable range of deviation of, for example, a difference between the two that is less than or equal to 5% of either.

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In this regard, the thicknesses of the layers and regions can be exaggerated for clarity. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein, but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have a curved shape. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the exemplary embodiments to a particular shape. The exemplary embodiments are thus to be accorded the scope of the claims and all equivalents thereof.

[0063] Referring to FIG. 1, an embodiment of the present disclosure provides a display device, and a display device 1000 is a product having an image display function. Exemplarily, the display device 1000 can be any device that displays whether moving (e.g., a video) or fixed (e.g., a still image) and whether a letter or an image.

[0064] Exemplarily, the display device 1000 can be a television, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a mobile phone (a cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear view camera in a vehicle), a wearable device, an Augmented Reality (AR) device, a Virtual Reality (VR) device, a Mixed Reality (MR) device, an in-vehicle display, a flight display, or the like, any product or component having a display function.

[0065] In some embodiments, the display device 1000 can be a liquid crystal display (LCD) in terms of the light emitting type of the display device 1000. The display device 1000 can be a flat display device or a curved display device, and the like, in terms of the form of the display device 1000. The display device 1000 can be rectangular or circular, and the like, in terms of the shape of the display device 1000. Of course, embodiments of the display device of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0066] In some embodiments, the display device 1000 can include a display panel 1100 (also referred to as a display substrate) and a driving circuit board. The driving circuit board can include, for example, a timing controller (TCON), a power management chip (DC / DC), and a variable resistance voltage dividing circuit (generating Vcom), and the like, and can further include other circuit structures, which are not listed one by one here. The driving circuit board is electrically connected to the display panel 1100, and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 can further include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize various functions such as touch, photographing, video recording, and fingerprint recognition, which are not listed one by one here.

[0067] In the case of a liquid crystal display device, referring to FIG. 2, the display device 1000 can further include a backlight module 1200 disposed on the backlight side of the display panel 1100, in addition to the display panel 1100 and the driving circuit board. The backlight module 1200 can be a direct type backlight module 1200 or an edge type backlight module 1200, and the like, for example, and is used to provide a light source for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, and each sub-pixel can adjust the amount of light passing through the sub-pixel, thereby making each sub-pixel display the same or different gray scale to achieve the purpose of image display.

[0068] Referring to FIG. 2, in a case where the display panel 1100 is a liquid crystal display panel, the display panel 1100 can include an array substrate 100 and an opposite substrate 200 arranged opposite to each other, and a liquid crystal layer 300 arranged between the array substrate 100 and the opposite substrate 200; the opposite substrate 200 can also be referred to as a color film substrate or an encapsulation substrate. Of course, the structure of the display panel 1100 is not limited to this, and the display panel 1100 can also include other structures as long as the same technical idea is adopted. For example, the display panel 1100 can also include a first alignment film (not shown in the figure) arranged on a side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) arranged on a side of the opposite substrate 200 close to the liquid crystal layer 300, and the like.

[0069] The array substrate 100 can include a plurality of pixel circuits arranged in an array and a plurality of signal lines, for example. The pixel circuit can include at least one thin film transistor (TFT) and at least one capacitor. Exemplarily, the pixel circuit can be a “1T1C” circuit, a “2T1C” circuit, or a “3T1C” circuit, or the like. Wherein, “T” refers to a thin film transistor, and the number before “T” refers to the number of thin film transistors; “C” refers to a capacitor, and the number before “C” refers to the number of capacitors. Of course, the structure of the pixel circuit in the embodiments of the present disclosure is not limited to this, as long as the same technical idea is adopted.

[0070] Exemplarily, the array substrate 100 further includes a common electrode layer and a pixel electrode, and the capacitor described above can be formed between the common electrode layer and the pixel electrode. In the working process of the display panel, the pixel circuit can transmit a data signal to the pixel electrode, and the pixel electrode can form an electric field with the common electrode layer under the control of the data signal. The liquid crystal molecules of the liquid crystal layer can be driven to deflect by using the electric field formed between the pixel electrode and the common electrode layer, and then the gray scale displayed by the display panel is adjusted. The signal line can be electrically connected with the thin film transistor of the pixel circuit and / or the common electrode layer, so as to provide a corresponding electric signal to the corresponding thin film transistor or the common electrode layer. In the following embodiments of the present disclosure, the present application is exemplarily described taking the pixel circuit including one transistor and one capacitor as an example.

[0071] The related technology provides an array substrate, which comprises a substrate and a plurality of top-gate transistors arranged on the substrate; the array substrate further comprises a common voltage signal line arranged in the same layer as a gate electrode of the transistors, and a data signal line located on a side of the common voltage signal line away from the substrate. The common voltage signal line is used to be electrically connected with a common electrode layer to provide a voltage signal for the common electrode layer, and the data signal line can be connected with the transistors to transmit a data signal to a pixel electrode through the transistors. In addition, the extension direction of the data signal line and the extension direction of the common voltage signal line intersect with each other, and the interval between the two is relatively close, so that a relatively large parasitic capacitance is generated between the data signal line and the common voltage signal line. The parasitic capacitance increases the load on the data signal line, is not conducive to improving the transmission of the data signal on the data line, is not conducive to improving the charging speed of the data signal, and further increases the power consumption of the array substrate.

[0072] To solve at least one of the above technical problems in the related technology, with reference to FIGS. 3 and 4, some embodiments of the present disclosure provide an array substrate 100, which comprises a substrate 10, a first conductive layer 20 arranged on one side of the substrate 10, a first transistor 30 arranged on a side of the first conductive layer 20 away from the substrate 10, a second signal line 40 arranged on a side of a first gate electrode 32 of the first transistor 30 away from the substrate 10, a common electrode layer 50 arranged on a side of the second signal line 40 away from the substrate 10, and a pixel electrode layer 60 arranged on a side of the common electrode layer 50 away from the substrate 10.

[0073] The first conductive layer 20 comprises a first signal line 21 and a light shielding pattern 22. The first transistor 30 is arranged on a side of the first conductive layer 20 away from the substrate 10, and comprises a first semiconductor layer 31 and a first gate electrode 32 located on a side of the first semiconductor layer 31 away from the substrate 10, that is, the first transistor 30 is a top-gate transistor. The first semiconductor layer 31 has a projection on the substrate 10, and the projection at least partially overlaps with a projection of the light shielding pattern 22 on the substrate 10. Therefore, the light shielding pattern 22 can shield the first semiconductor layer 31 to shield light from the side of the substrate 10 to the first semiconductor layer 31, so as to reduce the light irradiation on the first semiconductor layer 31, and improve the light stability of the first transistor 30.

[0074] The first semiconductor layer 31 of the first transistor 30 can include a channel region 311 and two connection regions 312 located on both sides of the channel region 311, the channel region 311 and the two connection regions 312 include the same semiconductor material, the difference between the channel region 311 and the connection region 312 is that the connection region 312 is subjected to a process (such as a doping process) that makes it more conductive, so that the connection region 312 can be formed into a conductor structure, while the channel region 311 remains a semiconductor structure. The orthographic projection of the light shielding pattern 22 on the substrate 10 can cover the orthographic projection of the channel region 311 on the substrate 10, so that the light shielding pattern 22 can greatly shield the light rays directed to the channel region 311, reducing the risk of drift of the photoelectric properties of the channel region 311.

[0075] In some embodiments, the material of the first semiconductor layer 31 can include a metal oxide semiconductor material, that is, the first transistor 30 is an oxide thin-film transistor (OTFT). The oxide thin-film transistor has the characteristic of low leakage current, and the use of the oxide thin-film transistor by the first transistor 30 is conducive to reducing the leakage current of the first transistor 30, simplifying the circuit structure of the pixel circuit, and improving the aperture ratio of the array substrate 100 and the light transmittance of the array substrate 100.

[0076] The second signal line 40 is electrically connected with the first transistor 30. Exemplarily, the second signal line 40 can be electrically connected with one of the connection regions 312 of the first semiconductor layer 31 of the first transistor 30. The second signal line 40 can be a data signal line, at this time, the second signal line 40 is used to transmit a data signal to the first transistor 30. The pixel electrode layer 60 can include a pixel electrode 61, and the pixel electrode 61 can be electrically connected with the other connection region 312 of the first semiconductor layer 31 of the first transistor 30, that is, the second signal line 40 and the pixel electrode 61 are connected with the two connection regions 312 of the first semiconductor layer 31 respectively. In this way, under the condition that the first transistor 30 is turned on, the second signal line 40 can transmit a data signal to the pixel electrode 61 through the first transistor 30, and the pixel electrode 61 can generate an electric field with the common electrode layer 50 under the control of the data signal, thereby driving the liquid crystal molecules in the liquid crystal layer to deflect, and the deflection direction of the liquid crystal molecules cooperates with the alignment film to adjust the amount of light passing through the display panel, so that the display panel realizes gray scale display.

[0077] The common electrode layer 50 is electrically connected with the first signal line 21, that is, the first signal line 21 can be a common voltage signal line for transmitting a voltage signal (such as a constant voltage signal) to the common electrode layer 50. The second signal line 40 has a projection on the substrate 10, which partially overlaps with the projection of the first signal line 21 on the substrate 10. Thus, the part where the projection of the second signal line 40 and the projection of the first signal line 21 on the substrate 10 overlap with each other forms a parasitic capacitance. The distance between the second signal line 40 and the first signal line 21 directly affects the size of the parasitic capacitance. In the embodiment of the present disclosure, the first signal line 21 and the first gate 32 of the first transistor 30 are arranged on different film layers, and the first signal line 21 is arranged in the first conductive layer 20 close to the substrate 10 of the first transistor 30. Thus, the spacing between the first signal line 21 and the second signal line 40 can be greatly increased, thereby greatly reducing the parasitic capacitance generated between the first signal line 21 and the second signal line 40, which is conducive to reducing the load on the second signal line 40, thereby improving the transmission efficiency of the signal (such as a data signal) on the second signal line 40 and reducing the power consumption of the array substrate 100.

[0078] In some embodiments, referring to FIGS. 3 and 5, the pixel electrode layer 60 is arranged on the side of the common electrode layer 50 away from the substrate 10, and the pixel electrode layer 60 further includes a connection pattern 62. The connection pattern 62 is electrically connected with the common electrode layer 50 and the first signal line 21, respectively. In other words, the first signal line 21 is electrically connected with the common electrode layer 50 through the connection pattern 62 arranged in the same layer as the pixel electrode 61. Thus, the connection via (the second via V2) for connecting the first signal line 21 and the connection pattern 62 can be formed synchronously with the connection via (the eighth via V8) for connecting the pixel electrode 61 and the first semiconductor layer 31, without the need to add an additional process to form the second via V2, which is conducive to simplifying the manufacturing process of the array substrate 100 and reducing the manufacturing difficulty and cost of the array substrate 100.

[0079] Of course, in other embodiments, the common electrode layer 50 can be directly electrically connected with the first signal line 21. Thus, during the manufacturing process of the array substrate 100, a mask needs to be added to form a connection via between the common electrode layer 50 and the first signal line 21.

[0080] In some embodiments, referring to FIGS. 3 and 6, the array substrate 100 can include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA and the peripheral area BB are different areas artificially divided on the array substrate 100, and there can be no obvious boundary between the two.

[0081] Exemplarily, in the embodiments of the present disclosure, the display area AA can refer to an area in the array substrate 100 for forming a pixel area; for example, as shown in FIG. 3, the array substrate 100 can include a plurality of third signal lines GL extending along a first direction X, which can be configured to form the first gate 32 of the first transistor 30, for example, a portion of the third signal line GL whose orthogonal projection on the substrate 10 coincides with the orthogonal projection of the first semiconductor layer 31 on the substrate 10 is configured to form the first gate 32. The plurality of third signal lines GL are spaced apart along a second direction Y, wherein the first direction X intersects the second direction Y, for example, the first direction X and the second direction Y are perpendicular to each other. The array substrate 100 further includes a plurality of second signal lines 40 extending along the second direction Y, and the plurality of second signal lines 40 are spaced apart along the first direction X. The orthogonal projections of the plurality of second signal lines 40 and the plurality of third signal lines GL on the substrate 10 intersect each other to form a grid structure, wherein one grid forms one pixel area, and one pixel electrode 61 can be disposed in one pixel area. The peripheral area BB refers to other areas of the display area AA close to the edge of the array substrate, and the peripheral area BB can be used to dispose structures including but not limited to power signal lines, clock signal lines, gate driving circuits and source driving chips. In a specific example, as shown in FIG. 3, the connection of the outer boundary of the most edge pixel area can be taken as the boundary between the display area AA and the peripheral area BB.

[0082] Referring to FIGS. 3 and 6, the first signal line 21 can include a first sub-line 211 and a plurality of second sub-lines 212, the first sub-line 211 is located in the peripheral area BB and at least partially surrounds the display area AA. Among them, only a few second sub-lines 212 are exemplarily shown in FIG. 6, which does not represent the specific number of second sub-lines 212.

[0083] Exemplarily, as shown in FIG. 6, the peripheral area BB can include a fan-out area BB4 located below the display area AA, a first sub-area BB1 located on the left side of the display area AA, a second sub-area BB2 located on the top side of the display area AA, and a third sub-area BB3 located on the right side of the display area AA. The first sub-line 211 at least partially surrounds the display area AA, which can be that the first sub-line 211 at least extends in the first sub-area BB1 and the third sub-area BB3, and extends to the fan-out area BB4 and is connected with the power signal end through the fan-out area BB4. For example, the first sub-line 211 can extend in the first sub-area BB1, the second sub-area BB2 and the third sub-area BB3, and be connected in sequence in the first sub-area BB1, the second sub-area BB2 and the third sub-area BB3. Alternatively, the first sub-line 211 can extend in the first sub-area BB1 and the third sub-area BB3. Of course, the setting position of the first sub-line 211 is not limited to this, and in the actual preparation process, the first sub-line 211 can be set at a suitable position in the peripheral area BB according to needs.

[0084] Continuing to refer to FIGS. 3 and 6, a plurality of second sub-lines 212 are located in the display area AA, the plurality of second sub-lines 212 each extend along the first direction X and are spaced apart along the second direction Y, and at least one end of each second sub-line 212 along the first direction X is electrically connected to the first sub-line 211, so as to facilitate signal transmission between the first sub-line 211 and the second sub-line 212. For example, both ends of each second sub-line 212 along the first direction X are electrically connected to the first sub-line 211, so that the plurality of second sub-lines 212 can form a parallel structure with the first sub-line 211, which is conducive to reducing the overall resistance of the first signal line 21.

[0085] As shown in FIGS. 3 and 5, the connection pattern 62 is located in the peripheral area BB and is electrically connected to the first sub-line 211, that is, the first signal line 21 is electrically connected to the common electrode layer 50 through the connection pattern 62 in the peripheral area BB, so that a plurality of structures including the connection pattern 62, a via for electrically connecting the connection pattern 62 and the first signal line 21, and a via for electrically connecting the connection pattern 62 and the common electrode layer 50 do not need to be arranged in the display area AA, which can effectively simplify the structure of the array substrate in the display area AA and is conducive to improving the transmittance and aperture ratio of the display area AA.

[0086] In some embodiments, referring to FIGS. 4 and 5, the array substrate 100 further includes an insulating layer located between adjacent conductive layers. For example, as shown in FIGS. 4 and 5, the array substrate 100 can include a first insulating layer BUF located between the first conductive layer 20 and the first semiconductor layer 31, a gate insulating layer GI located between the first semiconductor layer 31 and the first gate 32, a second insulating layer ILD located between the first gate 32 and the second signal line 40, a third insulating layer PVX1 located between the second signal line 40 and the common electrode layer 50, and a fourth insulating layer PVX2 located between the common electrode layer 50 and the pixel electrode layer 60. In addition, the array substrate 100 can further include a planarization layer PLN located between the third insulating layer PVX1 and the common electrode layer 50, which can increase the flatness of the common electrode layer 50 and is conducive to improving the uniformity of the electric field formed between the pixel electrode 61 and the common electrode layer 50.

[0087] As shown in FIG. 3, FIG. 4 and FIG. 5, the array substrate 100 further comprises a first via V1 and a second via V2. The first via V1 penetrates the second insulating layer ILD. At least part of the third insulating layer PVX1 is located in the first via V1 and contacts the first insulating layer BUF through the first via V1; that is, in the preparation process of the array substrate, the first via V1 can be formed first, and then the third insulating layer PVX1 is prepared. The second via V2 penetrates the fourth insulating layer PVX2, the third insulating layer PVX1 and the first insulating layer BUF and exposes part of the first sub-line 211. The orthographic projection of the second via V2 on the substrate 10 is located in the range of the orthographic projection of the first via V1 on the substrate 10. Exemplarily, the second via V2 can be prepared synchronously with an eighth via V8 for connecting the pixel electrode 61 and the first semiconductor layer 31, which is advantageous to simplify the preparation process of the array substrate 100 and reduce the preparation difficulty and cost of the array substrate 100. The area of the first via V1 is greater than the area of the second via V2, and the second via V2 penetrates the first via V1. In this way, the second via V2 can be located in the second insulating layer ILD, which is advantageous to reduce the depth of the second via V2, that is, to reduce the total thickness of the film layers penetrated by the second via V2. At the same time, the eighth via V8 needs to penetrate the fourth insulating layer PVX2, the third insulating layer PVX1 and the second insulating layer ILD. The thickness difference of the film layers penetrated by the second via V2 and the eighth via V8 is equal to the thickness difference between the second insulating layer ILD and the first insulating layer ILD. In this way, it is advantageous to reduce the thickness difference of the film layers penetrated by the second via V2 and the eighth via V8, thereby reducing or avoiding damage to the first semiconductor layer 31 in the process of etching to form the second via V2 and the eighth via V8, which is advantageous to protect the area where the first semiconductor layer 31 is connected with the pixel electrode 61 and improve the connection reliability between the pixel electrode 61 and the first semiconductor layer 31.

[0088] In some embodiments, the first via V1 can be prepared synchronously with a ninth via V9 for electrically connecting the second signal line 40 and the first semiconductor layer 31. In this way, the first via V1 can be formed without increasing additional processes, which is advantageous to simplify the preparation process of the array substrate 100 and reduce the preparation difficulty and cost of the array substrate 100.

[0089] It should be understood that, in the case that the array substrate 100 comprises the planar layer PLN, a hollow pattern P1 can be formed in the region where the eighth via V8 is located during the process of preparing the planar layer PLN, so that the eighth via V8 does not need to etch the planar layer PLN, which is beneficial to reduce the depth of the eighth via V8. The common electrode layer 50 can have a avoiding opening 51 at the positions of the first via V1 and the second via V2, and the size of the avoiding opening 51 can be greater than the size of the second via V2, so that the connection pattern 62 can be prevented from being short-circuited with the common electrode layer 50 on the sidewall of the second via V2.

[0090] Exemplarily, the size of the orthographic projection of the first via V1 on the substrate 10 can range from (4 μm x 4 μm) to (10 μm x 10 μm), and the size of the orthographic projection of the second via V2 on the substrate 10 can range from (3 μm x 3 μm) to (5 μm x 5 μm). The sizes of the first via V1 and the second via V2 are different, which is beneficial to reduce the alignment accuracy between the second via V2 and the first via V1, and ensure that the second via V2 can be located within the range of the first via V1.

[0091] Referring to FIG. 5, in some embodiments, the array substrate 100 further comprises a fifth via V5 which penetrates the fourth insulating layer PVX2 and exposes part of the common electrode layer 50. The part of the connection pattern 62 is located in the fifth via V5 and is electrically connected with the common electrode layer 50 through the fifth via V5. Exemplarily, the connection pattern 62 covers the fifth via V5. Moreover, the fifth via V5 can be prepared synchronously with the second via V2, for example, the second via V2, the eighth via V8 and the fifth via V5 can be prepared synchronously, so that an additional process is not needed to prepare the fifth via V5, which is beneficial to simplify the preparation process of the array substrate 100 and reduce the preparation difficulty and cost of the array substrate 100.

[0092] It should be understood that the common electrode layer 50 is usually prepared by using a transparent conductive material, which can include indium tin oxides (ITO) for example, and the thickness of the common electrode layer 50 is generally large (for example, 1000 nm or more). During the process of etching the fifth via V5, even if there is a certain over-etching amount, the common electrode layer 50 will not be etched through, so that the bottom of the fifth via V5 can be covered by the common electrode layer 50, to ensure that the common electrode layer 50 can be electrically connected with the connection pattern 62.

[0093] In some embodiments, the fifth via V5 has a projection on the substrate 10 that at least partially overlaps with a projection of the first sub-line 211 on the substrate 10, or in other words, at least a portion of the fifth via V5 is arranged directly above the first sub-line 211. Moreover, since the first via V1 and the second via V2 need to expose the first sub-line 211, the second via V2 also has a projection on the substrate 10 that at least partially overlaps with a projection of the first sub-line 211 on the substrate 10. The above arrangement can make the connection pattern 62 extend approximately along the extension direction of the first sub-line 211, and the connection pattern 62 and the fifth via V5 share at least part of the lateral (perpendicular to the extension direction of the peripheral region BB) space in the peripheral region BB with the first sub-line 211, which is conducive to reducing the width (dimension perpendicular to the extension direction of the peripheral region BB) of the connection pattern 62 and the fifth via V5 in the peripheral region BB, and is conducive to the narrow-frame design of the array substrate 100.

[0094] For example, the projection of the fifth via V5 on the substrate 10 is located within the projection of the first sub-line 211 on the substrate 10, so that the fifth via V5 can be completely arranged in the region where the first sub-line 211 is located, thereby greatly reducing the influence of the fifth via V5 and the connection pattern 62 on the width of the peripheral region BB, and facilitating the narrow-frame design of the array substrate 100.

[0095] In some embodiments, referring to FIGS. 4, 7 and 8, the array substrate 100 further includes insulating layers between adjacent conductive layers, for example, the array substrate 100 can include a first insulating layer BUF between the first conductive layer 20 and the first semiconductor layer 31, a gate insulating layer GI between the first semiconductor layer 31 and the first gate 32, a second insulating layer ILD between the first gate 32 and the second signal line 40, a third insulating layer PVX1 between the second signal line 40 and the common electrode layer 50, and a fourth insulating layer PVX2 between the common electrode layer 50 and the pixel electrode layer 60. In addition, the array substrate 100 can further include a planarization layer PLN between the third insulating layer PVX1 and the common electrode layer 50, which can increase the flatness of the common electrode layer 50 and facilitate the uniformity of the electric field formed between the pixel electrode 61 and the common electrode layer 50.

[0096] As shown in FIG. 7 and FIG. 8, the array substrate 100 further comprises a third via V3, a first transfer block 73 and a fourth via V4. The third via V3 penetrates the second insulating layer ILD and the first insulating layer BUF, and exposes a portion of the first sub-line 211. The first transfer block 73 is disposed on the side of the second insulating layer ILD away from the substrate 10, and at least part of the first transfer block 73 is located in the third via V3, and the first transfer block 73 is electrically connected to the first sub-line 211 through the third via V3. The fourth via V4 penetrates the fourth insulating layer PVX2 and the third insulating layer PVX1 and exposes a portion of the first transfer block 73. At least part of the connection pattern 62 is located in the fourth via V4, and the connection pattern 62 is electrically connected to the first transfer block 73 through the fourth via V4. In this way, the depth of the fourth via V4 can be further reduced (compared to the first via in the embodiment of FIG. 5), that is, the total thickness of the film layers etched by the fourth via V4 is reduced, and in the case of synchronous preparation of the fourth via V4 and the eighth via V8 for connecting the pixel electrode 61 and the first semiconductor layer 31, the damage to the first semiconductor layer 31 in the process of forming the fourth via V4 and the eighth via V8 can be further reduced, which is beneficial to protect the first semiconductor layer 31 and improve the connection reliability between the pixel electrode 61 and the first semiconductor layer 31.

[0097] For example, as shown in FIG. 8, the orthographic projection of the fourth via V4 on the substrate 10 covers the orthographic projection of the third via V3 on the substrate 10, so that the sidewall of the fourth via V4 can expose a portion of the first transfer block 73 located on the second insulating layer ILD, and the transfer pattern 62 can form a step structure in the fourth via V4 and on the surface of the first transfer block 73, which is beneficial to reduce the climbing difficulty of the transfer pattern 62 in the fourth via V4, increase the contact area between the transfer pattern 62 and the first transfer block 73, and reduce the connection resistance between the transfer pattern 62 and the first transfer block 73.

[0098] In some embodiments, the third via V3 can be synchronously prepared with the ninth via V9 (as shown in FIG. 4) for electrically connecting the second signal line 40 and the first semiconductor layer 31, so that an additional process is not needed, and the third via V3 can be prepared by using the existing process steps, which is beneficial to simplify the preparation process of the array substrate 100 and reduce the preparation difficulty and cost of the array substrate 100.

[0099] In some embodiments, the fourth via V4 can be synchronously prepared with the eighth via V8 for connecting the pixel electrode 61 and the first semiconductor layer 31, so that an additional process is not needed, and the third via V3 can be prepared by using the existing process steps, which is beneficial to simplify the preparation process of the array substrate 100 and reduce the preparation difficulty and cost of the array substrate 100.

[0100] Exemplarily, in some embodiments, the size of the third via V3 in the orthographic projection on the substrate 10 can range from (3 μm x 3 μm) to (5 μm x 5 μm), and the size of the fourth via V4 in the orthographic projection on the substrate 10 can range from (4 μm x 4 μm) to (10 μm x 10 μm). The sizes of the third via V3 and the fourth via V4 are different, which is advantageous for the fourth via V4 to expose the part of the first bump 73 on the second insulating layer ILD, so as to increase the contact area between the transfer pattern 62 and the first bump 73 and reduce the connection resistance between the transfer pattern 62 and the first bump 73.

[0101] Exemplarily, referring to FIGS. 7 and 8, in this exemplary embodiment, the array substrate 100 further comprises a fifth via V5, which penetrates the fourth insulating layer PVX2 and exposes part of the common electrode layer 50. Herein, part of the connection pattern 62 is located in the fifth via V5 and is electrically connected with the common electrode layer 50 through the fifth via V5. Exemplarily, the fifth via V5 can be formed synchronously with the fourth via V4, for example, the fourth via V4, the eighth via V8 and the fifth via V5 are formed synchronously, so that the fifth via V5 does not need to be prepared by adding an additional process, which is advantageous for simplifying the preparation process of the array substrate 100 and reducing the preparation difficulty and cost of the array substrate 100. It should be understood that the common electrode layer 50 is usually prepared by using a transparent conductive material, which can include indium tin oxides (ITO) for example, and the thickness of the common electrode layer 50 is generally large (for example, greater than 1000 nm), so that the common electrode layer 50 will not be etched through in the process of etching the fifth via V5, thereby ensuring that the bottom of the fifth via V5 is covered by the common electrode layer 50, so as to ensure that the common electrode layer 50 can be electrically connected with the connection pattern 62.

[0102] In some embodiments, as shown in FIG. 7, the orthographic projection of the fifth via V5 on the substrate 10 at least partially overlaps with the orthographic projection of the first sub-line 211 on the substrate 10, that is, at least part of the fifth via V5 is arranged directly above the first sub-line 211. In addition, since the third via V3 and the fourth via V4 need to expose the first sub-line 211, the orthographic projection of the fourth via V4 on the substrate 10 also at least partially overlaps with the orthographic projection of the first sub-line 211 on the substrate 10. The connection pattern 62 extends approximately along the extension direction of the first sub-line 211, and the connection pattern 62 and the fifth via V5 share at least part of the lateral (direction perpendicular to the extension direction of the peripheral region BB) space in the peripheral region BB with the first sub-line 211, which is advantageous for reducing the width (dimension perpendicular to the extension direction of the peripheral region) of the connection pattern 62 and the fifth via V5 in the peripheral region BB, and is advantageous for the array substrate 100 to be designed with a narrow frame.​

[0103] Exemplarily, the orthogonal projection of the fifth via V5 on the substrate 10 is located in the range of the orthogonal projection of the first sub-line 211 on the substrate 10, so that the fifth via V5 can be completely arranged in the area where the first sub-line 211 is located, thereby greatly reducing the influence of the fifth via V5 and the connection pattern 62 on the width of the peripheral area BB, and facilitating the narrow frame design of the array substrate 100.

[0104] In some embodiments, the first transfer block 73 can be arranged in the same layer and include the same material as the second signal line 40, for example, the first transfer block 73 and the second signal line 40 can be integrally prepared by using the same material and the same film forming process. In this way, an additional process for forming the first transfer block 73 is not needed, which is conducive to reducing the preparation difficulty and preparation cost of the array substrate 100.

[0105] In some embodiments, referring to FIGS. 9 and 10, the array substrate 100 further includes an auxiliary trace 70. The auxiliary trace 70 is located in the peripheral area BB and arranged on the side of the common electrode layer 50 close to the substrate 10. The auxiliary trace 70 is arranged in parallel with the common electrode layer 50, so as to reduce the resistance of the common electrode layer 50 and the first sub-line 211, reduce the voltage drop on the first sub-line 211 and the common electrode layer 50, and reduce the power consumption of the array substrate 100.

[0106] As shown in FIG. 10, the array substrate 100 can further include a sixth via V6. The sixth via V6 at least penetrates the fourth insulating layer PVX2 and the third insulating layer PVX1 and exposes a part of the auxiliary trace 70. A part of the connection pattern 62 is located in the sixth via V6 and electrically connected with the auxiliary trace 70 through the sixth via V6. That is, the common electrode layer 50 is electrically connected with the auxiliary trace 70 through the connection pattern 62. In this way, the sixth via V6 can be prepared synchronously with the eighth via V8 and the second via V2 or the fourth via V4 in the above-mentioned embodiments, and a special connection via does not need to be opened on the third insulating layer PVX1, which is conducive to simplifying the preparation process of the array substrate 100 and reducing the preparation difficulty and preparation cost of the array substrate 100.

[0107] In some embodiments, referring to FIGS. 9 and 10, the sixth via V6 can have a projection on the substrate 10 that at least partially overlaps with the projection of the first sub-line 211 on the substrate 10, so that the connection pattern 62 can extend approximately along the extension direction of the first sub-line 211, and the connection pattern 62 and the sixth via V6 share at least part of the lateral (direction perpendicular to the extension direction of the peripheral region BB) space within the peripheral region BB with the first sub-line 211, which is conducive to reducing the width (dimension perpendicular to the extension direction of the peripheral region BB) of the connection pattern 62 and the sixth via V6 within the peripheral region BB, and conducive to the narrow-frame design of the array substrate 100.

[0108] In some embodiments, as shown in FIGS. 9 and 10, the auxiliary wiring 70 can include a first wiring 71 extending along the second direction Y, so that the first wiring 71 and the first sub-line 211 share at least part of the lateral space within the peripheral region BB, which is conducive to reducing the width of the first wiring and the first sub-line 211 within the peripheral region BB, and conducive to the narrow-frame design of the array substrate 100. The first wiring 71 and the second signal line 40 are made of the same material and arranged in the same layer. For example, the first wiring 71 and the second signal line 40 can be integrally formed by using the same material and the same film-forming process. In this way, an additional process is not needed for forming the first wiring 71, which is conducive to reducing the manufacturing difficulty and cost of the array substrate 100.

[0109] As shown in FIGS. 9 and 10, in the case where the auxiliary wiring 70 includes the first wiring 71, the sixth via V6 can only penetrate the fourth insulating layer PVX2 and the third insulating layer PVX1, and expose part of the first wiring 71, and the connection pattern 62 is electrically connected to the first wiring 71 through the sixth via V6. For example, the sixth via V6 can also be located within the range of the avoidance opening 51 of the common electrode layer 50, so that the etching difficulty of the sixth via V6 can be reduced.

[0110] In some embodiments, referring to FIG. 11, the auxiliary wiring 70 can also include a second wiring 72 extending along the second direction Y, so that the second wiring 72 and the first sub-line 211 share at least part of the lateral space within the peripheral region BB, which is conducive to reducing the width of the connection pattern 62 and the second wiring 72 within the peripheral region BB, and conducive to the narrow-frame design of the array substrate 100. The second wiring 72 and the first gate 32 of the first transistor 30 are made of the same material and arranged in the same layer. For example, the second wiring 72 and the first gate 32 can be integrally formed by using the same material and the same film-forming process. In this way, an additional process is not needed for forming the second wiring 72, which is conducive to reducing the manufacturing difficulty and cost of the array substrate 100.

[0111] As shown in FIG. 11, in the case where the auxiliary wire 70 includes both the first wire 71 and the second wire 72, the sixth via V6 can only penetrate the fourth insulating layer PVX2 and the third insulating layer PVX1, and expose a partial region of the first wire 71, and the connection pattern 62 is electrically connected to the first wire 71 through the sixth via V6. In addition, the array substrate 100 further includes a seventh via V7, the seventh via V7 can penetrate the insulating layer (the second insulating layer ILD) between the first wire 71 and the second wire 72, and the first wire 71 is electrically connected to the second wire 72 through the seventh via V7. In this way, the first wire 71, the second wire 72, the connection pattern 62, the common electrode layer 50, and the first sub-wire 211 are all electrically connected to each other, which is conducive to reducing the resistance of the common electrode layer 50 and the first sub-wire 211, and is conducive to reducing the power consumption of the array substrate 100.

[0112] In other embodiments, the auxiliary wire 70 can also only include the second wire 72 without the first wire 71 (not shown in the figure), and the second wire 72 and the first gate 32 of the first transistor 30 are made of the same material and arranged in the same layer; for example, the second wire 72 and the first gate 32 can be integrally prepared by using the same material and the same film forming process. At this time, the sixth via V6 can penetrate the fourth insulating layer PVX2, the third insulating layer PVX1, and the second insulating layer ILD, and expose a partial region of the second wire 72.

[0113] In some embodiments, in the case where the auxiliary wire 70 of the array substrate 100 includes the above-mentioned first wire 71, as shown in FIGS. 9, 10, and 11, the orthographic projection of the first wire 71 on the substrate 10 at least partially overlaps with the orthographic projection of the first sub-wire 211 on the substrate 10, so that the first wire 71 and the first sub-wire 211 share at least part of the lateral space within the peripheral region BB, which is conducive to reducing the width of the first wire 71 and the first sub-wire 211 within the peripheral region BB, and is conducive to the narrow-frame design of the array substrate 100. For example, the orthographic projection of the first wire 71 on the substrate 10 coincides with the orthographic projection of the first sub-wire 211 on the substrate 10, or the orthographic projection of the first wire 71 on the substrate 10 is located within the range of the orthographic projection of the first sub-wire 211 on the substrate 10. Of course, the embodiments of the present disclosure are not limited to this, and in the actual preparation process of the array substrate 100, the orthographic projection of the first sub-wire 211 on the substrate 10 can also have part located outside the range of the orthographic projection of the first sub-wire 211 on the substrate 10, as long as the same technical idea is adopted, which will not be enumerated one by one here.

[0114] In the case that the auxiliary wire 70 of the array substrate 100 comprises the second wire 72 described above, the orthogonal projection of the second wire 72 on the substrate 10 at least partially overlaps with the orthogonal projection of the first sub-line 211 on the substrate 10, so that the second wire 72 and the first sub-line 211 share at least part of the lateral space within the peripheral region BB, which is conducive to reducing the width of the second wire 72 and the first sub-line 211 within the peripheral region BB, and conducive to the narrow-frame design of the array substrate 100. For example, the orthogonal projection of the second wire 72 on the substrate 10 overlaps with the orthogonal projection of the first sub-line 211 on the substrate 10; or, the orthogonal projection of the second wire 72 on the substrate 10 is within the range of the orthogonal projection of the first sub-line 211 on the substrate 10.

[0115] In some embodiments, referring to FIGS. 10 and 12, the array substrate 100 further comprises a third signal line GL configured to form the first gate 32 of the first transistor 30. For example, the part of the third signal line GL whose orthogonal projection on the substrate 10 overlaps with the first semiconductor layer 31 forms the first gate 32. The orthogonal projection of the third signal line GL on the substrate 10 partially overlaps with the orthogonal projection of the first sub-line 211 on the substrate 10, for example, the third signal line GL extends along the first direction X to the side of the first sub-line 211 away from the display region AA. At this time, the second wire 72 comprises a plurality of wire segments 721 distributed at intervals, and the first interval D1 is between any two adjacent wire segments 721. The third signal line GL passes through the first interval D1 and is spaced apart from the wire segments 721. The third signal line GL and the second wire 72 comprise the same material and are arranged in the same layer. By arranging the second wire 72 as a plurality of wire segments 721 arranged at intervals and arranging the third signal line GL in the first interval D1, the short circuit between the second wire 72 and the third signal line GL can be avoided.

[0116] In some embodiments, referring to FIGS. 12 and 13, the array substrate 100 can further comprise a first pad 81 arranged between the first signal line 21 (the second sub-line 212 of the first signal line 21) and the second signal line 40. The orthogonal projection of the first pad 81 on the substrate 10 partially overlaps with the orthogonal projection of the second signal line 40 and the first signal line 21 on the substrate 10, respectively. In this way, the arrangement of the first pad 81 is conducive to further increasing the interval between the first signal line 21 and the second signal line 40, thereby greatly reducing the parasitic capacitance generated between the first signal line 21 and the second signal line 40, reducing the load on the second signal line 40, improving the transmission efficiency of the signal (such as the data signal) on the second signal line 40, and reducing the power consumption of the array substrate 100.

[0117] In some embodiments, as shown in FIGS. 12 and 13, the first bump 81 covers the area 101 on the substrate 10 where the projections of the second signal line 40 and the first signal line 21 overlap with each other. In this way, the first bump 81 can uniformly increase the distance between the portions of the second signal line 40 and the first signal line 21 arranged opposite to each other, greatly reduce the parasitic capacitance generated between the first signal line 21 and the second signal line 40, and further reduce the load on the second signal line 40, improve the transmission efficiency of the signal on the second signal line 40, and reduce the power consumption of the array substrate 100.

[0118] In some embodiments, the first bump 81 and the first semiconductor layer 31 are made of the same material and arranged in the same layer. For example, the first bump 81 and the first semiconductor layer 31 can be integrally prepared by using the same material and the same film forming process. In this way, an additional process for forming the first bump 81 is not needed, which is advantageous for reducing the preparation difficulty and cost of the array substrate 100.

[0119] In some embodiments, as shown in FIGS. 14 and 15, the first transistor 30 further includes a gate insulating layer GI between the first semiconductor layer 31 and the first gate 32. The array substrate further includes a second bump 82 arranged between the first signal line 21 (the second sub-line 212 of the first signal line 21) and the second signal line 40. The projection of the second bump 82 on the substrate 10 partially overlaps with the projections of the second signal line 40 and the first signal line 21 on the substrate 10, respectively. In this way, the arrangement of the second bump 82 is advantageous for further increasing the distance between the first signal line 21 and the second signal line 40, greatly reducing the parasitic capacitance generated between the first signal line 21 and the second signal line 40, reducing the load on the second signal line 40, improving the transmission efficiency of the signal (such as a data signal) on the second signal line 40, and reducing the power consumption of the array substrate 100. The second bump 82 includes a first sub-portion 821 and a second sub-portion 822 arranged in layers. The first sub-portion 821 and the first gate 32 are made of the same material and arranged in the same layer. The second sub-portion 822 is located on the gate insulating layer GI. In this way, the second bump 82 can be formed by using the existing film layer structure, without the need to add an additional process for preparing the second bump 82, which is advantageous for reducing the preparation difficulty and cost of the array substrate 100.

[0120] As shown in FIG. 14, the second bump 82 covers the area 101 where the projections of the second signal line 40 and the first signal line 21 on the substrate 10 overlap with each other. In this way, the second bump 82 can uniformly increase the interval between the portions of the second signal line 40 and the first signal line 21 arranged opposite to each other, greatly reduce the parasitic capacitance generated between the first signal line 21 and the second signal line 40, further reduce the load on the second signal line 40, improve the transmission efficiency of the signal on the second signal line 40, and reduce the power consumption of the array substrate 100.

[0121] In some embodiments, referring to FIG. 15, the first sub-part 821 is electrically connected to the second signal line 40. In this way, no capacitance is formed between the first sub-part 821 and the second signal line 40, and the influence of the first sub-part 821 on the signal transmission on the second signal line 40 can be reduced.

[0122] In some examples, the dimension of the second sub-part 822 along the direction perpendicular to the substrate 10 is greater than the dimension of the second insulating layer along the direction perpendicular to the substrate 10. In this way, it can be ensured that, in the case where the second bump 82 is arranged and the first sub-part 821 is electrically connected to the second signal line 40, the interval between the second signal line 40 and the first signal line 21 can still be increased, the parasitic capacitance generated between the first signal line 21 and the second signal line 40 can still be reduced, the load on the second signal line 40 can still be reduced, the transmission efficiency of the signal on the second signal line 40 can still be improved, and the power consumption of the array substrate 100 can still be reduced.

[0123] It should be understood that, in the case where the second bump 82 is not arranged, the interval between the second signal line 40 and the first signal line 21 is equal to the sum of the thickness of the second insulating layer ILD and the thickness of the first insulating layer BUF. In the case where the second bump 82 is arranged and the first sub-part 821 of the second bump 82 is electrically connected to the second signal line 40, the interval between the second signal line 40 and the first signal line 21 can be considered as the interval between the first sub-part 821 and the first signal line 21, which is equal to the sum of the thickness of the gate insulating layer GI and the thickness of the first insulating layer BUF. In this way, it can be seen that, in the two cases of arranging or not arranging the second bump 82, the difference in the interval between the second signal line 40 and the first signal line 21 is equal to the difference between the dimension of the second sub-part 822 along the direction perpendicular to the substrate 10 and the dimension of the second insulating layer ILD along the direction perpendicular to the substrate 10, or equal to the difference between the thickness of the second sub-part 822 and the thickness of the second insulating layer ILD. Therefore, in the case where the dimension of the second sub-part 822 along the direction perpendicular to the substrate 10 is greater than the dimension of the second insulating layer along the direction perpendicular to the substrate 10, the second bump 82 is arranged and the first sub-part 821 is electrically connected to the second signal line 40, the interval between the second signal line 40 and the first signal line 21 can be increased, and the parasitic capacitance generated between the first signal line 21 and the second signal line 40 can be reduced.

[0124] The above-mentioned embodiments of the present disclosure can be implemented alone or in combination, for example, in the case where the connection pattern 62 is electrically connected to the first sub-line 211 of the first signal line 21 in the manner of Figs. 3 and 5, the first insulating layer BUF and the second insulating layer ILD can be included between the second signal line 40 and the second sub-line 212 of the first signal line 21, or the first insulating layer BUF, the second insulating layer ILD, and the first pad 81 can be included between the second signal line 40 and the second sub-line 212 of the first signal line 21, or the first insulating layer BUF, the second insulating layer ILD, the first pad 81, and the second pad 82 can be included between the second signal line 40 and the second sub-line 212 of the first signal line 21. Similarly, in the case where the connection pattern 62 is electrically connected to the first sub-line 211 of the first signal line 21 in the manner of Figs. 7 and 8, or in the manner of Figs. 9 and 10, the first insulating layer BUF and the second insulating layer ILD can be included between the second signal line 40 and the second sub-line 212 of the first signal line 21, or the first pad 81 and the second pad 82 can be further included. The embodiments of the present disclosure do not expand on the combination of the above-mentioned embodiments one by one.

[0125] In some embodiments, the array substrate 100 includes a display area AA and a peripheral area BB surrounding the display area AA. The first transistor 30 is located in the display area AA and configured to form a pixel circuit.

[0126] The applicant has found that, referring to Fig. 16, during the process of conducting (doping) the semiconductor layer ACT, the doping ions have a certain lateral diffusion, which causes a part of the edge of the conductor part ACT1 doped as a conductor in the semiconductor layer ACT to be arranged opposite to the shielding metal M (such as the first gate), or in other words, the orthographic projection of the shielding metal M on the substrate 10 overlaps the orthographic projection of the part of the edge of the conductor part ACT1 on the substrate 10. The orthographic projection of the part of the semiconductor part ACT2 not doped as a conductor in the semiconductor layer ACT on the substrate 10 is located within the range of the orthographic projection of the shielding metal M on the substrate 10, and the boundary of the semiconductor part ACT2 has a spacing DX from the boundary of the shielding metal M.

[0127] For the above reasons, in embodiments of the present disclosure, as shown in FIG. 14, along the width direction of the channel structure of the first transistor 30 (the first direction X in FIG. 14), the first gate 32 extends beyond the edge of the first semiconductor layer 31. Here, the channel structure of the first transistor 30 refers to the part of the first semiconductor layer 31 that remains a semiconductor, or the part of the first semiconductor layer 31 that has not been subjected to a process (the part where the channel region 311 is located); the width direction of the channel structure refers to the direction along which the channel structure (the channel region 311) is perpendicular to the line connecting the two connection regions 312 of the first semiconductor layer 31 (the dimension of the first direction X in FIG. 17), and along the width direction of the channel structure (the first direction X), the first gate 32 extends beyond the edge of the first semiconductor layer 31, which can effectively prevent the area near the edge of the channel structure of the first semiconductor layer 31 from being doped into a conductor, and is conducive to improving the reliability of the first transistor 30.

[0128] Referring to FIG. 17, the array substrate 100 further includes a second transistor 90 located in the peripheral region BB. For example, the second transistor 90 can be configured to form a gate drive circuit (GOA circuit) and a multiplexing circuit (MUX circuit), but is not limited thereto. The second transistor 90 includes a second semiconductor layer 91 and a second gate 92 located on the side of the second semiconductor layer 91 away from the substrate 10. Along the width direction M1 of the channel structure of the second transistor 90, both ends of the second gate 92 extend beyond the edge of the second semiconductor layer 91. In this way, the two side edges of the channel structure of the second semiconductor layer 91 (the part of the second semiconductor layer 91 that overlaps with the projection of the second gate 92) along the width direction M1 of the channel structure of the second transistor 90 can be doped into a conductor during the conductorization process of the second semiconductor layer 91, which is conducive to ensuring the reliability of the second transistor 90.

[0129] In some embodiments, along the width direction of the channel structure of the first transistor 30 (the first direction X in FIG. 14), the distance D2 by which the first gate 32 extends beyond the edge of the first semiconductor layer 31 is greater than or equal to 3 μm. In this way, it can be ensured that the edge of the first semiconductor layer 31 will not be doped into a conductor, and the channel structure of the first semiconductor layer 31 will remain a semiconductor, thereby reducing the risk of leakage of the channel structure of the first semiconductor layer 31 when the first transistor 30 is in an off state, and ensuring the reliability of the first transistor 30. For example, the distance D2 by which the first gate 32 extends beyond the edge of the first semiconductor layer 31 can be 3 μm, 3.5 μm, 4 μm, or 5 μm, and the like. Embodiments of the present disclosure do not list them one by one.

[0130] In one specific embodiment, as shown in FIG. 14, the third signal line GL is used to form the first gate 32, and extends along the width direction X of the channel structure of the first transistor 30, and the third signal line GL continuously extends, thus the distance of the edge of the third signal line GL extending out of the first semiconductor layer is greater than 3 μm.

[0131] As shown in FIG. 17, along the width direction M1 of the channel structure of the second transistor 90, the distance D3 of the edge of the second gate 92 extending out of the second semiconductor layer 91 is greater than or equal to 3 μm. In this way, it can be ensured that the upper and lower edges of the second semiconductor layer 91 will not be doped to form a conductor, and the channel structure of the second semiconductor layer 91 is ensured to be a semiconductor, thereby reducing the risk of current leakage of the channel structure of the second semiconductor layer 91 when the second transistor 90 is in an off state, and ensuring the reliability of the second transistor 90. For example, the distance D3 of the edge of the second gate 92 extending out of the second semiconductor layer 91 can be 3 μm, 4 μm, 4.5 μm, or 5 μm, etc., and the embodiments of the present disclosure will not be enumerated one by one.

[0132] Continuing to refer to FIG. 17, in some embodiments, the second semiconductor layer 91 includes a plurality of sub-semiconductor layers 911, and the plurality of sub-semiconductor layers 911 are spaced apart along the width direction M1 of the channel structure of the second transistor 90, and the size of each sub-semiconductor layer 911 along the width direction M1 of the channel structure of the second transistor 90 is less than or equal to 20 μm. In this way, in the case that the width of the channel structure of the second transistor 90 is large, the risk of characteristic drift or conductorization of the second transistor 90 can also be reduced, and the reliability of the second transistor 90 is improved.

[0133] As shown in FIG. 17, the material of the second semiconductor layer 91 includes metal oxide semiconductor material; that is, the second transistor 90 is an oxide thin-film transistor (OTFT). The oxide thin-film transistor has the characteristic of low leakage current, which is conducive to reducing the leakage current of the second transistor 90.

[0134] The second semiconductor layer 91 of the second transistor 30 includes a first region 912 and two second regions 913 located on both sides of the first region 912. The second region 913 is more conductive than the first region 912. For example, the first region 912 and the second region 913 both include the same semiconductor material, but the second region 913 is subjected to a process (such as a doping process) that makes it more conductive than the first region 912. The second region 913 is doped to form a conductor, and the first region 912 remains a semiconductor, and thus the second region 913 is more conductive than the first region 912.

[0135] In some embodiments, as shown in FIG. 17, the orthographic projection of the first region 912 on the substrate 10 is located within the orthographic projection of the second gate 92 on the substrate 10, and the orthographic projection of the second region 913 on the substrate 10, near the edge of the first region 912, coincides with the orthographic projection of the second gate 92 on the substrate 10, that is, the part of the edge of the second region 913 near the first region 912 is located opposite the second gate 92.

[0136] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art who thinks of changes or replacements within the technical scope disclosed by the present disclosure shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An array substrate, comprising: a substrate and a first conductive layer disposed on a side of the substrate, the first conductive layer comprising a first signal line and a light-shielding pattern; a first transistor disposed on a side of the first conductive layer away from the substrate, comprising a first semiconductor layer and a first gate electrode disposed on a side of the first semiconductor layer away from the substrate, a projection of the first semiconductor layer on the substrate at least partially overlapping a projection of the light-shielding pattern on the substrate; a second signal line disposed on a side of the first semiconductor layer of the first transistor away from the substrate, the second signal line electrically connected to the first transistor, and a projection of the second signal line on the substrate partially overlapping a projection of the first signal line on the substrate; a common electrode layer disposed on a side of the second signal line away from the substrate, electrically connected to the first signal line. 2.The array substrate of claim 1, further comprising: a pixel electrode layer disposed on a side of the common electrode layer away from the substrate, comprising a pixel electrode electrically connected to the first transistor and a connection pattern electrically connected to the common electrode layer and the first signal line respectively. 3.The array substrate of claim 2, comprising a display area and a peripheral area surrounding the display area; wherein: the first signal line comprises a first sub-line and a plurality of second sub-lines, the first sub-line is located in the peripheral area and at least partially surrounds the display area, the plurality of second sub-lines are located in the display area, the plurality of second sub-lines extend along a first direction and are spaced apart along a second direction, at least one end of each of the second sub-lines is electrically connected to the first sub-line, the first direction intersects the second direction; the second signal line extends along the second direction, a projection of the second signal line on the substrate partially overlaps a projection of the second sub-lines on the substrate and does not overlap a projection of the first sub-line on the substrate; the connection pattern is located in the peripheral area and is electrically connected to the first sub-line. 4.The array substrate of claim 3, further comprising: a first insulating layer disposed between the first conductive layer and the first semiconductor layer; a second insulating layer disposed between the first gate electrode and the second signal line; a first via hole penetrating through the second insulating layer; a third insulating layer disposed between the second signal line and the common electrode layer, at least partially located in the first via hole and contacting the first insulating layer through the first via hole; a fourth insulating layer disposed between the common electrode layer and the pixel electrode layer; a second via hole penetrating through the fourth insulating layer, the third insulating layer and the first insulating layer and exposing a portion of the first sub-line, a projection of the second via hole on the substrate is located within a range of a projection of the first via hole on the substrate; wherein the connection pattern is electrically connected to the first sub-line through the second via hole. 5.The array substrate of claim 3, further comprising: ​ a first insulating layer disposed between the first conductive layer and the first semiconductor layer; a second insulating layer disposed between the first gate and the second signal line; a third via hole penetrating the second insulating layer and the first insulating layer and exposing a portion of the first sub-line; a first transfer block disposed on a side of the second insulating layer away from the substrate, at least partially located in the third via hole, and electrically connected to the first sub-line through the third via hole; a third insulating layer disposed between the second signal line and the common electrode layer; a fourth insulating layer disposed between the common electrode layer and the pixel electrode layer; a fourth via hole penetrating the fourth insulating layer and the third insulating layer and exposing a portion of the first transfer block, a projection of the fourth via hole on the substrate covering a projection of the third via hole on the substrate; wherein the connection pattern is at least partially located in the fourth via hole and electrically connected to the first transfer block through the fourth via hole.

6. The array substrate according to claim 5, wherein, The first transfer block and the second signal line comprise the same material and are disposed in the same layer.

7. The array substrate according to any one of claims 4-6, further comprising: a fifth via hole penetrating the fourth insulating layer and exposing a partial area of the common electrode layer; wherein a portion of the connection pattern is located in the fifth via hole and electrically connected to the common electrode layer through the fifth via hole.

8. The array substrate according to claim 7, wherein a projection of the fifth via hole on the substrate at least partially coincides with a projection of the first sub-line on the substrate.

9. The array substrate according to claim 7 or 8, further comprising: an auxiliary wire located in the peripheral area and disposed on a side of the common electrode layer close to the substrate, the auxiliary wire being disposed in parallel with the common electrode layer.

10. The array substrate according to claim 9, further comprising: a sixth via hole penetrating at least the fourth insulating layer and the third insulating layer and exposing a portion of the auxiliary wire; wherein a portion of the connection pattern is located in the sixth via hole and electrically connected to the auxiliary wire through the sixth via hole.

11. The array substrate according to claim 10, wherein the auxiliary wire comprises a first wire extending along the second direction and comprising the same material as the second signal line and being disposed in the same layer; the sixth via hole penetrates the fourth insulating layer and the third insulating layer and exposes a portion of the first wire, the connection pattern being electrically connected to the first wire through the sixth via hole.

12. The array substrate according to claim 10 or 11, wherein the auxiliary wire further comprises a second wire extending along the second direction, the second wire comprising the same material as the first gate and being disposed in the same layer; the array substrate further comprises a seventh via hole penetrating the second insulating layer, the first wire being electrically connected to the second wire through the seventh via hole.

13. The array substrate according to claim 12, wherein The first trace and the second trace have their projections on the substrate at least partially overlap with the projection of the first sub-line on the substrate.

14. The array substrate of claim 12, further comprising: a third signal line configured to form the first gate, the third signal line having its projection on the substrate partially overlap with the projection of the first sub-line on the substrate; wherein the second trace comprises a plurality of trace segments spaced apart from each other, and the third signal line passes through the first space between two adjacent trace segments and is spaced apart from the trace segments.

15. The array substrate of any one of claims 1-14, further comprising: a first pad disposed between the first signal line and the second signal line, the first pad having its projection on the substrate partially overlap with the projection of the second signal line and the first signal line on the substrate, respectively.

16. The array substrate of claim 15, wherein the projection of the first pad on the substrate covers the area where the projection of the second signal line and the first signal line on the substrate overlap with each other.

17. The array substrate of claim 15 or 16, wherein the first pad and the first semiconductor layer comprise the same material and are disposed in the same layer.

18. The array substrate of any one of claims 1-17, wherein the first transistor further comprises a gate insulating layer between the first semiconductor layer and the first gate; the array substrate further comprises a second pad, the second pad having its projection on the substrate partially overlap with the projection of the second signal line and the first signal line on the substrate, respectively, and the second pad comprises a first sub-portion and a second sub-portion stacked, the first sub-portion and the first gate comprise the same material and are disposed in the same layer, and the second sub-portion is located on the gate insulating layer.

19. The array substrate of claim 18, wherein, the projection of the second pad on the substrate covers the area where the projection of the second signal line and the first signal line on the substrate overlap with each other.

20. The array substrate of claim 18 or 19, wherein the first sub-portion is electrically connected to the second signal line.

21. The array substrate of claim 20, wherein a dimension of the second sub-portion in a direction perpendicular to the substrate is greater than a dimension of the second insulating layer in the direction perpendicular to the substrate.

22. The array substrate of any one of claims 1-21, comprising a display area and a peripheral area surrounding the display area; wherein the first transistor is located in the display area, and along a width direction of a channel structure of the first transistor, the first gate extends beyond an edge of the first semiconductor layer; and / or the array substrate further comprises a second transistor, the second transistor is located in the peripheral area, comprises a second semiconductor layer and a second gate located on a side of the second semiconductor layer away from the substrate, and along a width direction of a channel structure of the second transistor, the second gate extends beyond an edge of the second semiconductor layer.

23. The array substrate according to claim 22, wherein, a distance of an edge of the first gate extending out of the first semiconductor layer is greater than or equal to 3 pm in a width direction of a channel structure of the first transistor; and / or, a distance of an end of the second gate extending out of the second semiconductor layer is greater than or equal to 3 pm in a width direction of a channel structure of the second transistor.

24. The array substrate according to claim 22 or 23, wherein, the second semiconductor layer comprises a plurality of sub-semiconductor layers, the plurality of sub-semiconductor layers are distributed at intervals in a width direction of a channel structure of the second transistor, and each of the sub-semiconductor layers has a size in the width direction of the channel structure of the second transistor less than or equal to 20 pm.

25. The array substrate according to any one of claims 22-24, wherein, a material of the second semiconductor layer comprises a metal oxide semiconductor material, and the second semiconductor layer comprises a first region and two second regions located on both sides of the first region, a footprint of the first region on the substrate is located within a footprint of the second gate on the substrate, and a footprint of the second region on the substrate, which is close to an edge of the first region, overlaps with the footprint of the second gate on the substrate; the second region has a higher conductivity than the first region.

26. A display panel, comprising: the array substrate according to any one of claims 1-25; an opposite substrate disposed opposite to the array substrate; a liquid crystal layer disposed between the array substrate and the opposite substrate.

27. A display device, comprising a backlight module and the display panel according to claim 26, the backlight module being disposed on a backlight side of the display panel.

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