Method for producing epitaxial wafer and epitaxial wafer

Abstract

This invention provides a method for producing epitaxial wafers and an epitaxial wafer. The method includes: obtaining the resistivity of a substrate wafer; adjusting the heating power of an epitaxial growth apparatus according to the resistivity and / or the target epitaxial layer thickness of the substrate wafer; and performing epitaxial growth on the substrate wafer using the adjusted epitaxial growth apparatus to obtain an epitaxial wafer. This invention, by adjusting the heating power of the epitaxial growth apparatus for substrate wafers with different resistivities and / or target epitaxial layer thicknesses, allows for the use of appropriate epitaxial process conditions to perform epitaxial growth on the substrate wafer, thereby ensuring the quality of the produced epitaxial wafer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an epitaxial wafer manufacturing method and an epitaxial wafer. Background Technology

[0002] Vapor phase epitaxy (VPE) is a common epitaxial growth technique that enables the growth of epitaxial layers on polished wafers that differ from the original wafer in conductivity, resistivity, and structure. These layers offer controllable thickness and resistivity, meeting diverse requirements and significantly improving the flexibility and performance of device designs. VPE has broad application prospects in various semiconductor functional devices. Specifically, the epitaxial manufacturing process typically utilizes chemical vapor deposition (CVD) to inject silicon source gas into the surface of a polished wafer within a high-temperature, sealed reaction chamber, depositing an epitaxial layer on the wafer's surface to obtain an epitaxial wafer. Compared to polished wafers, epitaxial wafers offer advantages such as fewer surface defects and the ability to control the thickness and resistivity of the epitaxial layer.

[0003] Currently, epitaxial growth processes often employ uniform process conditions for defect detection and growth control. However, polished wafers exhibit varying thermal stress response characteristics due to their different inherent properties and target epitaxial layer thicknesses during epitaxial growth. Therefore, using uniform process conditions for epitaxial growth can lead to ineffective growth control and inaccurate defect detection, ultimately resulting in unreliable quality of the produced epitaxial wafers. Summary of the Invention

[0004] In view of this, the present invention aims to provide an epitaxial wafer manufacturing method and an epitaxial wafer to solve the problem that the quality of epitaxial wafers produced in the prior art cannot be guaranteed.

[0005] This invention provides a method for producing epitaxial wafers, the method comprising: Obtain the resistivity of the substrate; The heating power of the epitaxial growth equipment is adjusted according to the resistivity and / or the target epitaxial layer thickness of the substrate. The substrate is epitaxially grown using an adjusted epitaxial growth device to obtain an epitaxial wafer.

[0006] In one embodiment, adjusting the heating power of the epitaxial growth apparatus according to the target epitaxial layer thickness of the substrate includes: If the target epitaxial layer thickness is greater than or equal to the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to the first heating power. If the target epitaxial layer thickness is less than the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to a second heating power; the second heating power is less than the first heating power.

[0007] In one embodiment, the preset thickness is 5µm.

[0008] In one embodiment, the ratio of the first heating power to the rated heating power of the epitaxial growth equipment ranges from 56% to 60%, and the ratio of the second heating power to the rated heating power of the epitaxial growth equipment ranges from 54% to 58%.

[0009] In one embodiment, adjusting the heating power of the epitaxial growth apparatus according to the resistivity includes: If the resistivity is greater than or equal to the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a first power ratio. If the resistivity is less than the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a second power ratio, wherein the first power ratio is less than the second power ratio. In one embodiment, the resistivity threshold is 1.0 Ω·cm.

[0010] In one embodiment, the first power ratio is 68 / 16.5, and the second power ratio is 78 / 19.

[0011] In one embodiment, after the epitaxial growth of the substrate using the adjusted epitaxial growth equipment to obtain the epitaxial wafer, the method further includes: Obtain the crystal orientation of the epitaxial wafer; Based on the crystal orientation, determine the target detection conditions for the epitaxial wafer; Defect detection is performed on the epitaxial wafer based on the target detection conditions to obtain the detection results; If the detection result meets the preset conditions, then return to the step of obtaining the resistivity of the substrate wafer until a preset number of epitaxial wafers are produced.

[0012] In one embodiment, determining the target detection conditions for the epitaxial wafer based on the crystal orientation includes: The epitaxial wafer type is determined based on the crystal orientation; The detection condition corresponding to the epitaxial wafer type among the preset detection conditions is determined as the target detection condition.

[0013] In one embodiment, determining the epitaxial wafer type based on the crystal orientation includes: If the crystal orientation is <100> If the crystal orientation is specified, the epitaxial wafer type is determined to be a first-type epitaxial wafer; If the crystal orientation is <110> If the crystal orientation is determined, the epitaxial wafer type is identified as a second type of epitaxial wafer; The step of determining the target detection condition from among a variety of preset detection conditions that corresponds to the epitaxial wafer type includes: The first test parameter corresponding to the first type of epitaxial wafer among the preset multiple detection conditions is determined as the target detection condition; the first test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process; Alternatively, the second test parameter corresponding to the second type of epitaxial wafer among the preset multiple detection conditions can be determined as the target detection condition. The second test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process. The first test parameter is different from the second test parameter.

[0014] In one embodiment, the first test parameter is a positioning notch angle of 0°; the first test parameter is a positioning notch angle of 45°.

[0015] In another aspect, the present invention provides an epitaxial wafer, which is manufactured by the epitaxial wafer manufacturing method described in the above embodiments.

[0016] In one embodiment, the difference between the nanomorphic values ​​of the epitaxial wafer and the nanomorphic values ​​of the substrate wafer is less than 2. In one embodiment, the resistivity uniformity of the epitaxial wafer is less than 2.5%; In one embodiment, the thickness uniformity of the epitaxial wafer is less than 0.8%.

[0017] Compared with related technologies, the epitaxial wafer production method provided by the present invention has the following advantages: The epitaxial wafer production method provided by this invention involves obtaining the resistivity of a substrate wafer; adjusting the heating power of the epitaxial growth equipment based on the resistivity and / or the target epitaxial layer thickness of the substrate wafer; and then performing epitaxial growth on the substrate wafer using the adjusted epitaxial growth equipment to obtain an epitaxial wafer. Since resistivity reflects the doping concentration of the substrate wafer, and substrate wafers with different doping concentrations and epitaxial wafers with different target epitaxial layer thicknesses all require appropriate temperature conditions to accurately control epitaxial growth, the target epitaxial layer thickness and doping concentration can be used to precisely control the heating conditions of the epitaxial growth equipment in the epitaxial growth process. This effectively suppresses epitaxial wafer defects caused by unreasonable thermal stress and thermal field distribution in the reaction chamber of the epitaxial growth equipment, ensuring the quality of the produced epitaxial wafers. Attached Figure Description

[0018] Figure 1 The diagram shown is a structural schematic of an epitaxial wafer provided in an embodiment of the present invention.

[0019] Figure 2 The diagram shown is a schematic diagram of a pin nano defect in an epitaxial wafer provided in an embodiment of the present invention.

[0020] Figure 3 The diagram shown is a flowchart of an epitaxial wafer manufacturing method according to an embodiment of the present invention.

[0021] Figure 4 The diagram shown is a schematic diagram of the reaction chamber in an epitaxial growth apparatus provided in an embodiment of the present invention.

[0022] Figure 5 The diagram shown is a structural schematic of an epitaxial growth apparatus provided in an embodiment of the present invention.

[0023] Figure 6 The diagram shown is a flowchart illustrating the specific implementation of an epitaxial wafer production method according to an embodiment of the present invention.

[0024] Figure 7 The diagram shown is a schematic diagram of Nanoparticle detection results for epitaxial wafers of different thicknesses obtained after the epitaxial growth process is improved according to an embodiment of the present invention.

[0025] Figure 8 The diagram shown is a flowchart illustrating the specific implementation of an epitaxial wafer production method according to another embodiment of the present invention.

[0026] Figure 9 The diagram shown is a schematic of the slip window detection results of P-lightly doped and P+ heavily doped epitaxial wafers according to an embodiment of the present invention.

[0027] Figure 10The diagram shows the slip detection results of P- and P+ epitaxial wafers produced by the improved epitaxial manufacturing process provided in an embodiment of the present invention.

[0028] Figure 11 The diagram shown is a flowchart illustrating the specific implementation of an epitaxial wafer production method according to another embodiment of the present invention.

[0029] Figure 12 The diagram shown is a schematic diagram of the detection results of detecting the slip line of an epitaxial wafer according to an embodiment of the present invention.

[0030] Figure 13 The diagram shown is a schematic block diagram of an epitaxial wafer production apparatus provided in an embodiment of the present invention.

[0031] Figure 14 The diagram shown is a block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0034] In semiconductor manufacturing, epitaxial growth of polished wafers is one of the key front-end processes. Its purpose is to grow a single-crystal silicon thin film with a complete crystal structure and precisely controllable resistivity and thickness on a polished silicon substrate. Currently, the mainstream process is Chemical Vapor Deposition (CVD). Typically, at high temperatures (e.g., 1100-1200℃), a mixture of silicon source gas (e.g., SiCl4, SiHCl3) and hydrogen is introduced into a reaction chamber, where it reacts and deposits on the surface of a rotating polished wafer, forming an epitaxial layer. The various defects in the epitaxial layer are related not only to the quality and surface condition of the polished wafer substrate but also to the process conditions used during epitaxial growth. The uniformity of temperature distribution within the reaction chamber of the epitaxial growth equipment (e.g., the epitaxial furnace) significantly affects the formation of defects on the back side of the epitaxial wafer. Specifically, the uniformity of temperature distribution greatly influences the formation of Pin Nano defects. Pin Nano defects refer to contamination marks appearing at the support pin locations on the polished wafer. As an example, [examples of Pin Nano defects would follow]. Figure 1 As shown, the epitaxial wafer structure includes a polished wafer (substrate) and an epitaxial layer on top of the polished wafer. During the epitaxial growth process, as the thickness of the epitaxial layer increases, more and more byproduct coatings are deposited on the upper quartz dome inside the epitaxial furnace. This phenomenon significantly alters the thermal field distribution within the reaction chamber, causing changes in the internal temperature field. Specifically, the increased dome coating thickness affects the uniformity of thermal radiation, resulting in a temperature difference between the back of the polished wafer and the contact area with the support lift pin. This temperature difference directly affects the heating uniformity of the polished wafer, potentially negatively impacting the growth quality of subsequent epitaxial layers. This leads to a temperature difference between the substrate surface and the polished wafer during film growth, causing pin nano defects during growth, such as… Figure 2 As shown, the Pin Nano defect is specifically manifested as black Pin Nano marks on the surface of the polished sheet.

[0035] Furthermore, the applicant discovered in its actual research that the cutting, grinding, and polishing processes during the processing of the polished substrate (hereinafter referred to as the substrate) introduce mechanical stress, while the thermal deformation of the substrate during epitaxy introduces thermal stress. When the total stress caused by both exceeds the critical stress value that causes lattice slip at the epitaxial temperature, slip lines will be generated. However, with the maturity of edge polishing technology, the mechanical stress introduced at the edge of the polished substrate has been significantly improved. Therefore, thermally induced stress (hereinafter also referred to as thermal stress) during epitaxial growth has become the main factor in the generation of slip lines on the epitaxial wafer surface. A large radial temperature gradient of the polished wafer during epitaxial growth easily causes slip lines.

[0036] Slip lines are typical crystallographic displacements of the crystal lattice structure caused by thermally induced stress. Slip is caused by temperature gradients in the silicon wafer. It generally starts from the edge of the wafer, and these misalignments tend to move towards the center. If slip already exists in the original wafer, it will extend into the epitaxial layer during epitaxial growth, resulting in slip line defects in the produced epitaxial wafer. Furthermore, heavily doped and lightly doped silicon wafers refer to two types of silicon materials with different dopant concentrations. Doping is the process of replacing atoms in a silicon wafer with atoms of other elements to adjust the electrical properties of the material. The doping concentration of heavily doped silicon wafers is typically 10¹⁸ / cm³ or higher, while the doping concentration of lightly doped silicon wafers is typically in the range of 10¹² to 10¹⁶ / cm³. The applicant also discovered in their research that, due to the difference in atomic density between heavily doped and lightly doped wafers, lightly doped silicon wafers (P-wafers) are more prone to slippage under thermal stress than heavily doped silicon wafers (P+wafers). Therefore, P+wafers have more slip windows than P-wafers. Improper use of slip windows can lead to slip lines, severely impacting product quality.

[0037] In view of the above problems, one embodiment of the present invention provides an epitaxial wafer manufacturing method. This method can be applied to an epitaxial growth system, which may include epitaxial growth equipment and defect detection equipment. The epitaxial growth equipment includes a reaction chamber, a base disposed within the reaction chamber, and supporting components. The epitaxial wafer manufacturing method can be executed by a controller integrated in the epitaxial growth equipment or the defect detection equipment, or by electronic equipment (e.g., a server or user terminal) connected to the epitaxial growth equipment and the defect detection equipment; no limitation is made herein. Figure 3 As shown, the epitaxial wafer manufacturing method may include: 110. Obtain the resistivity of the substrate.

[0038] As an example, such as Figure 4As shown, the epitaxial growth apparatus may include a reaction chamber, a conveying unit, and a controller. The conveying unit may include a support component and a conveying assembly, wherein the support component can be mounted on the conveying assembly and driven by it. Optionally, the support component may include one or more support pins or lift pins. The conveying assembly may include a conveyor belt, a conveying robot, etc.

[0039] Among them, the reaction chamber in the epitaxial growth equipment can be like Figure 4 As shown, the reaction chamber is used to perform chemical vapor deposition on the main surface of the polished wafer 8 to grow an epitaxial layer. The reaction chamber may include an upper quartz bell jar 1, a lower quartz bell jar 2, and a mounting component 4 arranged opposite each other.

[0040] Optionally, the reaction chamber may also be provided with an air inlet. Figure 4 (not shown in the image) and exhaust port ( Figure 4 (Not shown in the image). Optionally, the reaction chamber may further include a base 6 for placing the polishing disc 8 and a base support rod 7. Optionally, the reaction chamber may further include a heater, which may include an upper heating unit located above the base and / or a lower heating unit located below the base. The upper heating unit may include one or more heating lamps 3 (such as halogen lamps), and the lower heating unit may include one or more heating lamps 3. Figure 4 In this context, the gas flow direction 5 can be used to indicate the flow direction of the etching gas and / or silicon source gas.

[0041] As an example, epitaxial growth equipment can be as follows: Figure 5 As shown, for example, the epitaxial growth apparatus may include a reaction chamber 105 and a transfer unit ( Figure 5 (not shown in the image), controller ( Figure 5 (Not shown in the diagram) includes a transfer chamber 104, a load locking module 103, a front-end module 102, and a loading port 101. In practical applications, the transfer blades in the front-end module 102 transfer the polished wafer from the loading port 101 to the load locking module 103, where the load locking module 103 is evacuated and backfilled with nitrogen. A transfer unit (such as a transfer robot) located in the transfer chamber 104 loads the polished wafer from the load locking module 103 onto a base in the reaction chamber 105 for epitaxial growth. After growth is complete, the polished wafer returns along the original path.

[0042] In some embodiments, the controller can control the conveying unit in the epitaxial growth apparatus to load the polished wafer onto the base in the reaction chamber, supply raw material gas to the main surface of the polished wafer, thereby performing vapor phase growth. After vapor phase growth, the epitaxial wafer obtained through vapor phase growth is output outside the reaction chamber 105. During the growth process, the base support rod 7 serves to fix the base 6 and drive the base 6 to rotate, so that the epitaxial growth can be carried out uniformly on the substrate.

[0043] The defect detection equipment can be a commercially available optical defect detection instrument, such as the KLA SPX series detector, which captures wafer surface defect features through laser scanning and multi-mode imaging technology. In this embodiment, the optical defect detection instrument can detect the slip line on the epitaxial wafer surface by detecting the coordinate position of the slip on the epitaxial wafer.

[0044] The epitaxial wafer manufacturing method will be described below using the aforementioned electronic device as an example.

[0045] Optionally, the resistivity of the substrate can be measured by a suitable testing instrument (such as a four-probe resistivity meter) and then uploaded to the electronic device.

[0046] Alternatively, the electronic device can determine the crystal orientation of the substrate by reading the crystal orientation specification data of the batch to which the substrate belongs.

[0047] Crystal orientation refers to the direction in which atoms are arranged in a crystal, usually expressed by Miller indices (e.g., ). <100> , <110> , <111> (This is represented by the symbol ). Different crystal orientations correspond to different physical and chemical properties, such as defect density, surface smoothness, and dopant solubility. For example, <100> Crystal orientation: corresponding to the edge direction of a cube, with atoms arranged in a square grid. <110> Crystal orientation: The included crystal orientation is indistinguishable in electron diffraction and has specific diffraction characteristics.

[0048] 120. Adjust the heating power of the epitaxial growth equipment according to the resistivity and / or the target epitaxial layer thickness of the substrate.

[0049] The target epitaxial layer thickness can refer to the thickness that the epitaxial wafer obtained after the substrate undergoes the epitaxial growth process, or it can be understood as the thickness specification of the epitaxial wafer product that the user expects to produce.

[0050] Optionally, the target epitaxial layer thickness can be customized according to actual needs and input into the electronic device so that the electronic device can control the epitaxial growth equipment according to the target epitaxial layer thickness, thereby producing epitaxial wafers of the corresponding specifications.

[0051] 130. The substrate is epitaxially grown using the adjusted epitaxial growth equipment to obtain an epitaxial wafer.

[0052] In some embodiments, the specific implementation of adjusting the heating power of the epitaxial growth apparatus in step 120 according to the target epitaxial layer thickness may include: If the target epitaxial layer thickness is greater than or equal to the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to the first heating power. If the target epitaxial layer thickness is less than the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to a second heating power; the second heating power is less than the first heating power.

[0053] As an example, step 120 can be implemented in practical applications through the following steps: 121a. Determine the silicon wafer type of the substrate based on the target epitaxial layer thickness.

[0054] 122a. Select the process condition corresponding to the silicon wafer type from the preset multiple process conditions as the target process condition.

[0055] 123a. Adjust the heating power of the epitaxial growth equipment based on the target process conditions.

[0056] It is understandable that process conditions can be the growth environment conditions that need to be controlled by the epitaxial growth system when performing an epitaxial growth process. For example, process conditions may include temperature conditions, gas flow rate conditions, equipment power conditions, etc. in the reaction chamber.

[0057] In some implementations, the substrate can be pre-classified into different silicon wafer types based on substrate information such as the target epitaxial layer thickness and resistivity. Then, a process condition is associated with each silicon wafer type to obtain a process condition mapping table. This process condition mapping table can then be stored in the aforementioned electronic device. For example, this process condition mapping table can be as shown in Table 1: Table 1 As shown in Table 1, after determining the silicon wafer type of the current substrate based on the substrate information, the corresponding process conditions can be found in Table 1 as target process conditions. For example, if the silicon wafer type of the substrate is determined to be a type 2 silicon wafer, process condition 2 can be determined as the target process condition.

[0058] Following the example above, after determining the target process conditions, the electronic device can adjust the equipment parameters of the equipment in the epitaxial growth system (such as epitaxial growth equipment, defect detection equipment, etc.) so that the epitaxial growth system can perform epitaxial growth on the substrate under the target process conditions, thereby producing an epitaxial wafer.

[0059] In some embodiments, the substrate information includes the target epitaxial layer thickness. Specific embodiments of determining the silicon wafer type of the substrate based on the target epitaxial layer thickness in step 121a may include: If the target epitaxial layer thickness is greater than or equal to the preset thickness, the substrate is identified as a first-type silicon wafer.

[0060] If the target epitaxial layer thickness is less than the preset thickness, the substrate is identified as a second type of silicon wafer.

[0061] In this embodiment, the specific implementation of determining the process condition corresponding to the silicon wafer type among the preset multiple process conditions as the target process condition in step 122a may include: The first heating power corresponding to the first type of silicon wafer among the preset multiple process conditions is determined as the target process condition; the first heating power is the power of the epitaxial growth equipment when heating the lower surface of the substrate wafer in the epitaxial growth process.

[0062] Alternatively, the second heating power corresponding to the second type of silicon wafer among the preset multiple process conditions can be determined as the target process condition. The second heating power is the power of the epitaxial growth equipment when heating the lower surface of the substrate wafer in the epitaxial growth process. The second heating power is less than the first heating power.

[0063] Optionally, the preset thickness is 5µm.

[0064] Optionally, the ratio of the first heating power to the rated heating power of the epitaxial growth equipment ranges from 56% to 60%, and the ratio of the second heating power to the rated heating power of the epitaxial growth equipment ranges from 54% to 58%.

[0065] In some practical applications, the first heating power is 58% of the rated heating power of the epitaxial growth equipment, and the second heating power is 56% of the rated heating power of the epitaxial growth equipment.

[0066] For example, such as Figure 6 As shown, in practical applications, the specific implementation process of the epitaxial wafer production method in this embodiment may include: A1. First, prepare a substrate silicon wafer with a defect-free surface to obtain the substrate wafer, and ensure that its substrate flatness and cleanliness meet the process requirements.

[0067] A2. Before starting the epitaxial growth process, the precise target epitaxial layer thickness of the substrate can be obtained through a Manufacturing Execution System (MES). This thickness value is usually determined by product specifications (such as the breakdown voltage requirements of power devices). For example, a certain type of field-effect transistor (MOSFET) device requires an epitaxial layer thickness of 6µm to optimize the breakdown voltage.

[0068] A3. Based on the target epitaxial layer thickness of the substrate (also called the silicon wafer to be grown or silicon substrate), substrates are divided into two categories. For example, they can be classified into Category I and Category II products according to the target epitaxial layer thickness. Category I products (i.e., the first type of silicon wafer mentioned above) are silicon wafers or epitaxial wafers with a thickness > 5µm. These products are typically used in high-voltage or high-power devices (such as IGBT modules), where the epitaxial layer is thicker to provide sufficient carrier concentration and withstand voltage. Category II products (i.e., the second type of silicon wafer mentioned above) are silicon wafers with a thickness < 5µm. These products are mostly used in low-voltage or high-frequency devices (such as logic chips), where the epitaxial layer is thinner to reduce parasitic capacitance and on-resistance.

[0069] A4. Adjust the Bottom Power (heating power) of the reaction chamber in the epitaxial growth equipment to allow for different Bottom Powers for products with different target epitaxial layer thicknesses. Bottom Power is used to heat the lower surface of the substrate. Since the Bottom Power of the epitaxial furnace directly affects the temperature field distribution at the bottom of the silicon wafer, it consequently affects the uniformity and crystal quality of the epitaxial layer growth. Therefore, based on the classification results, the specific method for adjusting the Bottom Power is as follows: For Category I products (thickness > 5µm), the Bottom Power can be 58% of the rated heating power, i.e., the first heating power mentioned above. Higher power can compensate for heat loss during the growth of thicker epitaxial layers, ensuring that the temperature at the bottom of the silicon wafer remains stable within the range of 1120±5℃, avoiding a decrease in epitaxial layer growth rate or an increase in defects due to insufficient temperature. For Category II products (thickness < 5µm), the Bottom Power can be 56% of the rated heating power, i.e., the second heating power mentioned above. Lower power can prevent excessive temperature from causing silicon wafer warping or increased surface roughness, while also reducing the impact of thermal stress on thin epitaxial layers.

[0070] A5. Normal Continuous Production in the Epitaxial Furnace: After classification and Bottom Power adjustment, the epitaxial furnace enters normal continuous production mode. At this time, the following parameters must be continuously monitored: Real-time temperature: Monitor the silicon wafer surface and dome temperature using thermocouples to ensure thermal stability. Growth rate: Use a film thickness interferometer to detect the epitaxial layer thickness online and verify whether the growth rate meets expectations (e.g., 1.2 μm / min for Type I products, 0.8 μm / min for Type II products). If any abnormalities occur during production (e.g., temperature fluctuations exceeding ±10℃ or thickness deviations > ±0.2 μm), production must be immediately suspended and the cause investigated. Production should be restarted after the problem is resolved.

[0071] Following the above example, the epitaxial wafer produced using steps A1 to A5 in this embodiment is as follows: Figure 7 As shown, Figure 7 The nanoparticle detection results for epitaxial wafers of different thicknesses after the improvement of the epitaxial growth process are shown. Five epitaxial wafers (pcs) were used for testing and verification after the improvement: no pin nanoparticles appeared on the surface of the epitaxial wafers. It can be seen that after improving the epitaxial growth process through this embodiment, the occurrence rate of pin nanoparticles was reduced to 0%. The occurrence of pin nanoparticles in epitaxial wafers was effectively suppressed, improving the product quality of the epitaxial wafers.

[0072] In other embodiments, specific implementations of step 120 may include: If the resistivity is greater than or equal to the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a first power ratio. If the resistivity is less than the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a second power ratio, wherein the first power ratio is less than the second power ratio.

[0073] As an example, step 120 can be implemented in practical applications through the following steps: 121b. Determine the silicon wafer type of the substrate based on resistivity.

[0074] 122b. Select the process condition corresponding to the silicon wafer type from the preset multiple process conditions as the target process condition.

[0075] 123b. Adjust the heating power of the epitaxial growth equipment based on the target process conditions. Substrate information includes resistivity, in If the resistivity is greater than or equal to the resistivity threshold, the substrate is classified as a Class III silicon wafer. If the resistivity is less than the resistivity threshold, the substrate is classified as a Class IV silicon wafer.

[0076] In this embodiment, the specific implementation of determining the process condition corresponding to the silicon wafer type among the preset multiple process conditions as the target process condition in step 122b may include: The first power ratio corresponding to the third type of silicon wafer among the preset multiple process conditions is determined as the target process condition; the first power ratio is the ratio between the heating powers used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate wafer respectively in the epitaxial growth process.

[0077] Alternatively, the second power ratio corresponding to the fourth type of silicon wafer among the preset multiple process conditions can be determined as the target process condition. The second power ratio is the ratio between the heating powers used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate wafer in the epitaxial growth process, and the first power ratio is less than the second power ratio.

[0078] Optionally, the resistivity threshold is 1.0 Ω·cm.

[0079] Optionally, the first power ratio is 68 / 16.5, and the second power ratio is 78 / 19.

[0080] For example, such as Figure 8 As shown, in practical applications, the specific process of the epitaxial wafer production method in this embodiment may include: B1. First, prepare a substrate silicon wafer with no slip lines on the surface as the substrate wafer, and ensure that the flatness and cleanliness of the substrate meet the process requirements.

[0081] B2. The resistivity of the substrate silicon wafer was detected using the four-probe method.

[0082] B3. Classify the silicon substrates based on the resistivity test results. For example, silicon substrates with resistivity < 1.0 Ω·cm are classified as P+ heavily doped wafers (i.e., the third type of silicon wafers mentioned above), whose high doping concentration significantly improves carrier mobility; silicon substrates with resistivity > 1.0 Ω·cm are classified as P- lightly doped wafers (i.e., the fourth type of silicon wafers mentioned above), whose low doping characteristics are suitable for high-resistivity applications.

[0083] B4. Based on the silicon wafer type, the electronic equipment automatically adjusts the power balance of the reaction chamber of the epitaxial growth equipment. The power balance is the ratio between the power of the upper inner heater and the power of the lower inner heater, i.e., the power ratio mentioned above. Figure 9 The slip window detection results of P-lightly doped and P+ heavily doped epitaxial wafers are shown, and the classification effectiveness is verified by comparing the distribution of lattice defects. Figure 9It is known that the slip window for heavily doped P+ wafers is available in the range of 62 / 15 to 74 / 18. Optionally, a power ratio of 68 / 16.5 (i.e., the first power ratio mentioned above) is used for heavily doped P+ wafers to optimize the growth rate of the heavily doped epitaxial layer. The slip window for lightly doped P- wafers is available in the range of 74 / 18 to 82 / 20. Optionally, a power ratio of 78 / 19 (i.e., the second power ratio mentioned above) is used for lightly doped P- wafers. According to the above embodiments, the power balance of the epitaxial furnace chamber can be adjusted according to the slip window corresponding to different silicon wafer types to optimize the growth rate of the epitaxial layer, ensure the uniformity and crystal quality of the epitaxial layer, and thus achieve targeted improvement in the stability of the epitaxial process for different silicon wafer types.

[0084] B5. After automatically adjusting the reaction chamber of the epitaxial growth equipment to the power balance corresponding to the P-lightly doped epitaxial wafer or the P+ heavily doped epitaxial wafer, the epitaxial growth process is started to obtain the corresponding epitaxial wafer product.

[0085] Following the above example, the epitaxial wafer produced using steps B1 to B5 of this embodiment is as follows: Figure 9 As shown, Figure 10 The slide detection results of P- and P+ epitaxial wafers produced by the improved epitaxial manufacturing process through steps B1 to B5 are shown. Five wafers of each type were used for testing and verification after the improvement. It can be seen that no slide lines appeared on the surface of any of the epitaxial wafers. Therefore, by improving the epitaxial growth process through this embodiment, the occurrence rate of slide lines in the produced epitaxial wafers is reduced to 0%, thereby effectively suppressing the formation of slide lines on the epitaxial wafers and ensuring the quality of the produced epitaxial wafers.

[0086] In some implementations, after step 130, the method may further include: Obtain the crystal orientation of the epitaxial wafer.

[0087] Determine the target detection conditions for the epitaxial wafer based on the crystal orientation.

[0088] Defect detection is performed on epitaxial wafers based on target detection conditions to obtain detection results.

[0089] If the detection result meets the preset conditions, the process returns to the step of obtaining the resistivity of the substrate (i.e., re-execute step 110) until a preset number of epitaxial wafers are produced.

[0090] In some implementations, the specific implementation of the step "determine the target detection conditions of the epitaxial wafer according to the crystal orientation" may include: The epitaxial wafer type is determined based on the crystal orientation; The detection condition corresponding to the epitaxial wafer type among the preset detection conditions is determined as the target detection condition.

[0091] In some implementations, the specific implementation of the step "determine the epitaxial wafer type based on crystal orientation" may include: If the crystal orientation is <100> If the crystal orientation is determined, the substrate is identified as a type I epitaxial wafer.

[0092] If the crystal orientation is <110> If the crystal orientation is determined, the substrate is identified as a type II epitaxial wafer.

[0093] In this embodiment, the specific implementation method for determining the detection condition corresponding to the epitaxial wafer type from a variety of preset detection conditions as the target detection condition may include: The first test parameter corresponding to the first type of epitaxial wafer among the preset multiple test conditions is determined as the target test condition; the first test parameter is the notch angle of the epitaxial wafer positioning notch when the defect detection equipment in the epitaxial growth process tests the epitaxial wafer.

[0094] Alternatively, the second test parameter corresponding to the second type of epitaxial wafer among the preset multiple detection conditions can be determined as the target detection condition. The second test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process. The first test parameter is different from the second test parameter.

[0095] Optionally, the first test parameter is a positioning notch angle of 0°; or the first test parameter is a positioning notch angle of 45°.

[0096] For example, such as Figure 11 As shown, in practical applications, the specific process of the epitaxial wafer production method in this embodiment may include: C1. The substrate is loaded into the reaction chamber for epitaxial growth. Specifically, after the substrate enters the reaction chamber of the epitaxial furnace, a single-crystal silicon thin film is grown by chemical vapor deposition (CVD) to form an epitaxial layer, thereby obtaining an epitaxial wafer.

[0097] C2. Classify epitaxial wafers according to their crystal orientation. For example, classify them as follows: <100> Crystal-oriented epitaxial wafers are divided into Category I products (i.e., the first category of epitaxial wafers mentioned above), which will... <110> Crystal-oriented epitaxial wafers are classified into Category II products; C3. For epitaxial wafers (SPX) with different crystal orientations, different test parameters (Recipes) are used to test the silicon wafer slip, focusing on detecting slip line defects at the edge of the epitaxial wafer, thereby obtaining the test results. For example, for wafers with crystal orientations of... <100> For epitaxial wafers, a special inspection parameter called "100" can be loaded on defect inspection equipment (such as SPX). When this inspection parameter is executed, the defect inspection equipment requires the transfer unit or stage to place the notch (positioning notch) of the epitaxial wafer in a 0° reference direction for slip line detection. For crystal orientation... <110> For the epitaxial wafer, another dedicated inspection parameter called "110" is applied. When this inspection parameter is executed, the defect inspection equipment requires the Notch of the epitaxial wafer to be rotated and positioned at a 45° angle to detect slip lines.

[0098] C4. Based on the inspection results, classify the defects or conduct a re-inspection. For example, such as... Figure 12 As shown, the test results can be divided into qualified products and abnormal products. Among them, if the slip line length of the epitaxial wafer is less than or equal to 0µm (e.g., ... Figure 12 If the sample lengths of Sample 1 and Sample 4 are difficult to obtain, then the epitaxial wafer can be determined to be a qualified product. If the slip line length of the epitaxial wafer is greater than 0µm (e.g., ...), then the epitaxial wafer is qualified. Figure 12 Samples 2 and 3 (which are difficult to detect) can be identified as defective epitaxial wafers. Qualified products can proceed to subsequent processes; for example, the epitaxial growth equipment can continue producing epitaxial wafers under current process conditions until the required preset quantity is reached. Defective products require X-ray diffraction (XRD) analysis to determine the degree of lattice distortion. This is combined with manual re-inspection to confirm the type of defective silicon wafer, ultimately updating the defect database and improving the efficiency of subsequent automatic defect identification. If the same defect reappears, the system can automatically identify it, reducing human intervention and continuously improving the efficiency and accuracy of subsequent testing. Thus, through crystal orientation compatibility testing and multi-level defect screening, this process improves testing accuracy, reduces the risk of slip-line over-testing and under-testing, significantly improves testing precision and efficiency, and achieves accurate identification and comprehensive analysis of edge defects in epitaxial wafers, effectively improving the product quality of epitaxial wafers.

[0099] As can be seen, in this embodiment, the resistivity of the substrate is obtained; and the heating power of the epitaxial growth equipment is adjusted according to the resistivity and / or the target epitaxial layer thickness of the substrate; then, the substrate is epitaxially grown using the adjusted epitaxial growth equipment to obtain an epitaxial wafer. Since resistivity reflects the doping concentration of the substrate, and substrates with different doping concentrations and epitaxial wafers with different target epitaxial layer thicknesses all require appropriate temperature conditions to accurately control epitaxial growth, the heating conditions of the epitaxial growth equipment in the epitaxial growth process can be precisely controlled by utilizing the target epitaxial layer thickness and doping concentration. This effectively suppresses epitaxial wafer defects caused by unreasonable thermal stress and thermal field distribution in the reaction chamber of the epitaxial growth equipment, ensuring the quality of the produced epitaxial wafer.

[0100] An embodiment of the present invention also provides an epitaxial wafer, which is manufactured by the epitaxial wafer manufacturing method described in the above embodiment.

[0101] In some embodiments, the difference between the nanomorphic values ​​of the epitaxial wafer and the nanomorphic values ​​of the substrate wafer is less than 2.

[0102] In some implementations, the resistivity uniformity of the epitaxial wafer is less than 2.5%.

[0103] In some implementations, the thickness uniformity of the epitaxial wafer is less than 0.8%.

[0104] Figure 13 The diagram shown is a block diagram of an epitaxial wafer production apparatus according to an embodiment of the present invention. The epitaxial wafer production apparatus 300 includes: The acquisition module 310 is used to acquire the resistivity of the substrate. The adjustment module 320 is used to adjust the heating power of the epitaxial growth equipment according to the resistivity and / or the target epitaxial layer thickness of the substrate. Production module 330 is used to perform epitaxial growth on a substrate using an adjusted epitaxial growth device to obtain an epitaxial wafer.

[0105] In some implementations, the adjustment module 320 is specifically used for: If the target epitaxial layer thickness is greater than or equal to the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to the first heating power. If the target epitaxial layer thickness is less than the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to the second heating power; the second heating power is less than the first heating power.

[0106] In some implementations, the preset thickness is 5µm.

[0107] In some embodiments, the ratio of the first heating power to the rated heating power of the epitaxial growth equipment ranges from 56% to 60%, and the ratio of the second heating power to the rated heating power of the epitaxial growth equipment ranges from 54% to 58%.

[0108] In some implementations, the adjustment module 320 is specifically used for: If the resistivity is greater than or equal to the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to the first power ratio. If the resistivity is less than the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a second power ratio, where the first power ratio is less than the second power ratio.

[0109] In some implementations, the resistivity threshold is 1.0 Ω·cm.

[0110] In some implementations, the first power ratio is 68 / 16.5, and the second power ratio is 78 / 19.

[0111] In some embodiments, the device 300 may further include a detection module, which is used for: Obtain the crystal orientation of the epitaxial wafer; Determine the target detection conditions for the epitaxial wafer based on the crystal orientation; Defect detection is performed on epitaxial wafers based on target detection conditions to obtain detection results; If the detection result meets the preset conditions, the process returns to the step of obtaining the resistivity of the substrate wafer until a preset number of epitaxial wafers are produced.

[0112] In some implementations, the detection module is specifically used for: The epitaxial wafer type is determined based on the crystal orientation; The detection condition corresponding to the epitaxial wafer type among the preset detection conditions is determined as the target detection condition.

[0113] In some implementations, the detection module is further used for: If the crystal orientation is <100> Based on the crystal orientation, the substrate is identified as a type I epitaxial wafer; If the crystal orientation is <110> Based on the crystal orientation, the substrate is identified as a type II epitaxial wafer; The first test parameter corresponding to the first type of epitaxial wafer among the preset multiple detection conditions is determined as the target detection condition; the first test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process. Alternatively, the second test parameter corresponding to the second type of epitaxial wafer among the preset multiple detection conditions can be determined as the target detection condition. The second test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process. The first test parameter is different from the second test parameter.

[0114] In some implementations, the first test parameter is a positioning notch angle of 0°; the first test parameter is a positioning notch angle of 45°.

[0115] The specific implementation process of the functions and roles of each module in the above-mentioned device can be found in the implementation process of the corresponding steps of the epitaxial wafer production method in the above embodiments, and will not be repeated here.

[0116] Figure 14 The diagram shown is a block diagram of an electronic device 500 provided in an embodiment of the present invention.

[0117] Reference Figure 14 The electronic device 500 includes a processing component 510, which further includes one or more processors, and memory resources represented by memory 520 for storing instructions, such as application programs, that can be executed by the processing component 510. The application programs stored in memory 520 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 510 is configured to execute instructions to perform the epitaxial wafer manufacturing method described above.

[0118] Electronic device 500 may also include a power supply component configured to perform power management of electronic device 500, a wired or wireless network interface configured to connect electronic device 500 to a network, and an input / output (I / O) interface. Electronic device 500 may operate on an operating system stored in memory 520, such as Windows Server™, Mac OSX™, Unix™, Linux™, FreeBSD™, or similar.

[0119] A non-transitory computer-readable storage medium, wherein when the instructions in the storage medium are executed by the processor of the aforementioned electronic device 500, the electronic device 500 is able to perform the aforementioned epitaxial wafer manufacturing method.

[0120] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0121] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0123] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0124] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0125] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program verification codes, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0126] Furthermore, it should be noted that the combination of the various technical features in this case is not limited to the combination methods described in the claims of this case or the combination methods described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way, unless they contradict each other.

[0127] It should be noted that the above examples are merely specific embodiments of the present invention, and the present invention is obviously not limited to the above embodiments, with many similar variations. All modifications that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should fall within the protection scope of this invention.

[0128] It should be understood that the terms "first," "second," etc., mentioned in the embodiments of the present invention are merely for the purpose of more clearly describing the use of the technical solutions in the embodiments of the present invention, and are not intended to limit the scope of protection of the present invention.

[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for producing epitaxial wafers, characterized in that, The method includes: Obtain the resistivity of the substrate; The heating power of the epitaxial growth equipment is adjusted according to the resistivity and / or the target epitaxial layer thickness of the substrate. The substrate is epitaxially grown using an adjusted epitaxial growth device to obtain an epitaxial wafer.

2. The epitaxial wafer production method according to claim 1, characterized in that, The step of adjusting the heating power of the epitaxial growth equipment according to the target epitaxial layer thickness of the substrate includes: If the target epitaxial layer thickness is greater than or equal to the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to the first heating power. If the target epitaxial layer thickness is less than the preset thickness, the power of the epitaxial growth equipment when heating the lower surface of the substrate during the epitaxial growth process is adjusted to a second heating power; the second heating power is less than the first heating power.

3. The epitaxial wafer production method according to claim 2, characterized in that, The preset thickness is 5µm.

4. The epitaxial wafer production method according to claim 2, characterized in that, The ratio of the first heating power to the rated heating power of the epitaxial growth equipment ranges from 56% to 60%, and the ratio of the second heating power to the rated heating power of the epitaxial growth equipment ranges from 54% to 58%.

5. The epitaxial wafer production method according to claim 1, characterized in that, The step of adjusting the heating power of the epitaxial growth equipment according to the resistivity includes: If the resistivity is greater than or equal to the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a first power ratio. If the resistivity is less than the resistivity threshold, the ratio between the heating power used by the epitaxial growth equipment to heat the upper and lower surfaces of the substrate in the epitaxial growth process is adjusted to a second power ratio, wherein the first power ratio is less than the second power ratio.

6. The epitaxial wafer production method according to claim 5, characterized in that, The resistivity threshold is 1.0 Ω·cm.

7. The epitaxial wafer production method according to claim 5, characterized in that, The first power ratio is 68 / 16.5, and the second power ratio is 78 / 19.

8. The method for producing an epitaxial wafer according to any one of claims 1 to 7, characterized in that, After the epitaxial growth of the substrate using the adjusted epitaxial growth equipment to obtain the epitaxial wafer, the method further includes: Obtain the crystal orientation of the epitaxial wafer; Based on the crystal orientation, determine the target detection conditions for the epitaxial wafer; Defect detection is performed on the epitaxial wafer based on the target detection conditions to obtain the detection results; If the detection result meets the preset conditions, then return to the step of obtaining the resistivity of the substrate wafer until a preset number of epitaxial wafers are produced.

9. The epitaxial wafer production method according to claim 8, characterized in that, Determining the target detection conditions for the epitaxial wafer based on the crystal orientation includes: The epitaxial wafer type is determined based on the crystal orientation; The detection condition corresponding to the epitaxial wafer type among the preset detection conditions is determined as the target detection condition.

10. The epitaxial wafer production method according to claim 9, characterized in that, Determining the epitaxial wafer type based on the crystal orientation includes: If the crystal orientation is <100> If the crystal orientation is specified, the epitaxial wafer type is determined to be a first-type epitaxial wafer; If the crystal orientation is <110> If the crystal orientation is determined, the epitaxial wafer type is identified as a second type of epitaxial wafer; The step of determining the target detection condition from among a variety of preset detection conditions that corresponds to the epitaxial wafer type includes: The first test parameter corresponding to the first type of epitaxial wafer among the preset multiple detection conditions is determined as the target detection condition; the first test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process; Alternatively, the second test parameter corresponding to the second type of epitaxial wafer among the preset multiple detection conditions can be determined as the target detection condition. The second test parameter is the epitaxial wafer positioning notch angle when the defect detection equipment tests the epitaxial wafer in the epitaxial growth process. The first test parameter is different from the second test parameter.

11. The epitaxial wafer manufacturing method according to claim 10, characterized in that, The first test parameter is a positioning notch angle of 0°; the first test parameter is a positioning notch angle of 45°.

12. An epitaxial wafer, characterized in that, The epitaxial wafer is manufactured by the epitaxial wafer manufacturing method as described in any one of claims 1 to 11; The difference between the nanomorphic values ​​of the epitaxial wafer and the nanomorphic values ​​of the substrate wafer is less than 2. The resistivity uniformity of the epitaxial wafer is less than 2.5%; The thickness uniformity of the epitaxial wafer is less than 0.8%.

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