A hardware time delay self-destruct circuit for a shaped charge

Abstract

This invention discloses a hardware-delayed self-destruct circuit system for a high-explosive fragmentation bomb, comprising a power input circuit, a power conversion circuit, a power-down switching circuit, a power-on delay circuit, a power-down delay circuit, an ignition trigger circuit, and an ignition circuit. The power-on delay circuit and the power-down delay circuit both utilize the same frequency divider chip, enabling precise delay-triggered ignition. The advantages of this invention are: the frequency divider delay circuit achieves high reliability, high anti-interference capabilities, a simple circuit structure, and low cost; it ensures reliable detonation of the high-explosive fragmentation bomb within a certain time window, effectively preventing accidental detonation, misfires, and other dangerous accidents; the power input circuit also employs input filtering, reverse connection protection, current backflow prevention, and surge protection circuits; the power-down switching circuit uses an NMOS field-effect transistor switching circuit; and the ignition trigger circuit is implemented using a combination of a silicon controlled rectifier (SCR) and a PMOS transistor.

Description

Technical Field

[0001] This invention relates to the technical field of time-delay self-destruct circuits for explosive fragmentation munitions, and in particular to a hardware time-delay self-destruct circuit system for explosive fragmentation munitions. Background Technology

[0002] The use of a hardware-delayed self-destruct circuit in a certain type of high-explosive fragmentation bomb is based on a comprehensive consideration of operational requirements, cost, extreme operating environments, and safety. Operationally, the demand is high, reaching tens of thousands of rounds, requiring low cost. The operating environment, with overload values ​​reaching tens of thousands of Gs, generates strong centrifugal force, as well as severe impacts and vibrations. Simultaneously, the microcomputer (ARM, 8051, etc.) software programming is susceptible to electromagnetic interference and attacks from malicious software / virus code, with the possibility of viruses altering the delay time. These factors pose certain risks to the bomb's premature detonation, delayed detonation, and accidental detonation.

[0003] A certain type of high-explosive fragmentation grenade employs a hardware-based time-delay self-destruct circuit. The time-delay function is divided into two types: power-on time-delay self-destruct and power-off time-delay self-destruct. Power-on time-delay self-destruct occurs when the grenade fails to detonate within its set time; the circuit detonates the grenade immediately upon reaching the specified delay time. Similarly, power-off time-delay self-destruct occurs immediately upon reaching the specified delay time after a power outage.

[0004] To address the high reliability, high anti-interference, high-precision delay, and high cost-effectiveness requirements of a certain type of high-explosive fragmentation bomb's self-destruct circuit, while also considering the risks associated with software-programmed delays, the following measures can be taken: Implementing the self-destruct delay function using a circuit composed of a frequency divider chip. This circuit is purely hardware-based, requiring no software programming. The selected components are low-cost and reliable. The delay time can be changed by altering the resistance or capacitance values ​​connected to the frequency divider chip. Once adjusted, the delay time is immutable after encapsulation, making it unaffected by electromagnetic interference and software virus attacks. It features high reliability, high anti-interference, and high-precision delay, ensuring safety. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art. The frequency divider delay circuit can achieve high reliability, high anti-interference, simple circuit structure, and low cost. It can satisfy the requirement of reliable detonation of explosive fragmentation bombs within a certain time window, effectively avoiding dangerous accidents such as accidental detonation and misfires.

[0006] The objective of this invention is achieved through the following technical solution: a hardware delay self-destruct circuit system for a high-explosive fragmentation bomb, comprising a seven-part circuit system, characterized in that: the seven-part circuit system comprises a first part power input circuit, a second part power conversion circuit, a third part power-down switching circuit, a fourth part power-on delay circuit, a fifth part power-down delay circuit, a sixth part ignition trigger circuit, and a seventh part ignition circuit. The first part of the power input circuit includes a filter circuit, a reverse connection protection circuit, a surge absorption circuit, and a reverse current protection circuit. The filter circuit consists of a power input terminal V28, a ferrite bead L2, a capacitor C15, and a capacitor C16. The positive terminal of the power input terminal V28 is connected to the left end of the ferrite bead L2 and the upper end of the capacitor C16. The right end of the ferrite bead L2 is connected to the upper end of the capacitor C15, the upper end of the transient voltage suppression diode D9, and the anode of the rectifier diode D8 (i.e., the reverse current protection diode). The lower ends of the capacitors C16, C15, and D9 are all connected to the negative terminal of the input power supply V28.

[0007] Preferably, the second part of the power conversion circuit includes a step-down power supply chip U3, an output voltage regulator electrolytic capacitor C31, an electrolytic capacitor C32, and an electrolytic capacitor C33. The cathode of the rectifier diode D8 is connected to pin 1 of the step-down power supply chip U3. Pin 3 of the step-down power supply chip U3 is connected to the positive terminals of electrolytic capacitors C31, C32, and C33. Pin 4 of the step-down power supply chip U3, the negative terminals of electrolytic capacitors C31, C32, and C33 are all connected to the negative terminal of the input power supply V28.

[0008] Preferably, the third power-down switching circuit includes an NMOS field-effect transistor driving circuit and an NMOS field-effect transistor switching circuit. The NMOS field-effect transistor driving circuit includes a rectifier diode D7, i.e., a reverse current protection diode. The driving voltage divider resistors R41, R42, and C34 are connected in the following order: the anode of diode D7 is connected to the right end of the ferrite bead L2 in the power input circuit; the cathode of diode D7 is connected to the upper end of resistor R41 and the upper end of capacitor C34; the lower end of resistor R41 and the lower end of capacitor C34 are connected to the upper end of resistor R42 and the gate of the NMOS field-effect transistor, respectively; and the lower end of resistor R42 and the source of the NMOS field-effect transistor are connected to the negative terminal of the input power supply V28.

[0009] Preferably, the fourth power-on delay circuit includes a frequency divider chip U1, a chip peripheral circuit composed of resistors and capacitors, and a self-locking circuit composed of diodes. In the peripheral circuit of the frequency divider chip U1, pin 9 of chip U1 is connected to the right end of capacitor C20; pin 10 of chip U1 is connected to the right end of resistor R31; pin 11 of chip U1 is connected to the right end of resistor R30 and the upper end of capacitor C22; pin 12 of chip U1 is connected to the right end of resistor R32 and the upper end of capacitor C26; and pin 16 of chip U1 is connected to capacitor C2... 6. The lower end of the step-down chip U3 in the power conversion circuit is connected to pin 3. Pin 3 of chip U1 is connected to the left end of resistor R11. Pin 8 of chip U1, the lower end of capacitor C22, the lower end of capacitor C21, and the lower end of resistor R32 are all connected to the negative terminal of the input power supply V28. The left ends of capacitor C20, resistor R31, and resistor R32 are all connected to the upper end of capacitor C21 and the anode of rectifier diode D5 at the same point. The cathode of rectifier diode D5 is connected to the anode of thyristor D11 in the firing trigger circuit, forming a power-on delay self-locking circuit.

[0010] Preferably, the fifth part of the power-down delay circuit includes a frequency divider chip U4, a chip peripheral circuit composed of resistors and capacitors, and a self-locking circuit composed of diodes; wherein, in the peripheral circuit of the frequency divider chip U4, pin 9 of chip U4 is connected to the right end of capacitor C27, pin 10 of chip U4 is connected to the right end of resistor R38, pin 11 of chip U4 is connected to the right end of resistor R37 and the upper end of capacitor C29 respectively, pin 12 of chip U4 is connected to the right end of resistor R39 and the upper end of capacitor C30 respectively, and pin 16 of chip U1 is connected to the lower end of capacitor C30 and the lower end of current-limiting resistor R40 respectively. The upper end of the current-limiting resistor R40 is connected to pin 3 of the step-down chip U3 in the power conversion circuit. Pin 3 of chip U4 is connected to the left end of resistor R36. Pin 8 of chip U4, the lower end of capacitor C29, the lower end of capacitor C28, and the lower end of resistor R39 are all connected to the negative terminal of the input power supply V28. The left ends of capacitor C27, resistor R38, and resistor R37 are all connected to the upper end of capacitor C28. The anode of rectifier diode D6 is connected to a common point. The cathode of rectifier diode D6 is connected to the anode of thyristor D11 in the firing trigger circuit, forming a power-down delay self-locking circuit.

[0011] Preferably, the sixth part of the ignition triggering circuit includes a SCR D11 driving circuit, a SCR D11 switching circuit, and an ignition power input circuit. In the SCR D11 driving circuit, the upper anode of the common-cathode rectifier diode D4 is connected to the right end of R11 in the power-on delay circuit, and the lower anode of the common-cathode rectifier diode D4 is connected to the right end of R36 in the power-off delay circuit. The cathode of the common-cathode rectifier diode D4 is connected to the control electrode of the SCR D11, the upper end of resistor R26, and the upper end of capacitor C18, all sharing a common point. The lower ends of resistor R26, capacitor C18, and the cathode of the SCR D11 are all connected to the negative terminal of the input power supply V28. The SCR D11 switching circuit... In the circuit, resistors R24 and R25 form a voltage divider to drive the PMOS field-effect transistor Q4 in the ignition circuit. The anode of the thyristor D11 is connected to the lower end of resistor R25. The upper end of resistor R25, the lower end of resistor R24, and the gate of PMOS field-effect transistor Q4 are all connected to a single point. The upper end of resistor R24 ​​is connected to the right end of resistor R22. In the ignition power input circuit, the positive terminal of power input V28 is connected to the upper end of resistor R21, the upper end of capacitor C17, and the anode of rectifier diode D10. The lower ends of resistor R21 and capacitor C17 are both connected to the negative terminal of input V28. The cathode of rectifier diode D10 is connected to the left end of resistor R22.

[0012] Preferably, the seventh ignition circuit includes an ignition energy storage circuit and an ignition circuit composed of a PMOS field-effect transistor and an electric detonator. In the ignition energy storage circuit, the positive terminal of the tantalum capacitor C19, the upper end of the resistor R28, the source of the PMOS field-effect transistor Q4, and the right end of the resistor R22 in the ignition trigger circuit are all connected to a single point. In the ignition circuit composed of the PMOS field-effect transistor and the electric detonator, the drain of the PMOS field-effect transistor Q4 is connected to the upper end of the current-limiting resistor R27 and the upper end of the electric detonator analog resistor R29, and the lower end of the current-limiting resistor R27 and the lower end of the electric detonator analog resistor R29 are connected to the negative terminal of the input power supply V28.

[0013] The frequency divider chip used to implement the delay function mainly achieves power-on delay and power-down delay by controlling the oscillation period T=2.2RC of the two frequency divider chips respectively. The oscillation period is determined by the RC value connected to its pin, so the delay time can be changed by changing the RC value. That is, the power-on delay T_up=T*2^N (N is the N-division output terminal), and similarly, the power-down delay T_down=T*2^N (N is the N-division output terminal). The power input circuit, power conversion circuit, power-down switching circuit, ignition trigger circuit, ignition circuit and power-on and power-down delay of this invention together form a delay self-destruct function.

[0014] The present invention has the following advantages: 1. The hardware delay of this invention has high reliability and will not be affected by software virus code attacks that alter the delay time.

[0015] 2. The hardware delay of this invention has strong anti-interference capabilities. It uses a mechanical switch and a delay circuit to form a self-destruct delay, ensuring that it is not subject to electromagnetic interference.

[0016] 3. The hardware delay of this invention has a high cost-performance ratio. The frequency divider chip is cheaper than microcomputer control chips such as ARM / 8051, which is especially evident when the combat demand is tens of thousands of rounds. Attached Figure Description

[0017] Figure 1 This is a circuit structure block diagram of the present invention; Figure 2 This is the circuit schematic diagram of the present invention; Figure 3 This is a power input circuit diagram for the present invention; Figure 4 This is a power conversion circuit diagram of the present invention; Figure 5 This is a power-down switching circuit diagram of the present invention; Figure 6 This is a power-on delay circuit diagram of the present invention; Figure 7 This is a circuit diagram of the power-down delay of the present invention; Figure 8 This is the ignition triggering circuit diagram of the present invention; Figure 9 This is the ignition circuit diagram of the present invention; Figure 10 This is a waveform diagram showing the power-on delay of the present invention; Figure 11 This is a waveform diagram showing the power-down delay of the present invention; Figure 12 The schematic diagram shows the delay circuit of the present invention, which uses a crystal oscillator instead.

[0018] In the diagram, U1 / U2 are frequency divider chips; Q3 is an NMOS field-effect transistor; D11 is a thyristor; and R29 is a detonator analog resistor. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings. The scope of protection of the present invention is not limited to the following description: like Figures 1-12 As shown, a hardware-delayed self-destruct circuit system for a high-explosive fragmentation bomb includes seven circuit parts: a first part power input circuit, a second part power conversion circuit, a third part power-down switching circuit, a fourth part power-on delay circuit, a fifth part power-down delay circuit, a sixth part ignition trigger circuit, and a seventh part ignition circuit. The first part of the power input circuit includes a filter circuit, a reverse connection protection circuit, a surge absorption circuit, and a reverse current protection circuit. The filter circuit consists of a power input terminal V28, a ferrite bead L2, a capacitor C15, and a capacitor C16. The positive terminal of the power input terminal V28 is connected to the left end of the ferrite bead L2 and the upper end of the capacitor C16. The right end of the ferrite bead L2 is connected to the upper end of the capacitor C15, the upper end of the transient voltage suppressor diode D9, and the anode of the rectifier diode D8 (i.e., the reverse current protection diode). The lower ends of the capacitors C16, C15, and D9 are all connected to the negative terminal of the input power supply V28.

[0020] The second part of the power conversion circuit includes a step-down power supply chip U3, output voltage regulator electrolytic capacitors C31, C32, and C33. The cathode of the rectifier diode D8 is connected to pin 1 of the step-down power supply chip U3. Pin 3 of the step-down power supply chip U3 is connected to the positive terminals of electrolytic capacitors C31, C32, and C33. Pin 4 of the step-down power supply chip U3, the negative terminals of electrolytic capacitors C31, C32, and C33 are all connected to the negative terminal of the input power supply V28.

[0021] The third part, the power-down switching circuit, includes an NMOS field-effect transistor (FET) driver circuit and an NMOS FET switching circuit. The NMOS FET driver circuit includes a rectifier diode D7 (i.e., a reverse current protection diode). The driving voltage divider resistors R41, R42, and C34 are connected in the following order: the anode of diode D7 is connected to the right end of the ferrite bead L2 in the power input circuit; the cathode of diode D7 is connected to the upper end of resistor R41 and the upper end of capacitor C34; the lower end of resistor R41 and the lower end of capacitor C34 are connected to the upper end of resistor R42 and the gate of the NMOS FET, respectively; and the lower end of resistor R42 and the source of the NMOS FET are connected to the negative terminal of the input power supply V28.

[0022] The fourth part, the power-on delay circuit, includes a frequency divider chip U1, a chip peripheral circuit consisting of resistors and capacitors, and a self-locking circuit consisting of diodes. In the frequency divider chip U1 peripheral circuit, pin 9 of chip U1 is connected to the right end of capacitor C20; pin 10 of chip U1 is connected to the right end of resistor R31; pin 11 of chip U1 is connected to the right end of resistor R30 and the upper end of capacitor C22; pin 12 of chip U1 is connected to the right end of resistor R32 and the upper end of capacitor C26; and pin 16 of chip U1 is connected to the lower end of capacitor C26. In the power conversion circuit, pin 3 of the step-down chip U3 is connected, pin 3 of chip U1 is connected to the left end of resistor R11, pin 8 of chip U1, the lower end of capacitor C22, the lower end of capacitor C21, and the lower end of resistor R32 are all connected to the negative terminal of the input power supply V28; the left ends of capacitor C20, resistor R31, and resistor R32 are all connected to the upper end of capacitor C21 and the anode of rectifier diode D5 at the same point; the cathode of rectifier diode D5 is connected to the anode of thyristor D11 in the firing trigger circuit, forming a power-on delay self-locking circuit.

[0023] The fifth part, the power-down delay circuit, includes a frequency divider chip U4, a chip peripheral circuit consisting of resistors and capacitors, and a self-locking circuit consisting of diodes. In the frequency divider chip U4 peripheral circuit, pin 9 of chip U4 is connected to the right end of capacitor C27; pin 10 of chip U4 is connected to the right end of resistor R38; pin 11 of chip U4 is connected to the right end of resistor R37 and the upper end of capacitor C29; pin 12 of chip U4 is connected to the right end of resistor R39 and the upper end of capacitor C30; and pin 16 of chip U4 is connected to the lower end of capacitor C30 and the lower end of current-limiting resistor R40. Connect the upper end of the current-limiting resistor R40 to pin 3 of the step-down chip U3 in the power conversion circuit. Connect pin 3 of chip U4 to the left end of resistor R36. Connect pin 8 of chip U4, the lower end of capacitor C29, the lower end of capacitor C28, and the lower end of resistor R39 to the negative terminal of input power supply V28. Connect the left ends of capacitor C27, resistor R38, and resistor R37 to the upper end of capacitor C28. Connect the anode of rectifier diode D6 to a common point. Connect the cathode of rectifier diode D6 to the anode of thyristor D11 in the firing trigger circuit, thus forming a power-down delay self-locking circuit.

[0024] Part VI, the ignition trigger circuit, includes a SCR D11 driver circuit, a SCR D11 switching circuit, and an ignition power input circuit. In the SCR D11 driver circuit, the upper anode of the common-cathode rectifier diode D4 is connected to the right end of resistor R11 in the power-on delay circuit, and the lower anode of the common-cathode rectifier diode D4 is connected to the right end of resistor R36 in the power-off delay circuit. The cathode of the common-cathode rectifier diode D4 is connected to the control electrode of the SCR D11, the upper end of resistor R26, and the upper end of capacitor C18, all sharing a common point. The lower ends of resistor R26, capacitor C18, and the cathode of the SCR D11 are all connected to the negative terminal of the input power supply V28. The SCR D11 switching circuit... In the ignition circuit, resistors R24 and R25 form a voltage divider to drive the PMOS field-effect transistor Q4. The anode of the thyristor D11 is connected to the lower end of resistor R25. The upper end of resistor R25, the lower end of resistor R24, and the gate of PMOS field-effect transistor Q4 are all connected to a single point. The upper end of resistor R24 ​​is connected to the right end of resistor R22. In the ignition power input circuit, the positive terminal of power input V28 is connected to the upper end of resistor R21, the upper end of capacitor C17, and the anode of rectifier diode D10. The lower ends of resistor R21 and capacitor C17 are both connected to the negative terminal of input V28. The cathode of rectifier diode D10 is connected to the left end of resistor R22.

[0025] The seventh part, the ignition circuit, includes an ignition energy storage circuit and an ignition circuit composed of a PMOS field-effect transistor and an electric detonator. In the ignition energy storage circuit, the positive terminal of tantalum capacitor C19, the upper end of resistor R28, the source of PMOS field-effect transistor Q4, and the right end of resistor R22 in the ignition trigger circuit are all connected to a single point. In the ignition circuit composed of PMOS field-effect transistor and electric detonator, the drain of PMOS field-effect transistor Q4 is connected to the upper end of current-limiting resistor R27 and the upper end of electric detonator analog resistor R29. The lower end of current-limiting resistor R27 and the lower end of electric detonator analog resistor R29 are connected to the negative terminal of input power supply V28.

[0026] The working principle of this invention is as follows: It mainly achieves power-on delay and power-down delay by controlling the oscillation period T=2.2RC of two frequency divider chips respectively. The oscillation period is determined by the RC value connected to its pins (or a crystal oscillator can be used to achieve high-precision delay). Therefore, the delay time can be changed by altering the RC value. When using a crystal oscillator, the power-on delay T_up=(2^N) / (f_osc) (where N is the coefficient corresponding to the N-division output terminal, and f_osc is the crystal oscillator frequency). Similarly, the power-down delay T_down=(2^N) / (f_osc) (where N is the coefficient corresponding to the N-division output terminal, and f_osc is the crystal oscillator frequency). The delay circuit principle using a crystal oscillator is as follows: Figure 12 As shown, with Figure 2 The difference in the circuit schematic lies in the vibration pins 9, 10, and 11 of the frequency divider chip within the dashed box; the rest are the same. Figure 2Circuit schematic diagram; the power input circuit, power conversion circuit, power-down switching circuit, ignition trigger circuit, ignition circuit, and power-on / power-off delay of this invention together constitute a time-delay self-destruct function. Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hardware-delayed self-destruct circuit system for a high-explosive fragmentation bomb, comprising a seven-part circuit system, characterized in that: The seven-part circuit system includes a first part power input circuit, a second part power conversion circuit, a third part power-down switching circuit, a fourth part power-on delay circuit, a fifth part power-down delay circuit, a sixth part ignition trigger circuit, and a seventh part ignition circuit. The first part of the power input circuit includes a filter circuit, a reverse connection protection circuit, a surge absorption circuit, and a reverse current protection circuit. The filter circuit consists of a power input terminal V28, a ferrite bead L2, a capacitor C15, and a capacitor C16. The positive terminal of the power input terminal V28 is connected to the left end of the ferrite bead L2 and the upper end of the capacitor C16. The right end of the ferrite bead L2 is connected to the upper end of the capacitor C15, the upper end of the transient voltage suppression diode D9, and the anode of the rectifier diode D8 (i.e., the reverse current protection diode). The lower ends of the capacitors C16, C15, and D9 are all connected to the negative terminal of the input power supply V28.

2. The hardware delay self-destruct circuit system for a high-explosive fragmentation bomb according to claim 1, characterized in that: The second part of the power conversion circuit includes a step-down power supply chip U3, an output voltage regulator electrolytic capacitor C31, an electrolytic capacitor C32, and an electrolytic capacitor C33. The cathode of the rectifier diode D8 is connected to pin 1 of the step-down power supply chip U3. Pin 3 of the step-down power supply chip U3 is connected to the positive terminals of electrolytic capacitors C31, C32, and C33. Pin 4 of the step-down power supply chip U3, the negative terminals of electrolytic capacitors C31, C32, and C33 are all connected to the negative terminal of the input power supply V28.

3. The hardware delay self-destruct circuit system for a high-explosive fragmentation bomb according to claim 1, characterized in that: The third part of the power-down switching circuit includes an NMOS field-effect transistor driving circuit and an NMOS field-effect transistor switching circuit. The NMOS field-effect transistor driving circuit includes a rectifier diode D7, i.e., a reverse current protection diode. The driving voltage divider resistors R41, R42, and C34 are connected in the following order: the anode of diode D7 is connected to the right end of the ferrite bead L2 in the power input circuit; the cathode of diode D7 is connected to the upper end of resistor R41 and the upper end of capacitor C34; the lower end of resistor R41 and the lower end of capacitor C34 are connected to the upper end of resistor R42 and the gate of the NMOS field-effect transistor, respectively; and the lower end of resistor R42 and the source of the NMOS field-effect transistor are connected to the negative terminal of the input power supply V28.

4. The hardware delay self-destruct circuit system for a high-explosive fragmentation bomb according to claim 1, characterized in that: The fourth part, the power-on delay circuit, includes a frequency divider chip U1, a chip peripheral circuit composed of resistors and capacitors, and a self-locking circuit composed of diodes. In the peripheral circuit of the frequency divider chip U1, pin 9 of chip U1 is connected to the right end of capacitor C20; pin 10 of chip U1 is connected to the right end of resistor R31; pin 11 of chip U1 is connected to the right end of resistor R30 and the upper end of capacitor C22; pin 12 of chip U1 is connected to the right end of resistor R32 and the upper end of capacitor C26; and pin 16 of chip U1 is connected to the lower end of capacitor C26. Pin 3 of the step-down chip U3 in the power conversion circuit is connected. Pin 3 of chip U1 is connected to the left end of resistor R11. Pin 8 of chip U1, the lower end of capacitor C22, the lower end of capacitor C21, and the lower end of resistor R32 are all connected to the negative terminal of input power supply V28. The left ends of capacitor C20, resistor R31, and resistor R32 are all connected to the upper end of capacitor C21 and the anode of rectifier diode D5 at the same point. The cathode of rectifier diode D5 is connected to the anode of thyristor D11 in the firing trigger circuit, forming a power-on delay self-locking circuit.

5. The hardware delay self-destruct circuit system for a high-explosive fragmentation bomb according to claim 1, characterized in that: The fifth part, the power-down delay circuit, includes a frequency divider chip U4, a chip peripheral circuit consisting of resistors and capacitors, and a self-locking circuit consisting of diodes. In the frequency divider chip U4 peripheral circuit, pin 9 of chip U4 is connected to the right end of capacitor C27; pin 10 of chip U4 is connected to the right end of resistor R38; pin 11 of chip U4 is connected to the right end of resistor R37 and the upper end of capacitor C29; pin 12 of chip U4 is connected to the right end of resistor R39 and the upper end of capacitor C30; and pin 16 of chip U4 is connected to the lower end of capacitor C30 and the lower end of current-limiting resistor R40. Connect the upper end of the current-limiting resistor R40 to pin 3 of the step-down chip U3 in the power conversion circuit. Connect pin 3 of chip U4 to the left end of resistor R36. Connect pin 8 of chip U4, the lower end of capacitor C29, the lower end of capacitor C28, and the lower end of resistor R39 to the negative terminal of input power supply V28. Connect the left ends of capacitor C27, resistor R38, and resistor R37 to the upper end of capacitor C28. Connect the anode of rectifier diode D6 to a common point. Connect the cathode of rectifier diode D6 to the anode of thyristor D11 in the firing trigger circuit, thus forming a power-down delay self-locking circuit.

6. The hardware delay self-destruct circuit system for a high-explosive fragmentation bomb according to claim 1, characterized in that: Part VI, the ignition trigger circuit, includes a SCR D11 driver circuit, a SCR D11 switching circuit, and an ignition power input circuit. In the SCR D11 driver circuit, the upper anode of the common-cathode rectifier diode D4 is connected to the right end of resistor R11 in the power-on delay circuit, and the lower anode of the common-cathode rectifier diode D4 is connected to the right end of resistor R36 in the power-off delay circuit. The cathode of the common-cathode rectifier diode D4 is connected to the control electrode of the SCR D11, the upper end of resistor R26, and the upper end of capacitor C18, all sharing a common point. The lower ends of resistor R26, capacitor C18, and the cathode of the SCR D11 are all connected to the negative terminal of the input power supply V28. In the SCR D11 switching circuit... The circuit consists of voltage divider resistors R24 and R25, used to drive the PMOS field-effect transistor Q4 in the ignition circuit. The anode of the thyristor D11 is connected to the lower end of resistor R25. The upper end of resistor R25, the lower end of resistor R24, and the gate of PMOS field-effect transistor Q4 are all connected to a single point. The upper end of resistor R24 ​​is connected to the right end of resistor R22. In the ignition power input circuit, the positive terminal of power input V28 is connected to the upper end of resistor R21, the upper end of capacitor C17, and the anode of rectifier diode D10. The lower ends of resistor R21 and capacitor C17 are both connected to the negative terminal of input V28. The cathode of rectifier diode D10 is connected to the left end of resistor R22.

7. The hardware delay self-destruct circuit system for a high-explosive fragmentation bomb according to claim 1, characterized in that: The seventh part, the ignition circuit, includes an ignition energy storage circuit and an ignition circuit composed of a PMOS field-effect transistor and an electric detonator. In the ignition energy storage circuit, the positive terminal of tantalum capacitor C19, the upper end of resistor R28, the source of PMOS field-effect transistor Q4, and the right end of resistor R22 in the ignition trigger circuit are all connected to a single point. In the ignition circuit composed of PMOS field-effect transistor and electric detonator, the drain of PMOS field-effect transistor Q4 is connected to the upper end of current-limiting resistor R27 and the upper end of electric detonator analog resistor R29. The lower end of current-limiting resistor R27 and the lower end of electric detonator analog resistor R29 are connected to the negative terminal of input power supply V28.

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