Implementation method and device of multi-protocol bus interface based on programmable system on chip, computer device and medium

By building a multi-protocol bus interface on a programmable system-on-a-chip (SoC), the problem of low development efficiency of high-speed bus computing systems is solved, realizing an efficient and flexible hardware platform that can adapt to diverse application scenarios and reduce costs and power consumption.

CN122173434APending Publication Date: 2026-06-09INST OF ENGINEERING THERMOPHYSICS - CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
INST OF ENGINEERING THERMOPHYSICS - CHINESE ACAD OF SCI
Filing Date
2026-02-25
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

Existing high-speed bus computing systems are inefficient to develop and have high costs, especially in high-end fields such as aerospace and high-performance computing, where development is difficult and standardization is insufficient.

Method used

By using a programmable system-on-a-chip (SoC) chip, a minimal hardware platform is built by configuring the power supply voltage for the programmable logic, constructing a multi-protocol bus interface IP core, and running an embedded operating system in the processor system to establish a hardware-software co-processing architecture and dynamically switch the bus interface IP core.

Benefits of technology

It realizes a highly versatile and scalable hardware platform for heterogeneous computing systems, reduces material costs and power consumption, improves system flexibility and real-time performance, and meets the requirements for high reliability and multi-protocol communication.

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Abstract

This invention provides a method, apparatus, computer device, and medium for implementing a multi-protocol bus interface based on a programmable system-on-a-chip (SoC). The method includes the following steps: building a minimal hardware platform based on a SoC chip containing a processor system and programmable logic, and configuring external memory for the processor system; configuring the processor system's boot process; constructing bus interface IP cores for at least two different communication protocols using a hardware description language and deploying protocol stack drivers; establishing data and control paths through the SoC chip's on-chip high-speed interconnect bus to form a hardware-software co-processing architecture; and dynamically reconfiguring the programmable logic through the processor system, time-sharing or switching the execution of different bus interface IP cores. This invention provides a highly general and scalable hardware platform paradigm for the application of heterogeneous computing systems in the embedded field.
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