Hbf chip interconnection method and apparatus based on cb a bonding

Abstract

The application relates to the field of chip interconnection, in particular to a HBF chip interconnection method and device based on CBA bonding. The method comprises the following steps: performing topology scanning on a chip design graph to generate an initial bus data set; performing bus interconnection synthesis bonding according to the initial bus data set to obtain a bus interconnection path graph; performing cross-layer bus signal synchronous modulation based on the bus interconnection path graph to obtain a timing coordination parameter set; performing routing scheduling according to the timing coordination parameter set to construct a multi-channel transmission bus network; and performing bonding parameter fine tuning and multi-round structure reconstruction simulation according to the multi-channel transmission bus network to output a chip production structure template. The application realizes low delay, high throughput and high synchronization of the chip, and improves bus synchronization and structure optimization efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip interconnection, and more particularly to an HBF chip interconnection method and apparatus based on CBA bonding. Background Technology

[0002] With the rapid development of information technology, HBF chips (high-speed flash memory chips) are playing an increasingly important role in computer systems, servers, mobile devices, and fields such as artificial intelligence and big data processing. Especially against the backdrop of ever-increasing demands for high-bandwidth data transmission and high-speed storage, the performance bottlenecks and interconnect efficiency of flash memory chips, as core storage units, directly affect the throughput and reliability of the entire storage system. To meet the demands of modern applications for high-performance, high-reliability, and low-latency storage, the internal bus structure and interconnect design of flash memory chips have become key technological aspects for improving overall performance.

[0003] Traditional flash memory chip bus interconnects often employ single-channel or simple multi-channel routing, relying primarily on empirical optimization of module layout and static routing rules. While these methods meet basic requirements in low-speed or low-to-medium bandwidth applications, the traditional bus architecture faces severe performance and reliability limitations as flash memory read / write frequencies and bus parallelism increase. For example, single-channel buses are prone to causing transmission bottlenecks, and multi-channel buses lack efficient synchronization control, leading to signal crosstalk, latency inconsistencies, and increased power consumption. Furthermore, physical layout constraints under complex chip manufacturing processes make it difficult to balance signal integrity, timing coordination, and power consumption control in high-bandwidth bus design. Existing interconnect optimization methods largely depend on static simulation or simple bus path planning, lacking comprehensive analysis capabilities for CBA (Core Bus Architecture) and cross-layer signal synchronization. This limitation results in potential performance bottlenecks and reliability risks for flash memory chips operating under high bandwidth conditions, hindering truly efficient multi-channel transmission. Simultaneously, with increasing chip integration and bus network complexity, traditional methods lack the efficiency and accuracy required for routing scheduling, bus synchronization, and structural optimization, failing to meet the design requirements of next-generation high-performance flash memory chips. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes an HBF chip interconnection method and apparatus based on CBA bonding, thereby resolving at least one of the aforementioned technical problems.

[0005] To achieve the above objectives, the present invention provides an HBF chip interconnection method based on CBA bonding, comprising the following steps: Perform a topology scan on the chip design to generate an initial bus dataset; Based on the initial bus dataset, bus interconnect synthesis and bonding are performed to obtain the bus interconnect path diagram; Based on the bus interconnection path diagram, cross-layer bus signal synchronization modulation is performed to obtain a timing coordination parameter set; Routing scheduling is performed based on the timing coordination parameter set to construct a multi-channel transmission bus network; Based on the multi-channel transmission bus network, bonding parameter fine-tuning and multi-round structural reconstruction simulation are performed to output the chip production structure template.

[0006] This specification provides an HBF chip interconnect device based on CBA bonding for performing the HBF chip interconnect method based on CBA bonding as described above, including: The bus scanning module is used to perform topology scanning on the chip design diagram and generate an initial bus dataset. The interconnect synthesis and bonding module is used to perform bus interconnect synthesis and bonding based on the initial bus dataset to obtain the bus interconnect path diagram. The signal synchronization modulation module is used to perform cross-layer bus signal synchronization modulation based on the bus interconnection path diagram to obtain a timing coordination parameter set. The routing scheduling module is used to perform routing scheduling based on the timing coordination parameter set and to build a multi-channel transmission bus network. The reconstruction simulation module is used to perform bonding parameter fine-tuning and multi-round structural reconstruction simulation based on the multi-channel transmission bus network, and output the chip production structure template.

[0007] The beneficial effects of this invention are as follows: Through topology scanning, the physical connections between logic units, memory units, and control units within a chip can be quickly identified, generating an intuitive initial bus dataset. This mapping model accurately reflects the bus hierarchy, node density, and interconnect dependencies, providing a data foundation for subsequent interconnect synthesis. Topology scanning allows the system to identify module interfaces with different manufacturing processes and electrical characteristics, improving the compatibility and accuracy of subsequent synthesis and bonding. Automatically generating the initial bus dataset significantly reduces human error compared to manual drawing or configuration, improving design iteration efficiency. Synthesis bonding of the initial mapping model automatically selects the optimal interconnect path and signal convergence method, thereby reducing routing complexity. The path diagram optimizes the bus topology while considering resistance, capacitance, and delay characteristics, improving overall bandwidth utilization. The generated bus interconnect path diagram can serve as a standardized structural template, facilitating reuse and rapid migration of different flash memory modules. Path-level bonding optimization allows for reasonable planning of physical distances and routing levels between different buses, suppressing crosstalk and electromagnetic interference. Signal integrity simulation can identify potential issues such as reflections, crosstalk, and impedance mismatches in high-speed transmission in advance, and correct them through modulation optimization. Synchronous modulation across different metal layers or modules effectively coordinates delay differences in cross-layer signals, ensuring consistency in the timing of high-frequency data. The resulting timing coordination parameter set provides fundamental data for routing planning, clock allocation, and synchronization signal control. Multi-channel signal synchronous modulation significantly improves the signal quality and transmission accuracy of high-speed interfaces (such as DDR, GDDR, HBM, etc.). Scheduling based on timing coordination parameters enables multi-channel parallel data transmission while maintaining synchronization, significantly increasing bus network bandwidth. The routing scheduling mechanism automatically generates multi-layer interconnect paths that meet timing and load constraints, achieving efficient interoperability between multiple modules. Channel load balancing and signal isolation design are considered during routing scheduling to reduce the risk of mutual interference during multi-bus parallel transmission. Through multiple rounds of simulation and fine-tuning, the system can progressively optimize bus bonding parameters (such as line width, line spacing, and via size) to improve signal stability. The output production structure template can be directly used in chip manufacturing, ensuring high consistency between design data and physical manufacturing. By completing structural reconfiguration simulations during the design phase, interconnect performance and manufacturing process compatibility can be verified in advance, reducing the number of subsequent prototype corrections. The optimized bus structure template can achieve low latency, high throughput, and high synchronization interconnect characteristics, meeting the high-speed data interaction requirements of next-generation high-bandwidth flash memory. Attached Figure Description

[0008] Figure 1 This is a schematic flowchart illustrating the steps of an HBF chip interconnection method based on CBA bonding according to the present invention. Detailed Implementation

[0009] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0010] This application provides a method and apparatus for HBF chip interconnection based on CBA bonding. The execution entities of the HBF chip interconnection method and apparatus based on CBA bonding include, but are not limited to, mechanical equipment, data processing platforms, cloud server nodes, network upload devices, etc., which can be considered as general computing nodes in this application. The data processing platform includes, but is not limited to, at least one of an audio / image management system, an information management system, and a cloud data management system.

[0011] Please see Figure 1 This invention provides an HBF chip interconnection method based on CBA bonding, comprising the following steps: Perform a topology scan on the chip design to generate an initial bus dataset; Based on the initial bus dataset, bus interconnect synthesis and bonding are performed to obtain the bus interconnect path diagram; Based on the bus interconnection path diagram, cross-layer bus signal synchronization modulation is performed to obtain a timing coordination parameter set; Routing scheduling is performed based on the timing coordination parameter set to construct a multi-channel transmission bus network; Based on the multi-channel transmission bus network, bonding parameter fine-tuning and multi-round structural reconstruction simulation are performed to output the chip production structure template.

[0012] In the embodiments of the present invention, see Figure 1 The diagram below illustrates the steps of an HBF chip interconnection method based on CBA bonding according to the present invention. In this example, the steps of the HBF chip interconnection method based on CBA bonding include: Perform a topology scan on the chip design to generate an initial bus dataset; In this embodiment, during the initial structural design of the high-bandwidth flash memory chip, a topology scan is performed inside the chip to obtain the spatial distribution characteristics of the core bus and establish an initial mapping model. First, multi-dimensional scanning technology is used to perform layer-by-layer probing of the chip, including areas such as the control and scheduling layer, data exchange layer, and physical interface layer. During the scanning process, electromagnetic response imaging, optical reflectance measurement, and surface displacement detection are comprehensively utilized to capture the geometric structure data and conductive path distribution of each layer inside the chip. After spatial registration and geometric correction, the collected data generates three-dimensional dot matrix information containing bus nodes, trace directions, and inter-layer connection relationships.

[0013] Subsequently, topology analysis algorithms were used to reconstruct the interconnection relationships between nodes, mapping the sampled data into a logically connected graph. By comparing the electrical characteristics, on-resistance, and spatial distance of bus nodes, the relative layout of trunk and branch paths was identified. Finally, based on the comprehensive geometric distribution and signal channel attributes, an initial bus dataset was generated. This model accurately describes the structural topology and interconnection logic of the chip's core bus, providing a basic spatial data framework for subsequent synthesis, bonding, and signal simulation. This process realizes the mapping from physical form to topology and is the starting point for multilayer interconnect modeling.

[0014] Based on the initial bus dataset, bus interconnect synthesis and bonding are performed to obtain the bus interconnect path diagram; In this embodiment, after establishing the initial bus dataset, interconnect synthesis and bonding are performed on the multi-layer bus structure to achieve unification of the logic bus and physical conduction paths. Based on the node relationships and hierarchical distribution in the mapping model, the interconnection strategy between different layers of the bus is determined. By analyzing the distance between nodes, trace direction, and conductive material characteristics, an optimal matching scheme for the interconnection paths is established. During the synthesis and bonding process, multiple factors such as signal transmission distance, linewidth ratio, inter-layer alignment, and solder ball layout are considered to ensure minimal conduction impedance and signal loss between each path.

[0015] Subsequently, multi-layer path alignment fitting is performed in the bonding region to physically overlap the trunk bus and branch buses. Through thermoforming and geometric micro-alignment, precise bonding of the multi-layer interconnect structure in three-dimensional space is achieved. After bonding, path tracing and electrical connectivity verification methods are used to generate a complete bus interconnect path diagram. This path diagram clearly identifies the signal flow, node positions, and jumper relationships within the chip's multi-layer structure, establishing the physical channel foundation for subsequent signal transmission simulation and timing modulation, and enabling a visual representation of bus logic relationships at the structural level.

[0016] Based on the bus interconnection path diagram, cross-layer bus signal synchronization modulation is performed to obtain a timing coordination parameter set; In this embodiment, after obtaining the bus interconnection path diagram, the integrity of chip signal transmission is simulated, and signal timing coordination is achieved through cross-layer synchronous modulation. First, a signal transmission simulation model is established based on the geometric dimensions, dielectric constant, conductor resistance, and inter-layer coupling information in the interconnection path. The propagation, reflection, and attenuation characteristics of signals in multi-layer paths are simulated using time-domain and frequency-domain analysis methods to evaluate signal integrity. For delay differences and waveform distortion phenomena in different paths, time-domain alignment and phase-matching algorithms are used for correction to achieve cross-layer signal synchronization.

[0017] Subsequently, based on the synchronization results, the delay, phase difference, and waveform stability of each layer's signals are extracted to generate a timing coordination parameter set. This parameter set includes information such as signal arrival time, delay compensation, and synchronization correction coefficients, which guide subsequent routing scheduling and multi-channel construction. Through this process, the signal transmission of the chip's multi-layer interconnect structure achieves coordination and consistency in the time dimension, eliminating inter-layer timing offset issues and providing a fundamental guarantee for the signal consistency of high-bandwidth flash memory chips under high-speed communication conditions.

[0018] Routing scheduling is performed based on the timing coordination parameter set to construct a multi-channel transmission bus network; In this embodiment, after generating the timing coordination parameter set, the chip's bus network is routed and scheduled to construct a multi-channel parallel transmission structure. First, based on the delay compensation data and bandwidth requirements of each signal path, the backbone and branch paths are logically allocated, dividing signal traffic into different channels according to priority. A path optimization algorithm is used to adjust the signal transmission route in space, avoiding interconnection bottlenecks and path crossing interference. During the routing and scheduling process, bandwidth utilization, delay balance, and signal energy distribution are comprehensively considered to achieve load balancing for multi-path parallel transmission.

[0019] After path allocation, signal flow simulation was performed on the multi-channel structure to verify timing synchronization and data transmission consistency between paths. If delay deviations or signal congestion occur on some paths, transmission parameters are adjusted in real time through a dynamic bandwidth allocation mechanism. The final constructed multi-channel transmission bus network possesses high parallelism and high fault tolerance, enabling simultaneous transmission of multiple data streams under high bandwidth conditions. This network structure enables unified scheduling of the chip's core bus at both the physical and logical levels, laying the foundation for subsequent structural optimization and bonding parameter adjustment.

[0020] Based on the multi-channel transmission bus network, bonding parameter fine-tuning and multi-round structural reconstruction simulation are performed to output the chip production structure template.

[0021] In this embodiment, after constructing a multi-channel transmission bus network, the chip structure undergoes fine-tuning of bonding parameters and multiple rounds of structural reconstruction simulation to achieve the final production template output. First, parameters are fine-tuned for key nodes and high-load areas in the network, adjusting bonding pressure, solder ball size, heating rate, and cooling curve to achieve a more balanced interlayer stress distribution. Then, the adjusted parameters are input into the structural simulation model for multiple rounds of reconstruction simulation to comprehensively evaluate the structure's conductivity, thermal stability, and signal transmission consistency.

[0022] Through successive optimization rounds, the structural scheme with the lowest stress, lowest signal distortion rate, and optimal bonding strength was selected. The final optimal bonding structure maintains high-density interconnection while ensuring high-speed and stable bus transmission. Based on the final simulation results, the structural parameters, welding layout, material properties, and interconnect topology data were compiled to generate a chip manufacturing structure template. This template contains all key manufacturing parameters and inter-layer interconnection information and can be directly used in the chip manufacturing process, realizing a closed-loop transformation from structural design to production implementation, ensuring that high-bandwidth flash memory chips maintain stable signal performance and structural reliability under mass production conditions.

[0023] In this embodiment, the specific steps for performing topology scanning and probing on the chip to generate the initial bus dataset are as follows: Perform topology scanning and probing on the chip design diagram to extract core bus layout data, including the control and scheduling layer, data exchange layer, and physical interface layer; Based on the core bus layout data, the thickness, spacing, and alignment of each layer are calculated to obtain the basic information of the multi-layer structure; Identify bus routing paths and convergence nodes based on core bus layout data; perform inter-layer stacking analysis and fitting based on multi-layer structure basic information, bus routing paths and convergence nodes to generate a bus node topology matrix; An initial bus dataset is generated by performing correlation fitting based on the bus node topology matrix.

[0024] In this embodiment, when performing topology scanning on the chip, the target chip sample first needs to be depackaged and have its surface layer removed to expose the structural features of the core interconnect region. High-resolution multidimensional scanning technology is used to acquire structural image information of the chip's control and scheduling layer, data exchange layer, and physical interface layer. Electron beam and ion beam combined imaging is used at different tilt angles to perform interlayer perspective, obtaining three-dimensional layered structural data. After digital conversion, the scanned image information is used to distinguish features of the metal interconnect region, dielectric material region, and silicon substrate using a grayscale partitioning algorithm. Image enhancement and edge detection methods are used to identify the interconnect contours of each layer, and morphological filtering and region growing algorithms are combined to extract the geometric boundaries of bus traces and nodes. The obtained image set is then subjected to coordinate unification and spatial calibration, converting the data of each layer into a three-dimensional point cloud format to form a spatial distribution model of the core bus layout. Subsequently, based on pixel grayscale differences and electrical feature partitioning, the logic connection lines of the control and scheduling layer, the signal transmission lines of the data exchange layer, and the input / output paths of the physical interface layer are extracted to obtain complete core bus layout data, providing a basic topology framework for subsequent geometric feature extraction and stacking analysis. After acquiring the core bus layout data, the thickness, spacing, and alignment of the multi-layer structure are calculated using a geometric feature analysis algorithm. First, based on a 3D point cloud dataset, the reference plane position of each layer is determined using a least-squares plane fitting method, and the average height of each layer is calculated. The interlayer thickness is obtained from the distance difference between adjacent layer planes, and geometric corrections are applied to offsets caused by scanning tilt angles and material refraction. The interlayer spacing is evaluated using a combination of multi-point ranging and plane differencing to ensure that the mean square error of each measurement point remains within the nanometer range. Subsequently, a coordinate registration algorithm projects each layer onto the same reference coordinate system, calculating the overlap and offset angle of corresponding nodes in the XY plane direction, thus obtaining the interlayer alignment deviation. The alignment analysis results are recorded in vector form, describing the relationship between the angle difference and linear offset of traces in multi-layer stacking.

[0025] Based on the extracted core bus layout data, the routing paths and convergence nodes of each bus layer are identified and labeled. First, the interconnection routing of each layer is transformed into a graph theory structure model, defining each wire intersection point as a node and the wire segment between two nodes as an edge. By traversing the connection relationships, an initial topology graph structure for each layer is established. A path tracing algorithm is used to search for connected paths between the master control node of the control and scheduling layer and the terminal nodes of the physical interface layer, thereby identifying the main signal channels of the data exchange layer. To distinguish between valid interconnections and invalid segments, the connectivity weights between nodes are filtered based on the matching principles of geometric continuity and conduction characteristics. Convergence node identification is achieved through a comprehensive analysis of node degree and local density. When the number of connected edges in a certain area exceeds a threshold and the spatial distance is concentrated, that area is identified as a bus convergence node. After identification, a node index table and a path connectivity matrix are established to quantitatively describe the topological relationships between routing paths of each layer, providing basic node references and interconnection weight information for inter-layer stacking resolution.

[0026] After completing the calculation of multi-layer geometric parameters and path node identification, the stacking relationship between the control scheduling layer, data exchange layer, and physical interface layer is analyzed and fitted. First, using the control scheduling layer as the reference coordinate system, coordinate translation and rotation transformations are performed on other layers to achieve precise alignment in three-dimensional space. The Iterative Closest Point Registration (ICP) algorithm is used to match the point cloud data of each layer, and the optimal registration matrix is ​​obtained through error minimization iteration, thereby eliminating deviations when multiple layers are stacked. After registration, spatial overlap analysis is performed on the inter-layer routing to identify cross-layer connection areas and vertical interconnection points. The correspondence between nodes in the layers is calculated using a spatial matching function to generate a node mapping table. Based on the geometric distance between nodes, coupling area, and signal transmission path length, a multi-layer interconnection weight matrix is ​​constructed. After obtaining the bus node topology matrix, an initial bus dataset is established using an association fitting method. First, clustering and principal component decomposition are performed on the node relationships in the matrix to map the high-dimensional information of the multi-layer interconnection structure to a low-dimensional space to extract key interconnection features. Through multivariate linear fitting and weighted correlation analysis, the signal mapping rules between the control scheduling layer and the data exchange layer, as well as the priority distribution of inter-layer paths, are determined. Feature aggregation is performed on node pairs with high connection strength in the topology matrix to establish a main data path model. Furthermore, the latency, interference, and bandwidth weights of each path are calculated using a fitting function to achieve the correlation mapping between the functional layer and the physical layer. Finally, the fitting results are transformed into an initial bus dataset, and the model defines the logical correspondence, interconnection direction, and coupling hierarchy among nodes. This mapping model can be used to guide the subsequent multilayer interconnection optimization and structural bonding design of high-bandwidth flash memory chips, achieving efficient bus structure layout and structural-level mapping of signal transmission paths.

[0027] In this embodiment, the specific steps for generating the initial bus dataset by performing correlation fitting based on the bus node topology matrix are as follows: Perform inter-node coupling analysis on the bus node topology matrix to generate multi-node coupling strength; Perform trace type analysis based on bus trace paths, and mark the main bus and branch buses; Logical association analysis is performed on the main bus and branch buses to generate routing topology logical relationships; Based on the logical relationship of the routing topology and the coupling strength of multiple nodes, a nonlinear fitting is performed to generate an initial bus dataset.

[0028] In this embodiment, after obtaining the bus node topology matrix, a detailed coupling analysis of the connection characteristics between each node is required to form a quantitative description of the multi-node interconnection relationship. First, based on the spatial location of each node in the matrix, the signal transmission path length, and the contact or overlapping areas of metal wires, a coupling weight relationship between nodes is established. By comprehensively calculating parameters such as the distance between nodes, connection width, medium characteristics, and signal transmission delay, the coupling strength between different nodes is determined. To avoid data errors caused by local geometric distortions, a normalization method is used to unify the coupling weights to the same dimension range for subsequent analysis. Next, matrix clustering and eigenvalue decomposition methods are used to group and identify the coupling weights between nodes, grouping nodes with high coupling strength and dense connections into the same highly correlated region, forming coupling clusters. For nodes with weak coupling or unstable boundaries, threshold filtering can be used to extract representative and stable interconnection paths. The resulting multi-node coupling strength matrix reflects the energy distribution characteristics and signal coupling relationships of the bus network in the structural space, providing a quantitative basis for subsequent routing logic classification and mapping. After obtaining multi-node coupling information, the bus routing paths are analyzed to identify backbone buses and branch buses. First, a complete path tracing model is constructed based on the connection relationships of each node in the core bus layout data. The importance of each path in the entire interconnect network is analyzed by calculating its length, number of nodes, and average coupling strength along the path. If a path passes through a high proportion of highly coupled nodes and has high connectivity and signal transmission centrality in the network, it is defined as a backbone bus. Backbone buses are typically spatially continuous, with wide traces, and their connection range covers multiple functional areas.

[0029] In contrast, shorter branches derived from the main trunk or paths connecting only a few local nodes are labeled as branch buses. Branch buses typically have more inflection points, are shorter in length, and have relatively limited signal flow. By classifying and labeling all paths, a trunk-branch structure mapping table can be formed, recording the start and end points of each branch, its associated trunk, and its average coupling weight. After this step, the hierarchical structure and functional distribution of the entire bus network are clearly defined, providing a basic classification reference for constructing subsequent logical relationships.

[0030] After classifying the bus types, the logical relationships between the backbone bus and branch buses are analyzed in depth. First, the backbone bus is used as the central path, and the branch buses directly connected to it are established as directed connection nodes, thus constructing a logical network. By traversing the directionality of the paths and the hierarchical relationships of the nodes, the logical order and priority of signal transmission from the backbone to the branches are analyzed. Next, logical attribute labels are established based on the functional roles of each trace at the logical level, such as data transmission, clock synchronization, or control command allocation. Based on this, the degree of logical coupling between the backbone and branches is calculated, and their dependency relationships in signal scheduling are determined.

[0031] When multiple branch buses are attached to the same main path, the logical hierarchy of each branch is determined by comparing signal direction and delay path. For intersecting or overlapping routing areas, a logical constraint matching method is used to determine the main transmission direction to avoid logical aliasing. The final generated routing topology logic table clearly shows the logical connection mode, signal flow, and scheduling priority between each main bus and branch bus. This result realizes the mapping transformation from physical connection structure to logical functional structure, laying the logical framework foundation for establishing a comprehensive bus mapping model.

[0032] After obtaining the multi-node coupling strength and routing topology logic relationships, a comprehensive fitting analysis is performed to establish an initial bus mapping model. First, the coupling strength matrix and logic relationship table are merged into a unified data feature set. Then, the comprehensive mapping relationship between nodes is analyzed using nonlinear function fitting. This fitting process considers factors such as spatial distance between nodes, routing length, signal delay, and logical dependency weights, and minimizes the overall error of the model through multiple iterative optimizations. During the fitting process, weighting factors are used to balance the influence of physical structural coupling and logical dependencies, ensuring that the model reflects both the true strength of structural connections and the hierarchical order of logical functions.

[0033] After fitting, the resulting bus mapping model can describe the multi-layer interconnection relationship between the backbone and branches and its signal propagation laws. The model includes the logical correspondence of each node, spatial distribution parameters, signal transmission paths, and functional association information between layers. Through this model, a complete mapping from the physical topology of the core bus to the logical transmission channels can be achieved, providing a quantifiable reference for the interconnection design of high-bandwidth flash memory chips under multi-layer bonding conditions, and also providing theoretical support for subsequent structural optimization and signal integrity analysis.

[0034] In this embodiment, the specific steps for performing bus interconnect synthesis and bonding based on the initial bus dataset to obtain the bus interconnect path diagram are as follows: Based on the initial bus dataset, the chip layer interface position is located and adaptively calibrated to obtain the calibration interface coordinates; Perform 3D scanning of the chip's microbumps and mark the microbump array; Interlayer conductive polymerization analysis was performed based on the calibration interface coordinates and micro-bump array to generate conductive polymerization parameters. Based on conductive polymerization parameters, the solder ball distribution and welding process are optimized to generate a high-density interconnect layer structure. Bus interconnect synthesis and bonding are performed based on a high-density interconnect layer structure to obtain a bus interconnect path diagram.

[0035] In this embodiment, after establishing the initial bus dataset, the interface positions in the multi-layer structure of the chip need to be located and adaptively calibrated based on the model data. First, the coordinates of the logic nodes in the mapping model are spatially aligned with the chip's physical layer layout. A geometric matching algorithm is used to determine the precise position of each logic interface in the physical structure. The interface positioning process incorporates constraints on interlayer thickness, spacing, and alignment parameters to ensure accurate correspondence between interfaces at different levels in three-dimensional space. Subsequently, adaptive calibration is performed on the positioning results, correcting errors caused by manufacturing tolerances or packaging deformation by dynamically adjusting coordinate deviations and rotation angles. The calibration process introduces multiple well-normalized matrices and performs multiple rounds of iterative calculations on the interface coordinates, keeping the spatial offset of the interface center points within a minimal range. After calibration, a calibration interface coordinate set is formed. This coordinate set accurately reflects the positional relationship of each level of interface in the actual structure, providing a stable positioning reference for subsequent micro-bump scanning and conductive aggregation analysis. This process ensures spatial consistency between the logic mapping and the physical structure, a prerequisite for realizing a high-density interconnect structure. After obtaining the calibration interface coordinates, a three-dimensional scan of the micro-bumps on the chip surface is performed to establish an accurate bump distribution model. The scanning process combines high-precision optical measurement with surface reflection analysis, acquiring data on the height, diameter, spacing, and position of microbumps on the chip surface through multi-angle sampling. The scan results are digitized to form a 3D point cloud dataset. Spatial clustering algorithms are used to identify and group the microbumps, distinguishing the distribution areas of bumps belonging to different functional layers. By projecting the point cloud data onto a plane and matching the inter-layer coordinates, the spatial positions of the microbumps are compared with the calibration interface coordinates obtained in the previous step, marking the bump positions corresponding to the logic interfaces. For bump areas that do not directly correspond, their positional relationship in the overall array is calculated through interpolation and geometric fitting. The final microbump array marking map includes the center coordinates, height distribution, and layer affiliation of each bump, providing a basic geometric reference for subsequent conductive polymerization analysis and soldering process optimization. This process achieves precise identification at the microstructural level, providing an operational spatial positioning basis for multilayer interconnects.

[0036] After obtaining the calibration interface coordinates and micro-bump array marking information, an aggregation analysis is performed on the interlayer conductivity relationship between the two to generate conductivity aggregation parameters. First, an interlayer conductivity path model is established based on the spatial distance, contact area, and arrangement density between each interface and its corresponding micro-bump. By comparing the projection relationship of micro-bumps in adjacent layers, the conductivity connection distribution and coupling characteristics between different layers are analyzed. For multi-layer superimposed regions, a geometric overlap rate calculation method is used to determine their conductivity effectiveness, and the corresponding resistance, contact area, and conductivity path continuity are calculated. Subsequently, based on the conductivity intensity and distribution density of different regions, conductivity aggregation coefficients are extracted to characterize the uniformity and aggregation degree of current conduction in the multi-layer interconnect structure. For regions with uneven conductivity distribution, local aggregation parameters are adjusted to balance conductivity performance, thereby ensuring the electrical continuity and signal stability of the overall interconnect structure. The final generated conductivity aggregation parameter dataset includes the conductivity intensity, aggregation uniformity, and spatial distribution characteristics of each interlayer connection point, providing a quantitative basis for solder ball placement and interconnect optimization. After obtaining the conductivity aggregation parameters, the solder ball distribution design and welding process optimization stage begins. First, based on the conductivity and spatial distribution reflected in the conductive polymerization parameters, the optimal arrangement of solder balls between different layers is determined. By analyzing the correspondence between the polymerization coefficient and the contact area, the density and size of the solder balls are rationally allocated. The number of solder balls in high-conductivity areas is moderately increased to enhance signal transmission capability, while a lower distribution is maintained in low-coupling areas to reduce redundant interconnects. Subsequently, a multi-objective optimization method is used to comprehensively consider factors such as solder ball spacing, melting temperature, solder volume, and surface tension to determine the optimal combination of welding parameters, ensuring the flatness and mechanical stability of the interlayer structure after welding. Optimization of the welding process makes the morphological changes of the solder balls more controllable during heating and cooling, avoiding the formation of cold solder joints and voids. The final high-density interconnect layer structure has a uniform conductive path and stable mechanical support in spatial distribution, laying the structural foundation for the comprehensive bonding of bus interconnects.

[0037] After forming the high-density interconnect layer structure, comprehensive bonding of bus interconnects is performed to complete the construction of the overall connection path. First, based on the conductivity distribution information of the high-density interconnect layer and the initial bus dataset, path matching is performed on the interconnect points between each layer. Through a multi-layer interconnect mapping algorithm, the backbone bus and branch buses are physically mapped to the actual conductive paths, achieving full-layer signal path continuity. Subsequently, comprehensive bonding processing is performed on the matched paths, employing a partitioned sequential heating and pressure control strategy to ensure precise bonding layer by layer in the soldering area, guaranteeing the integrity of the conductive path and the stability of the inter-layer structure. After bonding, the bus interconnect path is structurally analyzed and visualized to form a bus interconnect path diagram. This path diagram includes the physical routing of all signal lines, inter-layer jumper positions, and node connection relationships, intuitively reflecting the multi-layer interconnect network structure of the entire chip. This step signifies that the high-bandwidth flash memory chip based on the core bus structure has achieved full-layer interconnection at the physical level, providing a structural foundation for its high-speed signal transmission and high-density integration.

[0038] In this embodiment, the specific steps for performing cross-layer bus signal synchronization modulation based on the bus interconnection path diagram to obtain the timing coordination parameter set are as follows: Signal integrity transmission simulation is performed based on the bus interconnection path diagram to generate signal simulation data; Extracting signal reception timestamps from cross-layer signal interfaces based on signal simulation data; Based on the signal reception timestamp, calculate the cross-layer signal transmission delay and generate a cross-layer delay distribution curve; Quantitative analysis of timing offset between the backbone bus and branch bus is performed based on cross-layer delay distribution curves to extract bus timing offset characteristics. Based on the bus timing offset characteristics, cross-layer bus signal synchronization modulation is performed to obtain a timing coordination parameter set.

[0039] In this embodiment, after the bus interconnection path diagram is established, the signal transmission characteristics in the multilayer interconnection structure need to be simulated to evaluate its signal integrity under high-frequency conditions. First, the physical parameters of the bus interconnection path are input into the signal simulation model, including wire length, interlayer thickness, dielectric constant, conductor resistivity, and coupling coefficient, to construct a three-dimensional electrical transmission model. This model describes the propagation, reflection, and loss processes of signals in the multilayer interconnection structure. Subsequently, the finite-difference time-domain method or equivalent transmission line model is used to dynamically simulate signal propagation, tracking the voltage and current changes at each path node under set input pulse conditions. By comparing the waveform characteristics and phase response of different paths, the distortion and attenuation of the signal when traversing the multilayer structure are identified.

[0040] During the simulation, the effects of parasitic capacitance and mutual inductance between multiple layers of conductors were considered, and signal reflection, crosstalk, and delay phenomena were quantitatively analyzed. The electrical response data of all nodes were sampled and digitized to form a signal simulation dataset. This dataset records the potential changes and signal transmission status of each node at different time points, providing fundamental data support for subsequent cross-layer interface reception time extraction and timing delay calculation.

[0041] After obtaining the signal simulation data, the receiving timing of the cross-layer signal interface is extracted to establish a signal propagation time stamp. First, key nodes on the cross-layer transmission path are selected from the signal simulation dataset to determine the waveform variation range of the signal at different layer interfaces. By comparing the rising edge and peak positions of the input and output signal waveforms, the time point when the signal arrives at a specific interface is identified. The extraction of the receiving timestamp employs a method combining waveform zero-crossing detection and peak tracking to ensure the accuracy and stability of time resolution. For nodes with signal noise or waveform distortion, smoothing filtering and dynamic threshold adjustment are used to correct abnormal data points, ensuring the accuracy of time extraction.

[0042] After extraction, the reception time of each interface is recorded in time series form, forming a cross-layer signal time distribution table. This table accurately reflects the propagation sequence and response interval of the signal from the transmitter to the receiver across different layers. Through unified timestamp calibration, time synchronization of signal events across different layers can be achieved, providing a basic time reference for calculating cross-layer transmission delay and timing analysis. This step establishes a time-domain benchmark for signal propagation and is a crucial step in quantifying cross-layer transmission characteristics.

[0043] After obtaining the cross-layer signal reception timestamps, the propagation delay of the signal between different layers is calculated to establish a delay distribution curve. First, the time difference between adjacent layer interfaces along the same path is calculated to obtain the signal transmission delay between individual layers. Then, these delay data are accumulated throughout the entire multi-layer interconnect structure to form a cross-layer delay sequence. To avoid deviations caused by local path length or material differences, normalization and linear smoothing are applied to adjust the delay data to a unified reference condition. Finally, the delay sequence is plotted as a delay distribution curve to reflect the overall distribution characteristics of signal propagation time in the multi-layer structure.

[0044] The fluctuations in delay curves reflect differences in signal transmission and interconnection inhomogeneities between layers, and can be used to identify areas of concentrated delay or timing misalignments in the structure. Statistical analysis of the delay curves extracts indicators such as average delay, maximum delay difference, and delay distribution deviation to evaluate the consistency and stability of signal transmission. The generated cross-layer delay distribution curves provide a visualized quantitative basis for subsequent timing offset analysis of the backbone and branch buses, and can also be used to optimize the physical design of interconnect layers and signal synchronization strategies.

[0045] After obtaining the delay distribution curves, a quantitative analysis of the timing offsets of the backbone bus and branch buses is performed. First, the delay curves of the backbone and branch buses are extracted separately, and their peak positions and delay gradients on the time axis are compared to calculate their relative offsets. Delay difference analysis identifies signal transmission inconsistencies between different buses and identifies regions of timing lag and advancement. Offset features are extracted based on statistical characteristics of the delay curves, including average offset, offset variance, and peak offset position.

[0046] The offset results are then spatially mapped to map the timing offset features to the physical layout, identifying the sources of physical offset caused by differences in trace length, conductor thickness, or interlayer dielectric variations. For regions with concentrated offsets, cluster analysis is used to extract typical feature patterns, forming a timing offset feature set. This feature set records the delay difference patterns and offset trends between the main trunk and branches in different regions, providing quantitative control parameters for cross-layer signal synchronization. By analyzing these features, the timing mismatch locations of critical paths can be identified, providing optimization directions for subsequent synchronization modulation.

[0047] After extracting the bus timing offset features, cross-layer signal synchronization modulation is performed to achieve timing coordination. First, a timing adjustment model is established based on the delay distribution pattern in the offset feature set, using the offset between the backbone and branches as input variables. A nonlinear correction algorithm is used to dynamically compensate for the signal transmission delay of each layer, adjusting the transmission time and reception phase of the signal between different layers to ensure that the signals on each path arrive synchronously at the target time. During modulation, factors such as signal transmission rate, inter-layer coupling strength, and path length difference are comprehensively considered to ensure that the compensated signal maintains consistency in the time domain.

[0048] After multiple rounds of modulation and correction, a timing coordination parameter set is generated, which includes the time adjustment amount, phase compensation value, and synchronization offset correction coefficient for each layer of signal path. This parameter set can be directly used for hardware configuration or process modification of multi-layer interconnect signal synchronization, providing precise timing control for cross-layer bus communication of high-bandwidth flash memory chips. Through this process, the chip's multi-layer bus achieves highly consistent data transmission and timing coordination, providing a crucial guarantee for the high-speed and stable operation of the overall interconnect structure.

[0049] In this embodiment, the specific steps for performing routing scheduling based on the timing coordination parameter set and constructing a multi-channel transmission bus network are as follows: Based on the timing coordination parameter set, multi-layer transmission synchronization coordination processing is performed on the signal simulation data to extract the full-layer synchronous transmission data stream. Based on the signal simulation data, the transmission path topology is analyzed to extract multiple signal transmission paths; Based on the bandwidth utilization of the full-layer synchronous transmission data stream; Based on the bandwidth utilization, perform path-by-path load analysis on multiple signal transmission paths to extract the transmission load of multiple paths; Dynamic bandwidth reallocation and routing scheduling are performed based on the transmission load to construct a multi-channel transmission bus network.

[0050] In this embodiment, after generating the timing coordination parameter set, multi-layer transmission synchronization coordination processing is required for the signal simulation data to achieve timing uniformity of the entire signal stream. First, the timing coordination parameters are input into the signal synchronization model to dynamically adjust the time offset and phase difference of signal transmission at each layer. By comparing the transmission delay and reception time of the signal between different layers, the synchronization correction amount for each layer is calculated, ensuring synchronous arrival under a unified time reference. Subsequently, time-domain alignment and phase-matching algorithms are used to smooth the signal waveform, eliminating arrival differences and jitter errors between layers, ensuring continuity and consistency of the signal during cross-layer propagation.

[0051] During the synchronization and coordination process, the multi-layer response of the original signal simulation data is reconstructed in time, and a full-layer synchronous transmission data stream is formed through data fusion and waveform fitting. This data stream records the real-time state changes of the signal across all interconnect layers, including the waveform amplitude, phase trajectory, and energy distribution characteristics of each path. By extracting the full-layer data stream, a unified timing performance of signal transmission under the chip's multi-layer interconnect structure can be obtained, providing a time-domain consistent input basis for subsequent transmission path topology analysis and bandwidth allocation analysis.

[0052] After obtaining the synchronized full-layer transmission data stream, topology analysis of the signal transmission path in the chip's multi-layer interconnect structure is required. First, based on the bus interconnect path diagram and the timing response relationship of the synchronization signal data, the transmission trajectory of the signal between different nodes is identified. By analyzing the timing correlation between nodes and the signal strength variation patterns, a transmission path mapping relationship is established. Using path tracing algorithms and spatial correlation analysis methods, the complete path structure of the signal from the source node to the target node is gradually analyzed.

[0053] During the analysis process, the main and branch paths in the multilayer interconnect are identified. By analyzing signal energy attenuation trends, phase delays, and waveform continuity, direct paths, cross paths, and reflection paths are distinguished. All identified paths are recorded as a path set according to the topological hierarchy, with each path containing node order, spatial distribution, and transmission attribute information. The resulting set of multiple signal transmission paths can fully describe the propagation direction and connection network of signals in the chip's multilayer structure, providing a structural foundation for subsequent bandwidth utilization and path load analysis. This step realizes the mapping from time-domain data to spatial topology, establishing a direct correspondence between the physical characteristics of signal transmission and the structural layout.

[0054] After extracting multiple signal transmission paths, the bandwidth utilization of the full-layer synchronous transmission data stream is analyzed. First, the signal amplitude, transmission rate, and time occupancy ratio in the full-layer data stream are used as input parameters to calculate the effective data transmission volume of each path per unit time. Bandwidth utilization is characterized by the ratio of the effective signal transmission interval to the total time-domain window, thus reflecting the resource utilization degree of each path. Cross-interference and redundant transmission areas between signals are considered in the analysis, and the net bandwidth occupancy value of each path is obtained through data filtering and weighted averaging.

[0055] Under multi-path conditions, the bandwidth utilization of all paths is normalized and compared to determine the load distribution of the backbone and branch paths in the overall data transmission. High-utilization paths typically correspond to areas with concentrated signals or main data transmission channels, while low-utilization paths indicate areas with insufficient resource use or limited signal coverage. By comparing the changes in bandwidth utilization at each layer and along each path, bandwidth bottlenecks in the structure can be identified, providing a quantitative basis for subsequent path load analysis and dynamic resource allocation.

[0056] After bandwidth utilization calculation, a path-by-path load analysis is performed on multiple signal transmission paths. First, bandwidth utilization is combined with path topology information to quantitatively evaluate the transmission capacity of each signal path. The load analysis comprehensively considers parameters such as path length, number of nodes, signal energy loss, and number of interconnect layers to assess the relative carrying capacity of each path in the overall transmission. After normalizing the parameters using a weighted algorithm, the overall transmission load value of the path is calculated.

[0057] Subsequently, the multi-path load data is clustered and sorted. Paths with high load are defined as high-pressure paths, requiring priority scheduling optimization, while paths with low load can participate in traffic sharing as auxiliary channels. By analyzing the load distribution balance, overloaded areas and idle channels in data transmission can be identified. The resulting transmission load data table records the bandwidth occupancy ratio, transmission pressure, and dynamic carrying capacity of each path, providing a basis for subsequent bandwidth reallocation and routing scheduling. This step quantifies the resource utilization of the signal transmission network, providing optimization directions for the construction of multi-channel network structures.

[0058] After obtaining multi-path transmission load information, dynamic bandwidth reallocation and routing scheduling are performed to construct a multi-channel transmission bus network. First, global bandwidth resources are reallocated based on the load intensity and bandwidth occupancy ratio of each path. A dynamic allocation algorithm adjusts the bandwidth weights of the backbone and branch paths, appropriately increasing the bandwidth of overloaded paths while reclaiming or sharing the bandwidth of underloaded paths. During bandwidth adjustment, signal timing synchronization is maintained to ensure continuous and stable data transmission after reallocation.

[0059] Based on bandwidth reallocation, routing scheduling is performed on multiple paths. The scheduling strategy comprehensively determines the transmission path selection of data packets based on transmission delay, load balance, and signal interference levels, thereby achieving multi-channel parallel transmission and adaptive resource utilization. After scheduling, a new multi-channel transmission bus network is formed, which has high bandwidth utilization and balanced load distribution characteristics. Through this process, the chip's cross-layer bus communication achieves dynamic adaptive optimization, enabling the multi-layer interconnect structure to have higher signal transmission efficiency and reliability under high bandwidth conditions.

[0060] In this embodiment, the specific steps for fine-tuning bonding parameters and performing multi-round structural reconstruction simulation based on a multi-channel transmission bus network to output a chip manufacturing structure template are as follows: Calculate the data transmission error rate and signal distortion rate of each path in the multi-channel transmission bus network; Signal quality is evaluated based on the data transmission error rate and signal distortion rate of each path to obtain the signal quality index for each path; The signal quality index is compared and analyzed based on a preset signal quality threshold to extract abnormal paths; A two-way spatiotemporal analysis of path noise interference is performed on abnormal paths to extract the interference status and intensity of abnormal paths. Based on the interference state and interference intensity, dynamic amplitude-frequency compensation and equalization filtering are performed to construct a compensation-optimized bus network. The bonding parameters of the compensation and optimization bus network are fine-tuned to output the chip manufacturing structure template.

[0061] In this embodiment, after constructing a multi-channel transmission bus network, the signal transmission accuracy of each path is quantitatively evaluated. First, based on the synchronized transmission data stream, the bit sequence consistency between the input and output signals is compared to calculate the transmission error rate for each path. The error rate calculation comprehensively considers factors such as signal loss, bit errors, and phase misalignment, and obtains the true transmission accuracy through a bit-matching rate statistical method. Second, spectral analysis and amplitude envelope extraction are performed on the waveform of each path's signal to assess the degree of signal distortion during transmission. The signal distortion rate is calculated based on waveform distortion, frequency offset, and nonlinear mismatch, reflecting the impact of dielectric loss, reflection interference, and coupling noise on the signal shape within the path.

[0062] During the calculation process, error and distortion data are normalized by combining path topology and physical parameters, such as conductor length, dielectric constant, and interconnection layer spacing, to ensure consistency in comparisons across different paths. The resulting error rate and distortion rate data table accurately reflects the stability and fidelity of signal transmission along each path in the multi-channel network, providing a quantitative basis for subsequent signal quality assessment and abnormal path identification. After obtaining the transmission error rate and signal distortion rate for each path, the overall signal quality of the multi-channel bus network is evaluated. First, the error rate and distortion rate are input as the main indicators into the signal quality model, and a signal quality index is generated through weighted averaging and normalization. This index characterizes the signal integrity and anti-interference capability of a path during actual transmission. The weight allocation is set based on signal transmission characteristics and path importance, with higher weights for backbone paths to highlight their impact on overall communication performance.

[0063] Subsequently, by comparing and analyzing the quality index distribution of different paths, regions with low signal stability were identified. Auxiliary parameters such as signal-to-noise ratio, phase consistency, and waveform symmetry were also considered during the evaluation process to make the signal quality assessment results more comprehensive. A signal quality matrix was formed by statistically organizing the signal quality indices of each path, where each element represents a path's stability performance index under different transmission conditions. This matrix provides a quantifiable reference standard for subsequent anomaly path detection and lays the foundation for signal-level judgments in bandwidth scheduling and structural optimization.

[0064] After calculating the signal quality index, a comparative analysis of multi-channel paths is performed based on preset signal quality thresholds to identify paths with abnormal transmission performance. First, a quality threshold range is set according to the overall network design requirements, and paths with a signal quality index below the threshold are judged as abnormal. Then, these paths are matched with the network topology to determine the specific distribution location of the abnormal regions within the chip. By analyzing the signal differences between abnormal paths and adjacent normal paths, possible causes of the anomalies are determined, such as poor local interconnection, uneven dielectric, or electrical noise interference.

[0065] To improve detection accuracy, a dynamic threshold adaptive algorithm is employed, automatically adjusting the upper and lower limits of the threshold based on the overall signal distribution characteristics to avoid misjudgments caused by local fluctuations. The resulting set of abnormal paths not only identifies the number and location of problematic paths but also includes the trend of their signal quality index changes and potential distortion characteristics. This step achieves signal-level problem screening, providing target areas for subsequent interference analysis and compensation optimization, and laying the foundation for refined adjustments to the entire interconnection network. After identifying abnormal paths, bidirectional spatiotemporal analysis of noise interference is performed on these paths to determine the interference state and intensity. First, in the time domain, the transient response characteristics of the signal waveform are analyzed to extract the frequency, duration, and amplitude variation trends of the interference signal. By statistically analyzing the waveform envelope and spectral energy density, the superposition effect of the interference signal on the main signal during transmission is determined. Second, in the spatial domain, the impact of factors such as electromagnetic coupling, reflected echoes, and interlayer crosstalk on signal stability is analyzed in conjunction with the physical layout of the path and the distribution of adjacent conductors.

[0066] By cross-analyzing time-domain and spatial-domain data, the distribution characteristics and energy concentration areas of interference are obtained, thereby extracting the interference state and intensity value of each abnormal path. The interference state characterizes the type of interference, such as random noise, periodic interference, or coupling crosstalk; the interference intensity quantifies its impact on the signal. The final interference parameter set includes information on time-domain fluctuation amplitude, spatial energy concentration, and coupling distribution, providing precise control basis for dynamic compensation and equalization filtering.

[0067] After obtaining the interference status and intensity of the abnormal path, dynamic amplitude-frequency compensation and equalization filtering are performed to restore signal integrity. First, the amplitude response is adjusted according to the interference intensity, and an adaptive amplitude compensation algorithm is used to correct the gain of the interfered signal, causing the energy distribution of the signal in different frequency bands to rebalance. Then, a dynamic frequency compensation method is used to correct the spectral shift caused by the interference, ensuring that the signal frequency components are consistent with the original design.

[0068] After amplitude-frequency compensation, equalization filtering is used to smooth and repair the signal waveform. The filtering process dynamically adjusts the filtering window and weights based on path characteristics to achieve accurate restoration of signal details. Through multi-layer iterative compensation and filtering reconstruction, interference-induced phase drift and amplitude imbalance in the transmitted waveform are eliminated, ultimately forming a compensated and optimized bus network. This network exhibits higher stability and anti-interference capabilities at the signal level, ensuring consistent signal response characteristics for multi-channel interconnects under high-frequency conditions, providing a high-precision signal environment foundation for subsequent structural output. After the compensated and optimized bus network is formed, bonding parameters are fine-tuned to ensure a perfect match between the physical structure and signal characteristics. First, based on the signal timing and conductivity characteristics of the compensated network, the contact pressure, solder ball volume, and temperature profile parameters of the bonding region are corrected. By analyzing the on-resistance and thermal stress distribution of each interconnect node, parameters in local bonding regions are fine-tuned to achieve an optimal balance between structural stress and electrical conductivity.

[0069] After the bonding parameters are adjusted, the optimized network topology, interconnect parameters, and physical layout data are integrated to generate a chip manufacturing structure template. This template includes interconnect layer stacking information, bus path distribution, soldering process parameters, and signal transmission performance indicators, and can be directly used in the manufacturing process of high-bandwidth flash memory chips. This step achieves a complete closed loop from signal-level optimization to structure-level output, ensuring that the chip maintains stable signal integrity and high-bandwidth interconnect performance under mass production conditions, providing the final structural basis for the industrialization of core bus structure bonded flash memory chips.

[0070] In this embodiment, the specific steps for fine-tuning the bonding parameters of the compensation optimization bus network and outputting the chip manufacturing structure template are as follows: Structural stress monitoring and signal transmission peak calculation are performed on the compensated and optimized bus network to identify interconnection bottleneck nodes; Fine-tune the bonding parameters of interconnect bottleneck nodes and extract the bonding adjustment parameters; Multi-round structural reconstruction simulations were performed based on bonding adjustment parameters to form the optimal bonding chip structure. The optimal bonding chip structure is output as a chip manufacturing structure template.

[0071] In this embodiment, after the compensation-optimized bus network is formed, structural stress monitoring and signal transmission peak calculation are performed to identify potential interconnect bottleneck nodes. First, based on the physical parameters of each interconnect layer in the network, stress distribution is detected at solder ball connection points, wire crossing areas, and interlayer transition areas in the chip structure. Through joint analysis of thermal conduction and mechanical response data, the stress concentration degree of each node under thermal cycling and current impact conditions is calculated. Stress monitoring combines geometric deformation, material elastic modulus, and local thermal expansion coefficient to determine stress accumulation trends and potential locations of structural fatigue.

[0072] Subsequently, peak response calculations were performed on the signal transmission paths, extracting the signal amplitude peaks and energy concentration areas for each path under high-frequency excitation conditions. By comparing the peak response amplitudes and phase shifts of different paths, energy accumulation at local nodes was identified. If a node exhibits high stress concentration during stress monitoring and also shows phase reflection or waveform distortion in signal peak calculations, it is defined as an interconnect bottleneck node. The final bottleneck node list includes node location, stress value, peak response intensity, and signal distortion characteristics, providing precise information for subsequent bonding parameter fine-tuning. After identifying interconnect bottleneck nodes, targeted bonding parameter fine-tuning was performed on these nodes to eliminate stress concentration and optimize signal transmission performance. First, based on the bottleneck node's level and physical structure characteristics, appropriate bonding adjustment directions were selected, including key parameters such as contact pressure, solder ball volume, welding temperature, and bonding time. By analyzing the stress distribution curve and signal peak response trends, local bonding strength was gradually adjusted to redistribute the mechanical stress in the node region and mitigate the stress concentration effect.

[0073] Simultaneously, the signal transmission characteristics at the nodes are dynamically monitored, and the waveform amplitude, phase consistency, and delay changes are observed in real time to determine the effectiveness of parameter adjustments. If the signal peak becomes smoother and the delay fluctuation decreases after adjustment, it indicates that the bonding parameters are approaching optimal. After multiple rounds of fine-tuning, the final parameters of each node are recorded as a bonding adjustment parameter set. This parameter set includes data such as the pressure correction value, temperature correction range, and welding time offset for each bottleneck node, which is used to guide the optimization adjustment of the local structure in subsequent structural reconstruction simulations, thereby achieving a dual balance between stress and signal transmission performance. After obtaining the bonding adjustment parameters, a multi-round structural reconstruction simulation stage is entered to determine the optimal chip bonding structure. First, the adjustment parameters are input into the chip's three-dimensional structural model, and the geometry of the welding area, material contact interface, and local interlayer thickness distribution are modified accordingly. Then, multiphysics coupling simulation is performed on the reconstructed structure to calculate its response characteristics under thermal, mechanical, and electrical multidimensional conditions. Key indicators are monitored during the simulation, including maximum stress value, thermal deformation rate, signal attenuation rate, and transmission delay difference.

[0074] Through multiple rounds of simulation iterations, a structural scheme with minimal stress, lowest signal distortion, and optimal conductivity was gradually selected. After each simulation, the trends in structural parameters before and after were compared, and local geometric proportions and interlayer spacing were adjusted to further optimize stress transmission paths and signal transmission channels. The final optimal bonded chip structure achieved a balance between stress equilibrium and signal synchronization in the multilayer interconnect region, enabling the entire chip to maintain structural stability and electrical consistency under high bandwidth conditions. This structural scheme provides a verified three-dimensional physical basis for the output of the final production structural template.

[0075] After determining the optimal bonding chip structure, the simulation results are integrated with actual manufacturing parameters to generate a chip structure template suitable for production. First, the 3D geometric data, material properties, and bonding adjustment parameters from the structural reconstruction simulation are compiled into a standardized data file to establish a complete multilayer interconnect layout description. The template includes key elements such as the thickness of each layer, interlayer spacing, solder ball distribution, bonding pressure, and thermal profile parameters. Subsequently, the template data is verified for accuracy to ensure its feasibility and consistency within manufacturing process constraints.

[0076] During the output phase, key nodes in the template are identified, clarifying their control requirements and process tolerances during manufacturing. This guides the automated parameter tuning of production equipment during bonding and packaging. The final output chip production structure template not only reflects the comprehensive results of multiple rounds of structural optimization and signal compensation but also serves as a standard input file for subsequent mass production. Through this template, the chip manufacturing process can achieve high-precision structural replication and high-consistency performance reproduction, ensuring that high-bandwidth flash memory chips based on core bus structure bonding possess stable interconnect performance and reliable signal transmission quality during the production phase.

[0077] In this embodiment, an HBF chip interconnect device based on CBA bonding is provided for performing the HBF chip interconnect method based on CBA bonding as described above, including: The bus scanning module is used to perform topology scanning on the chip design diagram and generate an initial bus dataset. The interconnect synthesis and bonding module is used to perform bus interconnect synthesis and bonding based on the initial bus dataset to obtain the bus interconnect path diagram. The signal synchronization modulation module is used to perform cross-layer bus signal synchronization modulation based on the bus interconnection path diagram to obtain a timing coordination parameter set. The routing scheduling module is used to perform routing scheduling based on the timing coordination parameter set and to build a multi-channel transmission bus network. The reconstruction simulation module is used to perform bonding parameter fine-tuning and multi-round structural reconstruction simulation based on the multi-channel transmission bus network, and output the chip production structure template.

[0078] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0079] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein are implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for interconnecting HBF chips based on CBA bonding, characterized in that, Includes the following steps: Perform a topology scan on the chip design to generate an initial bus dataset; Based on the initial bus dataset, bus interconnect synthesis and bonding are performed to obtain the bus interconnect path diagram; Based on the bus interconnection path diagram, cross-layer bus signal synchronization modulation is performed to obtain a timing coordination parameter set; Routing scheduling is performed based on the timing coordination parameter set to construct a multi-channel transmission bus network; Based on the multi-channel transmission bus network, bonding parameter fine-tuning and multi-round structural reconstruction simulation are performed to output the chip production structure template.

2. The HBF chip interconnection method based on CBA bonding according to claim 1, characterized in that, The specific steps for performing a topology scan on the chip to generate an initial bus dataset are as follows: Perform topology scanning and probing on the chip design diagram to extract core bus layout data, including the control and scheduling layer, data exchange layer, and physical interface layer; Based on the core bus layout data, the thickness, spacing, and alignment of each layer are calculated to obtain the basic information of the multi-layer structure; Identify bus routing paths and convergence nodes based on core bus layout data; Based on the multi-layer structure information, bus routing paths and convergence nodes, inter-layer stacking analysis and fitting are performed to generate a bus node topology matrix. An initial bus dataset is generated by performing correlation fitting based on the bus node topology matrix.

3. The HBF chip interconnection method based on CBA bonding according to claim 2, characterized in that, The specific steps for generating the initial bus dataset by performing correlation fitting based on the bus node topology matrix are as follows: Perform inter-node coupling analysis on the bus node topology matrix to generate multi-node coupling strength; Perform trace type analysis based on bus trace paths, and mark the main bus and branch buses; Logical association analysis is performed on the main bus and branch buses to generate routing topology logical relationships; Based on the logical relationship of the routing topology and the coupling strength of multiple nodes, a nonlinear fitting is performed to generate an initial bus dataset.

4. The HBF chip interconnection method based on CBA bonding according to claim 1, characterized in that, The specific steps for synthesizing and bonding the bus interconnects based on the initial bus dataset to obtain the bus interconnect path diagram are as follows: Based on the initial bus dataset, the chip layer interface position is located and adaptively calibrated to obtain the calibration interface coordinates; Perform 3D scanning of the chip's microbumps and mark the microbump array; Interlayer conductive polymerization analysis was performed based on the calibration interface coordinates and micro-bump array to generate conductive polymerization parameters. Based on conductive polymerization parameters, the solder ball distribution and welding process are optimized to generate a high-density interconnect layer structure. Bus interconnect synthesis and bonding are performed based on a high-density interconnect layer structure to obtain a bus interconnect path diagram.

5. The HBF chip interconnection method based on CBA bonding according to claim 1, characterized in that, The specific steps for performing cross-layer bus signal synchronization modulation based on the bus interconnection path diagram to obtain the timing coordination parameter set are as follows: Signal integrity transmission simulation is performed based on the bus interconnection path diagram to generate signal simulation data; Extracting signal reception timestamps from cross-layer signal interfaces based on signal simulation data; Based on the signal reception timestamp, calculate the cross-layer signal transmission delay and generate a cross-layer delay distribution curve; Quantitative analysis of timing offset between the backbone bus and branch bus is performed based on cross-layer delay distribution curves to extract bus timing offset characteristics. Based on the bus timing offset characteristics, cross-layer bus signal synchronization modulation is performed to obtain a timing coordination parameter set.

6. The HBF chip interconnection method based on CBA bonding according to claim 1, characterized in that, The specific steps for routing scheduling based on the timing coordination parameter set and constructing a multi-channel transmission bus network are as follows: Based on the timing coordination parameter set, multi-layer transmission synchronization coordination processing is performed on the signal simulation data to extract the full-layer synchronous transmission data stream. Based on the signal simulation data, the transmission path topology is analyzed to extract multiple signal transmission paths; Based on the bandwidth utilization of the full-layer synchronous transmission data stream; Based on the bandwidth utilization, perform path-by-path load analysis on multiple signal transmission paths to extract the transmission load of multiple paths; Dynamic bandwidth reallocation and routing scheduling are performed based on the transmission load to construct a multi-channel transmission bus network.

7. The HBF chip interconnection method based on CBA bonding according to claim 1, characterized in that, The specific steps for performing bonding parameter fine-tuning and multi-round structural reconstruction simulation based on a multi-channel transmission bus network to output the chip production structure template are as follows: Calculate the data transmission error rate and signal distortion rate of each path in the multi-channel transmission bus network; Signal quality is evaluated based on the data transmission error rate and signal distortion rate of each path to obtain the signal quality index for each path; The signal quality index is compared and analyzed based on a preset signal quality threshold to extract abnormal paths; A two-way spatiotemporal analysis of path noise interference is performed on abnormal paths to extract the interference status and intensity of abnormal paths. Based on the interference state and interference intensity, dynamic amplitude-frequency compensation and equalization filtering are performed to construct a compensation-optimized bus network. The bonding parameters of the compensation and optimization bus network are fine-tuned to output the chip manufacturing structure template.

8. The HBF chip interconnection method based on CBA bonding according to claim 7, characterized in that, The specific steps for fine-tuning the bonding parameters of the compensation and optimization bus network and outputting the chip manufacturing structure template are as follows: Structural stress monitoring and signal transmission peak calculation are performed on the compensated and optimized bus network to identify interconnection bottleneck nodes; Fine-tune the bonding parameters of interconnect bottleneck nodes and extract the bonding adjustment parameters; Multi-round structural reconstruction simulations were performed based on bonding adjustment parameters to form the optimal bonding chip structure. The optimal bonding chip structure is output as a chip manufacturing structure template.

9. An HBF chip interconnect device based on CBA bonding, characterized in that, The method for performing the HBF chip interconnect based on CBA bonding as described in claim 1 includes: The bus scanning module is used to perform topology scanning on the chip design diagram and generate an initial bus dataset. The interconnect synthesis and bonding module is used to perform bus interconnect synthesis and bonding based on the initial bus dataset to obtain the bus interconnect path diagram. The signal synchronization modulation module is used to perform cross-layer bus signal synchronization modulation based on the bus interconnection path diagram to obtain a timing coordination parameter set. The routing scheduling module is used to perform routing scheduling based on the timing coordination parameter set and to build a multi-channel transmission bus network. The reconstruction simulation module is used to perform bonding parameter fine-tuning and multi-round structural reconstruction simulation based on the multi-channel transmission bus network, and output the chip production structure template.

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